ADS8321 SBAS123B – SEPTEMBER 1999 – REVISED SEPTEMBER 2004 16-Bit, High Speed, MicroPower Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● BIPOLAR INPUT RANGE ● 100kHz SAMPLING RATE ● MICRO POWER: 4.5mW at 100kHz 1mW at 10kHz ● POWER DOWN: 3µA max ● MSOP-8 PACKAGE ● PIN-COMPATIBLE TO ADS7816 AND ADS7822 ● SERIAL (SPI/SSI) INTERFACE The ADS8321 is a 16-bit sampling analog-to-digital converter (ADC) with tested specifications over a 4.75V to 5.25V supply range. It requires very little power even when operating at the full 100kHz data rate. At lower data rates, the high speed of the device enables it to spend most of its time in the power-down mode—the average power dissipation is less than 1mW at 10kHz data rate. The ADS8321 also features a synchronous serial (SPI/SSI compatible) interface, and a differential input. The reference voltage can be set to any level within the range of 500mV to VCC/2. Ultra-low power and small size make the ADS8321 ideal for portable and battery-operated systems. It is also a perfect fit for remote data acquisition modules, simultaneous multi-channel systems, and isolated data acquisition. The ADS8321 is available in an MSOP-8 package. APPLICATIONS ● ● ● ● BATTERY OPERATED SYSTEMS REMOTE DATA ACQUISITION ISOLATED DATA ACQUISITION SIMULTANEOUS SAMPLING, MULTI-CHANNEL SYSTEMS ● INDUSTRIAL CONTROLS ● ROBOTICS ● VIBRATION ANALYSIS SAR VREF ADS8321 DOUT +In Serial Interface CDAC –In DCLOCK S/H Amp Comparator CS/SHDN Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 1999-2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ABSOLUTE MAXIMUM RATINGS(1) VCC ....................................................................................................... +6V Analog Input ............................................................. –0.3V to (VCC + 0.3V) Logic Input ............................................................................... –0.3V to 6V Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +125°C External Reference Voltage .............................................................. +5.5V NOTE: (1) Stresses above these ratings may permanently damage the device. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION(1) PRODUCT MAXIMUM INTEGRAL LINEARITY ERROR (%) NO MISSING CODE ERROR (LSB) ADS8321E 0.018 " " ADS8321EB " PACKAGE-LEAD PACKAGE DESIGNATOR(1) SPECIFICATION TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY 14 MSOP-8 DGK –40°C to +85°C A21 " " " " " 0.012 15 MSOP-8 DGK –40°C to +85°C A21 " " " " " " ADS8321E/250 ADS8321E/2K5 ADS8321EB/250 ADS8321EB/2K5 Tape and Reel, 250 Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 2500 NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. PIN CONFIGURATION PIN ASSIGNMENTS Top View MSOP VREF 1 +In 2 8 +VCC 7 DCLOCK PIN NAME DESCRIPTION 1 VREF Reference Input 2 +In Non Inverting Input 3 –In Inverting Input ADS8321 2 –In 3 6 DOUT GND 4 5 CS/SHDN 4 GND 5 CS/SHDN Chip Select when LOW, Shutdown Mode when HIGH. Ground 6 DOUT The serial output data word is comprised of 16 bits of data. In operation the data is valid on the falling edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After one null bit, data is valid for the next 16 edges. 7 DCLOCK Data Clock synchronizes the serial data transfer and determines conversion speed. 8 +VCC Power Supply. ADS8321 www.ti.com SBAS123B SPECIFICATIONS: +VCC = +5V At –40°C to +85°C, VREF = +2.5V, –In = 2.5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE, unless otherwise specified. ADS8321E PARAMETER CONDITIONS MIN TYP RESOLUTION ANALOG INPUT Full-Scale Input Span Absolute Input Range +In – (–In) +In –In –VREF –0.1 –0.1 REFERENCE INPUT Voltage Range Resistance ±0.018 ±2 ±0.006 ±0.2 ✻ ±0.05 ±0.05 +4.7V < VCC < 5.25V 100 2.9 ✻ 80 3 3.0 –0.3 4.0 ✻ ✻ ✻ –40 ✻ 5.25 5.25 1700 V GΩ GΩ µA µA µA V V V V ✻ ✻ ✻ ✻ ✻ ✻ ✻ 8.5 3 +85 ✻ ✻ ✻ 0.4 Binary Two’s Complement 1100 250 5.5 0.3 Clk Cycles Clk Cycles kHz MHz ✻ VCC + 0.3 0.8 4.75 2.7 Bits % of FSR mV µV/°C % % ppm/°C µVrms dB LSB(1) dB dB dB dB ✻ ✻ ✻ ✻ ✻ ✻ CMOS TEMPERATURE RANGE Specified Performance ±0.012 ±1 –86 84 86 87 VCC/2 5 5 40 0.8 0.1 CS = VCC V V V pF nA ✻ ✻ ✻ –84 82 84 85 0.5 Specified Performance ✻ ✻ ✻ ✻ 0.024 IIH = +5µA IIL = +5µA IOH = –250µA IOL = 250µA Bits ✻ 16 CS = GND, fSAMPLE = 0Hz CS = VCC ✻ ✻ ✻ ✻ ✻ 4.5 VIN = 5Vp-p at 10kHz VIN = 5Vp-p at 10kHz VIN = 5Vp-p at 10kHz UNITS ±0.024 ±0.024 ±0.3 60 80 3 fSAMPLE = 10kHz(3, 4) Power Dissipation Power Down ✻ ✻ ✻ MAX 15 ±0.008 ±0.4 ±1 fSAMPLE = 10kHz CS = VCC POWER SUPPLY REQUIREMENTS VCC VCC Range(2) Quiescent Current TYP ✻ ✻ 14 Current Drain DIGITAL INPUT/OUTPUT Logic Family Logic Levels: VIH VIL VOH VOL Data Format +VREF VCC + 0.1 +4.0 25 1 SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate Clock Frequency Range DYNAMIC CHARACTERISTICS Total Harmonic Distortion SINAD Spurious Free Dynamic Range SNR MIN 16 Capacitance Leakage Current SYSTEM PERFORMANCE No Missing Codes Integral Linearity Error Offset Error Offset Temperature Drift Gain Error, Positive Negative Gain Temperature Drift Noise Common-Mode Rejection Ratio Power Supply Rejection Ratio ADS8321EB MAX ✻ ✻ ✻ ✻ ✻ ✻ V V µA µA mW µA ✻ °C ✻ Specifications same as ADS8321E. NOTES: (1) LSB means Least Significant Bit. (2) See Typical Performance Curves for more information. (3) fCLK = 2.4MHz, CS = VCC for 216 clock cycles out of every 240. (4) See the Power Dissipation section for more information regarding lower sample rates. ADS8321 SBAS123B www.ti.com 3 TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = +5V, VREF = +2.5V, fSAMPLE = 100kHz, fCLK = 24 • fSAMPLE, unless otherwise specified. FREQUENCY SPECTRUM (8192 Point FFT, fIN = 10.03kHz, –0.3dB) INTEGRAL LINEARITY ERROR vs CODE (+25°C) 3 –20 2 Integral Linearity Error (LSB) 0 Amplitude (dB) –40 –60 –80 –100 –120 –140 –160 1 0 –1 –2 –3 –4 –5 –180 –6 0 10 20 30 40 50 0000H 4000H 7FF9H Frequency (kHz) DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) 2.5 1200 2.0 Supply Current (µA) Differential Linearity Error (LSB) 1400 1.5 1.0 0.5 0 1000 800 600 400 –0.5 200 –1.0 –1.5 0000H 3FFFH 7FFCH C000H 0 –50 FFFDH 0 50 100 Temperature (°C) Hex Code POWER-DOWN SUPPLY CURRENT vs TEMPERATURE QUIESCENT CURRENT vs VCC 600 1.20 500 1.10 Quiescent Current (mA) Supply Current (nA) FFFDH SUPPLY CURRENT vs TEMPERATURE 3.0 400 5V 300 200 100 1.00 0.90 0.80 0.70 0 0.60 –50 –25 0 25 50 75 100 2.0 Temperature (°C) 4 C000H Hex Code 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC (V) ADS8321 www.ti.com SBAS123B TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, VCC = +5V, VREF = +2.5V, fSAMPLE = 100kHz, fCLK = 24 • fSAMPLE, unless otherwise specified. SIGNAL-TO-NOISE AND SIGNAL-TO-(NOISE + DISTORTION) vs INPUT FREQUENCY MAXIMUM SAMPLE RATE vs VCC 1000 90 SNR SNR and SINAD (dB) Sample Rate (kHz) 85 100 10 80 SINAD 75 70 1 65 1 2 3 4 5 0.1 1 VCC (V) 10 100 Input Frequency (kHz) SPURIOUS FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY REFERENCE CURRENT vs SAMPLE RATE 35 90 SFDR 2.5V 30 Reference Current (µA) SNR and SINAD (dB) 85 THD 80 75 70 25 20 1.25V 15 10 5 0 65 0.1 1 10 Input Frequency (kHz) 0 100 20 40 60 80 100 Sample Rate (kHz) 120 140 CHANGE IN GAIN vs REFERENCE VOLTAGE NOISE vs REFERENCE VOLTAGE 15 18 10 14 Change in Gain (LSB) Peak-to-Peak Noise (LSB) 16 12 10 8 6 4 5 0 –5 –10 2 –15 0 0.1 1 Reference Voltage (V) 0 10 ADS8321 SBAS123B www.ti.com 0.5 1.0 1.5 2.0 Reference Voltage (V) 2.5 3.0 5 TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, VCC = +5V, VREF = +2.5V, fSAMPLE = 100kHz, fCLK = 24 • fSAMPLE, unless otherwise specified. CHANGE IN OFFSET vs TEMPERATURE 5.0 5.0 4.0 Change from +25°C (LSB) Change in BPZ (LSB) CHANGE IN BIPOLAR ZERO vs REFERENCE VOLTAGE 6.0 4.0 3.0 2.0 1.0 0 –1.0 –2.0 3.0 2.0 1.0 0 –1.0 –2.0 –3.0 –4.0 –3.0 –5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 –50 0 Reference Voltage (V) 100 COMMON-MODE REJECTION RATIO vs FREQUENCY CHANGE IN GAIN vs TEMPERATURE 5.0 90 4.0 80 3.0 70 2.0 CMRR (dB) Change from +25°C (LSB) 50 Temperature (°C) 1.0 0 –1.0 –2.0 60 50 40 30 –3.0 20 –4.0 10 VCM = 1Vp-p Sinewave 0 –5.0 –50 0 50 100 1 10 100 Temperature (°C) 1k 10k 100k 1M Frequency (Hz) REFERENCE CURRENT vs TEMPERATURE 70 Reference Current (µA) 60 50 5V 40 30 20 10 –50 –25 0 25 50 75 100 Temperature (°C) 6 ADS8321 www.ti.com SBAS123B THEORY OF OPERATION 2 • VREF peak-to-peak Single-Ended Input VREF peak-to-peak ADS821 Common Voltage VREF peak-to-peak Differential Input FIGURE 1. Methods of Driving the ADS8321—Single-Ended or Differential. 5 VCC = 5V 4.0 4 Single-Ended Input 3 2.8 2.2 2 1 0 –0.3 –1 0.0 0.5 1.0 1.5 2.0 2.5 VREF (V) FIGURE 2. Single-Ended Input—Common Voltage Range vs VREF. The analog input is bipolar and fully differential. There are two general methods of driving the analog input of the ADS8321: single-ended or differential (see Figure 1). When the input is single-ended, the –In input is held at a fixed voltage. The +In input swings around the same voltage and the peak-to-peak amplitude is 2 • VREF. The value of VREF determines the range over which the common voltage may vary (see Figure 2). When the input is differential, the amplitude of the input is the difference between the +In and –In input, or; +In – (–In). A voltage or signal is common to both of these inputs. The peak-to-peak amplitude of each input is VREF about this common voltage. However, since the inputs are 180°C outof-phase, the peak-to-peak amplitude of the difference voltage is 2 • VREF. The value of VREF also determines the range of the voltage that may be common to both inputs (see Figure 3). In each case, care should be taken to ensure that the output impedance of the sources driving the +In and –In inputs are matched. If this is not observed, the two inputs could have 5 VCC = 5V 4.0 4 Common Voltage Range (V) ANALOG INPUT 3 Differential Input 2.75 2 1 1.95 0 –0.3 –1 0.0 0.5 1.0 1.5 2.0 2.5 VREF (V) FIGURE 3. Differential Input—Common Voltage Range vs VREF. ADS8321 SBAS123B ADS8321 Common Voltage Common Voltage Range (V) The ADS8321 is a classic Successive Approximation Register (SAR) analog-to-digital converter (ADC). The architecture is based on capacitive redistribution which inherently includes a sample/hold function. The converter is fabricated on a 0.6µ CMOS process. The architecture and process allow the ADS8321 to acquire and convert an analog signal at up to 100,000 conversions per second while consuming less than 5.5mW from +VCC. The ADS8321 requires an external reference, an external clock, and a single power source (VCC). The external reference can be any voltage between 500mV and VCC/2. The value of the reference voltage directly sets the range of the analog input. The reference input current depends on the conversion rate of the ADS8321. The external clock can vary between 24kHz (1kHz throughput) and 2.4MHz (100kHz throughput). The duty cycle of the clock is essentially unimportant as long as the minimum high and low times are at least 200ns (4.75V or greater). The minimum clock frequency is set by the leakage on the capacitors internal to the ADS8321. The analog input is provided to two input pins: +In and –In. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. The digital result of the conversion is clocked out by the DCLOCK input and is provided serially, most significant bit first, on the DOUT pin. The digital data that is provided on the DOUT pin is for the conversion currently in progress—there is no pipeline delay. It is possible to continue to clock the ADS8321 after the conversion is complete and to obtain the serial data least significant bit first. See the digital timing section for more information. www.ti.com 7 different settling times. This may result in offset error, gain error, and linearity error which change with both temperature and input voltage. If the impedance cannot be matched, the errors can be lessened by giving the ADS8321 additional acquisition time. The input current on the analog inputs depends on a number of factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS8321 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (25pF) to 16-bit settling level within 4.5 clock cycles. When the converter goes into the hold mode or while it is in the power-down mode, the input impedance is greater than 1GΩ. Care must be taken regarding the absolute analog input voltage. The +In input should always remain within the range of GND – 300mV to VCC + 300mW. The –In input should always remain within the range of GND – 300mV to 4V. Outside of these ranges, the converter’s linearity may not meet specifications. NOISE The noise floor of the ADS8321 itself is extremely low, as can be seen from Figures 4 and 5, and is much lower than competing A/D converters. It was tested by applying a low noise DC input and a 2.5V reference to the ADS8321 and initiating 5,000 conversions. The digital output of the ADC will vary in output code due to the internal noise of the ADS8321. This is true for all 16-bit SAR-type ADCs. Using a histogram to plot the output codes, the distribution should appear bell-shaped with the peak of the bell curve representing the nominal code for the input value. The ±1σ, ±2σ, and ±3σ distributions will represent the 68.3%, 95.5%, and 99.7%, respectively, of all codes. The transition noise can be calculated by dividing the number of codes measured by 6 and this will yield the ±3σ distribution or 99.7% of all codes. Statistically, up to 3 codes could fall outside the distribution when executing 1000 conversions. The ADS8321, with five output codes for the ±3σ distribution, will yield a ±0.8LSB transition noise. Remember, to achieve this low noise performance, the peak-to-peak noise of the input signal and reference must be < 50µV. REFERENCE INPUT 1639 The external reference sets the analog input range. The ADS8321 will operate with a reference in the range of 500mV to 2.5V. There are several important implications of this. As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is often referred to as the Least Significant Bit (LSB) size and is equal to 2 • VREF divided by 65,535. This means that any offset or gain error inherent in the ADC will appear to increase, in terms of LSB size, as the reference voltage is reduced. The noise inherent in the converter will also appear to increase with lower LSB size. With a +2.5V reference, the internal noise of the converter typically contributes only 5 LSB peak-to-peak of potential error to the output code. When the external reference is 500mV, the potential error contribution from the internal noise will be 10 times larger—15 LSBs. The errors due to the internal noise are gaussian in nature and can be reduced by averaging consecutive conversion results. For more information regarding noise, consult the typical performance curve “Noise vs Reference Voltage.” Note that the Effective Number of Bits (ENOB) figure is calculated based on the converter’s signal-to-(noise + distortion) ratio with a 1kHz, 0dB input signal. SINAD is related to ENOB as follows: SINAD = 6.02 • ENOB + 1.76 With lower reference voltages, extra care should be taken to provide a clean layout including adequate bypassing, a clean power supply, a low-noise reference, and a low-noise input signal. Because the LSB size is lower, the converter will also be more sensitive to external sources of error such as nearby digital signals and electromagnetic interference. 1260 981 0 12 192 13 14 15 16 24 0 17 18 Code FIGURE 4. Histogram of 5,000 Conversions of a DC Input at the Code Transition. 2318 836 696 244 0 12 13 14 15 16 2 0 17 18 Code FIGURE 5. Histogram of 5,000 Conversions of a DC Input at the Code Center. 8 ADS8321 www.ti.com SBAS123B AVERAGING The noise of the ADC can be compensated by averaging the digital codes. By averaging conversion results, transition noise will be reduced by a factor of 1/√n, where n is the number of averages. For example, averaging 4 conversion results will reduce the transition noise by 1/2 to ±0.25 LSBs. Averaging should only be used for input signals with frequencies near DC. For AC signals, a digital filter can be used to low pass filter and decimate the output codes. This works in a similar manner to averaging; for every decimation by 2, the signalto-noise ratio will improve 3dB. SYMBOL SERIAL INTERFACE The ADS8321 communicates with microprocessors and other digital systems via a synchronous 3-wire serial interface as shown in Figure 6 and Table I. The DCLOCK signal synchronizes the data transfer with each bit being transmitted on the falling edge of DCLOCK. Most receiving systems will capture the bitstream on the rising edge of DCLOCK. However, if the minimum hold time for DOUT is acceptable, the system can use the falling edge of DCLOCK to capture each bit. MIN Analog Input Sample Time 4.5 TYP MAX UNITS 5.0 Clk Cycles tCONV Conversion Time tCYC Throughput Rate 100 kHz tCSD CS Falling to 0 ns 16 Clk Cycles DCLOCK LOW CS Falling to tSUCS 20 ns DCLOCK Rising DIGITAL INTERFACE SIGNAL LEVELS The digital inputs of the ADS8321 can accommodate logic levels up to 5.5V regardless of the value of VCC. The CMOS digital output (DOUT) will swing 0V to VCC. If VCC is 3V and this output is connected to a 5V CMOS logic input, then that IC may require more supply current than normal and may have a slightly longer propagation delay. DESCRIPTION tSMPL thDO DCLOCK Falling to Current DOUT Not Valid tdDO DCLOCK Falling to Next DOUT Valid tdis ten 5 15 ns 30 50 ns CS Rising to DOUT Tri-State 70 100 ns DCLOCK Falling to DOUT Enabled 20 50 ns tf DOUT Fall Time 5 25 ns tr DOUT Rise Time 7 25 ns TABLE I. Timing Specifications (VCC = 5V) –40°C to +85°C. A falling CS signal initiates the conversion and data transfer. The first 4.5 to 5.0 clock periods of the conversion cycle are used to sample the input signal. After the fifth falling DCLOCK edge, DOUT is enabled and will output a LOW value for one clock period. For the next 16 DCLOCK periods, DOUT will output the conversion result, most significant bit first. After the least significant bit (B0) has been output, subsequent clocks will repeat the output data but in a least significant bit first format. After the most significant bit (B15) has been repeated, DOUT will tri-state. Subsequent clocks will have no effect on the converter. A new conversion is initiated only when CS has been taken HIGH and returned LOW. Complete Cycle CS/SHDN tSUCS Sample Power Down Conversion DCLOCK tCSD DOUT Use positive clock edge for data transfer Hi-Z 0 tSMPL B15 B14 B13 B12 B11 B10 B9 B8 (MSB) tCONV B7 B6 B5 B4 B3 B2 B1 B0 (LSB) Hi-Z NOTE: Minimum 22 clock cycles required for 16-bit conversion. Shown are 24 clock cycles. If CS remains LOW at the end of conversion, a new datastream with LSB-first is shifted out again. FIGURE 6. ADS8321 Basic Timing Diagrams. ADS8321 SBAS123B www.ti.com 9 DATA FORMAT The output data from the ADS8321 is in Binary Two’s Complement format as shown in Table II. This table represents the ideal output code for the given input voltage and does not include the effects of offset, gain error, or noise. DESCRIPTION ANALOG VALUE Full-Scale Range 2 • VREF Least Significant Bit (LSB) 2 • VREF/65536 +Full Scale BINARY CODE HEX CODE +VREF – 1 LSB 0111 1111 1111 1111 7FFF 0V 0000 0000 0000 0000 0000 0V – 1 LSB 1111 1111 1111 1111 FFFF –VREF 1000 0000 0000 0000 8000 Midscale Midscale – 1LSB DIGITAL OUTPUT BINARY TWO’S COMPLEMENT –Full Scale TABLE II. Ideal Input Voltages and Output Codes. POWER DISSIPATION The architecture of the converter, the semiconductor fabrication process, and a careful design allow the ADS8321 to convert at up to a 100kHz rate while requiring very little power. Still, for the absolute lowest power dissipation, there are several things to keep in mind. The power dissipation of the ADS8321 scales directly with conversion rate. Therefore, the first step to achieving the lowest power dissipation is to find the lowest conversion rate that will satisfy the requirements of the system. In addition, the ADS8321 is in power-down mode under two conditions: when the conversion is complete and whenever CS is HIGH (see Figure 6). Ideally, each conversion should occur as quickly as possible, preferably at a 2.4MHz clock rate. This way, the converter spends the longest possible time in the power-down mode. This is very important as the converter not only uses power on each DCLOCK transition (as is typical for digital CMOS components) but also uses some current for the analog circuitry, such as the comparator. The analog section dissipates power continuously, until the power down mode is entered. 1.4V 3kΩ DOUT VOH DOUT VOL Test Point tr 100pF CLOAD tf Voltage Waveforms for DOUT Rise and Fall Times, tr, tf Load Circuit for tdDO, tr, and tf Test Point DCLOCK VIL VCC DOUT tdDO VOH DOUT tdis Waveform 2, ten 3kΩ tdis Waveform 1 100pF CLOAD VOL thDO Load Circuit for tdis and ten Voltage Waveforms for DOUT Delay Times, tdDO VIH CS/SHDN DOUT Waveform 1(1) CS/SHDN 90% DCLOCK 5 6 tdis DOUT Waveform 2(2) VOL DOUT 10% B11 ten Voltage Waveforms for tdis Voltage Waveforms for ten NOTES: (1) Waveform 1 is for an output with internal conditions such that the output is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with internal conditions such that the output is LOW unless disabled by the output control. FIGURE 7. Timing Diagrams and Test Circuits for the Parameters in Table I. 10 ADS8321 www.ti.com SBAS123B Supply Current (µA) 1000 TA = 25°C VCC = 5.0V VREF = 2.5V fCLK = 2.4MHz 100 10 1 0.1 1 10 100 Sample Rate (kHz) FIGURE 8. Maintaining fCLK at the Highest Possible Rate Allows Supply Current to Drop Linearly with Sample Rate. Supply Current (µA) 1000 100 10 TA = 25°C VCC = 5.0V VREF = 2.5V fCLK = 24 • fSAMPLE 1 0.1 1 10 100 Sample Rate (kHz) FIGURE 9. Scaling fCLK Reduces Supply Current Only Slightly with Sample Rate. Figure 8 shows the current consumption of the ADS8321 versus sample rate. For this graph, the converter is clocked at 2.4MHz regardless of the sample rate—CS is HIGH for the remaining sample period. Figure 9 also shows current consumption versus sample rate. However, in this case, the DCLOCK period is 1/24th of the sample period—CS is HIGH for one DCLOCK cycle out of every 16. There is an important distinction between the power-down mode that is entered after a conversion is complete and the full power-down mode which is enabled when CS is HIGH. CS LOW will shut down only the analog section. The digital section is completely shutdown only when CS is HIGH. Thus, if CS is left LOW at the end of a conversion and the converter is continually clocked, the power consumption will not be as low as when CS is HIGH. See Figure 10 for more information. SHORT CYCLING Another way of saving power is to utilize the CS signal to short cycle the conversion. Because the ADS8321 places the latest data bit on the DOUT line as it is generated, the converter can easily be short cycled. This term means that the conversion can be terminated at any time. For example, if only 14 bits of the conversion result are needed, then the conversion can be terminated (by pulling CS HIGH) after the 14th bit has been clocked out. This technique can be used to lower the power dissipation (or to increase the conversion rate) in those applications where an analog signal is being monitored until some condition becomes true. For example, if the signal is outside a predetermined range, the full 16-bit conversion result may not be needed. If so, the conversion can be terminated after the first n bits, where n might be as low as 3 or 4. This results in lower power dissipation in both the converter and the rest of the system, as they spend more time in the power-down mode. LAYOUT 1000 TA = 25°C VCC = 5.0V VREF = 2.5V fCLK = 24 • fSAMPLE Supply Current (µA) 800 600 CS LOW (GND) 400 200 0.250 CS HIGH (VCC) 0.00 0.1 1 10 100 Sample Rate (kHz) FIGURE 10. Shutdown Current with CS HIGH is 50nA Typically, Regardless of the Clock. Shutdown Current with CS LOW Varies with Sample Rate. For optimum performance, care should be taken with the physical layout of the ADS8321 circuitry. This will be particularly true if the reference voltage is low and/or the conversion rate is high. At a 100kHz conversion rate, the ADS8321 makes a bit decision every 416ns. That is, for each subsequent bit decision, the digital output must be updated with the results of the last bit decision, the capacitor array appropriately switched and charged, and the input to the comparator settled to a 16-bit level all within one clock cycle. The basic SAR architecture is sensitive to spikes on the power supply, reference, and ground connections that occur just prior to latching the comparator output. Thus, during any single conversion for an n-bit SAR converter, there are n “windows” in which large external transient voltages can easily affect the conversion result. Such spikes might originate from switching power supplies, digital logic, and high ADS8321 SBAS123B www.ti.com 11 power devices, to name a few. This particular source of error can be very difficult to track down if the glitch is almost synchronous to the converter’s DCLOCK signal—as the phase difference between the two changes with time and temperature, causing sporadic misoperation. With this in mind, power to the ADS8321 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the ADS8321 package as possible. In addition, a 1µF to 10µF capacitor and a 5Ω or 10Ω series resistor may be used to lowpass filter a noisy supply. The reference should be similarly bypassed with a 0.1µF capacitor. Again, a series resistor and large capacitor can be used to lowpass filter the reference voltage. If the reference voltage originates from an op amp, be careful that the op amp can drive the bypass capacitor without oscillation (the series resistor can help in this case). Keep in mind that while the ADS8321 draws very little current from the reference on average, there are still instantaneous current demands placed on the external input and reference circuitry. Texas Instruments OPA627 op amp provides optimum performance for buffering both the signal and reference inputs. For low cost, low voltage, single-supply applications, the OPA2350 or OPA2340 dual op amps are recommended. Also, keep in mind that the ADS8321 offers no inherent rejection of noise or voltage variation in regards to the reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply will appear directly in the digital results. While high frequency noise can be filtered out as described in the previous paragraph, voltage variation due to the line frequency (50Hz or 60Hz), can be difficult to remove. The GND pin on the ADS8321 should be placed on a clean ground point. In many cases, this will be the “analog” ground. Avoid connecting the GND pin too close to the grounding point for a microprocessor, microcontroller, or digital signal processor. If needed, run a ground trace directly from the converter to the power supply connection point. The ideal layout will include an analog ground plane for the converter and associated analog circuitry. APPLICATION CIRCUITS Figure 11 shows a basic data acquisition system. The ADS8321 input range is 0V to VCC, as the reference input is connected directly to the power supply. The 5Ω resistor and 1µF to 10µF capacitor filter the microcontroller “noise” on the supply, as well as any high-frequency noise from the supply itself. The exact values should be picked such that the filter provides adequate rejection of the noise. 5V 5Ω + 1µF to 10µF ADS8321 +2.5V Reference VREF VCC + 1µF to 10µF 0.1µF 0V to 5V +In CS –In DOUT GND Microcontroller DCLOCK FIGURE 11. Basic Data Acquisition System. 12 ADS8321 www.ti.com SBAS123B PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) ADS8321E/250 ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR ADS8321E/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR ADS8321E/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR ADS8321E/2K5G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR ADS8321EB/250 ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR ADS8321EB/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR ADS8321EB/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR ADS8321EB/2K5G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS8321E/250 VSSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8321E/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8321EB/250 VSSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8321EB/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8321E/250 VSSOP DGK 8 250 367.0 367.0 35.0 ADS8321E/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0 ADS8321EB/250 VSSOP DGK 8 250 367.0 367.0 35.0 ADS8321EB/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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