CAT93C86 16 Kb Microwire Serial EEPROM Description The CAT93C86 is a 16 Kb Serial EEPROM memory device which is configured as either registers of 16 bits (ORG pin at VCC) or 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C86 is manufactured using ON Semiconductor’s advanced CMOS EEPROM floating gate technology. The device is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. The device is available in 8−pin DIP and 8−pin SOIC packages. http://onsemi.com SOIC−8 V, W SUFFIX CASE 751BD Features • • • • • • • • • • • • • • High Speed Operation: 3 MHz / VCC = 5 V Low Power CMOS Technology 1.8 V to 5.5 V Operation Selectable x8 or x16 Memory Organization Self−timed Write Cycle with Auto−clear Hardware and Software Write Protection Power−up Inadvertent Write Protection Sequential Read Program Enable (PE) Pin 1,000,000 Program/Erase Cycles 100 Year Data Retention Industrial and Extended Temperature Ranges 8−lead PDIP and SOIC Packages These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS Compliant VCC SK SOIC−8 X SUFFIX CASE 751BE PIN CONFIGURATION CS SK DI DO 1 VCC PE ORG GND 1 PE VCC CS SK PIN FUNCTION Pin Name Function Chip Select SK Clock Input DI Serial Data Input DO Serial Data Output VCC Power Supply GND Ground GND ORG Memory Organization Figure 1. Functional Symbol PE DI CAT93C86 DO PE Note: When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 pin is selected. If the ORG pin is left unconnected, then an internal pull−up device will select the x16 organization. © Semiconductor Components Industries, LLC, 2013 October, 2013 − Rev. 12 1 ORG GND DO DI SOIC (W)* PDIP (L), SOIC (V, X) CS ORG CS PDIP−8 L SUFFIX CASE 646AA Program Enable ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. * Not Recommended for New Designs Publication Order Number: CAT93C86/D CAT93C86 Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Temperature Under Bias −55 to +125 °C Storage Temperature −65 to +150 °C −2.0 to +VCC +2.0 V Voltage on any Pin with Respect to Ground (Note 1) VCC with Respect to Ground −2.0 to +7.0 V Package Power Dissipation Capability (TA = 25°C) 1.0 W Lead Soldering Temperature (10 seconds) 300 °C Output Short Circuit Current (Note 2) 100 mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5 V, which may overshoot to VCC +2.0 V for periods of less than 20 ns. 2. Output shorted for no more than one second. No more than one output shorted at a time. Table 2. RELIABILITY CHARACTERISTICS Symbol Parameter Reference Test Method Min Units NEND (Note 3) Endurance MIL−STD−883, Test Method 1033 1,000,000 Cycles/Byte TDR (Note 3) Data Retention MIL−STD−883, Test Method 1008 100 Years VZAP (Note 3) ESD Susceptibility MIL−STD−883, Test Method 3015 2000 V ILTH (Notes 3, 4) Latch−Up JEDEC Standard 17 100 mA 3. These parameters are tested initially and after a design or process change that affects the parameter. 4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VCC +1 V. Table 3. D.C. OPERATING CHARACTERISTICS (VCC = +1.8 V to +5.5 V unless otherwise specified.) Symbol Parameter ICC1 Power Supply Current (Write) ICC2 Test Conditions Max Units fSK = 1 MHz; VCC = 5.0 V 3 mA Power Supply Current (Read) fSK = 1 MHz; VCC = 5.0 V 500 mA ISB1 Power Supply Current (Standby) (x8 Mode) CS = 0 V ORG = GND 10 mA ISB2 Power Supply Current (Standby) (x16 Mode) CS = 0 V ORG = Float or VCC 10 mA ILI Input Leakage Current VIN = 0 V to VCC 1 mA ILO Output Leakage Current (Including ORG pin) VOUT = 0 V to VCC, CS = 0 V 1 mA VIL1 Input Low Voltage 4.5 V ≤ VCC < 5.5 V −0.1 0.8 V VIH1 Input High Voltage 4.5 V ≤ VCC < 5.5 V 2 VCC + 1 V VIL2 Input Low Voltage 1.8 V ≤ VCC < 4.5 V 0 VCC x 0.2 V VIH2 Input High Voltage 1.8 V ≤ VCC < 4.5 V VCC x 0.7 VCC + 1 V 0.4 V VOL1 Output Low Voltage 4.5 V ≤ VCC < 5.5 V; IOL = 2.1 mA VOH1 Output High Voltage 4.5 V ≤ VCC < 5.5 V; IOH = −400 mA VOL2 Output Low Voltage 1.8 V ≤ VCC < 4.5 V; IOL = 1 mA VOH2 Output High Voltage 1.8 V ≤ VCC < 4.5 V; IOH = −100 mA http://onsemi.com 2 Min Typ 0 2.4 V 0.2 VCC − 0.2 V V CAT93C86 Table 4. PIN CAPACITANCE (Note 5) Test Symbol COUT CIN Conditions Output Capacitance (DO) Max Units VOUT = 0 V 5 pF VIN = 0 V 5 pF Input Capacitance (CS, SK, DI, ORG) Min Typ Table 5. POWER−UP TIMING (Notes 5, 6) Parameter Symbol Max Units tPUR Power−up to Read Operation 1 ms tPUW Power−up to Write Operation 1 ms Table 6. A.C. TEST CONDITIONS Input Rise and Fall Times ≤ 50 ns Input Pulse Voltages 0.4 V to 2.4 V 4.5 V ≤ VCC ≤ 5.5 V 0.8 V, 2.0 V 4.5 V ≤ VCC ≤ 5.5 V 0.2 x VCC to 0.7 x VCC 1.8 V ≤ VCC ≤ 4.5 V 0.5 x VCC 1.8 V ≤ VCC ≤ 4.5 V Timing Reference Voltages Input Pulse Voltages Timing Reference Voltages Table 7. A.C. CHARACTERISTICS Symbol Parameter Test Conditions VCC = 1.8 V − 5.5 V VCC = 2.5 V − 5.5 V VCC = 4.5 V − 5.5 V Min Min Min Max Max Max Units tCSS CS Setup Time 200 100 50 ns tCSH CS Hold Time 0 0 0 ns tDIS DI Setup Time 200 100 50 ns tDIH DI Hold Time 200 100 50 ns tPD1 Output Delay to 1 tPD0 Output Delay to 0 tHZ (Note 5) tEW CL = 100 pF (Note 7) Output Delay to High−Z Program/Erase Pulse Width 1 0.5 0.15 ms 1 0.5 0.15 ms 400 200 100 ns 5 5 5 ms tCSMIN Minimum CS Low Time 1 0.5 0.15 ms tSKHI Minimum SK High Time 1 0.5 0.15 ms tSKLOW Minimum SK Low Time 1 0.5 0.15 ms tSV Output Delay to Status Valid SKMAX Maximum Clock Frequency 1 DC 500 0.5 DC 1000 5. These parameters are tested initially and after a design or process change that affects the parameter. 6. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. 7. The input levels and timing reference points are shown in the “A.C. Test Conditions” table. http://onsemi.com 3 DC 0.1 ms 3000 kHz CAT93C86 Table 8. INSTRUCTION SET Address Data Instruction Start Bit Opcode x8 x16 READ 1 10 A10−A0 A9−A0 Read Address AN– A0 ERASE 1 11 A10−A0 A9−A0 Clear Address AN– A0 WRITE 1 01 A10−A0 A9−A0 EWEN 1 00 11XXXXXXXXX 11XXXXXXXX Write Enable EWDS 1 00 00XXXXXXXXX 00XXXXXXXX Write Disable ERAL 1 00 10XXXXXXXXX 10XXXXXXXX Clear All Addresses WRAL 1 00 01XXXXXXXXX 01XXXXXXXX Device Operation The CAT93C86 is a 16,384−bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C86 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 13−bit instructions control the reading, writing and erase operations of the device. When organized as X8, seven 14−bit instructions control the reading, writing and erase operations of the device. The CAT93C86 operates on a single power supply and will generate on chip, the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the falling edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The format for all instructions sent to the device is a logical “1” start bit, a 2−bit (or 4−bit) opcode, 10−bit address (an additional bit when organized X8) and for write operations a 16−bit data field (8−bit for X8 organizations). Note: The Write, Erase, Write all and Erase all instructions require PE = 1. If PE is left floating, 93C86 is in Program Enabled mode. For Write Enable and Write Disable instruction PE = don’t care. x8 D7−D0 D7−D0 x16 D15−D0 D15−D0 Comments Write Address AN– A0 Write All Addresses Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C86 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). After the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential READ mode. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. In the sequential READ mode, only the initial data word is preceeded by a dummy zero bit. All subsequent data words will follow without a dummy zero bit. Write After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C86 can be determined by selecting the device and polling the DO pin. Since this device features Auto−Clear before write, it is NOT necessary to erase a memory location before it is written into. http://onsemi.com 4 CAT93C86 tSKHI tSKLOW tCSH SK tDIS tDIH VALID DI VALID tCSS CS tPD0, tPD1 tDIS DO tCSMIN DATA VALID Figure 2. Synchronous Data Timing SK 1 1 1 1 1 AN AN−1 1 1 1 1 1 1 1 1 1 1 CS DI 1 1 Don’t Care A0 0 HIGH−Z DO Dummy 0 D15 . . . D0 or D7 . . . D0 Address + 1 D15 . . . D0 or D7 . . . D0 Address + 2 D15 . . . D0 or D7 . . . D0 Address + n D15 . . . or D7 . . . Figure 3. Read Instruction Timing SK tCSMIN CS AN AN−1 DI DO 1 0 A0 DN STATUS VERIFY D0 STANDBY 1 tSV HIGH−Z BUSY READY tEW Figure 4. Write Instruction Timing http://onsemi.com 5 tHZ HIGH−Z CAT93C86 Erase Erase All Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C86 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state. Upon receiving an ERAL command, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C86 can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical “1” state. Erase/Write Enable and Disable Write All The CAT93C86 powers up in the write disable state. Any writing after power−up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93C86 write and clear instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C86 can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed. SK CS AN DI DO 1 1 AN−1 A0 tCS STATUS VERIFY STANDBY 1 tSV HIGH−Z BUSY tEW Figure 5. Erase Instruction Timing http://onsemi.com 6 tHZ READY HIGH−Z CAT93C86 PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A SYMBOL MIN NOM A E1 5.33 A1 0.38 A2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 D 9.02 9.27 10.16 E 7.62 7.87 8.25 E1 6.10 6.35 7.11 e PIN # 1 IDENTIFICATION MAX 2.54 BSC eB 7.87 L 2.92 10.92 3.30 3.80 D TOP VIEW E A2 A A1 c b2 L e eB b SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. http://onsemi.com 7 CAT93C86 PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O E1 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 MAX 4.00 1.27 BSC e PIN # 1 IDENTIFICATION NOM h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 θ A c e b L SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. http://onsemi.com 8 CAT93C86 PACKAGE DIMENSIONS SOIC−8, 208 mils CASE 751BE−01 ISSUE O SYMBOL MIN NOM 2.03 A E1 E MAX A1 0.05 0.25 b 0.36 0.48 c 0.19 0.25 D 5.13 5.33 E 7.75 8.26 E1 5.13 5.38 1.27 BSC e L 0.51 0.76 θ 0º 8º PIN#1 IDENTIFICATION TOP VIEW D A e b q L A1 SIDE VIEW c END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with EIAJ EDR-7320. http://onsemi.com 9 CAT93C86 ORDERING INFORMATION Specific Device Marking Pkg Type Temperature Range Lead Finish CAT93C86LI−G 93C86L PDIP−8 Shipping I = Industrial (−40°C to +85°C) NiPdAu Tube, 50 Units / Tube CAT93C86VI−G 93C86V SOIC−8, JEDEC I = Industrial (−40°C to +85°C) NiPdAu Tube, 100 Units / Tube CAT93C86VI−GT3 93C86V SOIC−8, JEDEC I = Industrial (−40°C to +85°C) NiPdAu Tape & Reel, 3000 Units / Reel CAT93C86WI−G (Note 10) 93C86W SOIC−8, JEDEC I = Industrial (−40°C to +85°C) NiPdAu Tube, 100 Units / Tube CAT93C86WI−GT3 (Note 10) 93C86W SOIC−8, JEDEC I = Industrial (−40°C to +85°C) NiPdAu Tape & Reel, 3000 Units / Reel CAT93C86XI 93C86X SOIC−8, EIAJ I = Industrial (−40°C to +85°C) Matte−Tin Tube, 94 Units / Tube CAT93C86XI−T2 93C86X SOIC−8, EIAJ I = Industrial (−40°C to +85°C) Matte−Tin Tape & Reel, 2000 Units / Reel OPN 8. All packages are RoHS−compliant (Lead−free, Halogen−free). 9. The standard lead finish is NiPdAu. 10. Not recommended for new designs. 11. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 12. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 13. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device Nomenclature document, TND310/D, available at www.onsemi.com ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 10 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative CAT93C86/D