CAT93HC46 1K-Bit High Speed Microwire Serial EEPROM FEATURES ■ High speed operation: ■ Hardware and software write protection ■ Power-up inadvertent write protection – 93HC46: 3MHz ■ Low power CMOS technology ■ 1,000,000 program/erase cycles ■ 1.8 to 6.0 volt operation ■ 100 year data retention ■ Selectable x8 or x16 memory organization ■ Commercial, industrial and automotive temperature ranges ■ Self-timed write cycle with auto-clear ■ Sequential Read DESCRIPTION technology. The device is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. The CAT93HC46 is available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP packages. The CAT93HC46 is a 1K-bit Serial EEPROM memory devices which is configured as either registers of 16 bits (ORG pin at VCC) or 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93HC46 is manufactured using Catalyst’s advanced CMOS EEPROM floating gate PIN CONFIGURATION DIP Package (P) CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC ORG GND NC VCC CS SK 1 2 3 4 8 7 6 5 ORG GND DO DI CS SK DI DO 1 2 3 4 8 7 6 5 PIN FUNCTIONS Pin Name CS Chip Select SK Clock Input DI Serial Data Input DO Serial Data Output VCC +1.8 to 6.0V Power Supply GND Ground ORG Memory Organization NC No Connection PE* Program Enable VCC NC ORG GND CS SK 1 2 DI 3 4 DO 8 7 6 5 VCC NC ORG GND BLOCK DIAGRAM Function VCC ORG GND MEMORY ARRAY ORGANIZATION ADDRESS DECODER DATA REGISTER OUTPUT BUFFER DI CS PE* Note: When the ORG pin is connected to VCC, the X16 organization is selected. When it is connected to ground, the X8 pin is selected. If the ORG pin is left unconnected, then an internal pullup device will select the X16 organization. © 2001 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice TSSOP Package (U) SOIC Package (S) SOIC Package (J) SK MODE DECODE LOGIC CLOCK GENERATOR DO 93C46/56/57/66/86 F02 1 Doc. No. 1008,Rev. A CAT93HC46 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to Ground(1) ............ –2.0V to +VCC +2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND TDR (3) (3) Parameter Endurance Min. Max. Units Reference Test Method 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033 Data Retention 100 Years MIL-STD-883, Test Method 1008 VZAP(3) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILTH(3)(4) Latch-Up 100 mA JEDEC Standard 17 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified.) Limits Symbol Parameter Min. Typ. Max. Units Test Conditions ICC1 Power Supply Current (Operating Write) 3 mA fSK = 3MHz VCC = 5.0V ICC2 Power Supply Current (Operating Read) 500 µA fSK = 3MHz VCC = 5.0V ISB1 Power Supply Current (Standby) (x8 Mode) 10 µA CS = 0V ORG=GND ISB2(5) Power Supply Current (Standby) (x16Mode) 0 µA CS=0V ORG=Float or VCC ILI Input Leakage Current (Including ORG pin) 1 µA VIN = 0V to VCC ILO Output Leakage Current (Including ORG pin) 1 µA VOUT = 0V to VCC, CS = 0V VIL1 Input Low Voltage -0.1 0.8 V 4.5V≤VCC<5.5V VIH1 Input High Voltage 2 VCC+1 V 4.5V≤VCC<5.5V VIL2 Input Low Voltage 0 VCCX0.2 V 1.8V≤VCC<4.5V VIH2 Input High Voltage VCCX0.7 VCC+1 VOL1 Output Low Voltage VOH1 Output High Voltage VOL2 Output Low Voltage VOH2 Output High Voltage 0.4 2.4 0.2 VCC-0.2 V V 1.8V≤VCC<4.5V 4.5V≤VCC<5.5V, IOL=2.1mA V 4.5V≤VCC<5.5V, IOH = -400mA V 1.8V≤VCC<4.5V, IOL=1mA 1.8V≤VCC<4.5V, IOH = -100µA Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. (5) Standby Current (ISB2)=0µA (<900nA). Doc. No. 1008, Rev. A 2 CAT93HC46 RECOMMENDED OPERATING CONDITIONS Temperature Device Supply Voltage Range Minimum Maximum 0˚C +70˚C CAT93HC46 2.5V to 6.0V Industrial -40˚C +85˚C CAT93HC46-1.8 1.8V to 6.0V Automotive -40˚C +105˚C Extended -40˚C +125˚C Max. Units Conditions OUTPUT CAPACITANCE (DO) 5 pF VOUT=0V, tA=25˚C, fSK=1MHz INPUT CAPACITANCE (CS, SK, DI, ORG) 5 pF VIN=0V, tA=25˚C, fSK=1MHz Commercial PIN CAPACITANCE Symbol COUT (1) CIN(1) Test INSTRUCTION SET Instruction Start Bit Opcode x8 Address x16 Data x8 x16 Comments READ 1 10 A6-A0 A5-A0 Read Address AN–A0 ERASE 1 11 A6-A0 A5-A0 Clear Address AN–A0 WRITE 1 01 A6-A0 A5-A0 EWEN 1 00 11XXXXX 11XXXX Write Enable EWDS 1 00 00XXXXX 00XXXX Write Disable ERAL 1 00 10XXXXX 10XXXX Clear All Addresses WRAL 1 00 01XXXXX 01XXXX D7-D0 D7-D0 D15-D0 Write Address AN–A0 D15-D0 Write All Addresses Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. 3 Doc. No. 1008, Rev. A CAT93HC46 POWER-UP TIMING (1)(2) SYMBOL PARAMETER Max Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 1 ms A.C. CHARACTERISTICS Limits VCC = 1.8V-6V* VCC = 2.5V-6V Min. tCSS CS Setup Time 200 150 50 ns tCSH CS Hold Time 0 0 0 ns VIL = 0.45V tDIS DI Setup Time 400 250 50 ns VIH = 2.4V tDIH DI Hold Time 400 250 50 ns CL = 100pF tPD1 Output Delay to 1 1 0.5 0.1 µs tPD0 Output Delay to 0 1 0.5 0.1 µs C VLOL==100pF 0.8V (3) V = 2.0v 400 200 100 ns 5 5 5 ms tHZ Output Delay to High-Z Min. Max. Min. Max. Test SYMBOL PARAMETER (1) Max. VCC = 4.5V-5.5V UNITS tEW Program/Erase Pulse Width tCSMIN Minimum CS Low Time 1 0.5 0.1 µs tSKHI Minimum SK High Time 1 0.5 0.1 µs tSKLOW Minimum SK Low Time 1 0.5 0.1 µs tSV Output Delay to Status Valid SKMAX Maximum Clock Frequency 1 DC 0.5 250 DC 1000 DC 0.1 µs 3000 KHZ NOTE: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. (3) The input levels and timing reference points are shown in “AC Test Conditions” table. A.C. TEST CONDITIONS Input Rise and Fall Times ≤ 50ns Input Pulse Voltages 0.4V to 2.4V 4.5V ≤ VCC ≤ 5.5V Timing Reference Voltages 0.8V, 2.0V 4.5V ≤ VCC ≤ 5.5V Input Pulse Voltages 0.3VCC to 0.7VCC 1.8V ≤ VCC ≤ 4.5V Timing Reference Voltages 0.5VCC 1.8V ≤ VCC ≤ 4.5V Doc. No. 1008, Rev. A 4 Conditions OH CL = 100pF CAT93HC46 DEVICE OPERATION The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the falling edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The CAT93HC46 is a 1024-bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93HC46 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 9-bit instructions control the reading, writing and erase operations of the device. When organized as X8, seven 10-bit instructions control the reading, writing and erase operations of the device. The CAT93HC46 operates on a single power supply and will generate on chip, the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. Figure 1. Sychronous Data Timing tSKLOW tSKHI tCSH SK tDIS tDIH VALID DI VALID tCSS CS tDIS tPD0,tPD1 DO tCSMIN DATA VALID Figure 2a. Read Instruction Timing SK tCS MIN CS STANDBY AN DI DO 1 1 AN—1 A0 0 HIGH-Z tPD0 tHZ HIGH-Z 0 DN 5 DN—1 D1 D0 Doc. No. 1008, Rev. A CAT93HC46 The format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit byte/ word address (an additional bit when organized X8) and for write operations a 16-bit data field (8-bit for X8 organizations). back to address 0. In the sequential READ mode, only the initial data word is preceeded by a dummy zero bit. All subsequent data words will follow without a dummy zero bit. Write Read After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. (Note 1.) The ready/busy status of the CAT93HC46 can be determined by selecting the device and polling the DO pin. Since this device features Auto-Clear before write, it is NOT necessary to erase a memory location before it is written into. Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93HC46 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1) After the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the CAT93HC46 will automatically increment to the next address and shift out the next data word in a sequential READ mode. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN. The falling edge of CS will start the self clocking Figure 2b. Sequential Read Instruction Timing SK 1 1 1 1 1 AN AN–1 1 1 1 1 1 1 1 1 1 1 CS Don't Care DI 1 1 A0 0 HIGH-Z DO Dummy 0 D15 . . . D0 or D7 . . . D0 Address + 1 D15 . . . D0 or D7 . . . D0 Address + 2 D15 . . . D0 or D7 . . . D0 Address + n D15 . . . or D7 . . . Figure 3. Write Instruction Timing SK tCS MIN AN DI 1 0 AN-1 A0 DN D0 1 tSV DO STANDBY STATUS VERIFY CS tHZ BUSY HIGH-Z READY HIGH-Z tEW 93C46/56/57/66/86 F05 Doc. No. 1008, Rev. A 6 CAT93HC46 of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. (Note 1.) The ready/busy status of the CAT93HC46 can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical “1” state. clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. (Note 1.) The ready/ busy status of the CAT93HC46 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state. Write All Erase/Write Enable and Disable Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93HC46 can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed. The CAT93HC46 powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93HC46 write and clear instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/ disable status. Note 1: After the last data bit has been sampled, Chip Select (CS) must be brought Low before the next rising edge of the clock (SK) in order to start the self-timed high voltage cycle. This is important because if the CS is brought low before or after this specific frame window, the addressed location will not be programmed or erased. Erase All Upon receiving an ERAL command, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle Figure 4. Erase Instruction Timing SK STATUS VERIFY CS AN DI 1 1 tCS MIN A0 AN-1 STANDBY 1 tHZ tSV HIGH-Z DO BUSY READY HIGH-Z tEW 7 Doc. No. 1008, Rev. A CAT93HC46 Figure 5. EWEN/EWDS Instruction Timing SK STANDBY CS DI 1 0 0 * * ENABLE=11 DISABLE=00 Figure 6. ERAL Instruction Timing SK CS STATUS VERIFY STANDBY tCS MIN DI 1 0 0 0 1 tSV tHZ HIGH-Z DO BUSY READY HIGH-Z tEW Figure 7. WRAL Instruction Timing SK CS STATUS VERIFY STANDBY tCS MIN DI 1 0 0 0 DN 1 D0 tSV tHZ DO BUSY READY HIGH-Z tEW Doc. No. 1008, Rev. A 8 CAT93HC46 ORDERING INFORMATION Prefix Device # CAT Optional Company ID 93HC46 Product Number 93HC46: 1K Suffix -1.8 I S Temperature Range Blank = Commercial (0°C to +70°C) I = Industrial (-40°C to +85°C) A = Automotive (-40°C to +105°C) E = Extended (-40˚C to +125˚C) Package P = PDIP S = SOIC (JEDEC) J = SOIC (JEDEC) U = TSSOP TE13 Tape & Reel TE13: 2000/Reel Operating Voltage Blank (Vcc=2.5 to 6.0V) 1.8 (Vcc=1.8 to 6.0V) Notes: (1) The device used in the above example is a 93HC46SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage, Tape & Reel) 9 Doc. No. 1008, Rev. A Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. 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Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Publication #: Revison: Issue date: Type: 1008 A 10/16/01 Final