NSC DS92LX1622

June 1, 2010
10 - 50 MHz Channel Link III Serializer and Deserializer with
Embedded Bi-Directional Control Channel
General Description
■ Embedded clock with DC Balanced coding to support AC-
The DS92LX1621/DS92LX1622 chipset offers a Channel
Link III interface with a high-speed forward channel and a fullduplex control channel for data transmission over a single
differential pair. The Serializer/Deserializer pair is targeted for
direct connections between camera systems and Host Controller/Frame Grabbers. The primary transport sends 16 bits
of image data over a single high-speed serial stream together
with a low latency bi-directional control channel transport that
supports I2C. Included with the 16-bit payload is a selectable
data integrity option for CRC (Cyclic Redundancy Check) or
parity bit to monitor transmission link errors. Using National’s
embedded clock technology allows transparent full-duplex
communication over a single differential pair, carrying asymmetrical bi-directional control information without the dependency of video blanking intervals. This single serial stream
simplifies transferring a wide data bus over PCB traces and
cable by eliminating the skew problems between parallel data
and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce cable width, connector
size and pins.
In addition, the Deserializer inputs provide equalization control to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to
support AC-Coupled interconnects.
A sleep function provides a power-savings mode when the
high speed forward channel and embedded bi-directional
control channel are not needed.
The Serializer is offered in a 32-pin LLP package and Deserializer is offered in a 40-pin LLP package.
■ Capable to drive up to 10 meters shielded twisted-pair
■ Bi-directional control interface channel with I2C support
■ I2C interface for device configuration. Single-pin ID
coupled interconnects
addressing
■ 16–bit data payload with CRC (Cyclic Redundancy Check)
■
■
■
■
■
■
■
■
■
■
■
■
for checking data integrity with programmable data
transmission error detection and interrupt control
Up to 6 Programmable GPIO's
AT-SPEED BIST diagnosis feature to validate link integrity
Individual power-down controls for both SER and DES
User-selectable clock edge for parallel data on both SER
and DES
Integrated termination resistors
1.8V- or 3.3V-compatible parallel bus interface
Single power supply at 1.8V
IEC 61000–4–2 ESD compliant
No reference clock required on Deserializer
Programmable Receive Equalization
LOCK output reporting pin to ensure link status
EMI/EMC Mitigation
— DES Programmable Spread Spectrum (SSCG)
outputs
— DES Receiver Output Clock and Data Slew Rate Select
— DES Receiver staggered outputs
Temperature range −40°C to +85°C
SER package: 32 pin LLP (5mm x 5mm)
DES package: 40 pin LLP (6mm x 6mm)
Features
■
■
■
■ Configurable data throughput
Applications
— 12–bit (min) up to 600 Mbits/sec
— 16–bit (def) up to 800 Mbits/sec
— 18–bit (max) up to 900 Mbits/sec
■ 10 MHz to 50 MHz input clock support
■ Industrial Displays, Touch Screens
■ Medical Imaging
Typical Application Diagram
30123027
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2010 National Semiconductor Corporation
301230
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DS92LX1621 / DS92LX1622 10 - 50 MHz Channel Link III Serializer and Deserializer with
Embedded Bi-Directional Control Channel
DS92LX1621 / DS92LX1622
ADVANCE
INFORMATION
DS92LX1621 / DS92LX1622
Block Diagrams
30123028
FIGURE 1. Block Diagram
30123029
FIGURE 2. Application Block Diagram
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2
DS92LX1621 / DS92LX1622
DS92LX1621 Pin Diagram
30123019
Serializer - DS92LX1621 — Top View
3
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DS92LX1621 / DS92LX1622
DS92LX1621 Serializer Pin Descriptions
Pin Name
Number of Pins
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
DIN[13:0]
14
Inputs, LVCMOS w/ Parallel data inputs.
pull down
HSYNC
1
Inputs, LVCMOS w/ Horizontal SYNC Input, can be used as parallel data input 14
pull down
VSYNC
1
Inputs, LVCMOS w/ Vertical SYNC Input, can be used as parallel data input 15
pull down
PCLK
1
Input, LVCMOS w/
pull down
Pixel Clock Input Pin. Strobe edge set by TRFB configuration.
GENERAL PURPOSE INPUT OUTPUT (GPIO)
DIN[3:0]/
GPIO[5:2]
-
Input/Output, Digital DIN[3:0] general-purpose pins can be individually configured as either inputs
or outputs; used to control and respond to various commands.
GPIO[1:0]
2
Input/Output, Digital General-purpose pins can be individually configured as either inputs or
outputs; used to control and respond to various commands.
SERIAL CONTROL BUS - I2C COMPATIBLE
Clock line for the serial control bus communication
SCL requires an external pull-up resistor to VDDIO.
SCL
1
Input/Output, Digital
SDA
1
Input/Output, Open Data line for the serial control bus communication
SDA requires an external pull-up resistor to VDDIO.
Drain
M/S
CAD
1
1
Input, LVCMOS w/
pull down
I2C Master / Slave select
M/S = L, Master (default)r; device generates and drives the SCL clock line
M/S = H, Slave; device accepts SCL clock input
Input, analog
Continuous Address Decoder
Input pin to select the Slave Device Address.
Input is connect to external resistor divider to programmable Device ID
address (see Serial Control Bus Connection).
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB = H, Transmitter is enabled and is ON.
PDB = L, Transmitter is in Sleep (Power Down). When the transmitter is in
the SLEEP state, the PLL is shutdown, and IDD is minimized.
PDB
1
Input, LVCMOS w/
pull down
RES
1
Input, LVCMOS w/
pull down
Reserved. This pin MUST be tied LOW.
Channel Link III INTERFACE
DOUT+
1
Input/Output, CML
Non-inverting differential output, back-channel input.
DOUT-
1
Input/Output, CML
Inverting differential output, back-channel input.
VDDPLL
1
Power, Analog
PLL Power, 1.8V ±5%
VDDT
1
Power, Analog
Tx Analog Power, 1.8V ±5%
VDDCML
1
Power, Analog
LVDS & BC Dr Power, 1.8V ±5%
VDDD
1
Power, Digital
Digital Power, 1.8V ±5%
VDDIO
1
Power, Digital
Power for input stage, The single-ended inputs are powered from VDDIO.
VSS
-
Ground, DAP
All VSS pads are down bonded to DAP. DAP must be grounded.
Power and Ground
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DS92LX1621 / DS92LX1622
DS92LX1622 Pin Diagram
30123020
Deserializer - DS92LX1622 — Top View
5
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DS92LX1621 / DS92LX1622
DS92LX1622 Deserializer Pin Descriptions
Pin Name
Number of Pins
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
ROUT[13:0]
14
Outputs, LVCMOS
Parallel data outputs.
HSYNC
1
Output, LVCMOS
Horizontal SYNC Output, can be used as parallel data output 14
VSYNC
1
Output, LVCMOS
Vertical SYNC Output, can be used as parallel data output 15
PCLK
1
Output, LVCMOS
Pixel Clock Output Pin.
Strobe edge set by RFB configuration. In SLEEP, outputs are controlled by
the OSS_SEL.
General Purpose Input Output (GPIO)
ROUT[3:0] /
GPIO[5:2]
-
Input/Output, Digital
ROUT[3:0] general-purpose pins can be individually configured as either
inputs or outputs; used to control and respond to various commands.
GPIO[1:0]
2
Input/Output, Digital
General-purpose pins can be individually configured as either inputs or
outputs; used to control and respond to various commands.
SERIAL CONTROL BUS - I2C COMPATIBLE
Clock line for the serial control bus communication
SCL requires an external pull-up resistor to VDDIO.
SCL
1
Input/Output, Digital
SDA
1
Input/Output, Open Data line for serial control bus communication
SDA requires an external pull-up resistor to VDDIO.
Drain
M/S
1
CAD
Input, LVCMOS w/
pull up
1
Input, analog
I2C Master / Slave select
M/S = L, Master; device generates and drives the SCL clock line
M/S = H, Slave (default); device accepts SCL clock input
Continuous Address Decoder
Input pin to select the Slave Device Address.
Input is connect to external resistor divider to programmable Device ID
address (see Serial Control Bus Connection)
CONTROL AND CONFIGURATION
PDB
1
Input, LVCMOS w/
pull down
Power down Mode Input Pin.
PDB = H, Receiver is enabled and is ON.
PDB = L, Receiver is in Sleep (Power down mode). When the Receiver is in
the SLEEP state, the LVCMOS Outputs are in TRI-STATE, the PLL is
shutdown and IDD is minimized.
LOCK Status Output Pin.
LOCK = H, PLL is Locked, outputs are active
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL. May be used as Link Status.
LOCK
1
Output, LVCMOS
RES
3
-
Reserved.
Pin 40: This pin MUST be tied LOW.
Pins 32,33: Leave pin open.
1
Input, LVCMOS w/
pull down
BIST Enable Pin.
BISTEN = H, BIST Mode is enabled.
BISTEN = L, BIST Mode is disabled.
Output, LVCOMS
PASS Output Pin for BIST mode.
PASS = H, ERROR FREE Transmission
PASS = L, one or more errors were detected in the received payload.
Leave Open if unused. Route to test point (pad) recommended.
BIST MODE
BISTEN
PASS
1
Channel Link III INTERFACE
RIN+
1
Input/Output, CML
Noninverting differential input, back channel output.
RIN-
1
Input/Output, CML
Inverting differential input, back channel output.
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6
Number of Pins
I/O, Type
Description
POWER AND GROUND
VDDSSCG
1
Digital Power
SSCG Power, 1.8V ±5%
VDDOR1/2/3
3
Digital Power
TTL Output Buffer Power, The single-ended outputs and control input are
powered from VDDIO. VDDIO can be connected to a 1.8V ±5% or 3.3V ±10%
VDDD
1
Digital Power
Digital Core Power, 1.8V ±5%
VDDR
1
Analog Power
Rx Analog Power, 1.8V ±5%
VDDCML
1
Analog Power
BC Driver Power, 1.8V ±5%
VDDPLL
1
Analog Power
PLL Power, 1.8V ±5%
VSS
-
Ground
All VSS pads are down bonded to DAP. DAP must be grounded.
7
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DS92LX1621 / DS92LX1622
Pin Name
DS92LX1621 / DS92LX1622
Physical Dimensions inches (millimeters) unless otherwise noted
DS92LX1621 Serializer
NS Package Number SQA32A
DS92LX1622 Deserializer
NS Package Number SQA40A
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DS92LX1621 / DS92LX1622
Notes
DS92LX1621 / DS92LX1622 10 - 50 MHz Channel Link III Serializer and Deserializer with
Embedded Bi-Directional Control Channel
Notes
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