ADP3419 Dual Bootstrapped, High Voltage MOSFET Driver with Output Disable The ADP3419 is a dual MOSFET driver optimized for driving two N-channel switching MOSFETs in nonisolated synchronous buck power converters used to power CPUs in portable computers. The driver impedances have been chosen to provide optimum performance in multiphase regulators at up to 25 A per phase. The high-side driver can be bootstrapped relative to the switch node of the buck converter and is designed to accommodate the high voltage slew rate associated with floating high-side gate drivers. The ADP3419 includes an anticross-conduction protection circuit, undervoltage lockout to hold the switches off until the driver has sufficient voltage for proper operation, a crowbar input that turns on the low-side MOSFET independently of the input signal state, and a low-side MOSFET disable pin to provide higher efficiency at light loads. The SD pin shuts off both the high-side and the low-side MOSFETs to prevent rapid output capacitor discharge during system shutdown. The ADP3419 is specified over the extended commercial temperature range of 0°C to 100°C and is available in a 10-lead MSOP package. All-In-One Synchronous Buck Driver One PWM Signal Generates Both Drives Anticross-Conduction Protection Circuitry Output Disable Function Crowbar Control Synchronous Override Control Undervoltage Lockout Pb−Free Package is Available 1 MARKING DIAGRAM 10 P9x RYWG G 1 PIN ASSIGNMENT IN 1 SD APPLICATIONS • • • • MSOP−10 CASE 846AC P9x = Device Code x = A or B R = Assembly Location Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) FEATURES • • • • • • • • http://onsemi.com 2 DRVLSD 3 Mobile Computing CPU Core Power Converters Multiphase Desk-Note CPU Supplies Single-Supply Synchronous Buck Converters Non-Synchronous-to-Synchronous Drive Conversion CROWBAR 4 VCC 5 ADP3419 (Top View) 10 BST 9 DRVH 8 SW 7 GND 6 DRVL ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. © Semiconductor Components Industries, LLC, 2010 April, 2010 − Rev. 3 1 Publication Order Number: ADP3419/D ADP3419 VCC BST 5 10 IN 1 SD 2 DRVLSD 3 CROWBAR 5V 9 UVLO, OVERLAP PROTECTION, SHUTDOWN AND CROWBAR CIRCUITS 8 DRVH 5 FROM CONTROLLER PWM OUTPUT SW FROM SYSTEM ENABLE CONTROL FROM CONTROLLER 4 6 ADP3419 VDC DRVL FROM CONTROLLER CLAMP OUTPUT VCC 1 IN BST 10 ADP3419 DRVH 9 2 SD 3 DRVLSD 4 CROWBAR VOUT SW 8 DRVL 6 GND 7 7 GND Figure 1. Simplified Block Diagram Figure 2. General Application Circuit ABSOLUTE MAXIMUM RATINGS Parameter Rating Unit −0.3 to +7.0 V BST −0.3 to +30 V BST to SW −0.3 to +7.0 V VCC SW −3.0 to +25 V DRVH SW −0.3 to BST +0.3 V DRVL −0.3 to VCC +0.3 V All Other Inputs and Outputs −0.3 to VCC +0.3 qJA 340 220 2-Layer Board 4-Layer Board Operating Ambient Temperature Range V °C/W 0 to 100 °C Junction Temperature Range 0 to 150 °C Storage Temperature Range −65 to +150 °C Lead Temperature Range Soldering (10 s) Vapor Phase (60 s) Infrared (15 s) 300 215 220 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling. http://onsemi.com 2 ADP3419 PIN ASSIGNMENT Pin No. Mnemonic 1 IN Logic Level PWM Input. This pin has primary control of the drive outputs. In normal operation, pulling this pin low turns on the low-side driver; pulling it high turns on the high-side driver. Description 2 SD Shutdown Input. When low, this pin disables normal operation, forcing DRVH and DRVL low. 3 DRVLSD 4 CROWBAR Synchronous Rectifier Shutdown Input. When low, DRVL is forced low; when high, DRVL is enabled and controlled by IN and by the adaptive overlap protection control circuitry. Crowbar Input. When high, DRVL is forced high regardless of the high-side MOSFET switch condition. 5 VCC Input Supply. This pin should be bypassed to GND with a 4.7 mF or larger ceramic capacitor. 6 DRVL Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET. 7 GND Ground. This pin should be closely connected to the source of the lower MOSFET. 8 SW 9 DRVH 10 BST Switch Node Input. This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-on of the lower MOSFET until the voltage is below ~1 V. Buck Drive. Output drive for the upper (buck) MOSFET. Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this bootstrapped voltage for the high-side MOSFET as it is switched. ELECTRICAL CHARACTERISTICS VCC = SD = 5.0 V, BST = 4.0 V to 26 V. TA = 0°C to 100°C, unless otherwise noted All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. Parameter Symbol Conditions Min Typ Max Unit LOGIC INPUTS (IN, SD, DRVLSD, CROWBAR) Input Voltage High VIH Input Voltage Low VIL Input Current DRVLSD Propagation Delay Time IIN tpdl DRVLSD, tpdh DRVLSD 2.0 Inputs = 0 V or 5.0 V V −1.0 0.8 V +1.0 mA CLOAD = 3 nF, Figure 3 20 ns BST − SW = 4.6 V 1.7 3.3 HIGH-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times Propagation Delay Times (Note 1) W BST − SW = 4.6 V 0.8 2.3 W trDRVH tfDRVH BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4 BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4 14 11 35 25 ns tpdhDRVH tpdlDRVH BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4 BST − SW = 4.6 V, CLOAD = 3 nF, Figure 4 32 28 70 60 ns 1.7 3.3 W 15 LOW-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times Propagation Delay Times (Note 2) SW Transition Timeout (Note 1 and 2) Zero-Crossing Threshold 0.8 2.3 W trDRVL tfDRVL CLOAD = 3 nF, Figure 4 CLOAD = 3 nF, Figure 4 13 11 30 25 ns tpdhDRVL tpdlDRVL CLOAD = 3 nF, Figure 4 CLOAD = 3 nF, Figure 4 25 16 48 30 ns 350 600 ns tSWTO BST − SW = 4.6 V 150 VZC 1.0 V SUPPLY Supply Voltage Range Supply Current Normal Mode Shutdown Mode VCC ISYS(NM) ISYS(SD) 4.6 ICC + IBST, IN = 0 V or 5.0 V ICC + IBST, SD = 0 V 6.0 V 0.8 325 1.5 600 mA mA 4.5 V Undervoltage Lockout Threshold VCC rising 3.8 4.25 Undervoltage Lockout Hysteresis (Note 3) VCC falling 50 120 mV 1. For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to the signal going low with transitions measured at 50%. 2. The turn-on of DRVL is initiated after IN goes low by either SW crossing a ~1 V threshold or by expiration of tSWTO. 3. Guaranteed by characterization, not production tested. http://onsemi.com 3 ADP3419 IN 2.0V DRVLSD 0.8V tpdhDRVLSD tpdlDRVLSD DRVL Figure 3. Output Disable Timing Diagram (Timing is Referenced to the 90% and 10% Points Unless Otherwise Noted) IN tpdl DRVL tfDRVL trDRVL tpdl DRVH DRVL tpdhDRVH DRVH−SW tfDRVH trDRVH VTH VTH tpdhDRVL SW tSWTO 1V Figure 4. Non−Overlap Timing Diagram (Timing is Referenced to the 90% and 10% Points Unless Otherwise Noted) http://onsemi.com 4 ADP3419 TYPICAL CHARACTERISTICS Figure 5. DRVH Rise and DRVL Fall Times CH1 = IN, CH2 = DRVH, CH3 = DRVL Figure 6. DRVH Fall and DRVL Rise Times CH1 = IN, CH2 = DRVH, CH3 = DRVL 25 25 VCC = 5V CLOAD = 3nF VCC = 5V CLOAD = 3nF 20 20 15 TIME (ns) TIME (ns) RISE TIME FALLTIME 10 5 0 FALLTIME 10 5 0 25 50 75 100 JUNCTION TEMPERATURE (°C) 0 125 Figure 7. DRVH Rise and Fall Times vs. Temperature 80 0 25 50 75 100 JUNCTION TEMPERATURE (°C) 125 Figure 8. DRVL Rise and Fall Times vs. Temperature 25 VCC = 5V TA = 25°C VCC = 5V TA = 25°C DRVH 20 FALL TIME (ns) 60 RISE TIME (ns) RISE TIME 15 DRVH 40 DRVL 15 10 DRVL 20 0 5 0 2 4 6 8 0 10 LOAD CAPACITANCE (nF) Figure 9. DRVH and DRVL Rise Times vs. Load Capacitance 0 2 4 6 LOAD CAPACITANCE (nF) 8 10 Figure 10. DRVH and DRVL Fall Times vs. Load Capacitance http://onsemi.com 5 ADP3419 TYPICAL CHARACTERISTICS 50 40 VCC = 5V CLOAD = 3nF VCC = 5V CLOAD = 3nF tpdhDRVH tpdlDRVH 30 30 TIME (ns) TIME (ns) 40 tpdhDRVL 20 20 tpdlDRVL 10 10 0 0 0 25 50 75 100 JUNCTION TEMPERATURE (°C) 0 125 Figure 11. DRVH and DRVL tpdh vs. Temperature 125 50 VCC = 5V CLOAD= 3nF T A = 25°C 80 VCC = BST = 5V CLOAD = 3nF TA = 25°C 40 ISYS CURRENT (mA) PEAK INPUT CURRENT (μA) 50 75 100 JUNCTION TEMPERATURE (°C) Figure 12. DRVH and DRVL tpdl vs. Temperature 100 60 40 30 20 10 20 0 25 0 0 1 2 3 INPUT VOLTAGE (V) 4 5 0 Figure 13. IN Pin Input Current vs. Input Voltage ISYS CURRENT (mA) 1.5 200 400 600 800 IN FREQUENCY (kHz) Figure 14. Supply Current vs. Frequency VCC = 5V CLOAD = 3nF 1.0 0.5 0 0 25 1000 50 75 100 JUNCTION TEMPERATURE (°C) Figure 15. Supply Current vs. Temperature http://onsemi.com 6 125 1200 ADP3419 Theory of Operation High-Side Driver The ADP3419 is a dual MOSFET driver optimized for driving two N-channel MOSFETs in a synchronous buck converter topology. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each driver is capable of driving a 3 nF load at speeds up to 1 MHz. A more detailed description of the ADP3419 and its features follows. Refer to the detailed block diagram in Figure 16. The high-side driver is designed to drive a floating low RDS(ON) N-channel MOSFET. The bias voltage for the high-side driver is developed by an external bootstrap supply circuit, which is connected between the BST and SW pins. The bootstrap circuit comprises a diode, D1, and bootstrap capacitor, CBST. When the ADP3419 is starting up, the SW pin is at ground, so the bootstrap capacitor charges up to VCC through D1. Once the supply voltage ramps up and exceeds the UVLO threshold, the driver is enabled. When IN goes high, the high-side driver begins to turn on the high-side MOSFET (Q1) by transferring charge from CBST. As Q1 turns on, the SW pin rises up to VDCIN, forcing the BST pin to VDCIN + VC(BST), which is enough gate-to-source voltage to hold Q1 on. To complete the cycle, Q1 is switched off by pulling the gate down to the voltage at the SW pin. When the low-side MOSFET (Q2) turns on, the SW pin is pulled to ground. This allows the bootstrap capacitor to charge up to VCC again. When the driver is enabled, the driver’s output is in phase with the IN pin. Table 2 shows the relationship between DRVH and the different control inputs of the ADP3419. 5V VDCIN D1 VCC 5 ADP3419 UVLO AND BIAS CROWBAR 4 BST IN 1 10 RBST CBST + DRVH 9 Q1 SD 2 OVERLAP PROTECTION AND TIME−OUT CIRCUIT SW 8 VCC Overlap Protection Circuit DRVL The overlap protection circuit prevents both main power switches, Q1 and Q2, from being on at the same time. This is done to prevent shoot-through currents from flowing through both power switches and the associated losses that can occur during their on-off transitions. The overlap protection circuit accomplishes this by adaptively controlling the delay from Q1’s turn-off to Q2’s turn-on, and the delay from Q2’s turn-off to Q1’s turn-on. To prevent the overlap of the gate drives during Q1’s turn-off and Q2’s turn-on, the overlap circuit monitors the voltage at the SW pin and DRVH pin. When IN goes low, Q1 begins to turn off. The overlap protection circuit waits for the voltage at the SW and DRVH pins to both fall below 1.6 V. Once both of these conditions are met, Q2 begins to turn on. Using this method, the overlap protection circuit ensures that Q1 is off before Q2 turns on, regardless of variations in temperature, supply voltage, gate charge, and drive current. There is, however, a timeout circuit that overrides the waiting period for the SW and DRVH pins to reach 1.6 V. After the timeout period has expired, DRVL is asserted high regardless of the SW and DRVH voltages. In the opposite case, when IN goes high, Q2 begins to turn off after a propagation delay. The overlap protection circuit waits for the voltage at DRVL to fall below 1.6 V, after which DRVH is asserted high and Q1 turns on. 6 Q2 DRVLSD 3 7 GND Figure 16. Detailed Block Diagram of the ADP3419 Undervoltage Lockout The undervoltage lockout (UVLO) circuit holds both MOSFET driver outputs low during VCC supply ramp-up. The UVLO logic becomes active and in control of the driver outputs at a supply voltage of no greater than 1.5 V. The UVLO circuit waits until the VCC supply has reached a voltage high enough to bias logic level MOSFETs fully on before releasing control of the drivers to the control pins. Driver Control Input The driver control input (IN) is connected to the duty ratio modulation signal of a switch-mode controller. IN can be driven by 2.5 V to 5.0 V logic. The output MOSFETs are driven so that the SW node follows the polarity of IN. Low-Side Driver The low-side driver is designed to drive a ground-referenced low RDS(ON) N-channel synchronous rectifier MOSFET. The bias to the low-side driver is internally connected to the VCC supply and GND. Once the supply voltage ramps up and exceeds the UVLO threshold, the driver is enabled. When the driver is enabled, the driver’s output is 180° out of phase with the IN pin. Table 2 shows the relationship between DRVL and the different control inputs of the ADP3419. Low-Side Driver Shutdown The low-side driver shutdown DRVLSD allows a control signal to shut down the synchronous rectifier. Under light load conditions, DRVLSD should be pulled low before the polarity reversal of the inductor current to maximize light load conversion efficiency. DRVLSD can also be pulled low for reverse voltage protection purposes. http://onsemi.com 7 ADP3419 When DRVLSD is low, the low-side driver stays low. When DRVLSD is high, the low-side driver is enabled and controlled by the driver signals, as previously described. 4.7 mF multilayer ceramic (MLC) capacitor. MLC capacitors provide the best combination of low ESR and small size, and can be obtained from the following vendors. Low-Side Driver Timeout Table 2. In normal operation, the DRVH signal tracks the IN signal and turns off the Q1 high-side switch with a few 10 ns delay (tpdlDRVH) following the falling edge of the input signal. When Q1 is turned off, DRVL is allowed to go high, Q2 turns on, and the SW node voltage collapses to zero. But in a fault condition such as a high-side Q1 switch drain-source short circuit, the SW node cannot fall to zero, even when DRVH goes low. The ADP3419 has a timer circuit to address this scenario. Every time the IN goes low, a DRVL on-time delay timer is triggered. If the SW node voltage does not trigger a low-side turn-on, the DRVL on-time delay circuit does it instead, when it times out with tSW(TO) delay. If Q1 is still turned on, that is, its drain is shorted to the source, Q2 turns on and creates a direct short circuit across the VDCIN voltage rail. The crowbar action causes the fuse in the VDCIN current path to open. The opening of the fuse saves the load (CPU) from potential damage that the high-side switch short circuit could have caused. Vendor Part Number Web Address Murata GRM235Y5V106Z16 www.murata.com Taiyo-Yuden EMK325F106ZF www.t-yuden.com Tokin C23Y5V1C106ZP www.tokin.com Keep the ceramic capacitor as close as possible to the ADP3419. Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor (CBST) and a Schottky diode (D1), as shown in Figure 16. Selection of these components can be done after the high-side MOSFET has been chosen. The bootstrap capacitor must have a voltage rating that is able to handle at least 5.0 V more than the maximum supply voltage. The capacitance is determined by: C BST + Q HSGATE DV BST (eq. 1) CROWBAR UVLO SD DRVLSD IN DRVH DRVL where: QHSGATE is the total gate charge of the high-side MOSFET. DVBST is the voltage droop allowed on the high-side MOSFET drive. For example, two IRF7811 MOSFETs in parallel have a total gate charge of about 36 nC. For an allowed droop of 100 mV, the required bootstrap capacitance is 360 nF. A good quality ceramic capacitor should be used, and derating for the significant capacitance drop of MLCs at high temperature must be applied. In this example, selection of 470 nF or even 1 mF would be recommended. A Schottky diode is recommended for the bootstrap diode due to its low forward drop, which maximizes the drive available for the high-side MOSFET. The bootstrap diode must also be able to handle at least 5.0 V more than the maximum battery voltage. The average forward current can be estimated by: L L H H H H L I F(AVG) + Q HSGATE L L H H L L H L L H L H H L where fMAX is the maximum switching frequency of the controller. L L H L L L L Power and Thermal Considerations L L L * * L L L H * * * L L H L * * * L H The major power consumption of the ADP3419-based driver circuit is from the dissipation of MOSFET gate charge. It can be estimated as: H H * * * L H Crowbar Function In addition to the internal low-side drive time-out circuit, the ADP3419 includes a CROWBAR input pin to provide a means for additional overvoltage protection. When CROWBAR goes high, the ADP3419 turns off DRVH and turns on DRVL. The crowbar logic overrides the overlap protection circuit, the shutdown logic, the DRVLSD logic, and the UVLO protection on DRVL. Thus, the crowbar function maximizes the overvoltage protection coverage in the application. The CROWBAR can be either driven by the CLAMP pin of buck controllers, such as the ADP3422, ADP3203, ADP3204, or ADP3205, or controlled by an independent overvoltage monitoring circuit. Table 1. ADP3419 Truth Table P MAX [ VCC (Q HSGATE ) Q LSGATE) f MAX f MAX (eq. 2) (eq. 3) where: VCC is the supply voltage 5.0 V. fMAX is the highest switching frequency. QHSGATE and QLSGATE are the total gate charge of high-side and low-side MOSFETs, respectively. For example, the ADP3419 drives two IRF7821 high-side MOSFETs and two IRF7832 low-side MOSFETs. According * = Don’t Care. Application Information Supply Capacitor Selection For the supply input (VCC) of the ADP3419, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents drawn. Use a 10 mF or http://onsemi.com 8 ADP3419 The total MOSFET drive power dissipates in the output resistance of ADP3419 and in the MOSFET gate resistance as well. η represents the ratio of power dissipation inside the ADP3419 over the total MOSFET gate driving power. For normal applications, a rough estimation for η is 0.7. A more accurate estimation can be calculated using: to the MOSFET data sheets, QHSGATE = 18.6 nC and QLSGATE = 68 nC. Given that fMAX is 300 kHz, PMAX would be about 130 mW. Part of this power consumption generates heat inside the ADP3419. The temperature rise of the ADP3419 against its environment is estimated as: DT [ q JA P MAX h (eq. 4) where θJA is ADP3419’s thermal resistance from junction to air, given in the absolute maximum ratings as 220°C/W for a 4−layer board. h[ Q HSGATE Q HSGATE ) Q LSGATE Q LSGATE ) Q HSGATE ) Q LSGATE ǒ Ǔ 0.5 R1 0.5 R2 ) R1 ) R HSGATE ) R R2 ) R HSGATE ǒ 0.5 R3 ) 0.5 R4 R3 ) R LSGATE R4 ) R LSGATE (eq. 5) Ǔ • It is best to have the low-side MOSFET gate close to where: R1 and R2 are the output resistances of the high-side driver: R1 = 1.7 (DRVH − BST), R2 = 0.8 (DRVH − SW). R3 and R4 are the output resistances of the low-side driver: R3 = 1.7 (DRVL − VCC), R4 = 0.8 (DRVL − GND). R is the external resistor between the BST pin and the BST capacitor. RHSGATE and RLSGATE are gate resistances of high-side and low-side MOSFETs, respectively. Assuming that R = 0 and that RHSGATE = RLSGATE = 0.5, Equation 5 gives a value of η = 0.71. Based on Equation 4, the estimated temperature rise in this example is about 22°C. • PC Board Layout Considerations Use the following general guidelines when designing printed circuit boards. Figure 17 gives an example of the typical land patterns based on the guidelines given here. • The VCC bypass capacitor should be located as close as possible to the VCC and GND pins. Place the ADP3419 and bypass capacitor on the same layer of the board, so that the PCB trace between the ADP3419 VCC pin and the MLC capacitor does not contain any via. An ideal location for the bypass MLC capacitor is near Pin 5 and Pin 6 of the ADP3419. • High frequency switching noise can be coupled into the VCC pin of the ADP3419 via the BST diode. Therefore, do not connect the anode of the BST diode to the VCC pin with a short trace. Use a separate via or trace to connect the anode of the BST diode directly to the VCC 5.0 V power rail. the DRVL pin; otherwise, use a short and very thick PCB trace between the DRVL pin and the low-side MOSFET gate. Fast switching of the high-side MOSFET can reduce switching loss. However, EMI problems can arise due to the severe ringing of the switch node voltage. Depending on the character of the low-side MOSFET, a very fast turn-on of the high-side MOSFET may falsely turn on the low-side MOSFET through the dv/dt coupling of its Miller capacitance. Therefore, when fast turn-on of the high-side MOSFET is not required by the application, a resistor of about 1 W to 2 W can be placed between the BST pin and the BST capacitor to limit the turn-on speed of the high-side MOSFET. D1 RBST CBST TO SWITCH NODE SHORT, THICK TRACE TO THE GATES OF LOW-SIDE MOSFETS CVCC Figure 17. External Component Placement Example ORDERING INFORMATION Branding Package Type Shipping† ADP3419JRM−REEL P9A 10−Lead MSOP 3000 Tape & Reel ADP3419JRMZ−REEL P9B 10−Lead MSOP 3000 Tape & Reel ADP34190091RMZR P9B 10−Lead MSOP 3000 Tape & Reel Device Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *The “Z’’ suffix indicates Pb−Free part. http://onsemi.com 9 ADP3419 PACKAGE DIMENSIONS MSOP10 CASE 846AC−01 ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION “A” DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION “B” DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. 846B−01 OBSOLETE. NEW STANDARD 846B−02 −A− −B− K D 8 PL 0.08 (0.003) PIN 1 ID G 0.038 (0.0015) −T− SEATING PLANE M T B S A S DIM A B C D G H J K L C H L J MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.95 1.10 0.20 0.30 0.50 BSC 0.05 0.15 0.10 0.21 4.75 5.05 0.40 0.70 INCHES MIN MAX 0.114 0.122 0.114 0.122 0.037 0.043 0.008 0.012 0.020 BSC 0.002 0.006 0.004 0.008 0.187 0.199 0.016 0.028 SOLDERING FOOTPRINT* 10X 1.04 0.041 0.32 0.0126 3.20 0.126 8X 10X 4.24 0.167 0.50 0.0196 SCALE 8:1 5.28 0.208 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 10 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative ADP3419/D