Integrated Circuits Inc. aP8942A APLUS MAKE YOUR PRODUCTION A-PLUS VOICE OTP IC aP8942A – 42sec APLUS INTEGRATED CIRCUITS INC. Address: 3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei, Taiwan 115, R.O.C. Sales E-mail: [email protected] (115)台北市南港區成功路一段 32 號 3 樓之 10. TEL: 886-2-2782-9266 Ver 5.0 FAX: 886-2-2782-9255 Support E-mail: WEBSITE : http: //www.aplusinc.com.tw [email protected] 1 OCT 01, 2012 Integrated Circuits Inc. aP8942A FEATURES • • • • Standard CMOS process. Embedded 1M bits EPROM. 42 sec Voice Length at 6KHz sampling and 4-bit ADPCM compression. Maximum 32 voice groups. • • • • Combination of voice blocks to extend playback duration. 960 table entries are available for voice block combinations. User selectable PCM or ADPCM data compression. Two triggering modes are available (EPROM programmable options). - Key Trigger Mode – Combinations of S1 ~ S8 to trigger 32 Voice Groups; SBT sequential trigger is possible. - CPU Parallel Trigger Mode – Combinations of S1 ~ S5 with SBT goes HIGH to strobe start the voice playback. • • Voice Group Trigger Options: Edge / Level; Hold / Un-hold; Retrigger / Non-retrigger. Whole Chip Options: Ramp / No-ramp; Output Options; Key / CPU trigger mode. • • • • 16ms (@ 8KHz sampling rate) Debounce Time for both Key and CPU Trigger Mode. RST pin set to HIGH to stop playback at once. Two user programmable outputs for STOP pulse, BUSY signal and flashing LED. Built-in oscillator to control sampling frequency with an external resistor. • • • • 2.6V – 5.0V; Wide range single power supply and < 5uA low stand-by current. PWM Vout1 and Vout2 drive speaker directly. D/A COUT to drive speaker through an external BJT. Development System support voice compilation and options selection. DESCRIPTION aP8942A high performance Voice OTP is fabricated with Standard CMOS process with embedded 1M bits EPROM. It can store up to 42sec voice message with 4-bit ADPCM compression at 6KHz sampling rate. 8-bit PCM is also available as user selectable option. Two trigger modes, simple Key trigger mode and Parallel CPU trigger mode facilitate different user interface. User selectable triggering and output signal options provide maximum flexibility to various applications. Built-in resistor controlled oscillator, 8-bit current mode D/A output and PWM direct speaker driving output minimize the number of external components. PC controlled programmer and developing software are available. Ver 5.0 2 OCT 01, 2012 Integrated Circuits Inc. aP8942A PIN CONFIGURATIONS S8 1 20 S7 OUT1 2 19 RST VOUT1 3 18 SBT VOUT2 4 17 S4 VSS 5 16 S3 OUT2 6 15 VDD V33 7 14 S2 COUT 8 13 S1 OSC 9 12 VPP 10 11 S6 S5 DIP / SOP PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Ver 5.0 Playback Mode S8 OUT1 VOUT1 VOUT2 VSS OUT2 V33 COUT OSC S5 S6 VPP S1 S2 VDD S3 S4 SBT RST S7 OTP Program Mode OEB VSS IO V33 ACLK S5 S6 VPP S1 S2 VDD S3 S4 PGM DCLK S7 300 MIL Description Trigger pin (input with internal pull-down) Programmable output (I/O pin) PWM output to drive speaker directly PWM output to drive speaker directly Power Ground Programmable output (I/O pin) Power Supply for OTP programming D/A current output Oscillator input Trigger pin (input with internal pull-down) Trigger pin (input with internal pull-down) Supply voltage for OTP programming Trigger pin (input with internal pull-down) Trigger pin (input with internal pull-down) Positive Power Supply Trigger (input with internal pull-down) Trigger (input with internal pull-down) Trigger pin (input with internal pull-down) Reset pin (input with internal pull-down) Trigger pin (input with internal pull-down) 3 OCT 01, 2012 Integrated Circuits Inc. aP8942A PIN DESCRIPTIONS S1 ~ S8 Input Trigger Pins: - S1 to S8 are used to trigger the 32 Voice Groups in Key Mode. - S1 to S5 together with SBT are used to trigger the 32 Voice Groups in CPU Parallel Mode. - In OTP Programming Mode, S1 to S7 are used as program enable pins. SBT Input Trigger Pin: - In Key Trigger Mode, this pin is trigger pin to trigger the playback of Voice Groups one by one sequentially. - In CPU Parallel Command Mode, this pin is used as address strobe to latch the input from S1 to S5 and starts the voice playback. - In OTP Programming Mode, this pin is used as PGM signal. VDD and V33 Power Supply Pin for normal and programming operation VSS Power Ground Pin VOUT1 and VOUT2 Digital PWM output pins which can drive speaker and buzzer directly for voice playback. OSC During voice playback, an external resistor is connected between this pin and the VDD pin to set the sampling frequency. In OTP Programming Mode, this is the ACLK input signal. VPP No connection during voice playback. In OTP Programming Mode, this pin is connected to a separate 6.5V power supply. OUT1 and OUT2 - In Key Trigger Mode and CPU Parallel Command Mode, these pins are user programmable pins for the STOP pulse, BUSY and LED signals. - During OTP programming, OUT1 serves as OEB while OUT2 serves as data IO. COUT Analog 8-bit current mode D/A output for voice playback RST Chip reset in playback mode or DCLK pin in OTP programming mode. Ver 5.0 4 OCT 01, 2012 Integrated Circuits Inc. aP8942A VOICE SECTION COMBINATIONS Voice files created by the PC base developing system are stored in the built-in EPROM of the aP8942A chip as a number of fixed length Voice Blocks. Voice Blocks are then selected and grouped into Voice Groups for playback. Up to 32 Voice Groups are allowed. A Voice Block Table is used to store the information of combinations of Voice Blocks and then group them together to form Voice Group. Chip aP8942A Memory size 1M bits Max no. of Voice Block 252 No. of bytes per Voice Block 512 Max. no. of Voice Group 32 No. of Voice Table entries 960 Voice Length (@ 6KHz 4-bit ADPCM) 42 sec Example of Voice Block Combination Assume here we have three voice files, they are “How are You?”, Sound Effect and Music. Each of the voice file is divided into a number of fixed length Voice Block and stored into the memory. Voice File 1 - “How are You?” is stored in Voice Block B0 to B12. Voice File 2 - Sound Effect is stored in Voice Block B13 to B15. Voice File 3 - Music is Voice Block B16 to B40. Voice Blocks are grouped together using Voice Table to form Voice Group for playback: Group no. Voice Group contents Voice Table Entries Group 1 “How are You?” B0 … B12 Group 2 Sound Effect + “How are You?” B13 … B15 + B0 … B12 Group 3 “How are You?” + Music B0 … B12 + B16 … B40 Group 4 Music B16 … B40 Voice Data Compression Voice File data is stored in the on-chip EPROM as either 4-bit ADPCM or 8-bit PCM format. Voice data stored as 4-bit ADPCM provides 2:1 data compression which can save 50% of memory space. On the other hand, voice data are stored as 8-bit PCM format means no data compression is employed but voice playback quality will be better. Ver 5.0 5 OCT 01, 2012 Integrated Circuits Inc. aP8942A Programmable Options In both Key Trigger Mode and CPU Parallel Trigger Mode, user can select different trigger functions and output signals to be sent out from the pins OUT1 and OUT2. Options affect all Voice Group playback are called Whole Chip Options. Options only affect the playback of individual Voice Group are called Group Options. Whole Chip Options • • Key or CPU Parallel Trigger Mode. Ramp-up-down enable or disable: When COUT is used for playback, Ramp-up-down should be enabled. This function eliminates the ‘POP’ noise at the beginning and end of voice playback. When VOUT1 and VOUT2 are used to drive speaker directly, Ramp-up-down should be disabled. Fig. 1 Ramp-up-down Enable • Fig.2 Ramp-up-down Disable Output Options: This option sets up the three output pins OUT1 and OUT2 to send out different signals during voice playback. Four settings are allowed: OUT1 OUT2 Option 1 LED2 LED1 Option 2 STOP LED1 Option 3 LED1 BUSY Note: Stop plus must be set to enable in order to have STOP plus to come out. Fig. 3 Ver 5.0 Output waveforms 6 OCT 01, 2012 Integrated Circuits Inc. aP8942A Group Options User selectable options that affect each individual group are called Group Options. • • • • They are: Edge or Level trigger Unholdable or Holdable trigger Re-triggerable or non-retriggerable Stop pulse disable or enable Fig. 4 to Fig. 9 show the voice playback with different combination of triggering mode and the relationship between outputs and voice playback. Fig. 4 Level, Unholdable, Non-retriggerable Fig. 5 Fig. 6 Ver 5.0 Level Holdable SBT sequential trigger with Level Holdable and Unholdable 7 OCT 01, 2012 Integrated Circuits Inc. aP8942A Fig. 7 Edge, Unholdable, Non-retrigger Fig. 8 Fig. 9 Ver 5.0 Edge, Holdable SBT sequential trigger with Edge Holdable and Unholdable 8 OCT 01, 2012 Integrated Circuits Inc. aP8942A Overlap trigger is supported with Level/Unholdable trigger options: Fig. 10 Ver 5.0 Overlap trigger 9 OCT 01, 2012 Integrated Circuits Inc. aP8942A TRIGGER MODES There are two triggering modes available with aP8942A. Key or CPU Trigger modes are determined by setting the EPORM programmable options during voice data compilation. Key Trigger Mode With this trigger mode, up to 32 Voice Groups are triggered by setting S1 to S8 to HIGH or NC (not connected) in different combinations. Each Voice Group can have its only independent trigger options (See Fig. 4, 5, 7 and 8 for trigger options definition). Voice Groups can also be triggered sequentially by setting SBT pin to HIGH. CPU Parallel Trigger Mode In this mode, S1 to S5 are set to HIGH or LOW according to the table above and followed by setting the SBT input pin to HIGH, the corresponding Voice Group will be triggered. Trigger options defined in Fig. 4, 5, 7 and 8 are valid for this mode. Fig. 11 CPU Parallel Trigger Mode Note that SBT pin cannot be used as Single Button Sequential trigger in this mode. acts as a Strobe input to clock-in the data input from S1 to S5 into the chip. Ver 5.0 10 In stead, it OCT 01, 2012 Integrated Circuits Inc. aP8942A Key Trigger Mode Up to 32 Voice Groups can be triggered by S1 to S8. Voice Group S1 S2 S3 S4 S5 S6 S7 S8 1 2 HIGH NC NC HIGH NC NC NC NC NC NC NC NC NC NC NC NC 3 4 5 6 NC NC NC NC NC NC NC NC HIGH NC NC NC NC HIGH NC NC NC NC HIGH NC NC NC NC HIGH NC NC NC NC NC NC NC NC 7 8 9 10 11 12 13 NC NC HIGH NC NC NC NC NC NC HIGH HIGH NC NC NC NC NC NC HIGH HIGH NC NC NC NC NC NC HIGH HIGH NC NC NC NC NC NC HIGH HIGH NC NC NC NC NC NC HIGH HIGH NC NC NC NC NC NC NC HIGH NC NC NC NC NC 14 15 16 17 NC NC HIGH HIGH NC NC NC HIGH NC NC NC HIGH NC NC NC NC NC NC NC NC HIGH NC NC NC HIGH HIGH NC NC NC HIGH HIGH NC 18 19 20 21 NC NC NC NC HIGH NC NC NC HIGH HIGH NC NC HIGH HIGH HIGH NC NC HIGH HIGH HIGH NC NC HIGH HIGH NC NC NC HIGH NC NC NC NC 22 23 24 25 26 NC HIGH HIGH HIGH NC NC NC HIGH HIGH HIGH NC NC NC HIGH HIGH NC NC NC HIGH HIGH NC NC NC NC HIGH HIGH NC NC NC NC HIGH HIGH NC NC NC HIGH HIGH HIGH NC NC 27 28 29 NC NC NC NC NC NC HIGH NC NC HIGH HIGH NC HIGH HIGH HIGH HIGH HIGH HIGH NC HIGH HIGH NC NC HIGH 30 31 32 HIGH HIGH HIGH NC HIGH HIGH NC NC HIGH NC NC NC NC NC NC HIGH NC NC HIGH HIGH NC HIGH HIGH HIGH Ver 5.0 11 OCT 01, 2012 Integrated Circuits Inc. aP8942A CPU Trigger Mode Up to 32 Voice Groups can be triggered by supplying address to [S5:S1] with SBT as strobe signal. Voice Group S8 S7 S6 S5 S4 S3 S2 S1 1 NC NC NC 0 0 0 0 0 2 NC NC NC 0 0 0 0 1 3 NC NC NC 0 0 0 1 0 4 NC NC NC 0 0 0 1 1 5 NC NC NC 0 0 1 0 0 6 NC NC NC 0 0 1 0 1 7 NC NC NC 0 0 1 1 0 8 NC NC NC 0 0 1 1 1 9 NC NC NC 0 1 0 0 0 10 NC NC NC 0 1 0 0 1 11 NC NC NC 0 1 0 1 0 12 NC NC NC 0 1 0 1 1 13 NC NC NC 0 1 1 0 0 14 NC NC NC 0 1 1 0 1 15 NC NC NC 0 1 1 1 0 16 NC NC NC 0 1 1 1 1 17 NC NC NC 1 0 0 0 0 18 NC NC NC 1 0 0 0 1 19 NC NC NC 1 0 0 1 0 20 NC NC NC 1 0 0 1 1 21 NC NC NC 1 0 1 0 0 22 NC NC NC 1 0 1 0 1 23 NC NC NC 1 0 1 1 0 24 NC NC NC 1 0 1 1 1 25 NC NC NC 1 1 0 0 0 26 NC NC NC 1 1 0 0 1 27 NC NC NC 1 1 0 1 0 28 NC NC NC 1 1 0 1 1 29 NC NC NC 1 1 1 0 0 30 NC NC NC 1 1 1 0 1 31 NC NC NC 1 1 1 1 0 32 NC NC NC 1 1 1 1 1 Ver 5.0 12 OCT 01, 2012 Integrated Circuits Inc. aP8942A BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol VDD - VSS Rating -0.5 Unit ~ +6 V VIN VSS - 0.3<VIN<VDD/33 + 0.3 V VOUT VSS <VOUT<VDD/33 V T (Operating): -40 ~ +85 ℃ T (Junction) -40 ~ +125 ℃ T (Storage) -55 ~ +125 ℃ Ver 5.0 13 OCT 01, 2012 Integrated Circuits Inc. aP8942A DC CHARACTERISTICS ( TA = 0 to 70℃, VDD = 4.5V, VSS = 0V ) Symbol Parameter Min. Typ. Max. Unit Condition VDD Operating Voltage 2.6 4.5 5.0 V ISB Standby current 1 5 µA I/O open IOP Operating current 15 mA I/O open VIH "H" Input Voltage 2.5 3.0 3.5 V VDD=3.0V VIL "L" Input Voltage -0.3 0 0.5 V VDD=3.0V IOL VOUT low O/P Current 110 mA Vout=0.3V, VDD=5.0V IOH VOUT high O/P Current -110 mA Vout=2.5V, VDD=5.0V ICO COUT O/P Current -3 mA VCOUT=1.0V IOH O/P high Current -8 mA VOH=2.5V, VDD=5.0V IOL O/P low Current 8 mA VOL=0.3V, VDD=5.0V ∆F/F Frequency Stability -5 +5 % Fosc(5.0V) – Fosc(4.0V) Fosc(4.5V) Ver 5.0 14 OCT 01, 2012 Integrated Circuits Inc. aP8942A AC CHARACTERISTICS ( TA = 0 to 70℃ ℃, VDD = 4.5V, VSS = 0V, 8KHz sampling ) KEY Trigger Mode S1~S8, SBT COUT tKDD tKD tDN tUP tSTPD tSTPW STOP BUSY tBD tBH CPU Parallel Mode Addr. S1~S5 tASH SBT Ver 5.0 tASH tSBTW 15 OCT 01, 2012 Integrated Circuits Inc. Symbol Parameter tKD aP8942A Min. Typ. Max. Unit Note Key trigger debounce time 16 ms 1 tKD Key trigger debounce time – retrigger 24 ms 1 tUP Ramp up time 0 128/Fs −− s 3 tDN Ramp down time 0 −− 256/Fs s 3 tKDD Key trigger delay after ramp down −− 0 −− ms tSTPD STOP pulse output delay time 256 µs tSTPW STOP pulse width 64 ms tBD BUSY signal output delay time 100 ns tBH BUSY signal output hold time 100 ns tASH Address set-up / hold time 100 ns tSBTW SBT stroke pulse width 65 µs 1 tLEDC LED flash frequency 3 Hz 2 1 Notes : 1. This parameter is inversely proportional to the sampling frequency. 2. This parameter is proportional to the sampling frequency. 3. Fs is sampling frequency in Hz Ver 5.0 16 OCT 01, 2012 Integrated Circuits Inc. aP8942A OSCILLATOR RESISTANCE TABLE Sampling Frequency ROSC KΩ Ω Sampling Frequency KHz ROSC KΩ Ω 22 83 400 5.4 18 108 370 5.9 16 125 350 6.3 15 134 330 6.5 13 158 300 7.0 12 168 280 7.6 11 183 250 8.5 10 202 220 9.5 9 227 200 10.3 8 252 170 11.9 7 296 150 13.8 6 344 120 16.5 100 19.3 91 20.5 82 22.4 KHz Note: The data in the above tables are within 3% accuracy and measured at VDD = 4.5V. Oscillator frequency is subjected to IC lot to lot variation. FREQUENCY AGAINST VDD STABILITY aP8 9 2 1 A Freq en cy St ab i l i t y (R o sc = 2 9 3 K Oh m) 10.0% 5.0% △F (%) 0.0% -5.0% -10.0% -15.0% -20.0% -25.0% -30.0% 5.50 5.00 4.50 4.00 3.50 3.00 2.60 VDD (V) Ver 5.0 17 OCT 01, 2012 Integrated Circuits Inc. aP8942A TYPICAL APPLICATIONS Fig. 12 Using 4.5V Battery Note 1: Two capacitors Cin and Cout must be connected from VDD and V33 pins to VSS to stabilize the power supply to the chip. When small capacity battery, e.g. AG10, is used, Cin and Cout may need to be as large as 22uF. However, if Cin and Cout is too large, the power-up reset generated by 0.1uF at the RST pin may not be function because it takes longer time for both Cin and Cout to discharge. Note 2: 16 Ohm speaker will provide lauder and better sound quality when the VOUT speaker direct drive is used. Note 3: The value of the 390 Ohm base resistor should be modified according to different Vdd value, the kind of speaker and NPN transistor. Note 4: The VPP pin should be leave unconnected for playback. Ver 5.0 18 OCT 01, 2012 Integrated Circuits Inc. aP8942A BONDING PADS aP8942A Fig. 12 Pad Locations Notes: 1. VPP pad should be not connected during voice playback. 2. Substrate should be connected to the Power GND. Ver 5.0 19 OCT 01, 2012