Integrated Circuits Inc. aP89042 FEATURES l l l l l l l l l l l l l l l l l l Standard CMOS process. Embedded 1M EPROM. 42 Sec Voice Length at 6 KHz sampling and 4-bit ADPCM compression. Maximum 32 Voice Groups Combination of voice building blocks to extend playback duration. 960 table entries are available for voice block combinations. User selectable PCM or ADPCM data compress. Two triggering modes are available by whole chip option during voice compilation. - Key Trigger Mode – Combinations of S1 ~ S8 to trigger up to 32 voice groups; SBT for sequential trigger of the beginning 16 voice groups.. - CPU Parallel Trigger Mode – Combinations of S1 ~S5 with SBT goes HIGH to strobe start the voice playback. Voice Group Trigger Options: Edge / Level; Hold / Un-hold; Retrigger / Non-retrigger. Whole Chip Options: Ramp / No-ramp; Output Options; Key / CPU trigger mode. 16ms (@ 8KHz sampling rate) Debounce Time for both Key CPU Trigger Mode. RST pin set to HIHG to stop playback at once. Three user programmable outputs for STOP plus, BUSY signal and flashing LED. Built-in oscillator to control sampling frequency with an external resistor. 2.2V – 3.6V single power supply and < 5uA low stand-by current. PWM Vout1 and Vout2 drive speaker directly. D/A COUT to drive speaker through an external BJT. Development System support voice compilation and options selection. DESCRIPTION aP89042 high performance Voice OTP is fabricated with Standard CMOS process with embedded 1M bits EPROM. It can store up to 42 sec voice messages with 4-bit ADPCM compression at 6KHz sampling rate. 8-bit PCM is also available as user selectable option. Two trigger modes, simple Key trigger mode and Parallel CPU trigger mode facilitate different user interface. User selectable triggering and output signal options provide maximum flexibility to various applications. Built-in resistor controlled oscillator, 8-bit current mode D/A output and PWM direct speaker driving output minimize the number of external components. PC controlled programmer and developing software are available. Ver 2.3 2 May 15, 2006 Integrated Circuits Inc. aP89042 PIN CONFIGURATIONS S8 1 20 S7 OUT1 2 19 RST VOUT1 3 18 SBT VOUT2 4 17 S4 VSS 5 16 S3 OUT2 6 15 VDD OUT3 7 14 S2 COUT 8 13 S1 OSC 9 12 VPP 10 11 S6 S5 DIP / SOP 300 MIL PIN NAMES PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Ver 2.3 Playback Mode S8 OUT1 VOUT1 VOUT2 VSS OUT2 OUT3 COUT OSC S5 S6 VPP S1 S2 VDD S3 S4 SBT RST S7 OTP Program Mode OEB VSS IO ACLK S5 S6 VPP S1 S2 VDD S3 S4 PGM DCLK S7 Description Trigger pin (input with internal pull-down) Programmable output (I/O pin) PWM output to drive speaker directly PWM output to drive speaker directly Power Ground Programmable output (I/O pin) Programmable output (I/O pin) D/A current output Oscillator input Trigger pin (input with internal pull-down) Trigger pin (input with internal pull-down) Supply voltage for OTP programming Trigger pin (input with internal pull-down) Trigger pin (input with internal pull-down) Positive Power Supply Trigger (input with internal pull-down) Trigger (input with internal pull-down) Trigger pin (input with internal pull-down) Reset pin (input with internal pull-down) Trigger pin (input with internal pull-down) 3 May 15, 2006 Integrated Circuits Inc. aP89042 PIN DESCRIPTIONS S1 ~ S8 Input Trigger Pins: - S1 to S8 is used to trigger the 32 Voice Groups in both Key and CPU Parallel Trigger Mode. - In OTP Programming Mode, S1 to S7 are used as program enable pins. SBT Input Trigger Pin: - In Key Trigger Mode, this pin is trigger pin to trigger the playback of Voice Groups one by one sequentially. - In CPU Parallel Command Mode, this pin is used as address strobe to latch the input from S1 to S5 and starts the voice playback. - In OTP Programming Mode, this pin is used as PGM signal. VDD Power Supply Pin. VSS Power Ground Pin VOUT1 and VOUT2 Digital PWM output pins which can drive speaker and buzzer directly for voice playback. OSC During voice playback, an external resistor is connected between this pin and the VDD pin to set the sampling frequency. In OTP Programming Mode, this is the ACLK input signal. VPP Connection to VDD is required during voice playback. In OTP Programming Mode, this pin is connected to a separate 6.5V power supply. OUT1, OUT2 and OUT3 - In Key Trigger Mode and CPU Parallel Command Mode, these pins are user programmable pins for the STOP pulse, BUSY and LED signals. - During OTP programming, OUT1 serves as OEB while OUT2 serves as data IO. COUT Analog 8-bit current mode D/A output for voice playback RST Chip reset in playback mode or DCLK pin in OTP programming mode. Ver 2.3 4 May 15, 2006 Integrated Circuits Inc. aP89042 VOICE SECTION COMBINATIONS Voice files created by the PC base developing system are stored in the built-in EPROM of the aP89042 chip as a number of fixed length Voice Blocks. Voice Blocks are then selected and grouped into Voice Groups for playback. Up to 32 Voice Groups are allowed. A Voice Block Table is used to store the information of combinations of Voice Blocks and then group them together to form Voice Group. Chip aP89042 Memory size 1M bits Max no. of Voice Block 252 No. of bytes per Voice Block 512 Max. no. of Voice Group 32 No. of Voice Table entries 960 Voice Length (@ 6KHz 4-bit ADPCM) 42 sec Example of Voice Block Combination Assume here we have three voice files, they are “How are You?”, Sound Effect and Music. Each of the voice file is divided into a number of fixed length Voice Block and stored into the memory. Voice File 1 - “How are You?” is stored in Voice Block B0 to B12. Voice File 2 - Sound Effect is stored in Voice Block B13 to B15. Voice File 3 - Music is Voice Block B16 to B40. Voice Blocks are grouped together using Voice Table to form Voice Group for playback: Group no. Voice Group contents Voice Table Entries Group 1 “How are You?” B0 … B12 Group 2 Sound Effect + “How are You?” B13 … B15 + B0 … B12 Group 3 “How are You?” + Music B0 … B12 + B16 … B40 Group 4 Music B16 … B40 Voice Data Compression Voice File data is stored in the on-chip EPROM as either 4-bit ADPCM or 8-bit PCM format. Voice data stored as 4-bit ADPCM provides 2:1 data compression which can save 50% of memory space. On the other hand, voice data are stored as 8-bit PCM format means no data compression is employed but voice playback quality will be better. Ver 2.3 5 May 15, 2006 Integrated Circuits Inc. aP89042 Programmable Options In both Key Trigger Mode and CPU Parallel Trigger Mode, user can select different trigger functions and output signals to be sent out from the pins OUT1, OUT2 and OUT3. Options affect all Voice Group playback are called Whole Chip Options. Options only affect the playback of individual Voice Group are called Group Options. Whole Chip Options • Key or CPU Parallel Trigger Mode. • Ramp-up-down enable or disable: When COUT is used for playback, Ramp-up-down should be enabled. This function eliminates the ‘POP’ noise at the beginning and end of voice playback. When VOUT1 and VOUT2 are used to drive speaker directly, Ramp-up-down should be disabled. Fig. 1 Ramp-up-down Enable • Fig.2 Ramp-up-down Disable Output Options: This option sets up the three output pins OUT1 and OUT2 to send out different signals during voice playback. Four settings are allowed: OUT1 OUT2 OUT3 Option 1 LED2 LED1 BUSY Option 2 STOP LED1 LED2 Option 3 LED1 BUSY STOP Option 4 LED1 BUSY /BUSY Note: Stop plus and BUSY must be set to enable in order to have STOP plus and BUSY high to come out. Fig. 3 Output waveforms Ver 2.3 6 May 15, 2006 Integrated Circuits Inc. aP89042 Group Options User selectable options that affect each individual group are called Group Options. They are: • Edge or Level trigger • Unholdable or Holdable trigger • Re-triggerable or non-retriggerable • Stop pulse disable or enable Fig. 4 to Fig. 9 show the voice playback with different combination of triggering mode and the relationship between outputs and voice playback. Fig. 4 Level, Unholdable, Non-retriggerable Fig. 5 Level Holdable Fig. 6 SBT sequential trigger with Level Holdable and Unholdable Ver 2.3 7 May 15, 2006 Integrated Circuits Inc. aP89042 Fig. 7 Edge, Unholdable, Non-retrigger Fig. 8 Edge, Holdable Fig. 9 SBT sequential trigger with Edge Holdable and Unholdable Ver 2.3 8 May 15, 2006 Integrated Circuits Inc. aP89042 Overlap trigger is supported with Level/Unholdable trigger options: Fig. 10 Overlap trigger Ver 2.3 9 May 15, 2006 Integrated Circuits Inc. aP89042 TRIGGER MODES There are two triggering modes available with aP89042. Key or CPU Trigger modes are determined by setting the EPORM programmable options during voice data compilation. Key Trigger Mode With this trigger mode, up to 32 Voice Groups are triggered by setting S1 to S8 to HIGH or NC (not connected) in different combinations. Each Voice Group can have its only independent trigger options (See Fig. 4, 5, 7 and 8 for trigger options definition). Voice Groups can also be triggered sequentially by setting SBT pin to HIGH. CPU Parallel Trigger Mode In this mode, S1 to S5 are set to HIGH or LOW according to the table above and followed by setting the SBT input pin to HIGH, the corresponding Voice Group will be triggered. Trigger options defined in Fig. 4, 5, 7 and 8 are valid for this mode. Fig. 11 CPU Parallel Trigger Mode Note that SBT pin cannot be used as Single Button Sequential trigger in this mode. In stead, it acts as a Strobe input to clock-in the data input from S1 to S5 into the chip. Ver 2.3 10 May 15, 2006 Integrated Circuits Inc. aP89042 Key Trigger Mode Up to 32 Voice Groups can be triggered by S1 to S8. Voice Group 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Ver 2.3 S1 HIGH NC NC NC NC NC NC NC HIGH NC NC NC NC NC NC HIGH HIGH NC NC NC NC NC HIGH HIGH HIGH NC NC NC NC HIGH HIGH HIGH S2 NC HIGH NC NC NC NC NC NC HIGH HIGH NC NC NC NC NC NC HIGH HIGH NC NC NC NC NC HIGH HIGH HIGH NC NC NC NC HIGH HIGH S3 NC NC HIGH NC NC NC NC NC NC HIGH HIGH NC NC NC NC NC HIGH HIGH HIGH NC NC NC NC NC HIGH HIGH HIGH NC NC NC NC HIGH S4 NC NC NC HIGH NC NC NC NC NC NC HIGH HIGH NC NC NC NC NC HIGH HIGH HIGH NC NC NC NC HIGH HIGH HIGH HIGH NC NC NC NC 11 S5 NC NC NC NC HIGH NC NC NC NC NC NC HIGH HIGH NC NC NC NC NC HIGH HIGH HIGH NC NC NC NC HIGH HIGH HIGH HIGH NC NC NC S6 NC NC NC NC NC HIGH NC NC NC NC NC NC HIGH HIGH NC NC NC NC NC HIGH HIGH HIGH NC NC NC NC HIGH HIGH HIGH HIGH NC NC S7 NC NC NC NC NC NC HIGH NC NC NC NC NC NC HIGH HIGH NC NC NC NC NC HIGH HIGH HIGH NC NC NC NC HIGH HIGH HIGH HIGH NC S8 NC NC NC NC NC NC NC HIGH NC NC NC NC NC NC HIGH HIGH NC NC NC NC NC HIGH HIGH HIGH NC NC NC NC HIGH HIGH HIGH HIGH May 15, 2006 Integrated Circuits Inc. aP89042 CPU Trigger Mode Up to 32 Voice Groups can be triggered by supplying address to [S5:S1] with SBT as strobe signal. Voice Group 1 S8 NC S7 NC S6 NC S5 0 S4 0 S3 0 S2 0 S1 0 2 NC NC NC 0 0 0 0 1 3 NC NC NC 0 0 0 1 0 4 NC NC NC 0 0 0 1 1 5 NC NC NC 0 0 1 0 0 6 NC NC NC 0 0 1 0 1 7 NC NC NC 0 0 1 1 0 8 NC NC NC 0 0 1 1 1 9 NC NC NC 0 1 0 0 0 10 NC NC NC 0 1 0 0 1 11 NC NC NC 0 1 0 1 0 12 NC NC NC 0 1 0 1 1 13 NC NC NC 0 1 1 0 0 14 NC NC NC 0 1 1 0 1 15 NC NC NC 0 1 1 1 0 16 NC NC NC 0 1 1 1 1 17 NC NC NC 1 0 0 0 0 18 NC NC NC 1 0 0 0 1 19 NC NC NC 1 0 0 1 0 20 NC NC NC 1 0 0 1 1 21 NC NC NC 1 0 1 0 0 22 NC NC NC 1 0 1 0 1 23 NC NC NC 1 0 1 1 0 24 NC NC NC 1 0 1 1 1 25 NC NC NC 1 1 0 0 0 26 NC NC NC 1 1 0 0 1 27 NC NC NC 1 1 0 1 0 28 NC NC NC 1 1 0 1 1 29 NC NC NC 1 1 1 0 0 30 NC NC NC 1 1 1 0 1 31 NC NC NC 1 1 1 1 0 32 NC NC NC 1 1 1 1 1 Ver 2.3 12 May 15, 2006 Integrated Circuits Inc. aP89042 BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol Rating Unit VDD - VSS -0.5 ~ +4.5 V VIN VSS - 0.3<VIN<VDD + 0.3 V VOUT VSS <VOUT<VDD V T (Operating): DIP -10 ~ +70 SOP -40 ~ +85 T (Junction) -40 ~ +125 ℃ T (Storage) -55 ~ +125 ℃ ℃ Ver 2.3 13 May 15, 2006 Integrated Circuits Inc. aP89042 DC CHARACTERISTICS ( TA = 0 to 70℃, VDD = 3.3V, VSS = 0V ) Symbol Parameter Min. Typ. Max. Unit Condition VDD Operating Voltage 2.2 3.0 3.6 V ISB Standby current 1 5 μA I/O open IOP Operating current 15 mA I/O open VIH "H" Input Voltage 2.5 3.0 3.5 V VDD=3.0V VIL "L" Input Voltage -0.3 0 0.5 V VDD=3.0V IOL VOUT low O/P Current 120 mA Vout=0.3V, VDD=3.0V IOH VOUT high O/P Current -120 mA Vout=2.5V, VDD=3.0V ICO COUT O/P Current -3 mA VCOUT=1.0V, VDD=3.0V IOH O/P high Current -8 mA VOH=2.5V, VDD=3.0V IOL O/P low Current 8 mA VOL=0.3V, VDD=3.0V ∆F/F Ver 2.3 Frequency Stability -5 +5 14 % Fosc(2.7V) - Fosc(3.4V) Fosc(3V) May 15, 2006 Integrated Circuits Inc. aP89042 TIMING WAVEFORMS KEY Trigger Mode tKD S1~S8, SBT tSTPD COUT STOP tSTPW BUSY tBH tBD CPU Parallel Mode Addr. S1~S5 SBT tSBTW AC CHARACTERISTICS Symbol Parameter tKD tAH tAS ( TA = 0 to 70℃, VDD = 3.3V, VSS = 0V, 8KHz sampling ) Min. Typ. Max. Unit Note Key trigger debounce time 16 ms 1 tKD Key trigger debounce time – retrigger 24 ms 1 tSTPD STOP pulse output delay time 256 μs tSTPW STOP pulse width 64 ms tBD BUSY signal output delay time 100 ns tBH BUSY signal output hold time 100 ns tAS Address set-up time 100 ns tAH Address hold time 100 ns tSBTW SBT stroke pulse width 16 ms 1 tLEDC LED flash frequency 3 Hz 2 1 Notes : 1. This parameter is inversely proportional to the sampling frequency. 2. This parameter is proportional to the sampling frequency. Ver 2.3 15 May 15, 2006 Integrated Circuits Inc. aP89042 OSCILLATOR RESISTANCE TABLE Sampling Frequency KHz 4.90 5.26 5.88 6.09 6.33 6.67 6.85 7.14 7.46 7.70 8.06 8.47 8.93 9.26 9.80 10.42 ROSC KOhm ROSC KOhm 140 130 120 110 100 91 82 75 68 62 56 51 43 300 290 280 270 260 250 240 230 220 210 200 190 180 170 160 150 Sampling Frequency KHz 11.00 11.76 12.50 13.33 14.51 15.63 16.95 18.18 19.23 20.83 22.22 23.81 25.00 Note: The data in the above tables are within 3% accuracy and measured at VDD = 3.0V. Oscillator frequency is subjected to IC lot to lot variation. Ver 2.3 16 May 15, 2006 Integrated Circuits Inc. aP89042 TYPICAL APPLICATIONS Key Trigger Mode 0.1uF 0.01uF 8Ω Speaker VDD,VPP RST ROSC 390Ω S1 S2 S3 • • 3.3V • • • 8050D COUT OSC VOUT1 VOUT2 • S8 SBT 8 / 16Ω Speaker OUT1 VSS Fig. 12 Using 3.3V Battery HT7335 10uF 0.01uF 8Ω Speaker VDD,VPP ROSC RST 4.5V • • • 8050D COUT OSC S1 S2 S3 • • VOUT1 VOUT2 • S8 SBT 8 / 16Ω Speaker OUT1 VSS Output driving of HT LDO: HT7136 (30mA, 3.6V) HT7133 (30mA, 3.3V) HT7536 (100mA, 3.6V) HT7335 (250mA, 3.5V) Fig. 13 Using 4.5V Battery Ver 2.3 17 May 15, 2006 Integrated Circuits Inc. aP89042 CPU Parallel Mode VIN=+5V VOUT=+3.5V HT7335 10uF 0.01uF ROSC VDD,VPP RST OSC MCU Addr[0] Addr[1] Addr[2] • • • 8050D S1 S2 S3 • • • • • • Addr[4] I[0..2] COUT 8Ω Speaker S5 Rin 3 OUT[1..3] VSS Rin = 860KΩ x (VIN-VOUT) / VIN Fig. 14 5V CPU Control with COUT Ver 2.3 18 May 15, 2006