1024-/256-Position, 1% Resistor Tolerance Error, SPI Interface and 50-TP Memory Digital Rheostat AD5270/AD5271 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VDD POWER-ON RESET RDAC REGISTER SCLK SYNC SERIAL INTERFACE The AD5270/AD5271 ensure less than 1% end-to-end resistor tolerance error and offer 50-times programmable (50-TP) memory. The guaranteed industry leading low resistor tolerance error feature simplifies open-loop applications as well as precision calibration and tolerance matching applications. 1 EXT_CAP GND Figure 1. Mechanical rheostat replacements Op-amp: variable gain control Instrumentation: gain, offset adjustment Programmable voltage to current conversions Programmable filters, delays, time constants Programmable power supply Sensor calibration The AD5270/AD5271 are single-channel, 1024-/256-position digital rheostats that combine industry leading variable resistor performance with nonvolatile memory (NVM) in a compact package. W SDO VSS 1 A 10/8 50-TP MEMORY BLOCK DIN APPLICATIONS GENERAL DESCRIPTION AD5270/AD5271 08077-001 Single-channel, 1024-/256-position resolution 20 kΩ, 50 kΩ, 100 kΩ nominal resistance Maximum ±1% nominal resistor tolerance error 50-times programmable (50-TP) wiper memory Rheostat mode temperature coefficient: 5 ppm/°C 2.7 V to 5.5 V single-supply operation ±2.5 V to ±2.75 V dual-supply operation for ac or bipolar operations SPI-compatible interface Wiper setting readback Power on refreshed from 50-TP memory Thin LFCSP, 10-lead, 3 mm × 3 mm × 0.8 mm package Compact MSOP, 10-lead, 3 mm × 4.9 mm × 1.1 mm package The AD5270/AD5271 device wiper settings are controllable through the SPI digital interface. Unlimited adjustments are allowed before programming the resistance value into the 50-TP memory. The AD5270/AD5271 do not require any external voltage supply to facilitate fuse blow and there are 50 opportunities for permanent programming. During 50-TP activation, a permanent blow fuse command freezes the resistance position (analogous to placing epoxy on a mechanical trimmer). The AD5270/AD5271 are available in a 3 mm × 3 mm, 10-lead LFCSP package and in a 10-lead MSOP package. The parts are guaranteed to operate over the extended industrial temperature range of −40°C to +125°C. Protected by U.S.Patent Number 7688240 Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2009–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5270/AD5271 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Shift Register ............................................................................... 18 Applications ....................................................................................... 1 RDAC Register............................................................................ 18 Functional Block Diagram .............................................................. 1 50-TP Memory Block ................................................................ 18 General Description ......................................................................... 1 Write Protection ......................................................................... 18 Revision History ............................................................................... 2 RDAC and 50-TP Read Operation .......................................... 19 Specifications..................................................................................... 3 Shut-Down Mode ....................................................................... 20 Electrical Characteristics—AD5270 .......................................... 3 Resistor Performance Mode...................................................... 20 Electrical Characteristics—AD5271 .......................................... 5 Reset ............................................................................................. 20 Interface Timing Specifications .................................................. 7 SDO Pin and Daisy-Chain Operation ..................................... 21 Absolute Maximum Ratings ............................................................ 9 RDAC Architecture .................................................................... 21 Thermal Resistance ...................................................................... 9 Programming the Variable Resistor ......................................... 22 ESD Caution .................................................................................. 9 EXT_CAP Capacitor .................................................................. 22 Pin Configuration and Function Descriptions ........................... 10 Terminal Voltage Operating Range ......................................... 22 Typical Performance Characteristics ........................................... 11 Power-Up Sequence ................................................................... 22 Test Circuits ..................................................................................... 17 Outline Dimensions ....................................................................... 23 Theory of Operation ...................................................................... 18 Ordering Guide .......................................................................... 24 Serial Data Interface ................................................................... 18 REVISION HISTORY 11/10—Rev. C to Rev. D Changes to Figure 25 ...................................................................... 14 Added LFCSP Throughout ..............................................................1 Changed OTP to 50-TP Throughout..............................................1 Changes to Product Title, Features, and General Description ....1 Changes to Table 1.............................................................................3 Added Table 3; Renumbered Sequentially .....................................4 Changes to Table 4.............................................................................5 Added Table 6 ....................................................................................6 Changes to Table 8 and Table 9........................................................9 Added Figure 6 and changes to Table 10 ..................................... 10 Replaced Typical Performance Characteristics Section ............ 11 Changes to Figure 44...................................................................... 21 Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 24 9/10—Rev. B to Rev. C 3/10—Rev. 0 to Rev. A Changes to Figure 3 Caption ........................................................... 7 Changes to Figure 4 Caption ........................................................... 8 Deleted Daisy-Chain Operation Section, Added SDO Pin and Daisy-Chain Operation Section ................................................... 21 Changes to Product Title and General Description.....................1 3/13—Rev. E to Rev. F Changed Resistor Noise Density, RAW = 20 kΩ from 50 nV/√Hz to 13 nV/√Hz; Table 1 ...................................................................... 4 Changed Resistor Noise Density, RAW = 20 kΩ from 50 nV/√Hz to 13 nV/√Hz; Table 4 ...................................................................... 6 Updated Outline Dimensions ....................................................... 23 12/10—Rev. D to Rev. E Changes to SDO Pin Description ................................................. 10 Changes to SDO Pin and Daisy-Chain Operation Section....... 21 Changes to Theory of Operation Section...................................14 10/09—Revision 0: Initial Version 5/10—Rev. A to Rev. B Rev. F | Page 2 of 24 Data Sheet AD5270/AD5271 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—AD5270 VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted. Table 1. Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resolution Resistor Integral Nonlinearity 2, 3 Symbol Test Conditions/Comments Min R-INL RAW = 20 kΩ, |VDD − VSS| = 3.0 V to 5.5 V RAW = 20 kΩ, |VDD − VSS| = 2.7 V to 3.0 V RAW = 50 kΩ, 100 kΩ Resistor Differential Nonlinearity2 Nominal Resistor Tolerance R-Perf Mode 4 Normal Mode Resistance Temperature Coefficient 5, 6 Wiper Resistance RESISTOR TERMINALS Terminal Voltage Range5, 7 Capacitance5 A R-DNL 10 −1 −1 −1 −1 See Table 2 and Table 3 −1 Code = full scale Code = zero scale Tristate Leakage Current Output Capacitance5 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Supply Current Positive Negative 50-TP Store Current5, 8 Positive Negative OTP Read Current5, 9 Positive Negative ±0.5 ±15 5 35 VINH VINL IIN CIN VOH VOL Max Unit +1 +1.5 +1 +1 Bits LSB LSB LSB LSB +1 70 VDD V pF 40 pF 50 2.0 0.8 ±1 5 RPULL_UP = 2.2 kΩ to VDD RPULL_UP = 2.2 kΩ to VDD VDD = 2.7 V to 5.5 V, VSS = 0 V VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V VDD − 0.1 2.7 ±2.5 V V µA pF 5.5 ±2.75 V V 1 µA µA −1 IDD_OTP_STORE ISS_OTP_STORE 4 −4 IDD_OTP_READ ISS_OTP_READ mA mA 500 −500 Rev. F | Page 3 of 24 V V µA pF 0.4 0.6 +1 5 IDD ISS nA V −1 VSS = 0 V % % ppm/°C Ω 90 VSS f = 1 MHz, measured to GND, code = half scale f = 1 MHz, measured to GND, code = half scale VA = VW Capacitance5 W Common-Mode Leakage Current5 DIGITAL INPUTS Input Logic5 High Low Input Current Input Capacitance5 DIGITAL OUTPUT Output Voltage5 High Low Typ 1 µA µA AD5270/AD5271 Parameter Power Dissipation 10 Power Supply Rejection Ratio5 DYNAMIC CHARACTERISTICS5, 11 Bandwidth Total Harmonic Distortion Data Sheet Symbol PSRR Test Conditions/Comments VIH = VDD or VIL = GND ΔVDD/ΔVSS = ±5 V ± 10% RAW = 20 kΩ RAW = 50 kΩ RAW = 100 kΩ Min −3 dB, RAW = 10 kΩ, Terminal W, see Figure 42 RAW = 20 kΩ RAW = 50 kΩ RAW = 100 kΩ VA = 1 V rms, f = 1 kHz, Typ 1 Max 5.5 −66 −75 −78 −55 −67 −70 Unit µW dB kHz 300 120 60 dB code = half scale Resistor Noise Density RAW = 20 kΩ RAW = 50 kΩ RAW= 100 kΩ Code = half scale, TA = 25°C RAW = 20 kΩ RAW = 50 kΩ RAW = 100 kΩ −90 −88 −85 nV/√Hz 13 25 32 Typical specifications represent average readings at 25°C, VDD = 5 V, and VSS = 0 V. Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. 3 The maximum current in each code is defined by IAW = (VDD − 1)/RAW. 4 The terms resistor performance mode and R-Perf mode are used interchangeably. See the Resistor Performance Mode section. 5 Guaranteed by design and not subject to production test. 6 See Figure 25 for more details. 7 Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 8 Different from operating current, the supply current for the fuse program lasts approximately 55 ms. 9 Different from operating current, the supply current for the fuse read lasts approximately 500 ns. 10 PDISS is calculated from (IDD × VDD) + (ISS × VSS). 11 All dynamic characteristics use VDD = +2.5 V, VSS = −2.5 V. 1 2 Table 2. AD5270—20 kΩ Resistor Performance Mode Code Range Resistor Tolerance Per Code R-TOLERANCE 1% R-Tolerance 2% R-Tolerance 3% R-Tolerance |VDD − VSS| = 4.5 V to 5.5 V |VDD − VSS| = 2.7 V to 4.5 V From 0x078 to 0x3FF From 0x037 to 0x3FF From 0x028 to 0x3FF From 0x0BE to 0x3FF From 0x055 to 0x3FF From 0x037 to 0x3FF Table 3. AD5270—50 kΩ and 100 kΩ Resistor Performance Mode Code Range Resistor Tolerance Per Code R-TOLERANCE 1% R-Tolerance 2% R-Tolerance 3% R-Tolerance RAW = 50 kΩ RAW = 100 kΩ From 0x078 to 0x3FF From 0x055 to 0x3FF From 0x032 to 0x3FF From 0x04B to 0x3FF From 0x032 to 0x3FF From 0x019 to 0x3FF Rev. F | Page 4 of 24 Data Sheet AD5270/AD5271 ELECTRICAL CHARACTERISTICS—AD5271 VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted. Table 4. Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resolution Resistor Integral Nonlinearity 2, 3 Resistor Differential Nonlinearity2 Nominal Resistor Tolerance R-Perf Mode 4 Normal Mode Resistance Temperature Coefficient 5, 6 Wiper Resistance RESISTOR TERMINALS Terminal Voltage Range5, 7 Capacitance5 A Symbol Tristate Leakage Current Output Capacitance5 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Supply Current Positive Negative 50-TP Store Current5, 8 Positive Negative OTP Read Current5, 9 Positive Negative Power Dissipation 10 Power Supply Rejection Ratio5 Min Typ 1 8 −1 −1 R-INL R-DNL See Table 5 and Table 6 −1 Code = full scale Code = zero scale ±0.5 ±15 5 35 VSS f = 1 MHz, measured to GND, code = half scale f = 1 MHz, measured to GND, code = half scale VA = VW Capacitance5 W Common-Mode Leakage Current5 DIGITAL INPUTS Input Logic5 High Low5 Input Current Input Capacitance5 DIGITAL OUTPUT Output Voltage5 High Low Test Conditions/Comments VINH VINL IIN CIN VOH VOL Max Unit +1 +1 Bits LSB LSB +1 70 VDD 90 V pF 40 pF 50 2.0 0.8 ±1 5 RPULL_UP = 2.2 kΩ to VDD RPULL_UP = 2.2 kΩ to VDD VDD = 2.7 V to 5.5 V, VSS = 0 V VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V VDD − 0.1 2.7 ±2.5 V V µA pF 5.5 ±2.75 V V 1 µA µA −1 IDD_OTP_STORE ISS_OTP_STORE 4 −4 IDD_OTP_READ ISS_OTP_READ PSRR mA mA 500 −500 VIH = VDD or VIL = GND ΔVDD/ΔVSS = ±5 V ± 10% RAW = 20 kΩ RAW = 50 kΩ RAW = 100 kΩ Rev. F | Page 5 of 24 V V µA pF 0.4 0.6 +1 5 IDD ISS nA V −1 VSS = 0 V % % ppm/°C Ω 5.5 −66 −75 −78 −55 −67 −70 µA µA µW dB AD5270/AD5271 Parameter DYNAMIC CHARACTERISTICS5, 11 Bandwidth Total Harmonic Distortion Resistor Noise Density Data Sheet Symbol Test Conditions/Comments Min −3 dB, RAW = 10 kΩ, Terminal W, see Figure 42 RAW = 20 kΩ RAW = 50 kΩ RAW = 100 kΩ VA = 1 V rms, f = 1 kHz, code = half scale RAW = 20 kΩ RAW = 50 kΩ RAW = 100 kΩ Code = half scale, TA = 25°C RAW = 20 kΩ RAW = 50 kΩ RAW = 100 kΩ Typ 1 Max Unit kHz 300 120 60 dB −90 −88 −85 nV/√Hz 13 25 32 Typical specifications represent average readings at 25°C, VDD = 5 V, and VSS = 0 V. Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. 3 The maximum current in each code is defined by IAW = (VDD − 1)/RAW. 4 The terms resistor performance mode and R-Perf mode are used interchangeably. See the Resistor Performance Mode section. 5 Guaranteed by design and not subject to production test. 6 See Figure 25 for more details. 7 Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 8 Different from operating current, the supply current for the fuse program lasts approximately 55 ms. 9 Different from operating current, the supply current for the fuse read lasts approximately 500 ns. 10 PDISS is calculated from (IDD × VDD) + (ISS × VSS). 11 All dynamic characteristics use VDD = +2.5 V, VSS = −2.5 V. 1 2 Table 5. AD5271—20 kΩ Resistor Performance Mode Code Range Resistor Tolerance per Code R-TOLERANCE 1% R-Tolerance 2% R-Tolerance 3% R-Tolerance |VDD − VSS| = 4.5 V to 5.5 V |VDD − VSS| = 2.7 V to 4.5 V From 0x1E to 0xFF From 0x0F to 0xFF From 0x06 to 0xFF From 0x32 to 0xFF From 0x19 to 0xFF From 0x0E to 0xFF Table 6. AD5271—50 kΩ and 100 kΩ Resistor Performance Mode Code Range Resistor Tolerance per Code R-TOLERANCE 1% R-Tolerance 2% R-Tolerance 3% R-Tolerance RAW = 50 kΩ RAW = 100 kΩ From 0x1E to 0xFF From 0x14 to 0xFF From 0x0A to 0xFF From 0x14 to 0xFF From 0x0F to 0xFF From 0x0A to 0xFF Rev. F | Page 6 of 24 Data Sheet AD5270/AD5271 INTERFACE TIMING SPECIFICATIONS VDD = 2.5 V to 5.5 V, VSS = 0 V; VDD = 2.5 V, VSS = −2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 7. Limit1 20 10 10 15 5 5 1 500 15 450 2 600 6 350 0.6 2 Parameter t12 t2 t3 t4 t5 t6 t7 t83, 4 t9 t105 tRDAC_R-PERF tRDAC_NORMAL tMEMORY_READ tMEMORY_PROGRAM tRESET tPOWER-UP6 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max μs max ns max μs max ms max ms max ms max Test Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to next SCLK fall ignored SCLK rising edge to SDO valid RDAC register write command execute time RDAC register write command execute time Memory readback execute time Memory program time Reset 50-TP restore time Power-on 50-TP restore time 1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Maximum SCLK frequency is 50 MHz. 3 Refer to tRDAC_R-PER and tRDAC_NORMAL for RDAC register write operations. 4 Refer to tMEMORY_READ and tMEMORY_PROGRAM for memory commands operations. 5 RPULL_UP = 2.2 kΩ to VDD with a capacitance load of 168 pF. 6 Maximum time after VDD − VSS is equal to 2.5 V. 2 Shift Register and Timing Diagrams DB9 (MSB) C3 0 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 08077-002 0 DB0 (LSB) DATA BITS CONTROL BITS Figure 2. Shift Register Content t7 t4 t2 t1 SCLK t8 t9 t3 SYNC t5 t6 0 0 C3 C2 D7 D6 D5 D2 D1 D0 08077-003 DIN SDO Figure 3. Write Timing Diagram (CPOL = 0, CPHA = 1) Rev. F | Page 7 of 24 AD5270/AD5271 Data Sheet SCLK t9 SYNC DIN 0 0 C3 D0 D0 0 0 C3 D1 D0 SDO X X C3 Figure 4. Read Timing Diagram (CPOL = 0, CPHA = 1) Rev. F | Page 8 of 24 D1 D0 08077-004 t10 Data Sheet AD5270/AD5271 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 8. Parameter VDD to GND VSS to GND VDD to VSS VA, VW to GND Digital Input and Output Voltage to GND EXT_CAP to VSS IA, IW Continuous RAW = 20 kΩ RAW = 50 kΩ, 100 kΩ Pulsed 1 Frequency > 10 kHz Frequency ≤ 10 kHz Operating Temperature Range 4 Maximum Junction Temperature (TJ Maximum) Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Package Power Dissipation Rating –0.3 V to +7.0 V +0.3 V to −7.0 V 7V VSS − 0.3 V, VDD + 0.3 V −0.3 V to VDD + 0.3 V 7V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is defined by JEDEC specification JESD-51 and the value is dependent on the test board and test environment. Table 9. Thermal Resistance ±3 mA ±2 mA Package Type 10-Lead LFCSP 10-Lead MSOP ±MCC 2/d 3 ±MCC2/√d3 −40°C to +125°C 150°C 1 JEDEC 2S2P test board, still air (0 m/s air flow). ESD CAUTION −65°C to +150°C θJA1 50 135 260°C 20 sec to 40 sec (TJ max − TA)/θJA Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A and W terminals at a given resistance. 2 Maximum continuous current. 3 Pulse duty factor. 4 Includes programming of 50-TP memory. 1 Rev. F | Page 9 of 24 θJC 3 N/A Unit °C/W °C/W AD5270/AD5271 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 10 SYNC AD5270/ AD5271 9 SCLK W 3 VSS 4 (EXPOSED PAD) 7 SDO A 2 2 A W 3 VSS 4 10 SYNC AD5270/ AD5271 9 SCLK 8 TOP VIEW (Not to Scale) DIN 7 SDO 6 GND EXT_CAP 5 EXT_CAP 5 6 GND NOTES 1. THE EXPOSED PAD IS LEFT FLOATING OR IS TIED TO VSS. 08077-005 VDD 1 8 DIN 08077-040 VDD 1 Figure 6. LFCSP Pin Configuration Figure 5. MSOP Pin Configuration Table 10. Pin Function Descriptions Pin No. 1 2 3 4 Mnemonic VDD A W VSS 5 EXT_CAP 6 7 GND SDO 8 DIN 9 SCLK 10 SYNC EPAD Exposed Pad Description Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors. Terminal A of RDAC. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC. VSS ≤ VW ≤ VDD. Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors. External Capacitor. Connect a 1 μF capacitor between EXT_CAP and VSS. This capacitor must have a voltage rating of ≥7 V. Ground Pin, Logic Ground Reference. Serial Data Output. This pin can be used to clock data from the shift register in daisy-chain mode or in readback mode. This open-drain output requires an external pull-up resistor even if it is not use. Serial Data Line. This pin is used in conjunction with the SCLK line to clock data into or out of the 16-bit input register. Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz. Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC goes low, it enables the shift register and data is transferred in on the falling edges of the subsequent clocks. The selected register is updated on the rising edge of SYNC following the 16th clock cycle. If SYNC is taken high before the 16th clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the RDAC. Leave floating or connected to VSS. Rev. F | Page 10 of 24 Data Sheet AD5270/AD5271 TYPICAL PERFORMANCE CHARACTERISTICS 0.8 0.8 +125°C +25°C –40°C 0.6 RAW = 20kΩ TA = 25°C 0.4 0.2 0.2 0 0 –0.2 –0.2 0 128 256 384 512 640 768 896 1023 CODE (Decimal) –0.4 08077-010 –0.4 0 256 512 CODE (Decimal) 768 1023 08077-111 INL (LSB) 0.4 INL (LSB) 20kΩ 50kΩ 100kΩ 0.6 Figure 10. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5270) Figure 7. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5270) 0.6 0.2 TA = 25°C RAW = 20kΩ 0.1 0.4 0 0.2 DNL (LSB) DNL (LSB) –0.1 –0.2 0 –0.3 –0.2 –0.4 –0.4 –0.5 128 256 384 512 +125°C 640 896 768 1023 CODE (Decimal) 20kΩ –0.6 08077-011 0 0 50kΩ 256 100kΩ 512 CODE (Decimal) 768 Figure 11. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5270) Figure 8. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5270) 0.6 0.50 +125°C +25°C –40°C 0.40 1023 08077-120 +25°C –40°C –0.6 20kΩ 50kΩ 100kΩ TA = 25°C RAW = 20kΩ 0.4 INL (LSB) 0.20 0.2 0 0.10 –0.10 0 128 256 384 512 640 768 896 1023 CODE (Decimal) Figure 9. R-INL in Normal Mode vs. Code vs. Temperature (AD5270) –0.4 0 256 512 CODE (Decimal) 768 1023 08077-121 –0.2 0 08077-014 INL (LSB) 0.30 Figure 12. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5270) Rev. F | Page 11 of 24 AD5270/AD5271 Data Sheet 0.15 0.15 +125°C +25°C –40°C 0.10 RAW = 20kΩ 20kΩ 50kΩ 100kΩ TA = 25°C 0.10 0.05 DNL (LSB) DNL (LSB) 0.05 0 0 –0.05 –0.05 –0.10 –0.10 0 128 256 384 512 640 768 896 1023 CODE (Decimal) –0.20 08077-015 –0.15 Figure 13. R-DNL in Normal Mode vs. Code vs. Temperature (AD5270) 0 256 512 CODE (Decimal) 768 Figure 16. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5270) 0.15 0.20 +125°C +25°C –40°C 0.15 1023 08077-122 –0.15 20kΩ 100kΩ TA = 25°C RAW = 20kΩ 0.10 INL (LSB) INL (LSB) 0.10 0.05 0.05 0 0 0 64 128 CODE (Decimal) 192 255 –0.10 08077-013 –0.10 0 0.06 255 TA = 25°C 0.10 0.02 0 0.05 –0.02 DNL (LSB) –0.04 –0.06 0 –0.05 –0.08 –0.10 –0.10 –0.12 20kΩ 0 64 128 CODE (Decimal) 192 255 Figure 15. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5271) 100kΩ –0.15 08077-012 –0.14 0 64 128 CODE (Decimal) 192 255 08077-125 DNL (LSB) 192 0.15 +125°C +25°C –40°C 0.04 128 CODE (Decimal) Figure 17. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5271) Figure 14. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5271) RAW = 20kΩ 64 08077-123 –0.05 –0.05 Figure 18. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5271) Rev. F | Page 12 of 24 Data Sheet AD5270/AD5271 0.15 0.10 +125°C +25°C –40°C 0.08 RAW = 20kΩ 20kΩ 100kΩ TA = 25°C 0.10 INL (LSB) INL (LSB) 0.06 0.04 0.05 0 0.02 0 64 128 CODE (Decimal) 192 –0.10 08077-016 –0.02 255 0 128 CODE (Decimal) 192 255 Figure 22. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5271) Figure 19. R-INL in Normal Mode vs. Code vs. Temperature (AD5271) 0.010 0.03 100kΩ 20kΩ +125°C +25°C –40°C RAW = 20kΩ 0.02 TA = 25°C 0.008 0.006 DNL (LSB) 0.01 0 0.004 –0.01 0.002 –0.02 0 0 64 128 CODE (Decimal) 192 255 Figure 20. R-DNL in Normal Mode vs. Code vs. Temperature (AD5271) 0 64 128 CODE (Decimal) 192 08077-027 –0.002 –0.03 08077-017 DNL (LSB) 64 08077-126 –0.05 0 255 Figure 23. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5271) 1.0 500 400 IDD = 5V 0.8 300 CURRENT (mA) IDD = 3V 100 ISS = 3V 0 –100 0.6 0.4 –200 ISS = 5V 0.2 –300 –400 0 10 20 30 40 50 60 70 80 90 100 110 TEMPERATURE (°C) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOLTAGE (V) Figure 24. Supply Current IDD vs. Digital Input Voltage Figure 21. Supply Current (IDD, ISS) vs. Temperature Rev. F | Page 13 of 24 5.5 08077-023 –500 –40 –30 –20 –10 0 08077-018 CURRENT (nA) 200 AD5270/AD5271 Data Sheet 50 45 VDD/VSS = 5V/0V 20kΩ 50kΩ 100kΩ 20kΩ 50kΩ 100kΩ 6 THEORETICAL IWA_MAX (mA) 40 35 30 25 20 15 10 5 4 3 2 1 5 0 512 128 CODE (Decimal) 1023 AD5270 255 AD5271 768 192 0 0 0 1023 AD5270 255 AD5271 768 192 Figure 28. Theoretical Maximum Current vs. Code Figure 25. Tempco ΔRWA/ΔT vs. Code 0 0 AD5270 (AD5271) 0x200 (0x80) AD5270 (AD5271) 0x200 (0x80) –10 512 128 CODE (Decimal) 256 64 0x100 (0x40) –10 0x100 (0x40) 0x080 (0x20) 0x080 (0x20) 0x020 (0x08) 0x010 (0x04) 0x010 (0x04) 0x008 (0x02) –40 0x004 (0x01) 0x008 (0x02) –50 0x004 (0x01) 0x002 0x001 –50 –60 0x001 10k 100k 1M 10M FREQUENCY (Hz) –70 1k 08077-031 –60 1k 0x002 0 AD5270 (AD5271) –10 0x100 (0x40) –20 0x020 (0x08) 0x010 (0x04) –40 0x008 (0x02) –50 –70 0x002 0x001 –80 10k 100k 1M FREQUENCY (Hz) 10M 08077-032 –60 1k –40 –60 0x004 (0x01) –50 50kΩ 100kΩ 20kΩ –30 0x040 (0x10) PSRR (dB) –30 10M VDD /VSS= 5V/0V CODE = HALF SCALE 0x080 (0x20) –20 1M Figure 29. 100 kΩ Gain vs. Code vs. Frequency 0 –10 100k FREQUENCY (Hz) Figure 26. 20 kΩ Gain vs. Code vs. Frequency 0x200 (0x80) 10k 08077-041 –40 0x020 (0x08) –30 Figure 27. 50 kΩ Gain vs. Code vs. Frequency –90 100 1k 10k FREQUENCY (Hz) Figure 30. PSRR vs. Frequency Rev. F | Page 14 of 24 100k 08077-024 –30 0x040 (0x10) 0x040 (0x10) GAIN (dB) GAIN (dB) –20 –20 08077-028 256 64 08077-019 0 0 GAIN (dB) RHEOSTAT MODE TEMPCO (ppm/°C) 7 VDD/VSS= 5V/0V Data Sheet AD5270/AD5271 0 VDD/VSS = 5V/0V CODE = HALF SCALE fIN = 1kHz NOISE BW = 22kHz –10 –20 THD + N (dB) THD + N (dB) –20 0 20kΩ 50kΩ 100kΩ VDD/VSS= 5V/0V CODE = HALF SCALE NOISE BW = 22kHz VIN = 1V rms –40 –60 20kΩ 50kΩ 100kΩ –30 –40 –50 –60 –70 –80 –80 10k 100k FREQUENCY (Hz) 08077-025 1k –100 0.001 0.01 08077-026 –90 –100 100 1 0.1 VOLTAGE (VRMS) Figure 34. THD + N vs. Amplitude Figure 31. THD + N vs. Frequency 0.03 0.0010 20kΩ 50kΩ 100kΩ 0.02 VDD/VSS = 5V/0V IAW = 200µA CODE = HALF SCALE 0.0005 VOLTAGE (V) VOLTAGE (V) 0.01 0 –0.01 0 –0.0005 –0.02 14 19 –0.0015 –10 0 6.25 20 5.00 15 3.75 10 2.50 5 1.25 0 4.2 VDD (V) 4.7 5.2 NUMBER OF CODES (AD5270) 25 3.7 60 15.5 20kΩ 50kΩ 100kΩ 60 15.0 50 12.5 40 10.0 30 7.5 20 5.0 10 2.5 08077-021 8.75 7.50 3.2 50 VDD/VSS = 5V/0V 10.00 30 0 2.7 40 70 11.25 NUMBER OF CODES (AD5271) NUMBER OF CODES (AD5270) 35 30 Figure 35. Digital Feedthrough TA = 25°C 20kΩ 50kΩ 100kΩ 40 20 TIME (µs) Figure 32. Maximum Glitch Energy 45 10 0 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 Figure 36. Maximum Code Loss vs. Temperature Figure 33. Maximum Code Loss vs. Voltage Rev. F | Page 15 of 24 0 NUMBER OF CODES (AD5271) 9 TIME (µs) 08077-020 4 08077-043 –0.04 –1 08077-046 –0.0010 –0.03 AD5270/AD5271 Data Sheet 0.006 8 VDD/VSS = 5V/0V IAW = 10µA CODE = HALF SCALE 0.005 ΔRAW RESISTANCE (%) 6 5 0.004 0.003 0.002 0.001 0 4 0.07 0.09 0.11 0.13 0.15 TIME (Seconds) 0.17 –0.002 0 100 200 300 400 500 600 700 800 900 1000 OPERATION AT 150°C (Hours) Figure 37. VEXT_CAP Waveform While Writing Fuse Figure 38. Long-Term Drift Accelerated Average by Burn-In Rev. F | Page 16 of 24 08077-038 –0.001 08077-029 VOLTAGE (V) 7 Data Sheet AD5270/AD5271 TEST CIRCUITS Figure 39 to Figure 43 define the test conditions used in the Specifications section. DUT DUT IW VMS 08077-033 VMS Figure 42. Gain vs. Frequency Figure 39. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) RWA = DUT VMS IW GND ICM W CODE = 0x00 IW RW = V 08077-036 A A DUT 1GΩ W W +2.75V –2.75V RWA 2 A W GND VMS NC = NO CONNECT +2.75V Figure 40. Wiper Resistance V+ = VDD ±10% IW W V+ PSS (%/%) = –2.75V Figure 43. Common Leakage Current PSRR (dB) = 20 LOG VDD GND NC ΔVMS% ΔVDD% VMS VDD VMS 08077-035 A Figure 41. Power Supply Sensitivity (PSS, PSRR) Rev. F | Page 17 of 24 08077-037 08077-034 A AD5270/AD5271 Data Sheet THEORY OF OPERATION The AD5270 and AD5271 are designed to operate as true variable resistors for analog signals within the terminal voltage range of VSS < VTERM < VDD. The RDAC register contents determine the resistor wiper position. The RDAC register acts as a scratchpad register, which allows unlimited changes of resistance settings. The RDAC register can be programmed with any position setting using the SPI interface. When a desirable wiper position is found, this value can be stored in a 50-TP memory register. Thereafter, the wiper position is always restored to that position for subsequent power-up. The storing of 50-TP data takes approximately 350 ms; during this time, the AD5270/AD5271 lock to prevent any changes from taking place. The AD5270/AD5271 also feature a patented 1% end-to-end resistor tolerance. This simplifies precision, rheostat mode, and open-loop applications where knowledge of absolute resistance is critical. SERIAL DATA INTERFACE The AD5270/AD5271 contain a serial interface (SYNC, SCLK, DIN , and SDO), which is compatible with SPI interface standards, as well as most DSPs. This device allows writing of data via the serial interface to every register. SHIFT REGISTER For the AD5270/AD5271, the shift register is 16 bits wide, as shown in Figure 2. The 16-bit word consists of two unused bits, which should be set to zero, followed by four control bits and 10 RDAC data bits (note that for the AD5271 only, the lower two RDAC data bits are don’t care if the RDAC register is read from or written to). Data is loaded MSB first (Bit 15). The four control bits determine the function of the software command as listed in Table 11. Figure 3 shows a timing diagram of a typical AD5270/AD5271 write sequence. The write sequence begins by bringing the SYNC line low. The SYNC pin must be held low until the complete data-word is loaded from the DIN pin. When SYNC returns high, the serial data-word is decoded according to the instructions in Table 11. The command bits (Cx) control the operation of the digital potentiometer. The data bits (Dx) are the values that are loaded into the decoded register. The AD5270/AD5271 have an internal counter that counts a multiple of 16 bits (a frame) for proper operation. For example, AD5270/AD5271 each works with a 32-bit word but do not work properly with a 31-bit or 33-bit word. The AD5270/AD5271 do not require a continuous SCLK when SYNC is high. To minimize power consumption in the digital input buffers, operate all serial interface pins close to the VDD supply rails. RDAC REGISTER The RDAC register directly controls the position of the digital rheostat wiper. For example, when the RDAC register is loaded with all zeros, the wiper is connected to Terminal A of the variable resistor. The RDAC register is a standard logic register and there is no restriction on the number of changes allowed. The basic mode of setting the variable resistor wiper position (programming the RDAC register) is accomplished by loading the serial data input register with Command 1 (see Table 11) and with the desired wiper position data. 50-TP MEMORY BLOCK The AD5270/AD5271 contain an array of 50-TP programmable memory registers, which allow the wiper position to be programmed up to 50 times. Table 13 shows the memory map. When the desired wiper position is determined, the user can load the serial data input register with Command 3 (see Table 11) which stores the wiper position data in a 50-TP memory register. The first address to be programmed is Location 0x01 (see Table 13); the AD5270/AD5271 increments the 50-TP memory address for each subsequent program until the memory is full. Programming data to 50-TP consumes approximately 4 mA for 55 ms, and takes approximately 350 ms to complete, during which time the shift register locks to prevent any changes from occurring. Bit C3 of the control register can be polled to verify that the fuse program command was completed properly. No change in supply voltage is required to program the 50-TP memory; however, a 1 μF capacitor on the EXT_CAP pin is required (see Figure 46). Prior to 50-TP activation, the AD5270 and the AD5271 preset to midscale on power up. WRITE PROTECTION At power-up, the serial data input register write commands for both the RDAC register and the 50-TP memory registers are disabled. The RDAC write protect bit, C1, of the control register (see Table 13 and Table 14) is set to 0 by default. This disables any change of the RDAC register content regardless of the software commands, except that the RDAC register can be refreshed from the 50-TP memory using the software reset, Command 4. To enable programming of the RDAC register, the write protect bit (Bit C1), of the control register must first be programmed by loading the serial data input register with Command 7. To enable programming of the 50-TP memory, the program enable bit (Bit C0) of the control register, which is set to 0 by default, must first be set to 1. Rev. F | Page 18 of 24 Data Sheet AD5270/AD5271 RDAC AND 50-TP READ OPERATION Data from the selected memory location is clocked out of the SDO pin during the next SPI operation. A binary encoded version address of the most recently programmed wiper memory location can be read back using Command 6 (see Table 11). This can be used to monitor the spare memory status of the 50-TP memory block. A serial data output SDO pin is available for readback of the internal RDAC register or 50-TP memory contents. The contents of the RDAC register can be read back through SDO by using Command 2 (see Table 11). Data from the RDAC register is clocked out of the SDO pin during the last 10 clocks of the next SPI operation. Table 12 provides a sample listing for the sequence of serial data input (DIN) words with the serial data output appearing at the SDO pin in hexadecimal format for a write and read to both the RDAC register and the 50-TP memory (Memory Location 20). It is possible to read back the contents of any of the 50-TP memory registers through SDO by using Command 5. The lower six LSB bits, D0 to D5 of the data byte, select which memory location is to be read back, as shown in Table 13. Table 11. Command Operation Truth Table Command Number 0 1 Command[DB13:DB10] C3 C2 C1 C0 0 0 0 0 0 0 0 1 D7 X D7 Data[DB9:DB0] 1 D6 D5 D4 D3 X X X X D6 D5 D4 D3 D9 X D9 D8 X D8 D2 X D2 D1 X D1 2 D0 X D02 2 0 0 1 0 X X X X X X X X X X 3 0 0 1 1 X X X X X X X X X X 4 0 1 0 0 X X X X X X X X X X 53 0 1 0 1 X X X X D5 D4 D3 D2 D1 D0 6 0 1 1 0 X X X X X X X X X X 74 0 1 1 1 X X X X X X X D2 D1 D0 8 9 1 1 0 0 0 0 0 1 X X X X X X X X X X X X X X X X X X X D0 X is don’t care. AD5271 = don’t care. 3 See Table 15 for 50-TP memory map. 4 See Table 14 for bit details. 1 2 Rev. F | Page 19 of 24 Operation NOP: do nothing. Write contents of serial register data to RDAC. Read contents of RDAC wiper register. Store wiper setting: store RDAC setting to 50-TP. Software reset: refresh RDAC with last 50-TP memory stored value. Read contents of 50-TP from SDO output in the next frame. Read address of last 50-TP programmed memory location. Write contents of serial register data to control register. Read contents of control register. Software shutdown. D0 = 0; normal mode. D0 = 1; device placed in shutdown mode. AD5270/AD5271 Data Sheet SHUT-DOWN MODE RESISTOR PERFORMANCE MODE The AD5270/AD5271 can be shut down by executing the software shutdown command, Command 9 (see Table 11), and setting the LSB to 1. This feature places the RDAC in a zeropower-consumption state where Terminal Ax is open circuited and the Wiper Terminal Wx remains connected. It is possible to execute any command from Table 11 while the AD5270/AD5271 are in shutdown mode. The parts can be taken out of shutdown mode by executing Command 9 and setting the LSB to 0 or by a software reset, Command 4 (see Table 11). This mode activates a new, patented 1% end-to-end resistor tolerance that ensures a ±1% resistor tolerance error on each code, that is, code = half scale, RWA = 10 kΩ ± 100 Ω. See Table 2, Table 3, Table 5, and Table 6 to verify which codes achieve ±1% resistor tolerance. The resistor performance mode is activated by programming Bit C2 of the control register. RESET The AD5270/AD5271 can be reset through software by executing Command 4 (see Table 11). The reset command loads the RDAC register with the contents of the most recently programmed 50-TP memory location. The RDAC register loads with midscale if no 50-TP memory location has been previously programmed. Table 12. Write and Read to RDAC and 50-TP Memory DIN 0x1C03 0x0500 0x0800 0x0C00 SDO 1 0xXXXX 0x1C03 0x0500 0x100 0x1800 0x0000 0x0C00 0xXX19 0x1419 0x2000 0x0000 0x0100 0x0000 0xXXXX 1 Action Enable update of the wiper position and the 50-TP memory contents through the digital interface. Write 0x100 to the RDAC register; wiper moves to ¼ full-scale position. Prepares data read from RDAC register. Stores RDAC register content into the 50-TP memory. A 16-bit word appears out of SDO, where the last 10-bits contain the contents of the RDAC register (0x100). Prepares data read of last programmed 50-TP memory monitor location. NOP Instruction 0 sends a 16-bit word out of SDO, where the six LSBs last six bits contain the binary address of the last programmed 50-TP memory location, for example, 0x19 (see Table 13). Prepares data read from Memory Location 0x19. Prepares data read from the control register. Sends a 16-bit word out of SDO, where the last 10-bits contain the contents of Memory Location 0x19. NOP Instruction 0 sends a 16-bit word out of SDO, where the last four bits contain the contents of the control register. If Bit C3 = 1, the fuse program command successful. X is don’t care. Table 13. Control Register Bit Map DB9 0 DB8 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 C3 DB2 C2 DB1 C1 DB0 C0 Table 14. Control Register Bit Description Bit Name C0 C1 C2 C3 1 Description 50-TP program enable 0 = 50-TP program disabled (default) 1 = enable device for 50-TP program RDAC register write protect 0 = wiper position frozen to value in 50-TP memory (default) 1 1 = allow update of wiper position through digital interface R-performance enable 0 = RDAC resistor tolerance calibration enabled (default) 1 = RDAC resistor tolerance calibration disabled 50-TP memory program success bit 0 = fuse program command unsuccessful (default) 1 = fuse program command successful Wiper position frozen to the last value programmed in the 50-TP memory. The wiper is frozen to midscale if the 50-TP memory has not been previously programmed. Rev. F | Page 20 of 24 Data Sheet AD5270/AD5271 Table 15. Memory Map Command Number 5 1 D9 X X X X X … X X X X X D8 X X X X X … X X X X X D7 X X X X X … X X X X X Data Byte[DB9:DB8]1 D6 D5 D4 D3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 … … … … 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 1 0 1 1 0 D2 0 0 0 0 1 … 0 1 1 0 0 D1 0 0 1 1 0 … 1 0 1 0 1 D0 0 1 0 1 0 … 0 0 0 0 0 Register Contents Reserved 1st programmed wiper location (0x01) 2nd programmed wiper location (0x02) 3rd programmed wiper location (0x03) 4th programmed wiper location (0x04) … 10th programmed wiper location (0xA) 20th programmed wiper location (0x14) 30th programmed wiper location (0x1E) 40th programmed wiper location (0x28) 50th programmed wiper location (0x32) X is don’t care. VDD SDO PIN AND DAISY-CHAIN OPERATION MOSI SDO1 0xXXXX 0xXXXX 0x0000 High Impedance 1 RP 2.2kΩ AD5270/ AD5271 DIN U2 SDO µC SCLK SS SYNC SCLK SCLK 08077-006 SYNC Figure 44. Daisy-Chain Configuration Using SDO RDAC ARCHITECTURE To achieve optimum performance, Analog Devices has patented the RDAC segmentation architecture for all the digital potentiometers. In particular, the AD5270/AD5271 employ a three-stage segmentation approach as shown in Figure 45.The AD5270/ AD5271 wiper switch is designed with the transmission gate CMOS topology. A RL Table 16. Minimize Power Dissipation at the SDO Pin DIN 0xXXXX 0x8001 AD5270/ AD5271 DIN U1 SDO Action Last user command sent to the digipot. Prepares the SDO pin to be placed in high impedance mode. The SDO pin is placed in high impedance. RL 8-/10-BIT ADDRESS DECODER RM RM SW RW W RW 08077-007 The serial data output pin (SDO) serves two purposes: it can be used to read the contents of the wiper setting and 50-TP values using Command 2 and Command 5, respectively (see Table 11), or the SDO pin can be used in daisy-chain mode. Data is clocked out of SDO on the rising edge of SCLK. The SDO pin contains an open-drain N-channel FET that requires a pull-up resistor. To place the pin in high impedance and mini-mize the power dissipation when the pin is used, the 0x8001 data word followed by Command 0 should be sent to the part. Table 16 provides a sample listing for the sequence of the serial data input (DIN). Daisy chaining minimizes the number of port pins required from the controlling IC. As shown in Figure 44, the user must tie the SDO pin of one package to the DIN pin of the next package. The user may need to increase the clock period because the pull-up resistor and the capacitive loading at the SDO-toDIN interface may require additional time delay between subsequent devices. When two AD5270/AD5271 devices are daisy-chained, 32 bits of data are required. The first 16 bits go to U2, and the second 16 bits go to U1. X is don’t care. Keep the SYNC pin low until all 32 bits are clocked to their respective serial registers. The SYNC pin is then pulled high to complete the operation. Rev. F | Page 21 of 24 Figure 45. Simplified RDAC Circuit AD5270/AD5271 Data Sheet PROGRAMMING THE VARIABLE RESISTOR TERMINAL VOLTAGE OPERATING RANGE Rheostat Operation—1% Resistor Tolerance The positive VDD and negative VSS power supplies of the AD5270/AD5271 define the boundary conditions for proper 2-terminal digital resistor operation. Supply signals present on Terminal A and Terminal W that exceed VDD or VSS are clamped by the internal forward-biased diodes, see Figure 47. VDD A The digitally programmed output resistance between the W terminal and the A terminal, RWA, is calibrated to give a maximum of ±1% absolute resistance error over both the full supply and temperature ranges. As a result, the general equations for determining the digitally programmed output resistance between the W terminal and the A terminal are the following: For the AD5270 RWA (D) D RWA 1024 (1) For the AD5271 RWA (D) D RWA 256 (2) where: D is the decimal equivalent of the binary code loaded in the 10-/8-bit RDAC register. RWA is the end-to-end resistance. W VSS Figure 47. Maximum Terminal Voltages Set by VDD and VSS The ground pins of the AD5270/AD5271 devices are primarily used as digital ground references. To minimize the digital ground bounce, join the AD5270/AD5271 ground terminal remotely to the common ground. The digital input control signals to the AD5270/AD5271 must be referenced to the device ground pin (GND), and must satisfy the logic level defined in the Specifications section. An internal level shift circuit ensures that the common-mode voltage range of the three terminals extends from VSS to VDD, regardless of the digital input level. POWER-UP SEQUENCE In the zero-scale condition, a finite total wiper resistance of 120 Ω is present. Regardless of which setting the part is operating in, take care to limit the current between Terminal A to Terminal W to the maximum continuous current of ±3 mA or a pulse current specified in Table 8. Otherwise, degradation or possible destruction of the internal switch contact can occur. EXT_CAP CAPACITOR A 1 μF capacitor to VSS must be connected to the EXT_CAP pin, as shown in Figure 46, on power-up and throughout the operation of the AD5270/AD5271. Because there are diodes to limit the voltage compliance at Terminal A and Terminal W (see Figure 47), it is important to power VDD/VSS first before applying any voltage to Terminal A and Terminal W; otherwise, the diode is forward-biased such that VDD/VSS are powered unintentionally. The ideal power-up sequence is VSS, GND, VDD, digital inputs, VA, and VW. The order of powering VA, VW, and the digital inputs is not important as long as they are powered after VDD/VSS. As soon as VDD is powered, the power-on preset activates which first sets the RDAC to midscale and then restores the last programmed 50-TP value to the RDAC register. AD5270/ AD5271 EXT_CAP C1 1µF 50_OTP MEMORY BLOCK 08077-008 VSS VSS 08077-009 The nominal resistance between Terminal W and Terminal A, RWA, is 20 kΩ, 50 kΩ, or 100 kΩ and has 1024-/256-tap points accessed by the wiper terminal. The 10-/8-bit data in the RDAC latch is decoded to select one of the 1024 or 256 possible wiper settings. The AD5270 and AD5271 contain an internal ±1% resistor tolerance calibration feature that can be disabled or enabled, enabled by default, or by programming Bit C2 of the control register (see Table 13 and Table 14). Figure 46. EXT_CAP Hardware Setup Rev. F | Page 22 of 24 Data Sheet AD5270/AD5271 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 0.70 0.55 0.40 0.23 0.13 6° 0° 091709-A 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 48. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 10 6 1.74 1.64 1.49 EXPOSED PAD 0.50 0.40 0.30 1 5 BOTTOM VIEW TOP VIEW 0.80 0.75 0.70 SEATING PLANE 0.30 0.25 0.20 0.05 MAX 0.02 NOM COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF Figure 49. 10-Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3 mm Body, Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters Rev. F | Page 23 of 24 0.20 MIN PIN 1 INDICATOR (R 0.15) 02-05-2013-C PIN 1 INDEX AREA AD5270/AD5271 Data Sheet ORDERING GUIDE Model 1 AD5270BRMZ-20 AD5270BRMZ-20-RL7 AD5270BRMZ-50 AD5270BRMZ-50-RL7 AD5270BRMZ-100 AD5270BRMZ-100-RL7 AD5270BCPZ-20-RL7 AD5270BCPZ-100-RL7 AD5271BRMZ-20 AD5271BRMZ-20-RL7 AD5271BRMZ-100 AD5271BRMZ-100-RL7 AD5271BCPZ-20-RL7 AD5271BCPZ-100-RL7 EVAL-AD5270SDZ 1 RAW (kΩ) 20 20 50 50 100 100 20 100 20 20 100 100 20 100 Resolution 1,024 1,024 1,024 1,024 1,024 1,024 1,024 1,024 256 256 256 256 256 256 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Z = RoHS Compliant Part. ©2009–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08077-0-3/13(F) Rev. F | Page 24 of 24 Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead LFCSP_WD 10-Lead LFCSP_WD Evaluation Board Package Option RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 CP-10-9 CP-10-9 RM-10 RM-10 RM-10 RM-10 CP-10-9 CP-10-9 Branding D1X D1X DDP DDP D1W D1W DDY DDX DE0 DE0 DDZ DDZ DE2 DE1