Single-Channel, 1024-Position, 1% R-Tolerance Digital Potentiometer AD5293 FEATURES Single-channel, 1024-position resolution 20 kΩ nominal resistance Calibrated 1% nominal resistor tolerance (resistor performance mode mode) Rheostat mode temperature coefficient: 35 ppm/°C Voltage divider temperature coefficient: 5 ppm/°C Single-supply operation: 9 V to 33 V Dual-supply operation: ±9 V to ±16.5 V SPI-compatible serial interface Wiper setting readback FUNCTIONAL BLOCK DIAGRAM VDD RESET POWER-ON RESET AD5293 VLOGIC 10 SCLK SYNC RDAC REGISTER SERIAL INTERFACE A W DIN B SDO Mechanical potentiometer replacement Instrumentation: gain and offset adjustment Programmable voltage-to-current conversion Programmable filters, delays, and time constants Programmable power supply Low resolution DAC replacement Sensor calibration RDY VSS EXT_CAP GND 07675-001 APPLICATIONS Figure 1. GENERAL DESCRIPTION The AD5293 is a single-channel, 1024-position digital potentiometer1 with <1% end-to-end resistor tolerance error. The AD5293 performs the same electronic adjustment function as a mechanical potentiometer with enhanced resolution, solid state reliability, and superior low temperature coefficient performance. This device is capable of operating at high voltages and supporting both dual-supply operation at ±10.5 V to ±15 V and single-supply operation at 21 V to 30 V. 1 In this data sheet, the terms digital potentiometer and RDAC are used interchangeably. The AD5293 offers guaranteed industry-leading low resistor tolerance errors of ±1% with a nominal temperature coefficient of 35 ppm/°C. The low resistor tolerance feature simplifies open-loop applications as well as precision calibration and tolerance matching applications. The AD5293 is available in a compact 14-lead TSSOP package. The part is guaranteed to operate over the extended industrial temperature range of −40°C to +105°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. AD5293 TABLE OF CONTENTS Features ...............................................................................................1 Write Protection ......................................................................... 14 Applications ........................................................................................1 Basic Operation .......................................................................... 14 Functional Block Diagram ...............................................................1 Shutdown Mode.......................................................................... 14 General Description ..........................................................................1 Reset ............................................................................................. 15 Revision History ................................................................................2 Resistor Performance Mode ...................................................... 15 Specifications......................................................................................3 Daisy-Chain Operation ............................................................. 15 Electrical Characteristics ..............................................................3 RDAC Architecture .................................................................... 16 Resistor Performance (R-PERF) Mode Code Range ................4 Programming the Variable Resistor ......................................... 16 Interface Timing Specifications ...................................................5 Programming the Potentiometer Divider ............................... 16 Timing Diagrams...........................................................................6 EXT_CAP Capacitor .................................................................. 17 Absolute Maximum Ratings.............................................................7 Terminal Voltage Operating Range.......................................... 17 Thermal Resistance .......................................................................7 Applications Information .............................................................. 18 ESD Caution ...................................................................................7 High Voltage DAC ...................................................................... 18 Pin Configuration and Function Descriptions ..............................8 Programmable Voltage Source with Boosted Output............ 18 Typical Performance Characteristics ..............................................9 High Accuracy DAC .................................................................. 18 Test Circuits ..................................................................................... 13 Audio Volume Control .............................................................. 19 Theory of Operation ...................................................................... 14 Outline Dimensions ....................................................................... 20 Serial Data Interface ................................................................... 14 Ordering Guide........................................................................... 20 Shift Register ............................................................................... 14 RDAC Register ............................................................................ 14 REVISION HISTORY 4/09—Revision 0: Initial Version Rev. 0 | Page 2 of 20 AD5293 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VDD = 21 V to 33 V, VSS = 0 V; VDD = 10.5 V to 16.5 V, VSS = −10.5 V to −16.5 V; VLOGIC = 2.7 V to 5.5 V, VA = VDD, VB = VSS, −40°C < TA < +105°C, unless otherwise noted. Table 1. Parameter DC CHARACTERISTICS, RHEOSTAT MODE Resolution Resistor Differential Nonlinearity 2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance (R-Perf Mode) 3 Nominal Resistor Tolerance (Normal Mode) Resistance Temperature Coefficient 4 Wiper Resistance DC CHARACTERISTICS, POTENTIOMETER DIVIDER MODE Resolution Differential Nonlinearity 5 Integral Nonlinearity5 Voltage Divider Temperature Coefficient4 Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Terminal Voltage Range 6 Capacitance A, Capacitance B4 Capacitance W4 Common-Mode Leakage Current DIGITAL INPUTS Input Logic High Input Logic Low Input Current Input Capacitance4 DIGITAL OUTPUTS (SDO and RDY) Output High Voltage Output Low Voltage Tristate Leakage Current Output Capacitance4 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Negative Supply Current Logic Supply Range Logic Supply Current Power Dissipation 7 Power Supply Rejection Ratio4 Symbol Conditions Min N R-DNL R-INL R-INL ∆RAB/RAB RWB |VDD − VSS | = 26 V to 33 V |VDD − VSS | = 21 V to 26 V See Table 2 10 −1 −2 −3 −1 Typ 1 Max Unit ±0.5 +1 +2 +3 +1 Bits LSB LSB LSB % ∆RAB/RAB ±20 % (∆RAB/RAB)/∆T × 106 35 ppm/°C RW 60 N DNL INL (∆VW/VW)/∆T × 106 Code = half scale VWFSE VWZSE Code = full scale Code = zero scale VA, VB, VW CA, CB CW ICM 100 Ω +1 +1.5 Bits LSB LSB ppm/°C 0 8 LSB LSB VDD 50 V pF 65 pF 10 −1 −1.5 5 −8 0 VSS f = 1 MHz, measured to GND, code = half-scale f = 1 MHz, measured to GND, code = half-scale VA = VB = VW VIH VIL IIL CIL VLOGIC = 2.7 V to 5.5 V VLOGIC = 2.7 V to 5.5 V VIN = 0 V or VLOGIC VOH VOL RPULL_UP = 2.2 kΩ to VLOGIC RPULL_UP = 2.2 kΩ to VLOGIC ±1 JEDEC compliant 2.0 V V μA pF GND + 0.4 +1 V V μA pF VLOGIC − 0.4 −1 VDD VDD/VSS IDD ISS VLOGIC ILOGIC PDISS PSSR 0.8 ±1 5 COL 5 VSS = 0 V VDD/VSS = ±16.5 V VDD/VSS = ±16.5 V VLOGIC = 5 V; VIH = 5 V, or VIL = GND VIH = 5 V, or VIL = GND ∆VDD/∆VSS = ±15 V ± 10% Rev. 0 | Page 3 of 20 9 ±9 −2 2.7 0.1 −0.1 1 8 0.025 nA 33 ±16.5 2 5.5 10 110 0.08 V V μA μA V μA μW %/% AD5293 Parameter DYNAMIC CHARACTERISTICS4, 8 Bandwidth Total Harmonic Distortion VW Settling Time Resistor Noise Density Symbol Conditions BW THDW tS −3 dB VA = 1 V rms, VB = 0 V, f = 1 kHz, VA = 30 V, VB = 0 V, ±0.5 LSB error band, initial code = zero scale Code = full scale, normal mode Code = full scale, R-Perf mode Code = half scale, normal mode Code = half scale, R-Perf mode RWB = 10 kΩ, TA = 25°C, 0 kHz to 200 kHz eN_WB Min Typ 1 Max Unit 520 −93 kHz dB 750 2.5 2.5 5 0.11 ns μs μs μs nV/√Hz 1 Typicals represent average readings at 25°C; VDD = +15 V, VSS = −15 V, and VLOGIC = 5 V. Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between the RWB at Code 0x02 and the RWB at Code 0xFF or between RWA at Code 0xFD and RWA at Code 0x00. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode with a wiper current of 1 mA for VA < 12 V and 1.2 mA for VA ≥ 12 V. 3 The terms resistor performance mode and R-Perf mode are used interchangeably. 4 Guaranteed by design; not subject to production test. 5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 6 The A, B, and W resistor terminals have no limitations on polarity with respect to each other. Dual-supply operation enables ground-referenced bipolar signal adjustment. 7 PDISS is calculated from (IDD × VDD) + (ISS × VSS) + (ILOGIC × VLOGIC). 8 All dynamic characteristics use VDD = +15 V, VSS = −15 V, and VLOGIC = 5 V. 2 RESISTOR PERFORMANCE (R-PERF) MODE CODE RANGE Table 2. Resistor Tolerance per Code 1% R-Tolerance 2% R-Tolerance 3% R-Tolerance |VDD − VSS| = 30 V to 33 V RWB From 0x15E to 0x3FF From 0x8C to 0x3FF From 0x5A to 0x3FF RWA From 0x00 to 0x2A1 From 0x00 to 0x373 From 0x00 to 0x3A5 |VDD − VSS| = 26 V to 30 V RWB From 0x1F4 to 0x3FF From 0xB4 to 0x3FF From 0x64 to 0x3FF RWA From 0x00 to 0x20B From 0x00 to 0x34B From 0x00 to 0x39B Rev. 0 | Page 4 of 20 |VDD − VSS| = 22 V to 26 V RWB From 0x1F4 to 0x3FF From 0xFA to 0x3FF From 0x78 to 0x3FF RWA From 0x00 to 0x20B From 0x00 to 0x305 From 0x00 to 0x387 |VDD − VSS| = 21 V to 22 V RWB N/A RWA N/A From 0xFA to 0x3FF From 0x78 to 0x3FF From 0x00 to 0x305 From 0x00 to 0x387 AD5293 INTERFACE TIMING SPECIFICATIONS VDD = VSS = ±15 V, VLOGIC = 2.7 V to 5.5 V, and −40°C < TA < +105°C. All specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter t1 2 t2 t3 t4 t5 t6 t7 t8 t9 t10 4 t114 t124 t134 t144 tRESET tPOWER-UP 5 Limit 1 20 10 10 10 5 5 1 400 3 14 1 40 2.4 410 1.5 450 450 20 2 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max μs max ns max ms max ns max ns max ns min ms max Test Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to next SCLK falling edge ignore RDY rise to SYNC falling edge SYNC rise to RDY fall time RDY low time, RDAC register write command execute time (R-Perf mode) RDY low time, RDAC register write command execute time (normal mode) Software\hardware reset RDY low time, RDAC register read command execute time SCLK rising edge to SDO valid Minimum RESET pulse width (asynchronous) Power-on time to half scale 1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Maximum SCLK frequency = 50 MHz. 3 Refer to t12 and t13 for RDAC register command operations. 4 RPULL_UP = 2.2 kΩ to VLOGIC with a capacitance load of 168 pF. 5 Typical power supply voltage slew rate of 2 ms/V. 2 0 0 C3 C2 C1 C0 D9 D8 DB0 (LSB) D7 D6 D5 D4 DATA BITS CONTROL BITS Figure 2. Shift Register Contents Rev. 0 | Page 5 of 20 D3 D2 D1 D0 07675-002 DB9 (MSB) AD5293 TIMING DIAGRAMS t4 SCLK t2 t7 t1 t9 t3 t8 SYNC t5 t6 X X C3 C2 D7 D6 D2 D1 D0 SDO t11 t10 t12 RDY tRESET 07675-003 DIN RESET Figure 3. Write Timing Diagram SCLK t9 SYNC DIN X X C3 D0 D0 X X C3 D1 D0 t14 X t11 RDY t13 Figure 4. Read Timing Diagram Rev. 0 | Page 6 of 20 X C3 D1 D0 07675-004 SDO AD5293 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4 Parameter VDD to GND VSS to GND VLOGIC to GND VDD to VSS VA, VB, VW to GND IA, IB, IW Pulsed 1 Frequency >10 kHz Frequency ≤10 kHz Continuous Digital Input and Output Voltage to GND EXT_CAP Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJ max) Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Package Power Dissipation Rating –0.3 V to +35 V +0.3 V to −16.5 V –0.3 V to +7 V 35 V VSS − 0.3 V, VDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE 2 ±3 mA/d ±3 mA/√d2 ±3 mA –0.3 V to VLOGIC +0.3 V –0.3 V to +7 V −40°C to +105°C 150°C −65°C to +150°C θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance Package Type 14-Lead TSSOP 1 θJA 931 θJC 20 Unit °C/W JEDEC 2s2p test board, still air (from 0 m/sec to 1 m/sec of airflow). ESD CAUTION 260°C 20 sec to 40 sec (TJ max − TA)/θJA 1 Maximum terminal current is bounded by the maximum current handling of the switches, the maximum power dissipation of the package, and the maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 d = pulse duty factor. Rev. 0 | Page 7 of 20 AD5293 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RESET 1 14 RDY VSS 2 W 4 B 5 13 SDO AD5293 TOP VIEW Not to Scale 12 SYNC 11 SCLK 10 DIN VDD 6 9 GND EXT_CAP 7 8 VLOGIC 07675-005 A 3 Figure 5. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 Mnemonic RESET 2 VSS 3 4 5 6 7 8 9 10 A W B VDD EXT_CAP VLOGIC GND DIN 11 SCLK 12 SYNC 13 SDO 14 RDY Description Hardware Reset. Sets the RDAC register to midscale. RESET is activated at the logic high transition. Tie RESET to VLOGIC if not used. Negative Supply. Connect to 0 V for single-supply applications. This pin should be decoupled with 0.1 µF ceramic capacitors and 10 µF capacitors. Terminal A of RDAC. VSS ≤ VA ≤ VDD. Wiper Terminal W of RDAC. VSS ≤ VW ≤ VDD. Terminal B of RDAC. VSS ≤ VB ≤ VDD. Positive Power Supply. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors. Connect a 1 μF capacitor to EXT_CAP. This capacitor must have a voltage rating of ≥7 V. Logic Power Supply, 2.7 V to 5.5 V. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors. Ground, Logic Ground Reference. Serial Data Input. This part has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC goes low, it enables the shift register, and data is transferred in on the falling edges of the following clocks. The selected register is updated on the rising edge of SYNC, following the 16th clock cycle. If SYNC is taken high before the 16th clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC. Serial Data Output. This open-drain output requires an external pull-up resistor. SDO can be used to clock data from the serial register in daisy-chain mode or in readback mode. Ready. This active-high, open-drain output identifies the completion of a write or read operation to or from the RDAC register. Rev. 0 | Page 8 of 20 AD5293 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.15 –40°C +25°C +105°C 0.8 0.6 0.10 0.05 0.2 DNL (LSB) INL (LSB) 0.4 0 –0.2 –0.4 0 –0.05 –0.10 –0.6 –0.15 0 128 256 384 512 640 768 896 1024 CODE (Decimal) 0 128 256 +105°C +25°C –40°C –0.20 07675-106 –1.0 384 512 640 768 896 1024 CODE (Decimal) Figure 6. R-INL in R-Perf Mode vs. Code vs. Temperature 07675-011 –0.8 Figure 9. R-DNL in Normal Mode vs. Code vs. Temperature 0.6 1.5 0.5 1.0 0.4 0.5 INL (LSB) DNL (LSB) 0.3 0.2 0.1 0 0 –0.5 –0.1 –1.0 –0.2 256 384 512 640 768 896 1024 CODE (Decimal) 0 256 384 512 640 768 896 1024 CODE (Decimal) Figure 7. R-DNL in R-Perf Mode vs. Code vs. Temperature Figure 10. INL in R-Perf Mode vs. Code vs. Temperature 0.6 0.8 0.5 0.6 0.4 0.4 0.3 DNL (LSB) 1.0 0.2 0 0.2 0.1 0 –0.2 –0.1 –0.6 0 128 256 +105°C +25°C –40°C 384 512 640 768 896 1024 CODE (Decimal) Figure 8. R-INL in Normal Mode vs. Code vs. Temperature 0 128 256 +105°C +25°C –40°C –0.2 384 512 640 768 896 CODE (Decimal) Figure 11. DNL in R-Perf Mode vs. Code vs. Temperature Rev. 0 | Page 9 of 20 1024 07675-015 –0.4 07675-010 INL (LSB) 128 +105°C +25°C –40°C –1.5 07675-014 128 07675-007 0 +105°C +25°C –40°C –0.3 AD5293 700 0.4 0 –0.2 –0.4 –0.8 0 128 256 384 512 640 768 896 1024 CODE (Decimal) 400 300 200 100 0 07675-018 –0.6 500 0 768 700 0.10 POTENTIOMETER MODE TEMPCO (ppm/°C) –40°C +25°C +105°C 0.05 0 DNL (LSB) 512 CODE (Decimal) –0.05 –0.10 –0.15 500 400 300 200 100 256 384 512 640 768 896 1024 CODE (Decimal) 07675-019 128 VDD = 30V, VSS = 0V 600 0 –0.20 0 1024 Figure 15. Rheostat Mode Tempco ΔRWB/ΔT vs. Code Figure 12. INL in Normal Mode vs. Code vs. Temperature 0 256 512 768 1024 CODE (Decimal) Figure 16. Potentiometer Mode Tempco ΔRWB/ΔT vs. Code Figure 13. DNL in Normal Mode vs. Code vs. Temperature 0 450 VDD/VSS = ±15V VLOGIC = +5V 400 350 –4 0x200 –8 ILOGIC 300 GAIN (dB) 250 200 150 –12 0x100 –18 0x080 –24 0x040 –28 –32 0x020 –36 100 50 TEMPERATURE (°C) 0x004 0x002 –50 ISS 10 20 30 40 50 60 70 80 90 100 0x008 –44 0 –50 –40 –30 –20 –10 0 0x010 –40 IDD 07675-022 SUPPLY CURRENT (nA) 256 0x001 –54 1 10 100 1k 10k 100k FREQUENCY (Hz) Figure 17. 20 kΩ Gain vs. Frequency vs. Code Figure 14. Supply Current vs. Temperature Rev. 0 | Page 10 of 20 1M 07675-025 INL (LSB) 0.2 VDD = 30V, VSS = 0V 600 07675-024 0.6 RHEOSTAT MODE TEMPCO (ppm/°C) –40°C +25°C +105°C 07675-023 0.8 AD5293 8 68 64 THEORETICAL IWB_MAX (mA) 56 52 48 44 40 36 32 28 24 VDD/VSS = ±15V CODE = HALF SCALE VLOGIC = +5V 12 8 0.01 0.1 1 4 3 2 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) 0 07675-026 16 5 0 1024 1.0 VDD/VSS = ±15V CODE = HALF SCALE VIN = 1V rms VDD = ±15V 0.9 –70 THD + N (dB) 768 Figure 21. Theoretical Maximum Current vs. Code SUPPLY CURRENT I LOGIC (mA) –68 512 CODE (Decimal) Figure 18. Power Supply Rejection Ratio vs. Frequency –66 256 07675-029 20 6 –72 –74 –76 –78 –80 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 1k 10k 100k FREQUENCY (Hz) 0 07675-027 –82 100 0 Figure 19. Total Harmonic Distortion + Noise (THD + N) vs. Frequency 0 1.0 1.5 2.0 2.5 3.0 3.5 DIGITAL INPUT VOLTAGE (V) 4.0 4.5 5.0 Figure 22. Supply Current, ILOGIC, vs. Digital Input Voltage 35 VDD/VSS = ±15V, CODE = HALF SCALE fIN = 1kHz –10 0.5 07675-131 PSRR (dB) VDD/VSS = 30V/0V VA = VDD VB = VSS 7 60 VWB, CODE: FULL SCALE, NORMAL MODE 30 –20 VWB, CODE: FULL SCALE, R-PERF MODE 25 10 –70 5 –80 0 Figure 20. THD + Noise vs. Amplitude TIME (µs) 8.9 8.3 7.7 7.1 6.5 6.0 5.4 4.8 4.2 3.6 3.1 –5 2.5 AMPLITUDE (V) 10 1.9 1 1.3 0.1 VDD/VSS = 30V/0V VLOGIC = 5V VA = VDD VB = VSS SYNC 0.7 0.01 –1.0 –90 0.001 VWB, CODE: HALF SCALE, R-PERF MODE 0.2 –60 VWB, CODE: HALF SCALE, NORMAL MODE 15 –0.4 –50 20 07675-133 VOLTAGE (V) –40 07675-028 THD + N (dB) –30 Figure 23. Large-Signal Settling Time, Code from Zero Scale to Full Scale Rev. 0 | Page 11 of 20 AD5293 1.2 300 VDD/VSS = ±15V VLOGIC = +5V VA = VDD VB = VSS 1.0 0.8 250 NUMBER OF CODES 0.6 0.4 0.2 0 –0.2 –0.4 200 150 100 50 TIME (µs) 0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (°C) Figure 25. Code Range > 1% R-Tolerance Error vs. Temperature Figure 24. Maximum Transition Glitch Rev. 0 | Page 12 of 20 07675-056 –0.8 07675-135 –0.6 –0.4 –0.2 –0.1 0.1 0.2 0.4 0.5 0.7 0.8 1.0 1.1 1.3 1.4 1.6 1.7 1.9 2.0 2.2 2.3 2.5 2.6 2.8 2.9 3.1 3.2 3.4 3.6 VOLTAGE (V) VDD/VSS = ±15V AD5293 TEST CIRCUITS Figure 26 to Figure 31 define the test conditions used in the Specifications section. NC IW VA VMS V+ ~ W DUT 2.5V Figure 27. Potentiometer Divider Nonlinearity Error (INL, DNL) B + IWB A = NC – RW = 2 0.1V VSS TO VDD GND GND 0.1V IWB RWB VDD DUT A VSS GND B ICM W +15V –15V GND NC 07675-032 CODE = 0x00 W –15V –15V NC RWB = VOUT Figure 30. Gain vs. Frequency +15V DUT OP42 B OFFSET GND 07675-036 VIN W VMS ΔVMS% ΔVDD% +15V A V+ = VDD 1LSB = V+/2N B PSS (%/%) = VMS 07675-031 A W Figure 29. Power Supply Sensitivity (PSS, PSRR) Figure 26. Resistor Position Nonlinearity Error (Rheostat Operation: R-INL, R-DNL) V+ V+ = VDD ± 10% ΔVMS PSRR (dB) = 20 log ΔV DD B 07675-030 NC = NO CONNECT DUT A 07675-033 VDD B +15V Figure 28. Wiper Resistance GND NC = NO CONNECT –15V Figure 31. Common-Mode Leakage Current Rev. 0 | Page 13 of 20 07675-037 DUT A W AD5293 THEORY OF OPERATION The AD5293 digital potentiometer is designed to operate as a true variable resistor for analog signals that remain within the terminal voltage range of VSS < VTERM < VDD. The patented ±1% resistor tolerance feature helps to minimize the total RDAC resistance error, which reduces the overall system error by offering better absolute matching and improved open-loop performance. The digital potentiometer wiper position is determined by the RDAC register contents. The RDAC register acts as a scratchpad register, allowing as many value changes as necessary to place the potentiometer wiper in the correct position. The RDAC register can be programmed with any position setting via the standard serial peripheral interface (SPI) by loading the 16-bit data-word. SERIAL DATA INTERFACE WRITE PROTECTION On power-up, the serial data input register write command for the RDAC register is disabled. The RDAC write protect bit, C1 of the control register (see Table 9 and Table 10), is set to 0 by default. This disables any change of the RDAC register content, regardless of the software commands, except that the RDAC register can be refreshed to midscale using the software reset command (Command 3, see Table 8) or through hardware, using the RESET pin. To enable programming of the variable resistor wiper position (programming the RDAC register), the write protect bit, C1 of the control register, must first be programmed. This is accomplished by loading the serial data input register with Command 4 (see Table 8). BASIC OPERATION The AD5293 contains a serial interface (SYNC, SCLK, DIN, and SDO) that is compatible with SPI standards, as well as most DSPs. The device allows data to be written to every register via the SPI. SHIFT REGISTER The AD5293 shift register is 16 bits wide (see Figure 2). The 16-bit data-word consists of two unused bits, which are set to 0, followed by four control bits and 10 RDAC data bits. Data is loaded MSB first (Bit DB15). The four control bits determine the function of the software command (see Table 8). Figure 3 shows a timing diagram of a typical write sequence. The write sequence begins by bringing the SYNC line low. The SYNC pin must be held low until the complete data-word is loaded from the DIN pin. When SYNC returns high, the serial data-word is decoded according to the instructions in Table 8. The command bits (Cx) control the operation of the digital potentiometer. The data bits (Dx) are the values that are loaded into the decoded register. The AD5293 has an internal counter that counts a multiple of 16 bits (per frame) for proper operation. For example, the AD5293 works with a 32-bit word, but it cannot work properly with a 31- or 33-bit word. The AD5293 does not require a continuous SCLK, when SYNC is high, and all interface pins should be operated close to the supply rails to minimize power consumption in the digital input buffers. The basic mode of setting the variable resistor wiper position (programming the RDAC register) is accomplished by loading the serial data input register with Command 1 (see Table 8) and the desired wiper position data. The RDY pin can be used to monitor the completion of this RDAC register write command. Command 2 can be used to read back the contents of the RDAC register (see Table 8). After issuing the readback command, the RDY pin can be monitored to indicate when the data is available to be read out on SDO in the next SPI operation. Instead of monitoring the RDY pin, a minimum delay can be implemented when executing a write or read command (see Table 3). Table 7 provides an example listing of a sequence of serial data input (DIN) words with the serial data output appearing at the SDO pin in hexadecimal format for an RDAC write and read. Table 7. RDAC Register Write and Read Example DIN 0x1802 0x0500 SDO 0xXXXX1 0x1802 0x0800 0x0000 0x0500 0x0100 1 RDAC REGISTER The RDAC register directly controls the position of the digital potentiometer wiper. For example, when the RDAC register is loaded with all 0s, the wiper is connected to Terminal B of the variable resistor. The RDAC register is a standard logic register; there is no restriction on the number of changes allowed. The RDY pin can be used to monitor the completion of a write to or read from the RDAC register. The AD5293 presets to mid-scale on power-up. Action Enable update of wiper position. Write 0x100 to the RDAC register. Wiper moves to ¼ full-scale position. Prepare data read from RDAC register. NOP (Instruction 0) sends a 16-bit word out of SDO, where the last 10 bits contain the contents of the RDAC register. X = unknown. SHUTDOWN MODE The AD5293 can be placed in shutdown mode by executing the software shutdown command (see Command 6 in Table 8) and then setting the LSB to 1. This feature places the RDAC in a special state in which Terminal A is open-circuited and Wiper W is connected to Terminal B. The contents of the RDAC register are unchanged by entering shutdown mode. However, all commands listed in Table 8 are supported while in shutdown mode. Rev. 0 | Page 14 of 20 AD5293 The SDO pin contains an open-drain N-channel FET that requires a pull-up resistor, if this function is used. As shown in Figure 32, the SDO pin of one package must be tied to the DIN pin of the next package. Users may need to increase the clock period because the pull-up resistor and the capacitive loading at the SDO/DIN interface may require an additional time delay between subsequent devices. RESET A low-to-high transition of the hardware RESET pin loads the RDAC register with midscale. The AD5293 can also be reset through software by executing Command 3 (see Table 8). The control register is restored with default settings (see Table 10). RESISTOR PERFORMANCE MODE This mode activates a new, patented 1% end-to-end resistor tolerance that ensures a ±1% resistor tolerance on each code, that is, code = half scale, RWB = 10 kΩ ± 100 Ω. See Table 2 to verify which codes achieve ±1% resistor tolerance. The resistor performance mode is activated by programming Bit C2 of the control register (see Table 9 and Table 10). The typical settling time is shown in Figure 23. When two AD5293 devices are daisy-chained, 32 bits of data are required. The first 16 bits go to U2, and the second 16 bits go to U1. The SYNC pin should be held low until all 32 bits are clocked into their respective serial registers. The SYNC pin is then pulled high to complete the operation. VLOGIC AD5293 DAISY-CHAIN OPERATION MOSI MICROCONTROLLER SCLK SS The serial data output pin (SDO) serves two purposes. It can be used to read the contents of the wiper setting, using Command 2 (see Table 8), or it can be used for daisy-chaining multiple devices. The remaining instructions are valid for daisy-chaining multiple devices in simultaneous operations. Daisy chaining minimizes the number of port pins required from the controlling IC. DIN AD5293 DIN SDO U2 SYNC SCLK SDO SCLK 07675-039 SYNC U1 RP 2.2kΩ Figure 32. Daisy-Chain Configuration Using SDO Table 8. Command Operation Truth Table D7 X D7 Data Bits[B9:B0] 1 D6 D5 D4 D3 X X X X D6 D5 D4 D3 D2 X D2 D1 X D1 D0 X D0 X X X X X X X X X X X X X X X X X X X X X X X X D2 X D1 X X 1 X X X X X X X X X X 0 X X X X X X X X X D0 Command 0 1 Command Bits[B13:B10] C3 C2 C1 C0 0 0 0 0 0 0 0 1 D9 X D9 D8 X D8 2 0 0 1 0 X 3 4 0 0 1 1 0 1 0 0 5 0 1 1 6 1 0 0 1 Operation NOP command. Do nothing. Write contents of serial register data to RDAC. Read RDAC wiper setting from SDO output in the next frame. Reset. Refresh RDAC with midscale code. Write contents of serial register data to control register. Read control register from SDO output in the next frame. Software power-down. D0 = 0 (normal mode). D0 = 1 (device placed in shutdown mode). X = don’t care. Table 9. Control Register Bit Map D9 X1 1 D8 X1 D7 X1 D6 X1 D5 X1 D4 X1 D3 X1 D2 C2 X = don’t care. Table 10. Control Register Bit Descriptions Register Name Control Bit Name C2 C1 Description Calibration enable. 0 = Resistor Performance Mode (default). 1 = Normal Mode. RDAC register write protect. 0 = locks the wiper position through the digital interface (default). 1 = allows update of wiper position through digital interface. Rev. 0 | Page 15 of 20 D1 C1 D0 X1 AD5293 RDAC ARCHITECTURE To achieve optimum cost performance, Analog Devices, Inc., has patented the RDAC segmentation architecture for all the digital potentiometers. In particular, the AD5293 employs a three-stage segmentation approach, as shown in Figure 33. The AD5293 wiper switch is designed with transmission gate CMOS topology and with the gate voltage derived from VDD. A where: D is the decimal equivalent of the binary code loaded in the 10-bit RDAC register. RAB is the end-to-end resistance. RL RM Similar to the mechanical potentiometer, the resistance of the RDAC between the W terminal and the A terminal also produces a digitally controlled complementary resistance, RWA. RWA is also calibrated to give a maximum of 1% absolute resistance error. RWA starts at the maximum resistance value and decreases as the data loaded into the latch increases. The general equation for this operation is SW RM RW W RW 10-BIT ADDRESS DECODER RM RL RWA (D) = RM RL 07675-040 B Figure 33. Simplified RDAC Circuit PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation—1% Resistor Tolerance The AD5293 operates in rheostat mode when only two terminals are used as a variable resistor. The unused terminal can be left floating or can be tied to the W terminal as shown in Figure 34. A W B A W B (2) where: D is the decimal equivalent of the binary code loaded in the 10-bit RDAC register. RAB is the end-to-end resistance. In the zero-scale condition, a finite total wiper resistance of 120 Ω is present. Regardless of the setting in which the part is operating, care should be taken to limit the current between the A terminal and B terminal, the W terminal and A terminal, and the W terminal and B terminal to the maximum continuous current of ±3 mA or to the pulse current specified in Table 4. Otherwise, degradation, or possible destruction of the internal switch contact, can occur. PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation W B 07675-041 A 1024 − D × R AB 1024 Figure 34. Rheostat Mode Configuration The nominal resistance between Terminal A and Terminal B, RAB, is available in 20 kΩ and has 1024 tap points that are accessed by the wiper terminal. The 10-bit data in the RDAC latch is decoded to select one of the 1024 possible wiper settings. The AD5293 contains an internal ±1% resistor tolerance calibration feature that can be enabled or disabled (enabled by default) by programming Bit C2 of the control register (see Table 9 and Table 10). The digital potentiometer easily generates a voltage divider at the wiper-to-B terminal and the wiper-to-A terminal that is proportional to the input voltage at A to B, as shown in Figure 35. Unlike the polarity of VDD to GND, which must be positive, voltage across A to B, W to A, and W to B can be at either polarity. Rev. 0 | Page 16 of 20 VIN A W B VOUT 07675-042 RL The digitally programmed output resistance between the W terminal and the A terminal, RWA, and the W terminal and B terminal, RWB, is calibrated to give a maximum of ±1% absolute resistance error over both the full supply and temperature ranges. As a result, the general equation for determining the digitally programmed output resistance between the W terminal and B terminal is D (1) RWB (D ) = × R AB 1024 Figure 35. Potentiometer Mode Configuration AD5293 If ignoring the effect of the wiper resistance for simplicity, connecting the A terminal to 30 V and the B terminal to ground produces an output voltage at the Wiper W to Terminal B that ranges from 0 V to 30 V − 1 LSB. Each LSB of voltage is equal to the voltage applied across the A terminal and B terminal, divided by the 1024 positions of the potentiometer divider. The general equation defining the output voltage at VW, with respect to ground for any valid input voltage applied to Terminal A and Terminal B, is 1024 − D D ×VA + ×VB 1024 1024 The positive VDD and negative VSS power supplies of the AD5293 define the boundary conditions for proper 3-terminal, digital potentiometer operation. Supply signals present on the A, B, and W terminals that exceed VDD or VSS are clamped by the internal forward-biased diodes (see Figure 37). VDD (3) A To optimize the wiper position update rate when in voltage divider mode, it is recommended that the internal ±1% resistor tolerance calibration feature be disabled by programming Bit C2 of the control register (see Table 9 and Table 10). Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike when the part is in the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors, RWA and RWB, not on the absolute values. Therefore, the temperature drift reduces to 5 ppm/°C. EXT_CAP CAPACITOR A 1 μF capacitor to GND must be connected to the EXT_CAP pin (see Figure 36) on power-up and throughout the operation of the AD5293. This capacitor must have a voltage rating of ≥7 V. AD5293 C1 1µF EXT_CAP 07675-043 GND Figure 36. Hardware Setup for the EXT_CAP Pin W B VSS 07675-044 VW (D) = TERMINAL VOLTAGE OPERATING RANGE Figure 37. Maximum Terminal Voltages Set by VDD and VSS The ground pin of the AD5293 is primarily used as a digital ground reference. To minimize the digital ground bounce, the AD5293 ground pin should be joined remotely to common ground. The digital input control signals to the AD5293 must be referenced to the device ground pin (GND) to satisfy the logic level defined in the Specifications section. Power-Up Sequence Because there are diodes to limit the voltage compliance at the A, B, and W terminals (see Figure 37), it is important to power VDD and VSS first, before applying any voltage to the A, B, and W terminals. Otherwise, the diode is forward-biased such that VDD and VSS are powered up unintentionally. The ideal power-up sequence is GND, VSS, VLOGIC, VDD, the digital inputs, and then VA, VB, and VW. The order of powering up VA, VB, VW, and the digital inputs is not important, as long as they are powered after VDD, VSS, and VLOGIC. Regardless of the power-up sequence and the ramp rates of the power supplies, the power-on preset activates after VLOGIC is powered, restoring midscale to the RDAC register. Rev. 0 | Page 17 of 20 AD5293 APPLICATIONS INFORMATION HIGH VOLTAGE DAC HIGH ACCURACY DAC The AD5293 can be configured as a high voltage DAC, with output voltage as high as 33 V. The circuit is shown in Figure 38. The output is It is possible to configure the AD5293 as a high accuracy DAC by optimizing the resolution of the device over a specific reduced voltage range. This is achieved by placing external resistors on either side of the RDAC, as shown in Figure 40. The improved ±1% resistor tolerance specification greatly reduces errors that are associated with matching to discrete resistors. ⎡ D × ⎢1.2 V × 1024 ⎢⎣ ⎛ R ⎞⎤ ⎜ 1 + 2 ⎟⎥ ⎜ R1 ⎟⎠⎥⎦ ⎝ (4) where D is the decimal code from 0 to 1023. VOUT (D) = VDD VDD VDD U2 U1A AD8512 D1 U1 AD5293 V+ ADR512 B R1 AD5293 U1B 20kΩ V– R2 20kΩ VOUT AD8512 B VOUT 07675-153 VARIABLE GAIN INSTRUMENTATION AMPLIFIER For applications that require high current adjustments, such as a laser diode or tunable laser, a boosted voltage source can be considered (see Figure 39). U3 2N7002 The AD8221 in conjunction with the AD5293 and the ADG1207, as shown in Figure 41, make an excellent instrumentation amplifier for use in data acquisition systems. The data acquisition system is low distortion and low noise enable it to condition signals in front of a variety of ADCs. VOUT U1 CC AD5293 U2 OP184 SIGNAL ADG1207 RBIAS LD VDD +VIN1 IL AD5293 +VIN4 –VIN1 07675-155 VIN B V+ OP1177 Figure 40. Optimizing Resolution PROGRAMMABLE VOLTAGE SOURCE WITH BOOSTED OUTPUT W U2 ±1% R3 Figure 38. High Voltage DAC A VDD V– R2 R1 (5) R1 + ((1024 − D )1024) × RAB + R3 AD8221 –VIN4 Figure 39. Programmable Boosted Voltage Source VSS In this circuit, the inverting input of the op amp forces VOUT to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the supply via the N-channel FET (U3). The N-channel FET power handling must be adequate to dissipate (VIN − VOUT) × IL power. This circuit can source a maximum of 100 mA with a 33 V supply. VOUT 07675-156 RBIAS R3 + (D 1024 × RAB ) ×V DD 07675-154 VOUT (D) = Figure 41. Data Acquisition System The gain can be calculated by using Equation 6, as follows: Rev. 0 | Page 18 of 20 G(D) = 1 + 49.4 kΩ (D 1024) × R AB (6) AD5293 The input is ac-coupled by C1 and attenuated down before feeding into the window comparator formed by U2, U3, and U4B. U6 is used to establish the signal as zero reference. The upper limit of the comparator is set above its offset and, therefore, the output pulses high whenever the input falls between 2.502 V and 2.497 V (or a 0.005 V window) in this example. This output is AND’ed with the chip select signal such that the AD5293 updates whenever the signal crosses the window. To avoid a constant update of the device, the chip select signal should be programmed as two pulses, rather than as one. AUDIO VOLUME CONTROL The excellent THD performance and high voltage capability of the AD5293 make it ideal for digital volume control. The AD5293 is used as an audio attenuator; it can be connected directly to a gain amplifier. A large step change in the volume level at any arbitrary time can lead to an abrupt discontinuity of the audio signal, causing an audible zipper noise. To prevent this, a zero-crossing window detector can be inserted to the SYNC line to delay the device update until the audio signal crosses the window. Because the input signal can operate on top of any dc level, rather than absolute 0 V level, zero crossing in this case means the signal is ac-coupled, and the dc offset level is the signal zero reference point. In Figure 43, the lower trace shows that the volume level changes from a quarter-scale to full-scale when a signal change occurs near the zero-crossing window. The configuration to reduce zipper noise is shown in Figure 42, and the results of using this configuration are shown in Figure 43. C1 VIN 1µF 5V R1 100kΩ R2 200Ω R4 90kΩ C3 0.1µF U2 VCC ADCMP371 GND U3 VCC ADCMP371 GND 5V U6 V+ AD8541 V– 4 VDD AD5293 A 7408 5 –15V +15V VSS U4A 6 1 2 SYNC SCLK SCLK DIN W 20kΩ 7408 SYNC DIN U5 V+ VOUT V– B –15V GND 07675-157 R3 100kΩ U1 C2 0.1µF U4B +5V Figure 42. Audio Volume Control with Zipper Noise Reduction 1 2 CHANNEL 1 FREQ = 20.25kHz 1.03V p-p 07675-158 R5 10kΩ +15V +5V Figure 43. Zipper Noise Detector Rev. 0 | Page 19 of 20 AD5293 OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 SEATING PLANE 0.75 0.60 0.45 8° 0° 061908-A 1.05 1.00 0.80 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 44. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters ORDERING GUIDE Model AD5293BRUZ-20 1 AD5293BRUZ-20-RL71 1 RAB (kΩ) 20 20 Resolution 1,024 1,024 Temperature Range −40°C to +105°C −40°C to +105°C Z = RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07675-0-4/09(0) Rev. 0 | Page 20 of 20 Package Description 14-Lead TSSOP 14-Lead TSSOP Package Option RU-14 RU-14