ASAHI KASEI [AK5381] AK5381 96kHz 24Bit ∆Σ ADC AK5381 A/D 4kHz ∼ 96kHz ∆Σ AK5381 AK5381 ( AK5381 I2S) 16pin TSSOP AV ∆Σ ADC DC HPF S/(N+D): 96dB@5V (48kHz) DR: 106dB@5V (48kHz) S/N: 106dB@5V (48kHz) : 4kHz ∼ 96kHz : 256fs/384fs/512fs/768fs (∼ 48kHz) 256fs/384fs (∼ 96kHz) : TTL/CMOS (2 TTL : / 2 : 24bit /I S : 4.5 ∼ 5.5V (VA) 2.7 ∼ 5.5V (VD at 48kHz) 3.0 ∼ 5.5V (VD at 96kHz) Ta = −40 ∼ 85°C (VT), −20 ∼ 85°C (ET) : 16pin TSSOP AK5380 VA AGND ) MCLK VD DGND Clock Divider AINL AINR VCOM ∆Σ Modulator Decimation Filter ∆Σ Modulator Decimation Filter LRCK SCLK Serial I/O Interface Voltage Reference CKS2 CKS1 CKS0 PDN MS0200-J-02 SDTO DIF 2006/01 -1- ASAHI KASEI [AK5381] AK5381ET AK5381VT AKD5381 −20 ∼ +85°C −40 ∼ +85°C AK5381 16pin TSSOP (0.65mm pitch) 16pin TSSOP (0.65mm pitch) AINR 1 16 CKS0 AINL 2 15 CKS2 CKS1 3 14 DIF VCOM 4 13 PDN AGND 5 12 SCLK VA 6 11 MCLK VD 7 10 LRCK DGND 8 9 SDTO Top View AK5380 Master Mode HPF OFF TTL Level Mode VIH@TTL Level Mode VD (Digital Supply) Pin #3 Pin #15 Pin #16 AK5380 Not Available Not Available 4kHz to 96kHz 2.2V 4.5 to 5.5V@fs=96kHz NC TTL TST MS0200-J-02 AK5381 Available Available 4kHz to 48kHz 2.4V 3.0 to 5.5V@fs=96kHz CKS1 CKS2 CKS0 2006/01 -2- ASAHI KASEI No. Pin Name [AK5381] I/O Function Rch Analog Input Pin Lch Analog Input Pin Mode Select 1 Pin Common Voltage Output Pin, VA/2 Bias voltage of ADC input. Analog Ground Pin Analog Power Supply Pin, 4.5 ∼ 5.5V Digital Power Supply Pin, 2.7 ∼ 5.5V(fs=4k ∼ 48kHz), 3.0 ∼ 5.5V(fs=48k ∼ 96kHz) Digital Ground Pin Audio Serial Data Output Pin “L” Output at Power-down mode. Output Channel Clock Pin “L” Output in Master Mode at Power-down mode. Master Clock Input Pin Audio Serial Data Clock Pin “L” Output in Master Mode at Power-down mode. Power Down Mode Pin “H”: Power up, “L”: Power down Audio Interface Format Pin “H” : 24bit I2S Compatible, “L” : 24bit MSB justified Mode Select 2 Pin Mode Select 0 Pin 1 2 3 AINR AINL CKS1 I I I 4 VCOM O 5 6 7 8 AGND VA VD DGND - 9 SDTO O 10 LRCK I/O 11 MCLK I 12 SCLK I/O 13 PDN I 14 DIF I 15 16 CKS2 CKS0 I I Note: All digital input pins should not be left floating. MS0200-J-02 2006/01 -3- ASAHI KASEI [AK5381] (AGND, DGND=0V; Note 1) Parameter Power Supplies: Analog Digital |AGND – DGND| (Note 2) Input Current, Any Pin Except Supplies Analog Input Voltage (AINL, AINR, CKS1 pins) Digital Input Voltage (All digital input pins except CKS1 pin) Ambient Temperature (powered applied) AK5381ET AK5381VT Storage Temperature Note 1. Note 2. AGND, DGND Symbol VA VD ∆GND IIN VINA VIND Ta Ta Tstg min −0.3 −0.3 −0.3 −0.3 −20 -40 −65 max 6.0 6.0 0.3 ±10 VA+0.3 VD+0.3 85 85 150 Units V V V mA V V °C °C °C : (AGND, DGND=0V; Note 1) Parameter Power Supplies Analog (Note 3) Digital (fs=4kHz to 48kHz) Digital (fs=48kHz to 96kHz) Note 1. Note 3. VA Symbol VA VD VD min 4.5 2.7 3.0 typ 5.0 5.0 5.0 max 5.5 VA VA Units V V V VD : MS0200-J-02 2006/01 -4- ASAHI KASEI [AK5381] (Ta=25°C; VA=VD=5.0V; AGND=DGND=0V; fs=48kHz, 96kHz; SCLK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz at fs=48kHz, 40Hz ∼ 40kHz at fs=96kHz; unless otherwise specified) Parameter min typ max Units ADC Analog Input Characteristics: Resolution 24 Bits Input Voltage (Note 4) 2.7 3.0 3.3 Vpp S/(N+D) (−1dBFS) fs=48kHz 88 96 dB fs=96kHz 82 90 dB DR (−60dBFS) fs=48kHz, A-weighted 100 106 dB fs=96kHz 94 102 dB S/N fs=48kHz, A-weighted 100 106 dB fs=96kHz 94 102 dB Input Resistance fs=48kHz 10 15 kΩ fs=96kHz 6 9 kΩ Interchannel Isolation 90 110 dB Interchannel Gain Mismatch 0.1 0.5 dB Gain Drift 100 150 ppm/°C Power Supply Rejection (Note 5) 50 dB Power Supplies Power Supply Current Normal Operation (PDN pin = “H”) VA VD (fs=48kHz) VD (fs=96kHz) Power down mode (PDN pin = “L”) VA+VD Note 4. Note 5. VA, VD Note 6. 16 8 14 24 12 21 mA mA mA 10 100 µA (Note 6) (0dB) VA Vin = 0.6 x VA (Vpp) 1kHz, 50mVpp VD DGND MS0200-J-02 2006/01 -5- ASAHI KASEI [AK5381] (fs=48kHz) (Ta=Tmin ∼ Tmax; VA=4.5 ∼ 5.5V; VD=2.7 ∼ 5.5V) Parameter Symbol ADC Digital Filter (Decimation LPF): Passband (Note 7) ±0.005dB PB ±0.02dB −0.06dB −6.0dB Stopband SB Passband Ripple PR Stopband Attenuation SA Group Delay Distortion ∆GD Group Delay (Note 8) GD ADC Digital Filter (HPF): Frequency Response (Note 7) −3dB FR −0.5dB −0.1dB min typ max Units 0 26.5 21.768 22.0 24.0 21.5 - 0 27.6 kHz kHz kHz kHz kHz dB dB µs 1/fs 1.0 2.9 6.5 Hz Hz Hz ±0.005 80 (fs=96kHz) (Ta=Tmin ∼ Tmax; VA=4.5 ∼ 5.5V; VD=3.0 ∼ 5.5V) Parameter Symbol ADC Digital Filter (Decimation LPF): Passband (Note 7) ±0.005dB PB ±0.02dB −0.06dB −6.0dB Stopband SB Passband Ripple PR Stopband Attenuation SA Group Delay Distortion ∆GD Group Delay (Note 8) GD ADC Digital Filter (HPF): Frequency Response (Note 7) −3dB FR −0.5dB −0.1dB Note 7. Note 8. typ max Units 0 53.0 43.536 44.0 48.0 43.0 - 0 27.6 kHz kHz kHz kHz kHz dB dB µs 1/fs 2.0 5.8 13.0 Hz Hz Hz ±0.005 80 fs ( 24 min ) 1kHz ADC MS0200-J-02 2006/01 -6- ASAHI KASEI [AK5381] DC (CMOS Level Mode) (Ta=Tmin ∼ Tmax; VA=4.5 ∼ 5.5V; VD=2.7 ∼ 5.5V@fs=4kHz ∼ 48kHz, VD=3.0 ∼ 5.5V@fs=∼96kHz) Parameter Symbol min typ max High-Level Input Voltage VIH 70%VD Low-Level Input Voltage VIL 30%VD High-Level Output Voltage (Iout=−100µA) VOH VD-0.5 Low-Level Output Voltage (Iout=100µA) VOL 0.5 Input Leakage Current Iin ±10 Units V V V V µA DC (TTL Level Mode) (Ta=Tmin ∼ Tmax; VA=4.5 ∼ 5.5V; VD=4.5 ∼ 5.5V@fs=4kHz ∼ 48kHz) Parameter Symbol min High-Level Input Voltage (CKS2-0 pins) VIH 70%VD (All pins except CKS2-0 pins) VIH 2.4 Low-Level Input Voltage (CKS2-0 pins) VIL (All pins except CKS2-0 pins) VIL High-Level Output Voltage (Iout=−100µA) VOH VD-0.5 Low-Level Output Voltage (Iout=100µA) VOL Input Leakage Current Iin - Units V V V V V V µA MS0200-J-02 typ - max 30%VD 0.8 0.5 ±10 2006/01 -7- ASAHI KASEI [AK5381] (fs=4kHz ∼ 48kHz) (Ta=Tmin ∼ Tmax; VA=4.5 ∼ 5.5V; VD=2.7 ∼ 5.5V; CL=20pF) Parameter Symbol min Master Clock Timing Frequency fCLK 1.024 tCLKL 0.4/fCLK Pulse Width Low Pulse Width High tCLKH 0.4/fCLK LRCK Frequency Duty Cycle fs Slave mode Master mode tSCK tSCKL tSCKH tLRSH tSHLR tLRS tSSD fSCK dSCK tMSLR tSSD Reset Timing PDN Pulse Width (Note 10) PDN “↑” to SDTO valid at Slave Mode (Note 11) PDN “↑” to SDTO valid at Master Mode (Note 11) LRCK PDN pin = “L” 4 45 max Units 36.864 MHz ns ns 48 55 kHz % % 50 Audio Interface Timing Slave mode SCLK Period SCLK Pulse Width Low Pulse Width High LRCK Edge to SCLK “↑” (Note 9) SCLK “↑” to LRCK Edge (Note 9) LRCK to SDTO (MSB) (Except I2S mode) SCLK “↓” to SDTO Master mode SCLK Frequency SCLK Duty SCLK “↓” to LRCK SCLK “↓” to SDTO Note 9. Note 10. AK5381 Note 11. PDN typ SCLK LRCK tPD tPDV tPDV 160 65 65 30 30 35 35 ns ns ns ns ns ns ns 20 35 Hz % ns ns 64fs 50 −20 150 4132 4129 ns 1/fs 1/fs “↑” “↑” MS0200-J-02 2006/01 -8- ASAHI KASEI [AK5381] (fs=48kHz ∼ 96kHz) (Ta=Tmin ∼ Tmax; VA=4.5 ∼ 5.5V; VD=3.0 ∼ 5.5V; CL=20pF; CMOS Level Mode Parameter Symbol min Master Clock Timing Frequency fCLK 12.288 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK LRCK Frequency Duty Cycle fs Slave mode Master mode tSCK tSCKL tSCKH tLRSH tSHLR tLRS tSSD fSCK dSCK tMSLR tSSD Reset Timing PDN Pulse Width (Note 10) PDN “↑” to SDTO valid at Slave Mode (Note 11) PDN “↑” to SDTO valid at Master Mode (Note 11) LRCK PDN pin = “L” 48 45 max Units 36.864 MHz ns ns 96 55 kHz % % 50 Audio Interface Timing Slave mode SCLK Period SCLK Pulse Width Low Pulse Width High LRCK Edge to SCLK “↑” (Note 9) SCLK “↑” to LRCK Edge (Note 9) LRCK to SDTO (MSB) (Except I2S mode) SCLK “↓” to SDTO Master mode SCLK Frequency SCLK Duty SCLK “↓” to LRCK SCLK “↓” to SDTO Note 9. Note 10. AK5381 Note 11. PDN ) typ SCLK LRCK tPD tPDV tPDV 160 65 65 30 30 35 35 ns ns ns ns ns ns ns 20 35 Hz % ns ns 64fs 50 −20 150 4132 4129 ns 1/fs 1/fs “↑” “↑” MS0200-J-02 2006/01 -9- ASAHI KASEI [AK5381] 1/fCLK VIH MCLK VIL tCLKH tCLKL 1/fs VIH LRCK VIL tSCK VIH SCLK VIL tSCKH tSCKL Clock Timing VIH LRCK VIL tSHLR tLRSH VIH SCLK VIL tLRS tSSD SDTO 50%VD Audio Interface Timing (Slave mode) MS0200-J-02 2006/01 - 10 - ASAHI KASEI [AK5381] LRCK 50%VD tMSLR dSCK SCLK 50%VD tSSD SDTO 50%VD Audio Interface Timing (Master mode) VIH PDN VIL tPDV SDTO 50%VD tPD PDN VIL Power Down & Reset Timing MS0200-J-02 2006/01 - 11 - ASAHI KASEI [AK5381] AK5381 (CMOS or TTL) MCLK, SCLK, LRCK Table 1 CKS2-0 (Table 2) MCLK / MCLK LRCK (PDN pin = “H”) (MCLK, SCLK, LRCK) SCLK AK5381 HPF ON/OFF (PDN pin = “L”) (MCLK) fs 32kHz 44.1kHz 48kHz 96kHz MCLK 256fs 384fs 512fs 8.192MHz 12.288MHz 16.384MHz 11.2896MHz 16.9344MHz 22.5792MHz 12.288MHz 18.432MHz 24.576MHz 24.576MHz 36.864MHz N/A Table 1. System Clock Example CKS2 CKS1 CKS0 Input Level L L L CMOS L L H CMOS L L H H L H CMOS CMOS H L L TTL* H H H L H H H L H CMOS CMOS Note: SCLK = 32fs Note: 2 TTL SDTO HPF 768fs 24.576MHz 33.8688MHz 36.864MHz N/A Master/Slave MCLK 256/384fs (∼ 96kHz) ON Slave 512/768fs (∼ 48kHz) 256/384fs (∼ 96kHz) OFF Slave 512/768fs (∼ 48kHz) ON Master 256fs (∼ 96kHz) ON Master 512fs (∼ 48kHz) 256fs/384/512/768fs ON Slave (∼ 48kHz) Reserved ON Master 384fs (∼ 96kHz) ON Master 768fs (∼ 48kHz) Table 2. Mode Select SCLK ≥ 48fs or 32fs ≥ 48fs or 32fs 64fs 64fs ≥ 48fs or 32fs 64fs 64fs 16bit 2 DIF (Table 3) SDTO SCLK MSB LRCK Mode 0 1 DIF pin L H LRCK SCLK SCLK SDTO LRCK SCLK 24bit, MSB justified H/L ≥ 48fs or 32fs 24bit, I2S Compatible L/H ≥ 48fs or 32fs Table 3. Audio Interface Format MS0200-J-02 2’s fs 64fs Figure Figure 1 Figure 2 2006/01 - 12 - ASAHI KASEI [AK5381] LRCK 0 1 2 20 21 22 23 24 31 0 1 2 20 21 22 23 24 31 0 1 SCLK(64fs) SDTO(o) 23 22 4 3 2 1 0 23 22 4 3 2 1 0 23 23:MSB, 0:LSB Lch Data Rch Data Figure 1. Mode 0 Timing LRCK 0 1 2 3 21 22 23 24 25 0 1 2 21 22 23 24 25 0 1 SCLK(64fs) 23 22 SDTO(o) 4 3 2 1 0 23 22 4 3 2 1 0 23:MSB, 0:LSB Lch Data Rch Data Figure 2. Mode 1 Timing HPF ADC DC HPF HPF fc fs=48kHz 1.0Hz fs CKS2-0 HPF ON/OFF (Table 2) HPF ON/OFF DC (PDN pin = “L”) MS0200-J-02 2006/01 - 13 - ASAHI KASEI [AK5381] AK5381 PDN “L” VCOM AGND SDTO 4132 x LRCK ADC 4129 x LRCK 2’s ( 0 ADC ) (1) PDN Internal State Normal Operation Power-down Initialize Normal Operation GD (2) GD A/D In (Analog) A/D Out (Digital) Clock In “0”data Idle Noise (4) MCLK,LRCK,SCLK Notes: (1) (2) (3) (4) (3) “0”data Idle Noise 4132/fs 4129/fs (GD) ADC “0” (MCLK, SCLK, LRCK) Figure 3. / PDN “L” MCLK PDN LRCK ) ( “H” Mode 1 LRCK PDN “H” MCLK MS0200-J-02 2006/01 - 14 - ASAHI KASEI [AK5381] Figure 4 (AKD5381) Rch In 10u + Lch In + 1 AINR CKS0 16 2 AINL CKS2 15 10u 3 CKS1 2.2u 0.1u 4 VCOM + 5 AGND Analog 5V + 10u 0.1u + 10u 0.1u Mode Control DIF 14 AK5381 PDN 13 Reset SCLK 12 6 VA MCLK 11 7 VD LRCK 10 8 DGND SDTO 9 Audio Controller Analog Ground : - AK5381 - CKS1 System Ground AGND, DGND VA AGND Figure 4. Typical Connection Diagram Digital Ground Analog Ground System Controller 1 AINR CKS0 16 2 AINL CKS2 15 3 CKS1 DIF 14 4 VCOM PDN 13 5 AGND SCLK 12 6 VA MCLK 11 7 VD LRCK 10 8 DGND SDTO AK5381 9 Figure 5. Ground Layout : - AGND DGND MS0200-J-02 2006/01 - 15 - ASAHI KASEI [AK5381] 1. VA VD VA VD DGND PC AGND 2. VA VCOM 50%VA 2.2µF 0.1µF AGND VCOM VCOM, VA 3. ADC 0.6 x VA Vpp(typ.) 2’s 15kΩ(typ.) VCOM AK5381 AGND VA DC (ADC DC ) HPF AK5381 64fs 64fs AK5381 64fs (RC ) MS0200-J-02 2006/01 - 16 - ASAHI KASEI [AK5381] 16pin TSSOP (Unit: mm) *5.0±0.1 9 A 8 1 0.13 M 6.4±0.2 *4.4±0.1 16 1.05±0.05 0.22±0.1 0.17±0.05 0.65 Detail A 0.5±0.2 0.1±0.1 Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. 0-10° Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate MS0200-J-02 2006/01 - 17 - ASAHI KASEI [AK5381] AKM 5381VT XXYYY 1) 2) 3) Pin #1 indication Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code : 5381VT MS0200-J-02 2006/01 - 18 - ASAHI KASEI [AK5381] (AK5381ET) AKM 5381ET XXYYY 4) 5) 6) Pin #1 indication Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code : 5381ET MS0200-J-02 2006/01 - 19 - ASAHI KASEI [AK5381] Revision History Date (YY/MM/DD) 03/01/24 04/04/19 Revision 00 01 Reason Page Contents P.4 Analog Input Voltage (AINL, AINR pins) → Analog Input Voltage (AINL, AINR, CKS1 pins) Digital Input Voltage (All digital input pins) → Digital Input Voltage (All digital input pins except CKS1 pin) 06/01/11 02 P.2 AK5381ET P.19 AK5381ET • • • • • • MS0200-J-02 2006/01 - 20 -