データシート

[AK4371]
AK4371
PLL & HP-AMP
AK4371
PLL &
24bit D/A
I/F
PLL
16
40mW
ON/OFF
4mm
†
†
†8
†
†
†
†
†
†
†
†
ΔΣ
DAC
4mm
32pin QFN
DAC
- 8kHz ∼ 48kHz
FIR
: 20kHz
: ±0.02dB
: 54dB
: 32kHz, 44.1kHz, 48kHz
:
- PLL Mode (MCKI): 27MHz, 26MHz, 19.8MHz, 19.68MHz, 19.2MHz, 15.36MHz,
14.4MHz, 13MHz, 12MHz and 11.2896MHz
- PLL Mode (BICK or LRCK): 64fs, 32fs or fs
- EXT Mode: 256fs/384fs/512fs/768fs/1024fs
AC
I/F
: MSB First, 2’s Complement
2
, 24bit/20bit/16bit
- I S, 24bit
: LR, LL, RR, (L+R)/2
:6
or
- S/N: [email protected]
: +6 to –24dB (or 0 to –30dB), 2dB step
†
-
: 0.8mW @600Ω, 3.3V
: +6 to –24dB (or 0 to –30dB), 2dB step
†
: 40mW x 2ch @16Ω, 3.3V
- S/N: [email protected]
ON/OFF
: 0 ∼ –63dB & +12/+6/0dB Gain
1.5dB step (0 ∼ –30dB), 3dB step (–30 ∼ –63dB)
†
:3
/I2C
†
: 1.6V ∼ 3.6V
†
: 3.8mA @1.8V (6.8mW, DAC+HP,
)
† Ta: −30 ∼ 85°C
†
: 32pin QFN (4mm x 4mm, 0.4mm pitch)
† AK4368
MS0596-J-01
2008/12
-1-
[AK4371]
■
PVDD
BICK
LRCK
SDATA
VSS3
Audio
Interface
MCKO
MCKI
LIN3
AVDD
VSS1
VREF
VREF
VCOM
VCOM
PLL
DVDD
VSS2
LIN1/IN− LIN2
VCOC
DAC
Digital
Volume
Deemphasis
Bass
Boost
Digital
Filter
LOUT
(Lch)
ROUT
DAC
(Rch)
HF
Amp
PDN
I2C
MOUT
HDP
Amp
MUTE
HPL
HDP
Amp
MUTE
HPR
HVDD
MUTET
CAD0/CSN
SCL/CCLK
Serial I/F
SDA/CDTI
RIN1/IN+ RIN2
RIN3
Figure 1.
MS0596-J-01
2008/12
-2-
[AK4371]
■
AK4371VN
AKD4371
−30 ∼ +85°C
AK4371
32pin QFN (0.4mm pitch)
VSS1
HVDD
AVDD
VCOM
VREF
ROUT
LOUT
MOUT
24
23
22
21
20
19
18
17
■
CSN/CAD0
RIN3
29
Top View
12
CCLK/SCL
LIN3
30
11
CDTI/SDA
RIN1/IN+
31
10
MCKO
LIN1/IN−
32
9
VSS3
8
13
VSS2
AK4371VN
7
28
VCOC
LIN2
6
PDN
PVDD
14
5
27
DVDD
RIN2
4
I2C
MCKI
15
3
26
LRCK
HPL
2
MUTET
BICK
16
1
25
SDATA
HPR
MS0596-J-01
2008/12
-3-
[AK4371]
■ AK4368
1. Function
Function
AK4368
Analog Mixing
1-Stereo + 1-Mono
Single-ended Input
PLL Reference Clock
Internal VREF
Hands-free Amp
MCKI
256fs/512fs/1024fs,
12.288MHz(max)
No
No
HP-Amp Output Volume
No
HP-Amp Hi-Z Setting
3D Enhancement
ALC
Package
No
Yes
Yes
41BGA (4mm x 4mm, 0.5mm pitch)
MCKI at EXT Mode
2.
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
(AK4368
Register Name
Power Management 0
PLL Control
Clock Control
Mode Control 0
Mode Control 1
DAC Lch ATT
DAC Rch ATT
Headphone Out Select 0
Lineout Select 0
Lineout ATT
Reserved
Reserved
Reserved
Headphone Out Select 1
Headphone ATT
Lineout Select 1
Mono Mixing
Differential Select
MOUT Select
MOUT ATT
AK4371
3-Stereo
Single-ended Input
or Full-differential Input
MCKI/BICK/LRCK
256fs/384fs/512fs/768fs/1024fs,
24.576MHz(max)
Yes
Yes
0 to –63dB & +12/+6/0dB
1.5dB step (0 to –30dB)
3dB step (–30 to –63dB)
Yes
No
No
32QFN (4mm x 4mm, 0.4mm pitch)
)
D7
PMVREF
FS3
PLL4
0
ATS
ATTL7
ATTR7
HPG1
0
0
REF7
0
0
RIN3HR
0
RIN3R
0
0
RIN3M
0
D6
PMPLL
FS2
0
MONO1
DATTC
ATTL6
ATTR6
HPG0
LOG
0
REF6
0
0
RIN3HL
HPZ
RIN3L
0
0
LIN3M
PMMO
AK4371
AK4371
D5
PMLO
FS1
M/S
MONO0
LMUTE
ATTL5
ATTR5
LIN2HR
LIN2R
0
REF5
ALC
0
LIN3HR
HMUTE
LIN3R
L3M
0
RIN2M
MOG
MS0596-J-01
D4
MUTEN
FS0
MCKAC
BCKP
SMUTE
ATTL4
ATTR4
LIN2HL
LIN2L
0
REF4
ROTM1
0
LIN3HL
ATTH4
LIN3L
L3HM
0
LIN2M
MMUTE
D3
PMHPR
PLL3
BF
LRP
BST1
ATTL3
ATTR3
RIN1HR
RIN1R
ATTS3
REF3
ROTM0
DP1
RIN2HR
ATTH3
RIN2R
L2M
0
RIN1M
ATTM3
D2
PMHPL
PLL2
PS0
DIF2
BST0
ATTL2
ATTR2
LIN1HL
LIN1L
ATTS2
REF2
LMAT1
DP0
RIN2HL
ATTH2
RIN2L
L2HM
LDIFM
LIN1M
ATTM2
D1
PMDAC
PLL1
PS1
DIF1
DEM1
ATTL1
ATTR1
DARHR
DARR
ATTS1
REF1
LMAT0
3D1
LIN1HR
ATTH1
LIN1R
L1M
LDIFH
DARM
ATTM1
D0
PMVCM
PLL0
MCKO
DIF0
DEM0
ATTL0
ATTR0
DALHL
DALL
ATTS0
REF0
RATT
3D0
RIN1HL
ATTH0
RIN1L
L1HM
LDIF
DALM
ATTM0
2008/12
-4-
[AK4371]
No.
1
SDATA
I/O
I
2
BICK
I/O
3
LRCK
I/O
4
5
6
MCKI
DVDD
PVDD
I
-
7
VCOC
O
8
9
10
VSS2
VSS3
MCKO
SDA
CDTI
SCL
CCLK
CAD0
CSN
O
I/O
I
I
I
I
I
11
12
13
14
PDN
L/R
PLL
PLL
VSS3
, 1.6 ∼ 3.6V
, 1.6 ∼ 3.6V AVDD
(I2C
(3
0
(I2C
: I2C pin = “H”)
: I2C pin = “L”)
(I2C
: I2C pin = “H”)
(3
: I2C pin = “L”)
: I2C pin = “H”)
(3
: I2C pin = “L”)
&
“L”
I
“L”
15
I2C
I
16
MUTET
O
17
18
19
MOUT
LOUT
ROUT
O
O
O
20
VREF
O
21
VCOM
O
22
23
24
25
26
27
28
29
30
AVDD
HVDD
VSS1
HPR
HPL
RIN2
LIN2
RIN3
LIN3
RIN1
IN+
LIN1
IN−
O
O
I
I
I
I
I
I
I
I
31
32
Note 1.
“H”: I2C
, “L”: 3
VSS1 pin
Lch
Rch
VSS1 pin
VSS1 pin
0.22μF
2.2μF
, 1.6 ∼ 3.6V
, 1.6 ∼ 3.6V
Rch HP-Amp
Lch HP-Amp
Rch
Lch
Rch
Lch
Rch
2
2
3
3
1
(LDIF bit = “0” :
)
(LDIF bit = “1” :
)
Lch
1
(LDIF bit = “0” :
)
(LDIF bit = “1” :
)
(I2C, SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN)
MCKI pin
PDN pin = “L”
MS0596-J-01
2008/12
-5-
[AK4371]
■
Analog
Digital
LOUT, ROUT, MOUT, MUTET, HPR, HPL, RIN3,
LIN3, RIN2, LIN2, RIN1/IN+, LIN1/IN−
MCKI
MCKO
(VSS1=VSS2=VSS3=0V; Note 2, Note 3)
Parameter
Symbol
Power Supplies Analog
AVDD
Digital
DVDD
PLL
PVDD
HP-Amp
HVDD
Input Current (any pins except for supplies)
IIN
Analog Input Voltage (Note 4)
VINA
Digital Input Voltage (Note 5)
VIND
Ambient Temperature
Ta
Storage Temperature
Tstg
Note 2.
Note 3. VSS1, VSS2 VSS3
Note 4. LIN1/IN−, RIN1/IN+, LIN2, RIN2, LIN3 and RIN3 pins. Max
min
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−30
−65
VSS2
max
4.6
4.6
4.6
4.6
±10
(AVDD+0.3) or 4.6
(DVDD+0.3) or 4.6
85
150
(AVDD+0.3V)
Units
V
V
V
V
mA
V
V
°C
°C
4.6V
Note 5. SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN and I2C pins. Max
4.6V
(DVDD+0.3V)
:
(VSS1=VSS2=VSS3=0V; Note 2)
Parameter
Power Supplies Analog
(Note 6)
Digital (Note 7)
PLL
HP-Amp
Difference1
Difference2
Note 2.
Note 6. AVDD DVDD
OFF
HVDD
Note 7. Max (AVDD+0.2V)
Symbol
AVDD
DVDD
PVDD
HVDD
AVDD−PVDD
AVDD−HVDD
min
1.6
1.6
1.6
1.6
−0.3
−0.3
DVDD
AVDD
AVDD HVDD
1.6V
DVDD
typ
2.4
2.4
2.4
2.4
0
0
max
3.6
(AVDD+0.2) or 3.6
3.6
3.6
+0.3
+0.3
Units
V
V
V
V
V
V
AVDD
AVDD HVDD
OFF
3.6V
:
MS0596-J-01
2008/12
-6-
[AK4371]
(
Ta=25°C; AVDD=PVDD=DVDD=HVDD=2.4V, VSS1=VSS2=VSS3=0V; fs=44.1kHz; EXT mode;
BOOST OFF; Slave Mode; Signal Frequency =1kHz; Measurement band width=20Hz ∼ 20kHz; Headphone-Amp: RL
=16Ω, CL=220μF
(Figure 57))
Parameter
min
typ
max
Units
24
bit
DAC Resolution
Headphone-Amp: (HPL/HPR pins) (Note 8)
Analog Output Characteristics
THD+N
dB
−3dBFS Output, 2.4V, Po=10mW@16Ω
−50
−40
dB
0dBFS Output, 3.3V, Po=40mW@16Ω
−20
82
90
dB
D-Range
−60dBFS Output, A-weighted, 2.4V
92
dB
−60dBFS Output, A-weighted, 3.3V
S/N
A-weighted, 2.4V
82
90
dB
A-weighted, 3.3V
92
dB
Interchannel Isolation
60
80
dB
DC Accuracy
Interchannel Gain Mismatch
0.3
0.8
dB
Gain Drift
200
ppm/°C
Load Resistance (Note 9)
16
Ω
Load Capacitance
300
pF
1.04
1.16
1.28
Vpp
Output Voltage −3dBFS Output (Note 10)
0dBFS Output, 3.3V,
0.8
Vrms
Po=40mW@16Ω
Output Volume: (HPL/HPR pins)
Step Size
0.1
1.5
2.9
dB
0 ∼ –30dB
(HPG1-0 bits = “00”)
0.1
3
5.9
dB
–30 ∼ –63dB
Gain Control Range
Max (ATT4-0 bits = “00H”)
0
dB
(HPG1-0 bits = “00”)
Min (ATT4-0 bits = “1FH”)
dB
−63
Stereo Line Output: (LOUT/ROUT pins, RL=10kΩ) (Note 11)
Analog Output Characteristics:
THD+N (0dBFS Output)
dB
−60
−50
S/N
A-weighted, 2.4V
80
87
dB
A-weighted, 3.3V
90
dB
DC Accuracy
Gain Drift
200
ppm/°C
Load Resistance (Note 9)
10
kΩ
Load Capacitance
25
pF
Output Voltage (0dBFS Output) (Note 12)
1.32
1.47
1.61
Vpp
Output Volume: (LOUT/ROUT pins)
Step Size
1
2
3
dB
Gain Control Range
Max (ATTS3-0 bits = “FH”)
0
dB
(LOG1-0 bit = “0”)
Min (ATTS3-0 bits = “0H”)
dB
−30
Note 8. DALHL=DARHR bits = “1”, LIN1HL=RIN1HL=LIN2HL=RIN2HL=LIN3HL=RIN3HL
=LIN1HR=RIN1HR=LIN2HR=RIN2HR=LIN3HR=RIN3HR bits = “0”
Note 9. AC
Note 10.
AVDD
PMVREF bit = “0”
Vout = 0.48 x AVDD(typ)@−3dBFS
PMVREF bit = “1”
Vout = 0.52 x AVDD(typ)@0dBFS.
Note 11. DALL=DARR bits = “1”, LIN1L=RIN1L=LIN2L=RIN2L=LIN3L=RIN3L
=LIN1R=RIN1R=LIN2R=RIN2R=LIN3R=RIN3R bits = “0”
Note 12.
AVDD
PMVREF bit = “0”
Vout = 0.61 x AVDD(typ)@0dBFS PMVREF
bit = “1”
Vout = 0.46 x AVDD(typ)@0dBFS.
MS0596-J-01
2008/12
-7-
[AK4371]
Parameter
Mono Handsfree Output: (MOUT pin, RL=600Ω) (Note 13)
Analog Output Characteristics:
THD+N (0dBFS Output)
S/N
A-weighted, 2.4V
A-weighted, 3.3V
DC Accuracy
Gain Drift
Load Resistance (Note 9)
Load Capacitance
Output Voltage (0dBFS Output) (Note 14)
Output Volume: (MOUT pin)
Step Size
Gain Control Range
Max (ATTM3-0 bits = “FH”)
(MOG1-0 bit = “0”)
Min (ATTM3-0 bits = “0H”)
min
typ
max
Units
80
-
−60
87
90
−50
-
dB
dB
dB
600
1.32
200
1.47
25
1.61
ppm/°C
Ω
pF
Vpp
1
-
2
0
−30
3
-
dB
dB
dB
Note 13. DALM=DARM bits = “1”, LIN1M=RIN1M=LIN2M=RIN2M=LIN3M=RIN3M bits = “0”
Note 9. AC
Note 14.
AVDD
PMVREF bit = “0”
Vout = 0.61 x AVDD(typ)@0dBFS PMVREF
bit = “1”
Vout = 0.46 x AVDD(typ)@0dBFS.
MS0596-J-01
2008/12
-8-
[AK4371]
Parameter
LINEIN: (LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 pins)
Analog Input Characteristics
Input Resistance (Figure 25, Figure 26, Figure 27 and Figure 28.)
LIN1 pin
LIN1HL=LIN1HR=LIN1L=LIN1R=LIN1M bits = “1”
LIN1HL bit = “1”, LIN1HR=LIN1L=LIN1R=LIN1M bits = “0”
LIN1HR bit = “1”, LIN1HL=LIN1L=LIN1R=LIN1M bits = “0”
LIN1L bit = “1”, LIN1HL=LIN1HR=LIN1R=LIN1M bits = “0”
LIN1R bit = “1”, LIN1HL=LIN1HR=LIN1L=LIN1M bits = “0”
LIN1M bit = “1”, LIN1HL=LIN1HR=LIN1L=LIN1R bits = “0”
RIN1 pin
RIN1HL=RIN1HR=RIN1L=RIN1R=RIN1M bits = “1”
RIN1HL bit = “1”, RIN1HR=RIN1L=RIN1R=RIN1M bits = “0”
RIN1HR bit = “1”, RIN1HL=RIN1L=RIN1R=RIN1M bits = “0”
RIN1L bit = “1”, RIN1HL=RIN1HR=RIN1R=RIN1M bits = “0”
RIN1R bit = “1”, RIN1HL=RIN1HR=RIN1L=RIN1M bits = “0”
RIN1M bit = “1”, RIN1HL=RIN1HR=RIN1L=RIN1R bits = “0”
LIN2 pin
LIN2HL=LIN2HR=LIN2L=LIN2R=LIN2M bits = “1”
LIN2HL bit = “1”, LIN2HR=LIN2L=LIN2R=LIN2M bits = “0”
LIN2HR bit = “1”, LIN2HL=LIN2L=LIN2R=LIN2M bits = “0”
LIN2L bit = “1”, LIN2HL=LIN2HR=LIN2R=LIN2M bits = “0”
LIN2R bit = “1”, LIN2HL=LIN2HR=LIN2L=LIN2M bits = “0”
LIN2M bit = “1”, LIN2HL=LIN2HR=LIN2L=LIN2R bits = “0”
RIN2 pin
RIN2HL=RIN2HR=RIN2L=RIN2R=RIN2M bits = “1”
RIN2HL bit = “1”, RIN2HR=RIN2L=RIN2R=RIN2M bits = “0”
RIN2HR bit = “1”, RIN2HL=RIN2L=RIN2R=RIN2M bits = “0”
RIN2L bit = “1”, RIN2HL=RIN2HR=RIN2R=RIN2M bits = “0”
RIN2R bit = “1”, RIN2HL=RIN2HR=RIN2L=RIN2M bits = “0”
RIN2M bit = “1”, RIN2HL=RIN2HR=RIN2L=RIN2R bits = “0”
LIN3 pin
LIN3HL=LIN3HR=LIN3L=LIN3R=LIN3M bits = “1”
LIN3HL bit = “1”, LIN3HR=LIN3L=LIN3R=LIN3M bits = “0”
LIN3HR bit = “1”, LIN3HL=LIN3L=LIN3R=LIN3M bits = “0”
LIN3L bit = “1”, LIN3HL=LIN3HR=LIN3R=LIN3M bits = “0”
LIN3R bit = “1”, LIN3HL=LIN3HR=LIN3L=LIN3M bits = “0”
LIN3M bit = “1”, LIN3HL=LIN3HR=LIN3L=LIN3R bits = “0”
RIN3 pin
RIN3HL=RIN3HR=RIN3L=RIN3R=RIN3M bits = “1”
RIN3HL bit = “1”, RIN3HR=RIN3L=RIN3R=RIN3M bits = “0”
RIN3HR bit = “1”, RIN3HL=RIN3L=RIN3R=RIN3M bits = “0”
RIN3L bit = “1”, RIN3HL=RIN3HR=RIN3R=RIN3M bits = “0”
RIN3R bit = “1”, RIN3HL=RIN3HR=RIN3L=RIN3M bits = “0”
RIN3M bit = “1”, RIN3HL=RIN3HR=RIN3L=RIN3R bits = “0”
Gain
LIN1/LIN2/LIN3/RIN1/RIN2/RIN3 Æ LOUT/ROUT
LIN1/LIN2/LIN3/RIN1/RIN2/RIN3 Æ HPL/HPR
LIN1/LIN2/LIN3/RIN1/RIN2/RIN3 Æ MOUT
MS0596-J-01
min
typ
max
Units
14
-
20
100
100
100
100
100
-
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
14
-
20
100
100
100
100
100
-
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
14
-
20
100
100
100
100
100
-
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
14
-
20
100
100
100
100
100
-
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
14
-
20
100
100
100
100
100
-
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
14
-
20
100
100
100
100
100
-
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
−1
−0.05
−1
0
+0.95
0
+1
+1.95
+1
dB
dB
dB
2008/12
-9-
[AK4371]
Parameter
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”) (Note 15)
AVDD+PVDD+DVDD
HVDD
Power-Down Mode (PDN pin = “L”) (Note 16)
min
typ
max
Units
-
3.8
1.2
1
5.5
2.5
100
mA
mA
μA
Note 15. PMDAC=PMHPL=PMHPR=PMLO bits = “1”, MUTEN bit = “1”, PMMO=MCKO bits = “0”, HP-Amp
PMDAC=PMHPL=PMHPR= “1”, PMLO=PMMO bits = “0” ,
AVDD+PVDD+DVDD+HVDD=4.0mA (typ) @2.4V, 3.8mA (typ) @1.8V.
Note 16.
(MCKI, BICK, LRCK)
VSS2
MS0596-J-01
2008/12
- 10 -
[AK4371]
(Ta=25°C; AVDD=DVDD=PVDD=HVDD=1.6 ∼ 3.6V; fs=44.1kHz; De-emphasis = “OFF”)
Parameter
Symbol
min
typ
DAC Digital Filter: (Note 17)
Passband (Note 18)
PB
0
−0.05dB
22.05
−6.0dB
Stopband (Note 18)
SB
24.1
Passband Ripple
PR
Stopband Attenuation
SA
54
Group Delay (Note 19)
GD
22
Group Delay Distortion
0
ΔGD
DAC Digital Filter + Analog Filter: (Note 17) (Note 20)
Frequency Response
FR
0 ∼ 20.0kHz
±0.5
Analog Filter: (Note 21)
Frequency Response
FR
0 ∼ 20.0kHz
±1.0
BOOST Filter: (Note 20) (Note 22)
Frequency Response
20Hz
FR
5.76
MIN
100Hz
2.92
1kHz
0.02
20Hz
FR
10.80
MID
100Hz
6.84
1kHz
0.13
20Hz
FR
16.06
MAX 100Hz
10.54
1kHz
0.37
Note 17. BOOST OFF (BST1-0 bit = “00”)
Note 18.
fs (
)
PB=0.4535fs(@−0.05dB) SB=0.546fs(@−54dB)
Note 19.
max
Units
20.0
±0.02
-
kHz
kHz
kHz
dB
dB
1/fs
µs
-
dB
-
dB
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
Note 20. DAC Æ HPL, HPR, LOUT, ROUT, MOUT
Note 21. LIN1/LIN2/LIN3/RIN1/RIN2/RIN3 Æ HPL/HPR/LOUT/ROUT/MOUT
Note 22.
fs
Boost Filter (fs=44.1kHz)
20
MAX
15
Gain [dB]
MID
10
MIN
5
0
-5
10
100
1000
10000
Frequency [Hz]
Figure 2. Boost Frequency (fs=44.1kHz)
MS0596-J-01
2008/12
- 11 -
[AK4371]
DC
(Ta=25°C; AVDD=DVDD=PVDD=HVDD=1.6 ∼ 3.6V)
Parameter
Symbol
High-Level Input Voltage
2.2V≤DVDD≤3.6V
VIH
1.6V≤DVDD<2.2V
VIH
Low-Level Input Voltage
2.2V≤DVDD≤3.6V
VIL
1.6V≤DVDD<2.2V
VIL
Input Voltage at AC Coupling (Note 23)
VAC
High-Level Output Voltage
VOH
(Iout=−200μA)
Low-Level Output Voltage
VOL
(Except SDA pin: Iout=200μA)
VOL
(SDA pin, 2.0V≤DVDD≤3.6V: Iout=3mA)
VOL
(SDA pin, 1.6V≤DVDD<2.0V: Iout=3mA)
Input Leakage Current
Iin
Note 23. MCKI pin
min
70%DVDD
80%DVDD
0.4
DVDD−0.2
typ
-
max
30%DVDD
20%DVDD
-
Units
V
V
V
V
Vpp
V
-
-
0.2
0.4
20%DVDD
±10
V
V
V
μA
(Figure 57)
MS0596-J-01
2008/12
- 12 -
[AK4371]
(Ta=25°C; AVDD=DVDD=PVDD=HVDD=1.6 ∼ 3.6V; CL = 20pF; unless otherwise specified)
Parameter
Symbol
min
typ
Master Clock Input Timing
Frequency (PLL mode)
fCLK
11.2896
(EXT mode)
fCLK
2.048
Pulse Width Low (Note 24)
tCLKL
0.4/fCLK
Pulse Width High (Note 24)
tCLKH
0.4/fCLK
AC Pulse Width (Note 25)
tACW
18.5
LRCK Timing
Frequency
fs
8
44.1
Duty Cycle: Slave Mode
Duty
45
Master Mode
Duty
50
MCKO Output Timing (PLL mode)
Frequency
fCLKO
0.256
Duty Cycle (Except fs=32kHz, PS1-0= “00”)
dMCK
40
(fs=32kHz, PS1-0= “00”)
dMCK
33
Serial Interface Timing (Note 26)
Slave Mode (M/S bit = “0”):
BICK Period (Note 27)
(Except PLL Mode, PLL4-0 = “EH”, “FH”)
tBCK
312.5 or 1/(64fs)
(PLL Mode, PLL4-0 bits = “EH”)
tBCK
1/(32fs)
(PLL Mode, PLL4-0 bits = “EH”)
tBCK
1/(64fs)
BICK Pulse Width Low
(Except PLL Mode, PLL4-0 = “EH”, “FH”)
tBCKL
100
(PLL Mode, PLL4-0 bits = “EH”, “FH”)
tBCKL
0.4 x tBCK
BICK Pulse Width High
(Except PLL Mode, PLL4-0 = “EH”, “FH”)
tBCKL
100
(PLL Mode, PLL4-0 bits = “EH”, “FH”)
tBCKH
0.4 x tBCK
tLRB
50
LRCK Edge to BICK “↑” (Note 28)
tBLR
50
BICK “↑” to LRCK Edge (Note 28)
SDATA Hold Time
tSDH
50
SDATA Setup Time
tSDS
50
Master Mode (M/S bit = “1”):
BICK Frequency (BF bit = “1”)
fBCK
64fs
(BF bit = “0”)
fBCK
32fs
BICK Duty
dBCK
50
tMBLR
BICK “↓” to LRCK
−50
SDATA Hold Time
tSDH
50
SDATA Setup Time
tSDS
50
Control Interface Timing (3-wire Serial mode)
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
40
CSN “H” Time
tCSW
150
tCSS
50
CSN “↑” to CCLK “↑”
tCSH
50
CCLK “↑” to CSN “↑”
Note 24. AC
Note 25. MCKI pin
(Figure 3)
Note 26.
Note 27. PLL Mode, PLL4-0 bits = “EH”, “FH”
312.5ns
1/(64fs)
Note 28.
LRCK
BICK “↑”
MS0596-J-01
max
Units
27
24.576
-
MHz
MHz
ns
ns
ns
48
55
-
kHz
%
%
12.288
60
-
MHz
%
%
1/(32fs)
-
ns
ns
ns
-
ns
ns
-
ns
ns
ns
ns
ns
ns
50
-
Hz
Hz
%
ns
ns
ns
-
ns
ns
ns
ns
ns
ns
ns
ns
2008/12
- 13 -
[AK4371]
Parameter
Control Interface Timing (I2C Bus mode): (Note 29)
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 30)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Capacitive Load on Bus
Pulse Width of Spike Noise Suppressed by Input Filter
Power-down & Reset Timing
PDN Pulse Width (Note 31)
Note 29. I2C
Note 30.
Note 31.
Philips Semiconductors
300ns (SCL
PDN pin “L”
Symbol
min
typ
max
Units
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
Cb
tSP
1.3
0.6
1.3
0.6
0.6
0
0.1
0.6
0
-
400
0.3
0.3
400
50
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
tPD
150
-
-
ns
)
“H”
MS0596-J-01
2008/12
- 14 -
[AK4371]
■
1/fCLK
tACW
1000pF
tACW
Measurement
Point
MCKI Input
VAC
100kΩ
VSS2
VSS2
Figure 3. MCKI AC Coupling Timing
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
MCKO
50%
DVDD
tH
tL
dMCK=tH/(tH+tL) or tL/(tH+tL)
Figure 4. Clock Timing
MS0596-J-01
2008/12
- 15 -
[AK4371]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDH
tSDS
VIH
SDATA
VIL
Figure 5. Serial Interface Timing (Slave Mode)
50%DVDD
LRCK
tMBLR
BICK
50%DVDD
tSDH
tSDS
VIH
SDATA
VIL
Figure 6. Serial Interface Timing (Master mode)
MS0596-J-01
2008/12
- 16 -
[AK4371]
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
CDTI
C1
tCDH
C0
R/W
VIH
A4
VIL
Figure 7. WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
D3
CDTI
D2
D1
VIH
D0
VIL
Figure 8. WRITE Data Input Timing
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
Start
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Figure 9. I2C Bus Mode Timing
tPD
PDN
VIL
Figure 10. Power-down & Reset Timing
MS0596-J-01
2008/12
- 17 -
[AK4371]
■
I/F
6
Mode
PLL Master Mode
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
(PLL Reference Clock: BICK pin)
PLL Slave Mode 3
(PLL Reference Clock: LRCK pin)
EXT Master Mode
EXT Slave Mode
Mode
(Table 1, Table 2.)
PMPLL bit
1
M/S bit
1
PLL4-0 bits
See Table 4
Figure
Figure 11
1
0
See Table 4
Figure 12
1
0
See Table 4
Figure 13
1
0
See Table 4
Figure 14
x
x
Figure 15
Figure 16
0
1
0
0
Table 1. Clock Mode Setting (x: Don’t care)
MCKO bit
0
PLL Master Mode
1
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
0
1
MCKO pin
“L”
PS1-0 bits
“L”
PS1-0 bits
MCKI pin
PLL4-0 bits
PLL4-0 bits
PLL Slave Mode 2
(PLL Reference Clock: BICK pin)
0
“L”
GND
PLL Slave Mode 3
(PLL Reference Clock: LRCK pin)
0
“L”
GND
EXT Master Mode
0
“L”
EXT Slave Mode
0
“L”
FS3-0 bits
FS3-0 bits
BICK pin
Output
(BF bit
)
LRCK pin
Input
(32fs ∼ 64fs)
Input
(1fs)
Input
(PLL4-0 bits
)
Input
(32fs ∼ 64fs)
Output
(BF bit
)
Input
(32fs ∼ 64fs)
Output
(1fs)
Input
(1fs)
Input
(1fs)
Output
(1fs)
Input
(1fs)
Table 2. Clock pins state in Clock Mode
■
M/S bit
(PDN pin = “L”)
AK4371
M/S bit
“1”
“0”
“1”
M/S bit “1”
AK4371 LRCK, BICK pin
AK4371
LRCK, BICK pin
100kΩ
M/S bit
Mode
0
Slave Mode
1
Master Mode
Table 3. Select Master/Slave Mode
MS0596-J-01
(default)
2008/12
- 18 -
[AK4371]
■ PLL
(PMPLL bit = “1”)
PMPLL bit = “1”
PLL
PLL
FS3-0 bit, PLL4-0 bit (Table 4, Table 5, Table 6)
PMPLL bit “0” Æ “1”
Table 4
1) PLL Mode
Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Others
PLL4
PLL3
PLL2
PLL1
PLL0
Reference Clock
0
0
0
0
0
MCKI
0
0
0
0
1
MCKI
0
0
0
1
0
MCKI
0
0
0
1
1
MCKI
0
0
1
0
0
MCKI
0
0
1
0
1
MCKI
0
0
1
1
0
MCKI
0
0
1
1
1
MCKI
0
1
0
0
0
MCKI
0
1
0
0
1
MCKI
0
1
0
1
0
MCKI
0
1
0
1
1
MCKI
0
1
1
0
0
MCKI
0
1
1
0
1
MCKI
0
1
1
1
0
BICK
0
1
1
1
1
BICK
1
0
0
0
0
LRCK
Others
N/A
Note 32. Type 1-4 Table 5
Note 33. Mode10-13 Mode5/7/8/9
Note 34. Mode 14-16 Slave Mode
Table 4. PLL
R,C at VCOC
C[F]
R[Ω]
10k
22n
10k
22n
10k
47n
10k
22n
10k
22n
15k
330n
10k
47n
10k
47n
15k
330n
10k
47n
10k
22n
10k
22n
10k
22n
10k
22n
6.8k
47n
6.8k
47n
6.8k
330n
fs
(Note 32)
11.2896MHz
14.4MHz
12MHz
19.2MHz
15.36MHz
13MHz
19.68MHz
19.8MHz
26MHz
27MHz
13MHz
26MHz
19.8MHz
27MHz
32fs
64fs
fs
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 2
Type 2
Type 3
Type 4
Table 6
Table 6
Table 6
PLL Lock
Time (typ
20ms
20ms
20ms
20ms
20ms
100ms
20ms
20ms
100ms
20ms
20ms
20ms
20ms
20ms
20ms
20ms
80ms
(default)
(PLL mode)
2) PLL Mode
PLL
MCKI
Table 5
Mode
FS3
FS2
FS1
FS0
0
1
2
4
5
6
8
9
10
3, 7,
11-15
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
Others
Table 5.
fs
Type 1
48kHz
24kHz
12kHz
32kHz
16kHz
8kHz
44.1kHz
22.05kHz
11.025kHz
Type 2
48.0007kHz
24.0004kHz
12.0002kHz
32.0005kHz
16.0002kHz
8.0001kHz
44.0995kHz
22.0498kHz
11.0249kHz
Type 3
47.9992kHz
23.9996kHz
11.9998kHz
31.9994kHz
15.9997kHz
7.9999kHz
44.0995kHz
22.0498kHz
11.0249kHz
Type 4
47.9997kHz
23.9999kHz
11.9999kHz
31.9998kHz
15.9999kHz
7.9999kHz
44.0995kHz
22.0498kHz
11.0249kHz
N/A
N/A
N/A
N/A
(PLL mode,
MS0596-J-01
(default)
=MCKI)
2008/12
- 19 -
[AK4371]
PLL
BICK
Mode
0
1
2
3
4
Others
FS3 bit
1
1
1
1
1
Table 6.
LRCK
Table 6
FS2 bit
FS1 bit
FS0 bit
0
0
0
0
1
0
0
0
1
0
1
1
1
0
0
Others
(PLL Mode,
Sampling Frequency Range
32kHz < fs ≤ 48kHz
24kHz < fs ≤ 32kHz
16kHz < fs ≤ 24kHz
12kHz < fs ≤ 16kHz
8kHz ≤ fs ≤ 12kHz
N/A
=BICK or LRCK)
(default)
■ PLL
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
BICK
(M/S bit = “1”) PMPLL bit = “0” Æ “1”
PMDAC bit = “0” Æ “1”
LRCK BICK “L”
MCKO bit = “1”
MCKO pin
MCKO bit = “0”
MCKO pin
“L”
PLL
AK4371
(Table 7)
PLL
LRCK
Master Mode (M/S bit = “1”)
Power Up
Power Down
PLL Unlock
(PMDAC bit= PMPLL bit= “1”) (PMDAC bit= PMPLL bit= “0”)
MCKI pin Refer to Table 4.
Input or
Refer to Table 4.
fixed to “L” or “H” externally
MCKO pin MCKO bit = “0”: “L”
“L”
MCKO bit = “0”: “L”
MCKO bit = “1”: Output
MCKO bit = “1”: Unsettling
BICK pin
BF bit = “1”: 64fs output
“L”
“L”
BF bit = “0”: 32fs output
LRCK pin Output
“L”
“L”
Table 7. Clock Operation in Master mode (PLL mode)
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
MCKO bit = “0”
9
(M/S bit = “0”) PMPLL bit = “0” Æ “1”
MCKO bit = “1”
MCKO pin
MCKO pin “L”
PMDAC bit = “0” Æ “1”
PLL
Slave Mode (M/S bit = “0”)
Power Up
Power Down
(PMDAC bit= PMPLL bit= “1”) (PMDAC bit= PMPLL bit= “0”)
MCKI pin Refer to Table 4.
Input or
fixed to “L” or “H” externally
MCKO pin MCKO bit = “0”: “L”
“L”
MCKO bit = “1”: Output
BICK pin
Input
Fixed to “L” or “H” externally
LRCK pin
Input
PLL
MCKO pin
Table
PLL Unlock
Refer to Table 4.
MCKO bit = “0”: “L”
MCKO bit = “1”: Unsettling
Input or
Fixed to “L” or “H”
externally
Fixed to “L” or “H” externally
Input or
Fixed to “L” or “H”
externally
Table 8. Clock Operation in Slave mode (PLL mode)
MS0596-J-01
2008/12
- 20 -
[AK4371]
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
26MHz, 27MHz
MCKO
BICK
BF bit
11.2896MHz, 12MHz, 13MHz, 14.4MHz, 15.36MHz, 19.2MHz, 19.68MHz, 19.8MHz,
PLL
MCKO, BICK, LRCK
PS1-0 bits (Table 9)
MCKO bit
ON/OFF
32fs or 64fs
(Table 10)
27MHz,26MHz,19.8MHz,19.68MHz,
19.2MHz,15.36MHz,14.4MHz,13MHz,
12MHz,11.2896MHz
AK4371
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
32fs, 64fs
1fs
MCLK
BCLK
LRCK
SDTO
SDATA
Figure 11. PLL Master Mode
PS1
PS0
MCKO
0
0
256fs
(default)
0
1
128fs
1
0
64fs
1
1
32fs
Table 9. MCKO
(PLL mode, MCKO bit = “1”)
BF bit
BICK
0
32fs
(default)
1
64fs
Table 10. BICK Output Frequency at Master Mode
MS0596-J-01
2008/12
- 21 -
[AK4371]
■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
MCKI, BICK or LRCK pin
PLL
a) PLL
MCKO
bit
PLL
AK4371
(Table 4)
PLL4-0 bit
: MCKI pin
BICK, LRCK
MCKO LRCK
(MCKO pin) PS1-0 bit (Table 9)
FS3-0 bit
ON/OFF
(PMDAC bit = “1”)
MCKI, LRCK
MCKO
(Table 5)
BICK
(PMDAC bit = “0”)
27MHz,26MHz,19.8MHz,19.68MHz,
19.2MHz,15.36MHz,14.4MHz,13MHz,
12MHz,11.2896MHz
AK4371
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
32fs ~ 64fs
1fs
MCLK
BCLK
LRCK
SDTO
SDATA
Figure 12. PLL Slave Mode (PLL Reference Clock: MCKI pin)
b) PLL
FS3-0 bit
: BICK pin
8kHz ∼ 48kHz
(Table 6)
AK4371
DSP or μP
MCKI
MCKO
BICK
LRCK
32fs or 64fs
1fs
BCLK
LRCK
SDTO
SDATA
Figure 13. PLL Slave Mode (PLL Reference Clock: BICK pin)
MS0596-J-01
2008/12
- 22 -
[AK4371]
c) PLL
FS3-0 bit
: LRCK pin
8kHz ∼ 48kHz
(Table 6)
AK4371
DSP or μP
MCKI
MCKO
BICK
LRCK
32fs ∼ 64fs
1fs
BCLK
LRCK
SDTO
SDATA
Figure 14. PLL Slave Mode (PLL Reference Clock: LRCK pin)
MS0596-J-01
2008/12
- 23 -
[AK4371]
■ EXT Mode (PMPLL bit = “0”: Default)
PMPLL bit
“0”
DAC
(Table 11)
PS1-0 bit
PLL4-0 bits
(M/S bit = “1”)
“1”)
(EXT mode)
MCKI pin
MCKI pin
MCKO
MCKO bit
DAC
(PMDAC bit = “1”)
“0”
LRCK
BICK
AK4371
(Figure 15)
PLL
FS3-0 bits
ON/OFF
(PMDAC bit =
MCKI pin
DAC
(PMDAC bit = “0”)
AK4371
DSP or μP
MCKO
256fs, 384fs, 512fs,
768fs or 1024fs
MCKI
32fs, 64fs
BICK
1fs
LRCK
MCLK
BCLK
LRCK
SDTO
SDATA
Figure 15. EXT Master Mode
(M/S bit = “0”)
MCKI, BICK, LRCK
(Figure 16) MCKI
DAC
(PMDAC bit = “1”)
LRCK
(MCKI, BICK, LRCK)
DAC
(PMDAC bit = “0”)
AK4371
DSP or μP
MCKO
MCKI
BICK
LRCK
256fs, 384fs, 512fs,
768fs or 1024fs
32fs
64fs
1fs
MCLK
BCLK
LRCK
SDTO
SDATA
Figure 16. EXT Slave Mode
MS0596-J-01
2008/12
- 24 -
[AK4371]
Mode
0
1
2
4
5
6
8
9
10
12
13
Others
FS3
0
0
0
0
0
0
1
1
1
1
1
FS2
0
0
0
1
1
1
0
0
0
1
1
Others
Table 11.
FS1
0
0
1
0
0
1
0
0
1
0
0
FS0
0
1
0
0
1
0
0
1
0
0
1
fs
8kHz ∼ 48kHz
8kHz ∼ 48kHz
8kHz ∼ 24kHz
8kHz ∼ 48kHz
8kHz ∼ 48kHz
8kHz ∼ 24kHz
8kHz ∼ 48kHz
8kHz ∼ 48kHz
8kHz ∼ 24kHz
8kHz ∼ 48kHz
8kHz ∼ 24kHz
N/A
MCKI
PS1
PS0
0
0
0
1
1
0
1
1
Table 12. MCKO
MCKI
256fs
512fs
1024fs
256fs
512fs
1024fs
256fs
512fs
1024fs
384fs
768fs
N/A
(EXT mode)
(default)
MCKO
256fs
(default)
128fs
64fs
32fs
(EXT mode, MCKO bit = “1”)
Master Mode (M/S bit = “1”)
Power Up (PMDAC bit = “1”)
Power Down (PMDAC bit = “0”)
MCKI pin Refer to Table 11.
Input or
fixed to “L” or “H” externally
MCKO pin MCKO bit = “0”: “L”
“L”
MCKO bit = “1”: Output
BICK pin
BF bit = “1”: 64fs output
“L”
BF bit = “0”: 32fs output
LRCK pin Output
“L”
Table 13. Clock Operation in Master mode (EXT mode)
Slave Mode (M/S bit = “0”)
Power Up (PMDAC bit = “1”)
Power Down (PMDAC bit = “0”)
MCKI pin Refer to Table 11.
Input or
fixed to “L” or “H” externally
MCKO pin MCKO bit = “0”: “L”
“L”
MCKO bit = “1”: Output
BICK pin
Input
Fixed to “L” or “H” externally
LRCK pin Input
Fixed to “L” or “H” externally
Table 14. Clock Operation in Slave mode (EXT mode)
DR, S/N
Table 15
DR, S/N
MCKI
DAC
DR,
S/N
MCKI
256fs/384fs/512fs
768fs/1024fs
Table 15. MCKI
DR, S/N (BW=20kHz, A-weight)
fs=8kHz
fs=16kHz
56dB
75dB
75dB
90dB
DR, S/N
(2.4V)
MS0596-J-01
2008/12
- 25 -
[AK4371]
■
SDATA, BICK, LRCK 3pin
(Table 16) DIF2-0 bits
Mode 1 Mode 0 20bit
DSP
Mode 2 3 16bit
LSB
21∼24bit
4
5
Mode 0
16bitDAC
Mode 4 Mode 0 24bit
Mode 3 I2S
LSB
17∼24bit
“0”
Mode 2
8
BICK=32fs(BF bit = “0”)
Mode
0
1
2
3
4
DIF2
0
0
0
0
1
DIF1
0
0
1
1
0
DIF0
0
1
0
1
0
ADC
BICK≥48fs
20bit
“0”
Mode 1, 2, 4
BICK
32fs ≤ BICK ≤ 64fs
40fs ≤ BICK ≤ 64fs
48fs ≤ BICK ≤ 64fs
BICK=32fs or 48fs ≤ BICK ≤ 64fs
48fs ≤ BICK ≤ 64fs
0: 16bit,
1: 20bit,
2: 24bit,
3: I2S
4: 24bit,
Table 16.
Figure 17
Figure 18
Figure 19
Figure 20
Figure 18
(default)
LRCK
BICK
(32fs)
SDATA
Mode 0
15
14
6
5
4
3
2
15
14
1
0
15
14
0
Don’t care
6
5
4
3
2
1
0
15
14
0
19
0
19
0
15
14
BICK
SDATA
Mode 0
Don’t care
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 17. Mode 0
(LRP = BCKP bits = “0”)
LRCK
BICK
SDATA
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19:MSB, 0:LSB
SDATA
Mode 4
Don’t care
23
22
21
20
23
22
21
20
23:MSB, 0:LSB
Lch Data
Figure 18. Mode 1, 4
Rch Data
(LRP = BCKP bits = “0”)
MS0596-J-01
2008/12
- 26 -
[AK4371]
Rch
Lch
LRCK
BICK
SDATA
15
14
0
19
18
4
1
0
23
22
8
3
4
Don’t
care
15
14
0
Don’t
care
19
18
4
1
0
Don’t
care
23
22
8
3
4
Don’t
care
15
14
Don’t
care
19
18
Don’t
care
23
22
16bit
SDATA
20bit
SDATA
1
0
1
0
24bit
Figure 19. Mode 2
(LRP = BCKP bits = “0”)
Lch
LRCK
Rch
BICK
SDATA
16bit
SDATA
20bit
SDATA
15
14
0
19
18
4
1
0
23
22
8
3
4
1
0
15
14
6
5
4
3
2
Don’t
care
15
14
0
Don’t
care
19
18
4
1
0
Don’t
care
23
22
8
3
4
1
15
14
6
5
4
3
Don’t
care
15
Don’t
care
19
0
Don’t
care
23
2
1
24bit
BICK
(32fs)
SDATA
16bit
0
Figure 20. Mode 3
1
0
0
15
(LRP = BCKP bits = “0”)
MS0596-J-01
2008/12
- 27 -
[AK4371]
■
AK4371
MUTE
0.5dB
256
DAC
(Table 17) DATTC bit “1”
ATTL7-0 bit
DATTC bit “0”
Lch, Rch
(DATT)
0dB
Lch, Rch
−127dB
ATTL7-0
Attenuation
ATTR7-0
FFH
0dB
FEH
−0.5dB
FDH
−1.0dB
FCH
−1.5dB
:
:
:
:
02H
−126.5dB
01H
−127.0dB
00H
(default)
MUTE (−∞)
Table 17. Digital Volume ATT
ATT7-0
ATT
@fs=44.1kHz)
“0”
00H
ATS bit 1061/fs 7424/fs
1062
FFH(0dB)
PDN pin “L”
ATT7-0 00H
PMDAC bit “1”
ATS
0
1
Table 18.
ATT speed
0dB to MUTE
1 step
1061/fs
4/fs
7424/fs
29/fs
ATT7-0
MS0596-J-01
(Table 18) ATS bit = “0”
00H(MUTE)
1061/fs (24ms
ATT7-0 PMDAC bit
(default)
2008/12
- 28 -
[AK4371]
■
×ATT
−∞
ATT
SMUTE bit
−∞ (“0”)
(Table 18)
×ATT
“1”
ATT
SMUTE bit
−∞
ATT
ATT
“0”
ATT
SMUTE bit
ATS bit
ATS bit
(1)
(1)
ATT Level
(3)
Attenuation
-∞
GD
(2)
GD
Analog Output
Figure 21.
Notes:
(1) ATT
3712/fs
(2)
(3)
×ATT
(Table 18)
ATS bit = “1”
ATT
“128”(−63.5dB)
(GD)
−∞
ATT
MS0596-J-01
2008/12
- 29 -
[AK4371]
■
IIR
3
DEM1-0 bit
(32kHz, 44.1kHz, 48kHz)
(50/15µs
(Table 19)
DEM1 bit
DEM0 bit
0
0
0
1
1
0
1
1
Table 19.
De-emphasis
44.1kHz
OFF
48kHz
32kHz
)
(default)
■
BST1-0 bit
DAC
(Table 20)
BST1 bit
0
0
1
1
BST0 bit
0
1
0
1
Table 20.
BOOST
OFF
MIN
MID
MAX
(default)
■
MONO1-0 bit
(Table 21)
DAC
MONO1 bit
0
0
1
1
Lch/Rch
MONO0 bit
0
1
0
1
Table 21.
Lch
L
L
R
(L+R)/2
Rch
R
L
R
(L+R)/2
(default)
■
PDN pin = “L”
PDN pin = “L”
AK4371
VCOM, DAC, HPL, HPR, LOUT, ROUT, MOUT
150ns
PDN pin
DAC
PMDAC bit
“1”
MCKI
MCKI
MS0596-J-01
2008/12
- 30 -
[AK4371]
■
(HPL, HPR pins)
HVDD
PMHPL=PMHPR bits = “1”
MUTEN bit “0”
16Ω
tr:
tf:
(VCOM/2
(VCOM/2
Table 22.
: MUTET pin
MUTET pin
MUTEN bit
“1”
VCOM(=0.475 x AVDD)
VSS1
70k x C (typ)
60k x C (typ)
)
)
C=1μF
(VCOM/2
(VCOM/2
): tr = 70k x 1μ = 70ms(typ)
): tf = 60k x 1μ = 60ms(typ)
PMHPL, PMHPR bits “0”
HPL, HPR pins VSS1
PMHPL/R bit
MUTEN bit
HPL/R pin
VCOM
VCOM/2
tf
tr
(1) (2)
(3)
(4)
Figure 22.
(1)
(2)
(PMHPL, PMHPR bits = “1”)
VSS1
(MUTEN bit = “1”) MUTET
MUTET pin
“C”
(tr)
70k x C(typ)
(3)
VSS1
VCOM/2
(4)
VCOM/2
(tf)
(MUTEN bit = “0”) MUTET
MUTET pin
60k x C(typ)
(PMHPL, PMHPR bits = “0”)
VSS1
MS0596-J-01
“C”
2008/12
- 31 -
[AK4371]
(fc)
(fc)
PMVREF bit = “0”
0.48 x AVDD (Vpp) @−3dBFS
Table 23
RL
16Ω
AVDD=2.4V, 3.0V, 3.3V
HP-AMP
R
C
Headphone
16Ω
AK4371
Figure 23.
R [Ω]
0
6.8
16
C [μF]
220
100
100
47
100
47
fc [Hz]
BOOST=OFF
45
100
70
149
50
106
Table 23.
fc [Hz]
BOOST=MIN
Output Power [mW]
17
43
28
78
19
47
,
f
2.4V
3.0V
3.3V
21
33
40
10
16
20
5
8
10
(PMVREF bit = “0”)
Wired OR
PMVCM=PMHPL=PMHPR bits = “0”, HPZ bit = “1”
200kΩ(typ) VSS1
OR
PMVCM
x
0
1
1
PMHPL/R
0
0
1
1
HP-Amp
AK4371 HP-Amp
HPMTN
HPZ
Mode
x
0
Power-down & Mute
x
1
Power-down
0
x
Mute
1
x
Normal Operation
Table 24. HP-Amp Mode Setting (x: Don’t care)
HPL, HPR pins
HP-Amp Wired
HPL/R pins
VSS1
Pull-down by 200kΩ
VSS1
Normal Operation
(default)
HPL pin
AK4371
Headphone
HPR pin
Another
HP-Amp
Figure 24.
Wired OR
MS0596-J-01
2008/12
- 32 -
[AK4371]
HPL
ON/OFF
DALHL, LIN1HL, RIN1HL, LIN2HL, RIN2HL, LIN3HL, RIN3HL bits
HPR
ON/OFF
DARHR, LIN1HR, RIN1HR, LIN2HR, RIN2HR,
LIN3HR, RIN3HR bits
L1HM=L2HM=L3HM bits = “0”, HPG1-0 bits = “00” (R1H= R2H= R3H= RDH =
100k), ATTH4-0 bits = “00H”(0dB)
+0.95dB(typ)
HPG1-0 bit = “01”
DAC
+6.95dB(typ)
HPG1-0 bit = “10” (RDH= 25k)
(RDH= 50k)
DAC
+12.95dB(typ)
L1HM, L2HM, L3HM bit
LIN1/RIN1,
LIN2/RIN2, LIN3/RIN3
(L+R)/2
HPL/R
(R1H= R2H= R3H= 200k)
LDIF=LDIFH=LIN1L=RIN1R bits = “1”
HPL/R pins
LIN1/RIN1 pins
IN−/+ pins
LIN1HL, RIN1HL, LIN1HR, RIN1HR bits
OFF
VCOM
“0”
(= 0.475 x AVDD)
Figure 58
100k(typ)
Figure 27
LDIFH bit
R1H
LIN1 pin
LIN1HL bit
R1H
RIN1 pin
RIN1HL bit
R2H
LIN2 pin
LIN2HL bit
R2H
RIN2 pin
RIN2HL bit
R3H
LIN3 pin
LIN3HL bit
R3H
100k(typ)
RIN3 pin
1.11RH
RIN3HL bit
RDH
DAC Lch
DALHL bit
−
RH
+
−
HPL pin
+
HP-Amp
100k(typ)
Figure 27
LDIFH bit
R1H
LIN1 pin
LIN1HR bit
R1H
RIN1 pin
RIN1HR bit
R2H
LIN2 pin
LIN2HR bit
R2H
RIN2 pin
RIN2HR bit
R3H
LIN3 pin
LIN3HR bit
R3H
100k(typ)
RIN3 pin
1.11RH
RIN3HR bit
RDH
DAC Rch
DARHR bit
−
RH
+
−
+
HPR pin
HP-Amp
Figure 25. HPL/R
MS0596-J-01
2008/12
- 33 -
[AK4371]
■
HPL/HPR
HMUTE bit = “0”
ATTH4-0 bit
+6dB ∼ −57dB or 0dB ∼ −63dB, 1.5dB or 3dB step, Table 25)
HMUTE
0
1
ATTH4-0
00H
01H
02H
03H
:
:
12H
13H
14H
15H
16H
:
:
1DH
1EH
1FH
x
HPG1-0 bits = “10”
HPG1-0 bits = “01”
HPG1-0 bits = “00”
(DAC Only)
(DAC Only)
+12dB
+6dB
0dB
+10.5dB
+4.5dB
−1.5dB
+9dB
+3dB
−3dB
+7.5dB
+1.5dB
−4.5dB
:
:
:
:
:
:
−15dB
−21dB
−27dB
−16.5dB
−22.5dB
−28.5dB
−18dB
−24dB
−30dB
−21dB
−27dB
−33dB
−24dB
−30dB
−36dB
:
:
:
:
:
:
−45dB
−51dB
−57dB
−48dB
−54dB
−60dB
−51dB
−57dB
−63dB
MUTE
MUTE
MUTE
Table 25. HPL/HPR Volume ATT values (x: Don’t care)
MS0596-J-01
(+12dB ∼ −51dB or
STEP
(default)
1.5dB
3dB
2008/12
- 34 -
[AK4371]
■
(LOUT, ROUT pins)
0.475 x AVDD
10kΩ
PMLO bit = “1”
LOUT
ON/OFF
DALL, LIN1L, RIN1L, LIN2L, RIN2L, LIN3L, RIN3L bits
ROUT
ON/OFF
DARR, LIN1R, RIN1R, LIN2R, RIN2R, LIN3R, RIN3R bits
L1M=L2M=L3M bits = “0”, LOG bit = “0” (R1L= R2L= R3L = RDL= 100k), ATTS3-0 bits = “0FH”(0dB)
0dB(typ)
LOG bit = “1” (RDL= 50k)
DAC
+6dB
L1M, L2M, L3M bit
LIN1/RIN1, LIN2/RIN2, LIN3/RIN3
(L+R)/2
LOUT/ROUT
(R1L= R2L= R3L = 200k)
OFF
VCOM
(= 0.475 x AVDD)
Figure 58
R1L
LIN1 pin
LIN1L bit
R1L
RIN1 pin
RIN1L bit
R2L
LIN2 pin
LIN2L bit
R2L
RIN2 pin
RIN2L bit
R3L
LIN3 pin
LIN3L bit
R3L
100k(typ)
RIN3 pin
RL
RIN3L bit
RDL
DAC Lch
DALL bit
−
RL
+
−
LOUT pin
+
R1L
LIN1 pin
LIN1R bit
R1L
RIN1 pin
RIN1R bit
R2L
LIN2 pin
LIN2R bit
R2L
RIN2 pin
RIN2R bit
R3L
LIN3 pin
LIN3R bit
R3L
100k(typ)
RIN3 pin
RL
RIN3R bit
RDL
DAC Rch
DARR bit
−
RL
+
−
+
ROUT pin
Figure 26. LOUT/ROUT
MS0596-J-01
2008/12
- 35 -
[AK4371]
LDIF=LIN1L=RIN1R bits = “1”
LOUT/ROUT pins
LIN1/RIN1 pins
IN−/+ pins
LOUT/ROUT pins
OFF
VCOM
(= 0.475 x AVDD)
Figure 58
Figure 25
HPL/R pins
Figure 28
MOUT pin
LDIFH bit
R1L
IN− pin
100k(typ)
LDIFM bit
RL
LIN1L bit
100k(typ)
LDIF bit
−
RL
+
R1L
IN+ pin
−
LOUT pin
+
100k(typ)
RL
RIN1R bit
−
RL
+
−
ROUT pin
+
Figure 27. LOUT/ROUT
(
)
■
(+6dB ∼ −24dB or
LOUT/ROUT
LMUTE bit = “0”
ATTS3-0 bit
0dB ∼ −30dB, 2dB step, Table 26) LOUT/ROUT
LMUTE
0
1
LOG bit = “1”
(DAC Only)
FH
+6dB
EH
+4dB
DH
+2dB
CH
0dB
:
:
:
:
1H
−22dB
0H
−24dB
x
MUTE
Table 26. LOUT/ROUT Volume ATT
ATTS3-0
MS0596-J-01
LOG bit = “0”
0dB
−2dB
−4dB
−6dB
:
:
−28dB
−30dB
MUTE
(x: Don’t care)
(default)
2008/12
- 36 -
[AK4371]
■
(MOUT pin)
0.475 x AVDD
600Ω
PMMO bit = “1”
MOUT
ON/OFF
DALM, DARM, LIN1M, RIN1M, LIN2M, RIN2M, LIN3M, RIN3M bits
MOG bit = “0”(RDM=100k), ATTM3-0 bits = “0FH”(0dB)
−6dB(typ)
MOG bit = “1” (RDM= 50k), ATTM3-0 bits = “0FH”(0dB)
DAC
0dB
LDIF=LDIFM=LIN1L=RIN1R bits = “1”
LIN1/RIN1 pins
MOUT pin
LIN1M, RIN1M bits “0”
IN−/+ pins
OFF
VCOM
(= 0.475 x AVDD)
Figure 58
100k(typ)
Figure 27
LDIFM bit
100k(typ)
LIN1 pin
LIN1M bit
100k(typ)
RIN1 pin
RIN1M bit
100k(typ)
LIN2 pin
LIN2M bit
100k(typ)
RIN2 pin
RIN2M bit
100k(typ)
LIN3 pin
LIN3M bit
100k(typ)
50k(typ)
RIN3 pin
RM
RIN3M bit
RDM
DAC Lch
DALM bit
RDM
−
RM
+
−
+
MOUT pin
DAC Rch
DARM bit
Figure 28. MOUT
■
MOUT
MMUTE bit = “0”
∼ −30dB, 2dB step, Table 27) MOUT
MMUTE
0
1
(+6dB ∼ −24dB or 0dB
ATTM3-0 bit
MOG bit = “1”
MOG bit = “0”
(DAC Only)
FH
+6dB
0dB
EH
+4dB
−2dB
DH
+2dB
−4dB
CH
0dB
−6dB
:
:
:
:
:
:
1H
−22dB
−28dB
0H
−24dB
−30dB
X
MUTE
MUTE
Table 27. MOUT Volume ATT (x: Don’t care)
ATTM3-0
MS0596-J-01
(default)
2008/12
- 37 -
[AK4371]
■
(EXT mode)
1) DAC → HP-Amp
(10)
Power Supply
(1)
>150ns
PDN pin
Don’t care
(2) >0s
PMVCM bit
Don’t care
(3)
Don’t care
Don’t care
Clock Input
PMDAC bit
DAC Internal
State
PD
Normal Operation
PD
Normal Operation
PD
SDTI pin
DALHL,
DARHR bits
(4) >0s
PMHPL,
PMHPR bits
(4) >0s
(5) >2ms
(5) >2ms
MUTEN bit
ATTL7-0
ATTR7-0 bits
00H(MUTE)
FFH(0dB)
(8) GD (9) 1061/fs
FFH(0dB)
00H(MUTE)
(8)
(8) (9)
(6)
(9)
00H(MUTE)
(8) (9)
(6)
(7)
(7)
HPL/R pin
Figure 29. DAC
(1) AVDD DVDD
AVDD HVDD
150ns
(2) PDN pin “H”
(3) DAC
HP-amp
DVDD
1.6V
AVDD
PDN pin “H”
PMVCM, PMDAC bit “1”
(MCKI, BICK, LRCK)
(4) PMVCM, PMDAC bits “1”
(5) DALHL, DARHR bits “1”
PMHPL, PMHPR, MUTEN bits “1”
(6)
(tr) 70k x C(typ)
C=1μF
(7)
(tf) 60k x C(typ)
C=1μF
DARHR bits
(Don’t care: Hi-Z
)
AVDD
HVDD
PMDAC bit = “0”
DALHL, DARHR bits
2ms
(VCOM pin
“1”
MUTET pin
(C)
tr 70ms(typ)
MUTET pin
(C)
tf 60ms(typ)
PMHPL, PMHPR “0”
2.2μF
)
VCOM/2
VCOM/2
DALHL,
“0”
(8)
(9)
(10)
AVDD
HVDD
22/fs(=499µs@fs=44.1kHz)
(GD)
ATS bit
1061/fs(=24ms@fs=44.1kHz)
OFF
AVDD DVDD
DVDD
AVDD HVDD
AVDD
MS0596-J-01
2008/12
- 38 -
[AK4371]
2) DAC → Lineout
Power Supply
(1) >150ns
PDN pin
(2)
>0s
PMVCM bit
Don’t care
(5)
Clock Input
Don’t care
Don’t care
(4) >0s
PMDAC bit
DAC Internal
State
PD
Normal Operation
PD(Power-down)
Normal Operation
SDTI pin
DALL,
DARR bits
(3) >0s
PMLO bit
ATTL/R7-0 bits
LMUTE,
ATTS3-0 bits
FFH(0dB)
00H(MUTE)
Figure 30. DAC
FFH(0dB)
0FH(0dB)
10H(MUTE)
(7) GD
LOUT/ROUT pins
00H(MUTE)
(8) 1061/fs (7)
(6)
(8)
(7)
(Hi-Z)
(8)
(6)
(6)
(Hi-Z)
Lineout
(Don’t care: Hi-Z
)
(1) AVDD DVDD
DVDD 1.6V
AVDD
AVDD HVDD
AVDD HVDD
150ns
PDN pin “H”
(2) PDN pin “H”
PMVCM bit “1”
(3) PMVCM bit “1”
DALL, DARR bits “1”
(4) DALL, DARR bits “1”
PMDAC, PMLO bits “1”
(5) DAC
(MCKI, BICK, LRCK)
PMDAC bit = “0”
LOUT/ROUT
(6) PMLO bit
LOUT, ROUT pins
(7)
22/fs(=499µs@fs=44.1kHz)
(GD)
(8)
ATS bit
1061/fs(=24ms@fs=44.1kHz)
MS0596-J-01
2008/12
- 39 -
[AK4371]
3) DAC → MOUT
Power Supply
(1) >150ns
PDN pin
(2)
>0s
PMVCM bit
Don’t care
(5)
Clock Input
Don’t care
Don’t care
(4) >0s
PMDAC bit
DAC Internal
State
PD
Normal Operation
PD(Power-down)
Normal Operation
SDTI pin
DALM,
DARM bits
(3) >0s
PMMO bit
ATTL/R7-0 bits
MMUTE,
ATTM3-0 bits
FFH(0dB)
00H(MUTE)
Figure 31. DAC
FFH(0dB)
0FH(0dB)
10H(MUTE)
(7) GD
MOUT pin
00H(MUTE)
(8) 1061/fs (7)
(6)
(8)
(7)
(Hi-Z)
(8)
(6)
(6)
(Hi-Z)
MOUT
(Don’t care: Hi-Z
)
(1) AVDD DVDD
DVDD 1.6V
AVDD
AVDD HVDD
AVDD HVDD
150ns
PDN pin “H”
(2) PDN pin “H”
PMVCM bit “1”
(3) PMVCM bit “1”
DALM, DARM bits “1”
(4) DALM, DARM bits “1”
PMDAC, PMMO bits “1”
(5) DAC
(MCKI, BICK, LRCK)
PMDAC bit = “0”
MOUT
(6) PMMO bit
MOUT pins
(7)
22/fs(=499µs@fs=44.1kHz)
(GD)
(8)
ATS bit
1061/fs(=24ms@fs=44.1kHz)
MS0596-J-01
2008/12
- 40 -
[AK4371]
4) LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 → HP-Amp
Power Supply
(1) >150ns
PDN pin
(2) >0s
PMVCM bit
Don’t care
LIN1HL, LIN2HL, LIN3HL
RIN1HR, RIN2HR, RIN3HL bits
(3) >0s
PMHPL/R bits
(5) >2ms
(5) >2ms
MUTEN bit
LIN1/RIN1/
LIN2/RIN2/
LIN3/RIN3 pins
(4)
(Hi-Z)
(Hi-Z)
(7)
(6)
(6)
HPL/R pins
Figure 32. LIN1/RIN1/LIN2/RIN2/LIN3/RIN3
(1) AVDD DVDD
AVDD HVDD
150ns
(MCKI, BICK, LRCK)
(2) PDN pin “H”
(3) PMVCM bit “1”
HP-amp
DVDD
PDN pin
1.6V
AVDD
“H”
AVDD
HVDD
DAC
PMVCM bit “1”
LIN1HL, LIN2HL, LIN3HL, RIN1HR, RIN2HR, RIN3HR bits
(4) LIN1HL, LIN2HL, LIN3HL, RIN1HR, RIN2HR, RIN3HR bits “1”
LIN3, RIN3
pin 0.475 x AVDD
(5) LIN1HL, LIN2HL, LIN3HL, RIN1HR, RIN2HR, RIN3HR bits “1”
2.2μF
)
PMHPL, PMHPR, MUTEN bits “1”
(6)
MUTET pin
(C)
(tr) 70k x C(typ)
C=1μF
tr 70ms(typ)
(7)
MUTET pin
(C)
(tf) 60k x C(typ)
C=1μF
tf 60ms(typ)
PMHPL, PMHPR bits “0”
LIN2HL, LIN3HL, RIN1HR, RIN2HR, RIN3HR bits “0”
MS0596-J-01
“1”
LIN1, RIN1, LIN2, RIN2,
2ms
(VCOM pin
VCOM/2
VCOM/2
LIN1HL,
2008/12
- 41 -
[AK4371]
5) LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 → Lineout
Power Supply
(1) >150ns
PDN pin
(2) >0s
PMVCM bit
Don’t care
LIN1L, RIN1R,
LIN2L, RIN2R,
LIN3L, RIN3R bits
(3) >0s
PMLO bit
(5) >2ms
(Hi-Z)
(4)
LIN1/RIN1/
LIN2/RIN2/
LIN3/RIN3 pins
LMUTE,
ATTS3-0 bits
(5) >2ms
(Hi-Z)
0FH(0dB)
10H(MUTE)
LOUT/ROUT pins
(6)
(6)
(Hi-Z)
Figure 33. LIN1/RIN1/LIN2/RIN2/LIN3/RIN3
(1) AVDD DVDD
AVDD HVDD
150ns
(MCKI, BICK, LRCK)
(2) PDN pin “H”
(3) PMVCM bit “1”
(6)
(Hi-Z)
LOUT/ROUT
DVDD
PDN pin
1.6V
AVDD
“H”
AVDD
HVDD
DAC
PMVCM bit “1”
LIN1L, LIN2L, LIN3L, RIN1R, RIN2R, RIN3R bits
(4) LIN1L, LIN2L, LIN3L, RIN1R, RIN2R, RIN3R bits
pin 0.475 x AVDD
(5) LIN1L, LIN2L, LIN3L, RIN1R, RIN2R, RIN3R bits
2.2μF
)
PMLO bit “1”
(6) PMLO bit
LOUT, ROUT pins
“1”
“1”
LIN1, RIN1, LIN2, RIN2, LIN3, RIN3
“1”
2ms
MS0596-J-01
(VCOM pin
2008/12
- 42 -
[AK4371]
6) LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 → MOUT
Power Supply
(1) >150ns
PDN pin
(2) >0s
PMVCM bit
Don’t care
LIN1M, RIN1M,
LIN2M, RIN2M,
LIN3M, RIN3M bits
(3) >0s
PMMO bit
(5) >2ms
(Hi-Z)
(4)
LIN1/RIN1/
LIN2/RIN2/
LIN3/RIN3 pins
MMUTE,
ATTM3-0 bits
(5) >2ms
(Hi-Z)
0FH(0dB)
10H(MUTE)
MOUT pin
(6)
(6)
(Hi-Z)
Figure 34. LIN1/RIN1/LIN2/RIN2/LIN3/RIN3
(1) AVDD DVDD
AVDD HVDD
150ns
(MCKI, BICK, LRCK)
(2) PDN pin “H”
(3) PMVCM bit “1”
(6)
(Hi-Z)
MOUT
DVDD
PDN pin
1.6V
AVDD
“H”
AVDD
HVDD
DAC
PMVCM bit “1”
LIN1M, LIN2M, LIN3M, RIN1M, RIN2M, RIN3M bits
(4) LIN1M, LIN2M, LIN3M, RIN1M, RIN2M, RIN3M bits
RIN3
pin 0.475 x AVDD
(5) LIN1M, LIN2M, LIN3M, RIN1M, RIN2M, RIN3M bits
2.2μF
)
PMMO bits “1”
(6) PMMO bit
MOUT pins
“1”
“1”
LIN1, RIN1, LIN2, RIN2, LIN3,
“1”
2ms
MS0596-J-01
(VCOM pin
2008/12
- 43 -
[AK4371]
„
(PLL Slave mode)
1) DAC → HP-Amp
Power Supply
(12)
(1)
>150ns
PDN pin
Don’t care
(2) >0s
PMVCM, PMPLL,
PMDAC, MCKO bits
Don’t care
(3)
Don’t care
Don’t care
MCKI pin
Unstable
(4) ~20ms
Don’t care
(5)
Unstable
(4) ~20ms
MCKO pin
Unstable
Don’t care
BICK,
LRCK pins
Unstable
Unstable
DAC Internal
State
PD
Don’t care
Normal Operation
PD
Unstable
Normal Operation
PD
Don’t care
SDTI pin
DALHL,
DARHR bits
Unstable
(6) >0s
PMHPL,
PMHPR bits
(6) >0s
(7) >2ms
(7) >2ms
MUTEN bit
ATTL7-0
ATTR7-0 bits
00H(MUTE)
FFH(0dB)
FFH(0dB)
00H(MUTE)
(9)
(8)
00H(MUTE)
(10)(11) (10) (11)
(10) GD (11) 1061/fs (10) (11)
(9)
(8)
HPL/R pin
Figure 35. DAC
HP-amp
(Don’t care: Hi-Z
DVDD 1.6V
(1) AVDD DVDD
AVDD HVDD
AVDD HVDD
150ns
PDN pin “H”
PMVCM, PMPLL, PMDAC, MCKO bits “1”
(2) PDN pin “H”
PLL
(3) MCKI pin
Table 4
PLL
MCKO pin
(4) PLL
MCKO
(BICK, LRCK)
(5) DAC
)
AVDD
PMDAC bit = “0”
DALHL, DARHR bits “1”
(6) PLL
2ms
(VCOM pin
2.2μF
)
(7) DALHL, DARHR bits “1”
PMHPL, PMHPR, MUTEN bits “1”
MUTET pin
(C)
VCOM/2
(8)
C=1μF
tr 70ms(typ)
(tr) 70k x C(typ)
MUTET pin
(C)
VCOM/2
(9)
C=1μF
tf 60ms(typ)
(tf) 60k x C(typ)
PMHPL, PMHPR “0”
DALHL,
DARHR bits “0”
22/fs(=499µs@fs=44.1kHz)
(GD)
(10)
ATS bit
1061/fs(=24ms@fs=44.1kHz)
(11)
OFF
AVDD DVDD
(12)
AVDD
DVDD
AVDD HVDD
HVDD
AVDD
MS0596-J-01
2008/12
- 44 -
[AK4371]
2) DAC → Lineout
Power Supply
(1) >150ns
PDN pin
(2)>0s
PMVCM, PMPLL,
PMDAC, MCKO bits
Don’t care
Don’t care
Don’t care
(3)
MCKI pin
(4) ~20ms
Unstable
Unstable
(4) ~20ms
MCKO pin
Don’t care
Unstable
(5)
Unstable
BICK, LRCK pins
Unstable
DAC Internal
State
Unstable
PD
Normal Operation
Don’t care
PD
Normal Operation
Unstable
Unstable
SDTI pin
DALL,
DARR bits
(6) >0s
(6) >0s
(7) >0s
(7) >0s
PMLO bit
ATTL/R7-0 bits
LMUTE,
ATTS3-0 bits
00H(MUTE)
FFH(0dB)
10H(MUTE)
Figure 36. DAC
(8)
(9) (10)
(9)
(Hi-Z)
(Hi-Z)
Lineout
DALL, DARR bits
(10)
(8)
(8)
(Don’t care: Hi-Z
(1) AVDD DVDD
DVDD 1.6V
AVDD HVDD
AVDD HVDD
150ns
PDN pin “H”
(2) PDN pin “H”
PMVCM, PMPLL, PMDAC, MCKO bits “1”
(3) MCKI pin
PLL
(4) PLL
Table 4
PLL
MCKO pin
(5) DAC
MCKO
(BICK, LRCK)
LOUT/ROUT
(6) PLL
(7) PMLO bit
(8) PMLO bit
(9)
(10)
FFH(0dB)
0FH(0dB)
(9) GD (10) 1061/fs
LOUT/ROUT pins
00H(MUTE)
)
AVDD
PMDAC bit = “0”
“1”
“1”
LOUT, ROUT pins
22/fs(=499µs@fs=44.1kHz)
ATS bit
MS0596-J-01
(GD)
1061/fs(=24ms@fs=44.1kHz)
2008/12
- 45 -
[AK4371]
3) DAC → MOUT
Power Supply
(1) >150ns
PDN pin
(2)>0s
PMVCM, PMPLL,
PMDAC, MCKO bits
Don’t care
Don’t care
Don’t care
(3)
MCKI pin
(4) ~20ms
Unstable
Unstable
(4) ~20ms
MCKO pin
Don’t care
Unstable
(5)
Unstable
BICK, LRCK pins
Unstable
DAC Internal
State
Unstable
PD
Normal Operation
Don’t care
PD
Normal Operation
Unstable
Unstable
SDTI pin
DALM,
DARM bits
(6) >0s
(6) >0s
(7) >0s
(7) >0s
PMMO bit
ATTL/R7-0 bits
00H(MUTE)
MMUTE,
ATTM3-0 bits
FFH(0dB)
00H(MUTE)
10H(MUTE)
FFH(0dB)
0FH(0dB)
(10) GD (11) 1061/fs (10) (11)
(9)
MOUT pins
(1) AVDD
(9)
(Hi-Z)
Figure 37. DAC
(5) DAC
(11)
(9)
(Hi-Z)
MOUT
DVDD
AVDD
(2) PDN pin “H”
(3) MCKI pin
(4) PLL
(10)
(Don’t care: Hi-Z
DVDD
1.6V
HVDD
AVDD HVDD
150ns
PDN pin “H”
PMVCM, PMPLL, PMDAC, MCKO bits “1”
PLL
Table 4
PLL
MCKO pin
MCKO
(BICK, LRCK)
)
AVDD
PMDAC bit = “0”
MOUT
(6) PLL
(7) PMLO bit
(8) PMLO bit
(9)
(10)
DALM, DARM bits
“1”
“1”
MOUT pin
22/fs(=499µs@fs=44.1kHz)
ATS bit
MS0596-J-01
(GD)
1061/fs(=24ms@fs=44.1kHz)
2008/12
- 46 -
[AK4371]
4) LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 → HP-Amp
Power Supply
(1) >150ns
PDN pin
(2) >0s
PMVCM bit
Don’t care
LIN1HL, LIN2HL, LIN3HL
RIN1HR, RIN2HR, RIN3HL bits
(3) >0s
PMHPL/R bits
(5) >2ms
(5) >2ms
MUTEN bit
LIN1/RIN1/
LIN2/RIN2/
LIN3/RIN3 pins
(4)
(Hi-Z)
(Hi-Z)
(7)
(6)
(6)
HPL/R pins
Figure 38. LIN1/RIN1/LIN2/RIN2/LIN3/RIN3
(1) AVDD
HP-amp
DVDD
AVDD
DVDD 1.6V
AVDD
HVDD
AVDD HVDD
150ns
PDN pin “H”
DAC
(MCKI, BICK, LRCK)
(2) PDN pin “H”
PMVCM bit “1”
(3) PMVCM bit “1”
LIN1HL, LIN2HL, LIN3HL, RIN1HR, RIN2HR, RIN3HR bits
(4) LIN1HL, LIN2HL, LIN3HL, RIN1HR, RIN2HR, RIN3HR bits “1”
LIN3, RIN3
pin 0.475 x AVDD
(5) LIN1HL, LIN2HL, LIN3HL, RIN1HR, RIN2HR, RIN3HR bits “1”
2.2μF
)
PMHPL, PMHPR, MUTEN bits “1”
(6)
MUTET pin
(C)
(tr) 70k x C(typ)
C=1μF
tr 70ms(typ)
(7)
MUTET pin
(C)
(tf) 60k x C(typ)
C=1μF
tf 60ms(typ)
PMHPL, PMHPR bits
LIN2HL, LIN3HL, RIN1HR, RIN2HR, RIN3HR bits “0”
MS0596-J-01
“1”
LIN1, RIN1, LIN2, RIN2,
2ms
(VCOM pin
VCOM/2
VCOM/2
“0”
LIN1HL,
2008/12
- 47 -
[AK4371]
5) LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 → Lineout
Power Supply
(1) >150ns
PDN pin
(2) >0s
PMVCM bit
Don’t care
LIN1L, RIN1R,
LIN2L, RIN2R,
LIN3L, RIN3R bits
(3) >0s
PMLO bit
LIN1/RIN1/
LIN2/RIN2/
LIN3/RIN3 pins
LMUTE,
ATTS3-0 bits
LOUT/ROUT pins
(5) >2ms
(5) >2ms
(4)
(Hi-Z)
(Hi-Z)
0FH(0dB)
10H(MUTE)
(6)
(6)
(Hi-Z)
Figure 39. LIN1/RIN1/LIN2/RIN2/LIN3/RIN3
(1) AVDD
DVDD
AVDD
(6)
(Hi-Z)
DVDD
LOUT/ROUT
1.6V
AVDD
“H”
AVDD
HVDD
HVDD
150ns
PDN pin
DAC
(MCKI, BICK, LRCK)
(2) PDN pin “H”
PMVCM bit “1”
(3) PMVCM bit “1”
LIN1L, LIN2L, LIN3L, RIN1R, RIN2R, RIN3R bits
(4) LIN1L, LIN2L, LIN3L, RIN1R, RIN2R, RIN3R bits
pin 0.475 x AVDD
(5) LIN1L, LIN2L, LIN3L, RIN1R, RIN2R, RIN3R bits
2.2μF
)
PMLO bit “1”
(6) PMLO bit
LOUT, ROUT pins
“1”
“1”
LIN1, RIN1, LIN2, RIN2, LIN3, RIN3
“1”
2ms
MS0596-J-01
(VCOM pin
2008/12
- 48 -
[AK4371]
6) LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 → MOUT
Power Supply
(1) >150ns
PDN pin
(2) >0s
PMVCM bit
Don’t care
LIN1M, RIN1M,
LIN2M, RIN2M,
LIN3M, RIN3M bits
(3) >0s
PMMO bit
(5) >2ms
(4)
LIN1/RIN1/
LIN2/RIN2/
LIN3/RIN3 pins
MMUTE,
ATTM3-0 bits
(5) >2ms
(Hi-Z)
(Hi-Z)
0FH(0dB)
10H(MUTE)
MOUT pin
(6)
(6)
(Hi-Z)
Figure 40. LIN1/RIN1/LIN2/RIN2/LIN3/RIN3
(1) AVDD DVDD
AVDD HVDD
150ns
(MCKI, BICK, LRCK)
(2) PDN pin “H”
(3) PMVCM bit “1”
(6)
(Hi-Z)
MOUT
DVDD
PDN pin
1.6V
AVDD
“H”
AVDD
HVDD
DAC
PMVCM bit “1”
LIN1M, LIN2M, LIN3M, RIN1M, RIN2M, RIN3M bits
(4) LIN1M, LIN2M, LIN3M, RIN1M, RIN2M, RIN3M bits
RIN3
pin 0.475 x AVDD
(5) LIN1M, LIN2M, LIN3M, RIN1M, RIN2M, RIN3M bits
2.2μF
)
PMMO bits “1”
(6) PMMO bit
MOUT pin
“1”
“1”
LIN1, RIN1, LIN2, RIN2, LIN3,
“1”
2ms
MS0596-J-01
(VCOM pin
2008/12
- 49 -
[AK4371]
„
(PLL Master mode)
1) DAC → HP-Amp
Power Supply
(11)
(1)
>150ns
PDN pin
Don’t care
(2) >0
M/S, PMVCM, PMPLL,
PMDAC, MCKO bits
Don’t care (3)
Don’t care
Don’t care
MCKI pin
Unstable
(4) ~20ms
Unstable
(4) ~20ms
MCKO pin
Don’t care “L”
Unstable
Don’t care
BICK, LRCK pins
Unstable
Unstable
DAC Internal
State
PD
Normal Operation
PD
Don’t care
Normal Operation
PD
Unstable
Don’t care
SDTI pin
Unstable
DALHL,
DARHR bits
(5) >0
PMHPL,
PMHPR bits
(6) >0
(6) >2ms
(7) >2ms
MUTEN bit
ATTL7-0
ATTR7-0 bits
00H(MUTE)
FFH(0dB)
(9) GD (10) 1061/fs (9)
FFH(0dB)
00H(MUTE)
(10)
(7)
(8)
(9) (10)
00H(MUTE)
(9)(10)
(7)
(8)
HPL/R pin
Figure 41. DAC
HP-amp
(Don’t care: Hi-Z
)
(1) AVDD DVDD
DVDD 1.6V
AVDD
AVDD HVDD
AVDD HVDD
150ns
PDN pin "H"
(2) PDN pin "H"
PMVCM, PMPLL, PMDAC, MCKO, M/S bits “1”
(3) MCKI pin
PLL
(4) PLL
Table 4
PLL
BICK, LRCK, MCKO pins
(5) PLL
DALHL, DARHR bits “1”
(6) DALHL, DARHR bits “1”
2ms
(VCOM pin
2.2µF
)
PMHPL, PMHPR, MUTEN bits “1”
(7)
MUTET pin
(C)
VCOM/2
(tr) 70k x C(typ)
C=1µF
tr 70ms(typ)
(8)
MUTET pin
(C)
VCOM/2
(tf) 60k x C(typ)
C=1µF
tf 60ms(typ)
PMHPL, PMHPR bits “0”
DALHL,
DARHR bits “0”
(9)
22/fs(=499µs@fs=44.1kHz)
(GD)
(10)
ATS bit
1061/fs(=24ms@fs=44.1kHz)
(11)
OFF
AVDD DVDD
AVDD
DVDD
AVDD HVDD
HVDD
AVDD
MS0596-J-01
2008/12
- 50 -
[AK4371]
2) DAC → Lineout
Power Supply
(1) >150ns
PDN pin
(2)
>0
M/S, PMVCM, PMPLL,
PMDAC, MCKO bits
Don’t care
Don’t care
Don’t care
(3)
MCKI pin
(4) ~20ms
Unstable
Unstable
(4) ~20ms
MCKO pin
Don’t care
“L”
Unstable
BICK, LRCK pins
Unstable
DAC Internal
State
Unstable
PD
Normal Operation
Don’t care
PD
Unstable
Normal Operation
Unstable
SDTI pin
DALL,
DARR bits
(5) >0
(5) >0
(6) >0
(6) >0
PMLO bit
ATTL/R7-0 bits
LMUTE,
ATTS3-0 bits
FFH(0dB)
00H(MUTE)
10H(MUTE)
(7)
(8) (9)
(8)
(9)
(7)
(8)
(Hi-Z)
Figure 42. DAC
FFH(0dB)
0FH(0dB)
(8) GD (9) 1061/fs
LOUT/ROUT pins
00H(MUTE)
(Hi-Z)
Lineout
(Don’t care: Hi-Z
)
(1) AVDD DVDD
DVDD 1.6V
AVDD
AVDD HVDD
AVDD HVDD
150ns
PDN pin “H”
(2) PDN pin “H”
PMVCM, PMPLL, PMDAC, MCKO, M/S bits “1”
(3) MCKI pin
PLL
(4) PLL
Table 4
PLL
BICK, LRCK, MCKO pins
(5) PLL
(6) PMLO bit
(7) PMLO bit
(8)
(9)
DALL, DARR bits
“1”
“1”
LOUT, ROUT pins
22/fs(=499μs@fs=44.1kHz)
ATS bit
MS0596-J-01
(GD)
1061/fs(=24ms@fs=44.1kHz)
2008/12
- 51 -
[AK4371]
3) DAC → MOUT
Power Supply
(1) >150ns
PDN pin
(2)
>0
M/S, PMVCM, PMPLL,
PMDAC, MCKO bits
Don’t care
Don’t care
Don’t care
(3)
MCKI pin
(4) ~20ms
Unstable
Unstable
(4) ~20ms
MCKO pin
Don’t care
“L”
Unstable
BICK, LRCK pins
Unstable
DAC Internal
State
Unstable
PD
Normal Operation
Don’t care
PD
Unstable
Normal Operation
Unstable
SDTI pin
DALM,
DARM bits
(5) >0
(5) >0
(6) >0
(6) >0
PMMO bit
ATTL/R7-0 bits
MMUTE,
ATTM3-0 bits
FFH(0dB)
00H(MUTE)
10H(MUTE)
(7)
(8) (9)
(8)
(9)
(7)
(7)
(Hi-Z)
Figure 43. DAC
FFH(0dB)
0FH(0dB)
(8) GD (9) 1061/fs
MOUT pin
00H(MUTE)
(Hi-Z)
MOUT
(Don’t care: Hi-Z
)
(1) AVDD DVDD
DVDD 1.6V
AVDD
AVDD HVDD
AVDD HVDD
150ns
PDN pin “H”
(2) PDN pin “H”
PMVCM, PMPLL, PMDAC, MCKO, M/S bits “1”
(3) MCKI pin
PLL
(4) PLL
Table 4
PLL
BICK, LRCK, MCKO pins
(5) PLL
(6) PMMO bit
(7) PMMO bit
(8)
(9)
DALM, DARM bits
“1”
“1”
MOUT pin
22/fs(=499μs@fs=44.1kHz)
ATS bit
MS0596-J-01
(GD)
1061/fs(=24ms@fs=44.1kHz)
2008/12
- 52 -
[AK4371]
4) LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 → HP-Amp
Power Supply
(1) >150ns
PDN pin
(2) >0s
PMVCM bit
Don’t care
LIN1HL, LIN2HL, LIN3HL
RIN1HR, RIN2HR, RIN3HL bits
(3) >0s
PMHPL/R bits
(5) >2ms
(5) >2ms
MUTEN bit
LIN1/RIN1/
LIN2/RIN2/
LIN3/RIN3 pins
(Hi-Z)
(4)
(Hi-Z)
(7)
(6)
(6)
HPL/R pins
Figure 44. LIN1/RIN1/LIN2/RIN2/LIN3/RIN3
(1) AVDD
DVDD
AVDD HVDD
150ns
(MCKI, BICK, LRCK)
(2) PDN pin “H”
(3) PMVCM bit “1”
HP-amp
DVDD
PDN pin
1.6V
AVDD
“H”
AVDD
HVDD
DAC
PMVCM bit “1”
LIN1HL, LIN2HL, LIN3HL, RIN1HR, RIN2HR, RIN3HR bits
(4) LIN1HL, LIN2HL, LIN3HL, RIN1HR, RIN2HR, RIN3HR bits “1”
LIN3, RIN3
pin 0.475 x AVDD
(5) LIN1HL, LIN2HL, LIN3HL, RIN1HR, RIN2HR, RIN3HR bits “1”
2.2μF
)
PMHPL, PMHPR, MUTEN bits “1”
(6)
MUTET pin
(C)
(tr) 70k x C(typ)
C=1μF
tr 70ms(typ)
(7)
MUTET pin
(C)
(tf) 60k x C(typ)
C=1μF
tf 60ms(typ)
PMHPL, PMHPR bits “0”
LIN2HL, LIN3HL, RIN1HR, RIN2HR, RIN3HR bits “0”
MS0596-J-01
“1”
LIN1, RIN1, LIN2, RIN2,
2ms
(VCOM pin
VCOM/2
VCOM/2
LIN1HL,
2008/12
- 53 -
[AK4371]
5) LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 → Lineout
Power Supply
(1) >150ns
PDN pin
(2) >0s
PMVCM bit
Don’t care
LIN1L, RIN1R,
LIN2L, RIN2R,
LIN3L, RIN3R bits
(3) >0s
PMLO bit
LIN1/RIN1/
LIN2/RIN2/
LIN3/RIN3 pins
LMUTE,
ATTS3-0 bits
LOUT/ROUT pins
(5) >2ms
(5) >2ms
(Hi-Z)
(4)
(Hi-Z)
0FH(0dB)
10H(MUTE)
(6)
(6)
(Hi-Z)
Figure 45. LIN1/RIN1/LIN2/RIN2/LIN3/RIN3
(6)
(Hi-Z)
LOUT/ROUT
(1) AVDD
DVDD
DVDD 1.6V
AVDD
AVDD HVDD
AVDD HVDD
150ns
PDN pin “H”
DAC
(MCKI, BICK, LRCK)
(2) PDN pin “H”
PMVCM bit “1”
(3) PMVCM bit “1”
LIN1L, LIN2L, LIN3L, RIN1R, RIN2R, RIN3R bits “1”
(4) LIN1L, LIN2L, LIN3L, RIN1R, RIN2R, RIN3R bits
pin 0.475 x AVDD
(5) LIN1L, LIN2L, LIN3L, RIN1R, RIN2R, RIN3R bits
2.2μF
)
PMLO bit “1”
(6) PMLO bit
LOUT, ROUT pins
“1”
LIN1, RIN1, LIN2, RIN2, LIN3, RIN3
“1”
2ms
MS0596-J-01
(VCOM pin
2008/12
- 54 -
[AK4371]
6) LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 → MOUT
Power Supply
(1) >150ns
PDN pin
(2) >0s
PMVCM bit
Don’t care
LIN1M, RIN1M,
LIN2M, RIN2M,
LIN3M, RIN3M bits
(3) >0s
PMMO bit
LIN1/RIN1/
LIN2/RIN2/
LIN3/RIN3 pins
MMUTE,
ATTM3-0 bits
MOUT pin
(5) >2ms
(5) >2ms
(Hi-Z)
(4)
(Hi-Z)
0FH(0dB)
10H(MUTE)
(6)
(6)
(Hi-Z)
(6)
(Hi-Z)
Figure 46. LIN1/RIN1/LIN2/RIN2/LIN3/RIN3
MOUT
(1) AVDD
DVDD
DVDD 1.6V
AVDD
AVDD HVDD
AVDD HVDD
150ns
PDN pin “H”
DAC
(MCKI, BICK, LRCK)
(2) PDN pin “H”
PMVCM bit “1”
(3) PMVCM bit “1”
LIN1M, LIN2M, LIN3M, RIN1M, RIN2M, RIN3M bits
(4) LIN1M, LIN2M, LIN3M, RIN1M, RIN2M, RIN3M bits
RIN3
pin 0.475 x AVDD
(5) LIN1M, LIN2M, LIN3M, RIN1M, RIN2M, RIN3M bits
2.2μF
)
PMMO bits “1”
(6) PMMO bit
MOUT pin
“1”
“1”
LIN1, RIN1, LIN2, RIN2, LIN3,
“1”
2ms
MS0596-J-01
(VCOM pin
2008/12
- 55 -
[AK4371]
■
(1) 3
(I2C pin = “L”)
3
I/F
: CSN, CCLK, CDTI
I/F
Chip
address(2bits, “01”
), Read/Write(1bit, Fixed to “1”, Write only), Register address(MSB first, 5bits), Control
data(MSB first, 8bits)
CCLK
CCLK 16
1
CSN
“H”
CCLK
5MHz (max)
PDN pin = “L”
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (Fixed to “01”)
READ/WRITE (Fixed to “1”, Write only)
Register Address
Control Data
Figure 47. 3
I/F
MS0596-J-01
2008/12
- 56 -
[AK4371]
(2) I2C
AK4371
(I2C pin = “H”)
Fast-mode (max:400kHz, Ver1.0)
I 2C
(2)-1. WRITE
I2C
(Start Condition)
(Figure 54)
8bit
IC
AK4371
SCL
2
“L”
7bit
6bit
“001000”
(Figure 49)
1bit
(Acknowledge)
(Figure 55) R/W
(
(Figure 50)
3
(Figure 51) AK4371
“L”
IC
“H”
SDA
(R/W)
CAD0 pin
SDA
“1”
R/W
Figure 48
“H”
)
8bit MSB first
8bit
(Stop Condition)
(Figure 54)
“H”
“0”
SCL
AK4371
“H”
3bit “0”
MSB first
SDA
1
“13H”
“00H”
“H”
SDA
SCL
“L”
(Figure 56)
“H”
SCL
“L”
“H”
SDA
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “0”
Slave
Address
Sub
Address(n)
A
C
K
Data(n)
Data(n+x)
Data(n+1)
A
C
K
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 48. I2C
0
0
1
0
0
0
CAD0
R/W
A3
A2
A1
A0
D3
D2
D1
D0
(CAD0 pin
Figure 49. 1
0
0
0
A4
Figure 50.
D7
D6
D5
Figure 51.
)
2
D4
3
MS0596-J-01
2008/12
- 57 -
[AK4371]
(2)-2. READ
R/W
“1”
AK4371
READ
“13H”
“00H”
AK4371
2
READ
(2)-2-1.
AK4371
AK4371
(READ
WRITE
“n+1”
(R/W = “1”)
READ
)
“n”
1
READ
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
Data(n+2)
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 52. CURRENT ADDRESS READ
(2)-2-2.
READ
(R/W bit= “1”)
“0”)
WRITE
WRITE
AK4371
(R/W bit= “1”)
READ
(R/W =
AK4371
1
READ
S
T
A
R
T
SDA
S
S
T
A
R
T
R/W= “0”
Sub
Address(n)
Slave
Address
A
C
K
S
A
C
K
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+x)
Data(n+1)
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 53. RANDOM ADDRESS READ
MS0596-J-01
2008/12
- 58 -
[AK4371]
SDA
SCL
S
P
start condition
stop condition
Figure 54.
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 55. I2C
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 56. I2C
MS0596-J-01
2008/12
- 59 -
[AK4371]
■
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
Register Name
Power Management 0
PLL Control
Clock Control
Mode Control 0
Mode Control 1
DAC Lch ATT
DAC Rch ATT
Headphone Out Select 0
Lineout Select 0
Lineout ATT
Reserved
Reserved
Reserved
Headphone Out Select 1
Headphone ATT
Lineout Select 1
Mono Mixing
Differential Select
MOUT Select
MOUT ATT
PDN pin = “L”
PDN pin “L”
14H
1FH
“0”
D7
PMVREF
FS3
PLL4
0
ATS
ATTL7
ATTR7
HPG1
0
0
0
0
0
RIN3HR
0
RIN3R
0
0
RIN3M
0
D6
PMPLL
FS2
0
MONO1
DATTC
ATTL6
ATTR6
HPG0
LOG
0
0
0
0
RIN3HL
HPZ
RIN3L
0
0
LIN3M
PMMO
D5
PMLO
FS1
M/S
MONO0
LMUTE
ATTL5
ATTR5
LIN2HR
LIN2R
0
0
0
0
LIN3HR
HMUTE
LIN3R
L3M
0
RIN2M
MOG
D4
MUTEN
FS0
MCKAC
BCKP
SMUTE
ATTL4
ATTR4
LIN2HL
LIN2L
0
0
0
0
LIN3HL
ATTH4
LIN3L
L3HM
0
LIN2M
MMUTE
D3
PMHPR
PLL3
BF
LRP
BST1
ATTL3
ATTR3
RIN1HR
RIN1R
ATTS3
0
0
0
RIN2HR
ATTH3
RIN2R
L2M
0
RIN1M
ATTM3
D2
PMHPL
PLL2
PS0
DIF2
BST0
ATTL2
ATTR2
LIN1HL
LIN1L
ATTS2
0
0
0
RIN2HL
ATTH2
RIN2L
L2HM
LDIFM
LIN1M
ATTM2
D1
PMDAC
PLL1
PS1
DIF1
DEM1
ATTL1
ATTR1
DARHR
DARR
ATTS1
0
0
0
LIN1HR
ATTH1
LIN1R
L1M
LDIFH
DARM
ATTM1
D0
PMVCM
PLL0
MCKO
DIF0
DEM0
ATTL0
ATTR0
DALHL
DALL
ATTS0
0
0
0
RIN1HL
ATTH0
RIN1L
L1HM
LDIF
DALM
ATTM0
“1”
MS0596-J-01
2008/12
- 60 -
[AK4371]
■
Addr
00H
Register Name
Power Management 0
R/W
Default
D7
PMVREF
R/W
0
D6
PMPLL
R/W
0
D5
PMLO
R/W
0
D4
MUTEN
R/W
0
D3
PMHPR
R/W
0
D2
PMHPL
R/W
0
D1
PMDAC
R/W
0
D0
PMVCM
R/W
0
PMVCM: VCOM
0: Power OFF (default)
1: Power ON
PMDAC: DAC
0: Power OFF (default)
1: Power ON
OFF
ON
ATT
PMHPL: Lch
0: Power OFF (default)
1: Power ON
HPL pin
VSS1 (0V)
PMHPR: Rch
0: Power OFF (default)
1: Power ON
HPR pin
VSS1 (0V)
MUTEN:
0:
1:
(default)
DC
VSS1 (0V)
0.475 x AVDD
PMLO:
0: Power OFF (default)
1: Power ON
Hi-Z
PMPLL: PLL
0: Power OFF: EXT mode (default)
1: Power ON: PLL mode
PMVREF: VREF
0: Power OFF (default)
1: Power ON
ON/OFF “1” /“0”
PDN pin
“L”
PMVCM, PMDAC, PMHPL, PMHPR, PMLO, PMMO, PMPLL, MCKO, PMVREF bits
20μA(typ)
(typ. 1μA)
MS0596-J-01
“0”
PDN pin = “L”
2008/12
- 61 -
[AK4371]
Addr
01H
Register Name
PLL Control
R/W
Default
D7
FS3
R/W
1
D6
FS2
R/W
0
D5
FS1
R/W
0
D4
FS0
R/W
0
D3
PLL3
R/W
0
D2
PLL2
R/W
0
D1
PLL1
R/W
0
D0
PLL0
R/W
0
D6
0
RD
0
D5
M/S
R/W
0
D4
MCKAC
R/W
0
D3
BF
R/W
0
D2
PS0
R/W
0
D1
PS1
R/W
0
D0
MCKO
R/W
0
FS3-0:
PLL mode: Table 5
EXT mode: Table 11
PLL4-0: PLL
PLL mode: Table 4
EXT mode:
PLL4 bit Addr=02H, D7
Addr
02H
Register Name
Clock Control
R/W
Default
D7
PLL4
R/W
0
MCKO: MCKO
0: Disable (default)
1: Enable
PS1-0: MCKO
PLL mode: Table 9
EXT mode: Table 12
BF:
BICK
0: 32fs (default)
1: 64fs
MCKAC: MCKI
0: CMOS
1: AC
M/S:
(default)
/
0:
1:
PLL4: PLL
PLL3-0 bits
(default)
Addr=01H, D3-0
MS0596-J-01
2008/12
- 62 -
[AK4371]
Addr
03H
Register Name
Mode Control 0
R/W
Default
D7
0
RD
0
D6
D5
MONO1
MONO0
R/W
0
R/W
0
DIF2-0:
D4
BCKP
R/W
0
D3
LRP
R/W
0
D2
DIF2
R/W
0
D1
DIF1
R/W
1
D0
DIF0
R/W
0
D2
BST0
R/W
0
D1
DEM1
R/W
0
D0
DEM0
R/W
1
(Table 16)
Default: “010” (Mode 2)
LRP: LRCK
0:
1:
(
(default)
)
BCKP: BICK
(
0:
(default)
1:
)
MONO1-0:
Default: “00” (LR)
Addr
04H
Register Name
Mode Control 1
R/W
Default
(Table 21)
D7
ATS
R/W
0
D6
DATTC
R/W
0
DEM1-0:
Default: “01” (OFF)
D5
LMUTE
R/W
1
D4
SMUTE
R/W
0
D3
BST1
R/W
0
(Table 19)
BST1-0:
(Table 20)
Default: “00” (OFF)
SMUTE: DAC
0:
1: DAC
(default)
LMUTE: LOUT/ROUT
0:
ATTS3-0 bits
1: Mute ATTS3-0 bits
(Table 26)
(default)
DATTC:
0: Independent (default)
1: Dependent
“0” Lch, Rch
DATTC bit = “1”
ATS:
“1” Lch ATT
ATTR7-0 bit
ATTL7-0 bit
Rch
ATT
(Table 18)
0: 1061/fs (default)
1: 7424/fs
MS0596-J-01
2008/12
- 63 -
[AK4371]
Addr
05H
06H
Register Name
DAC Lch ATT
DAC Rch ATT
R/W
Default
D7
ATTL7
ATTR7
R/W
0
D6
ATTL6
ATTR6
R/W
0
D5
ATTL5
ATTR5
R/W
0
ATTL7-0: DAC Lch
ATTR7-0: DAC Rch
Default: “00H” (MUTE)
Addr
07H
Register Name
Headphone Out Select 0
R/W
Default
D4
ATTL4
ATTR4
R/W
0
D3
ATTL3
ATTR3
R/W
0
D2
ATTL2
ATTR2
R/W
0
D1
ATTL1
ATTR1
R/W
0
D0
ATTL0
ATTR0
R/W
0
D3
RIN1HR
R/W
0
D2
LIN1HL
R/W
0
D1
DARHR
R/W
0
D0
DALHL
R/W
0
(Table 17)
(Table 17)
D7
HPG1
R/W
0
D6
HPG0
R/W
0
D5
LIN2HR
R/W
0
DALHL: DAC Lch
0: OFF (default)
1: ON
Lch
DARHR: DAC Rch
0: OFF (default)
1: ON
Rch
D4
LIN2HL
R/W
0
LIN1HL: LIN1 pin
0: OFF (default)
1: ON
Lch
RIN1HR: RIN1 pin
0: OFF (default)
1: ON
Rch
LIN2HL: LIN2 pin
0: OFF (default)
1: ON
Lch
LIN2HR: LIN2 pin
0: OFF (default)
1: ON
Rch
HPG1-0: DACÆHPL/R Gain (Table 25)
Default: “00”: +0.95dB
MS0596-J-01
2008/12
- 64 -
[AK4371]
Addr
08H
Register Name
Lineout Select 0
R/W
Default
D7
0
RD
0
DALL: DAC Lch
0: OFF (default)
1: ON
LOUT
DARR: DAC Rch
0: OFF (default)
1: ON
ROUT
D6
LOG
R/W
0
LIN1L: LIN1 pin
0: OFF (default)
1: ON
LOUT
RIN1R: RIN1 pin
0: OFF (default)
1: ON
ROUT
LIN2L: LIN2 pin
0: OFF (default)
1: ON
LOUT
LIN2R: LIN2 pin
0: OFF (default)
1: ON
ROUT
D5
LIN2R
R/W
0
D4
LIN2L
R/W
0
D3
RIN1R
R/W
0
D2
LIN1L
R/W
0
D1
DARR
R/W
0
D0
DALL
R/W
0
D5
0
RD
0
D4
0
RD
0
D3
ATTS3
R/W
0
D2
ATTS2
R/W
0
D1
ATTS1
R/W
0
D0
ATTS0
R/W
0
LOG: DAC Æ LOUT/ROUT Gain
0: 0dB (default)
1: +6dB
Addr
09H
Register Name
Lineout ATT
R/W
Default
D7
0
RD
0
D6
0
RD
0
ATTS3-0: LOUT/ROUT
(Table 27)
Default: LMUTE bit = “1”, ATTS3-0 bits = “0000” (MUTE)
ATTS3-0 bits
LMUTE bit
“0”
MS0596-J-01
2008/12
- 65 -
[AK4371]
Addr
0DH
Register Name
Headphone Out Select 1
R/W
Default
D7
RIN3HR
R/W
0
D6
RIN3HL
R/W
0
D5
LIN3HR
R/W
0
D4
LIN3HL
R/W
0
RIN1HL: RIN1 pin
0: OFF (default)
1: ON
Lch
LIN1HR: LIN1 pin
0: OFF (default)
1: ON
Rch
RIN2HL: RIN2 pin
0: OFF (default)
1: ON
Lch
RIN2HR: RIN2 pin
0: OFF (default)
1: ON
Rch
LIN3HL: LIN3 pin
0: OFF (default)
1: ON
Lch
LIN3HR: LIN3 pin
0: OFF (default)
1: ON
Rch
RIN3HL: RIN3 pin
0: OFF (default)
1: ON
Lch
RIN3HR: RIN3 pin
0: OFF (default)
1: ON
Rch
Addr
0EH
Register Name
Headphone ATT
R/W
Default
D7
0
RD
0
D6
HPZ
R/W
0
D5
HMUTE
R/W
0
D4
ATTH4
R/W
0
D3
RIN2HR
R/W
0
D2
RIN2HL
R/W
0
D1
LIN1HR
R/W
0
D0
RIN1HL
R/W
0
D3
ATTH3
R/W
0
D2
ATTH2
R/W
0
D1
ATTH1
R/W
0
D0
ATTH0
R/W
0
ATTH4-0: HPL/HPR
(Table 25)
Default: HMUTE bit = “0”, ATTH4-0 bits = “00H” (0dB)
ATTH4-0 bits
HMUTE bit
HMUTE: HPL/HPR
0:
ATTH4-0 bits
1: Mute ATTH4-0 bits
HPZ: HP-Amp
0:
1: 200kΩ(typ)
“0”
(Table 25)
(default)
(default)
MS0596-J-01
2008/12
- 66 -
[AK4371]
Addr
0FH
Register Name
Lineout Select 1
R/W
Default
D7
RIN3R
R/W
0
D6
RIN3L
R/W
0
RIN1L: RIN1 pin
0: OFF (default)
1: ON
LOUT
LIN1R: LIN1 pin
0: OFF (default)
1: ON
ROUT
RIN2L: RIN2 pin
0: OFF (default)
1: ON
LOUT
RIN2R: RIN2 pin
0: OFF (default)
1: ON
ROUT
LIN3L: LIN3 pin
0: OFF (default)
1: ON
LOUT
LIN3R: LIN3 pin
0: OFF (default)
1: ON
ROUT
RIN3L: RIN3 pin
0: OFF (default)
1: ON
LOUT
RIN3R: RIN3 pin
0: OFF (default)
1: ON
ROUT
D5
LIN3R
R/W
0
MS0596-J-01
D4
LIN3L
R/W
0
D3
RIN2R
R/W
0
D2
RIN2L
R/W
0
D1
LIN1R
R/W
0
D0
RIN1L
R/W
0
2008/12
- 67 -
[AK4371]
Addr
10H
Register Name
Mono Mixing
R/W
Default
D7
0
RD
0
D6
0
RD
0
L1HM: LIN1/RIN1 pins
0: OFF (default)
1: ON
(L+R)/2
L1M: LIN1/RIN1 pins
0: OFF (default)
1: ON
(L+R)/2
L2HM: LIN2/RIN2 pins
0: OFF (default)
1: ON
(L+R)/2
L2M: LIN2/RIN2 pins
0: OFF (default)
1: ON
(L+R)/2
L3HM: LIN3/RIN3 pins
0: OFF (default)
1: ON
(L+R)/2
L3M: LIN3/RIN3 pins
0: OFF (default)
1: ON
Addr
11H
Register Name
Differential Select
R/W
Default
LDIF: IN+/− pins
0: OFF (default)
1: ON
LDIF bit = “1”
D5
L3M
R/W
0
(L+R)/2
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
L3HM
R/W
0
D3
L2M
R/W
0
D2
L2HM
R/W
0
D1
L1M
R/W
0
D0
L1HM
R/W
0
D2
LDIFM
R/W
0
D1
LDIFH
R/W
0
D0
LDIF
R/W
0
HPL/R
LOUT/ROUT
HPL/R
LOUT/ROUT
HPL/R
LOUT/ROUT
D4
0
RD
0
D3
0
RD
0
LOUT/ROUT
LIN1/RIN1
IN+/IN−
LDIFH: IN+/− pins
0: OFF (default)
1: ON
HPL/R
(LDIF bit = “1”
)
LDIFM: IN+/− pins
0: OFF (default)
1: ON
MOUT
(LDIF bit = “1”
)
MS0596-J-01
2008/12
- 68 -
[AK4371]
Addr
12H
Register Name
MOUT Select
R/W
Default
D7
RIN3M
R/W
0
D6
LIN3M
R/W
0
DALM: DAC Lch
0: OFF (default)
1: ON
MOUT
DARM: DAC Rch
0: OFF (default)
1: ON
MOUT
LIN1M: LIN1 pin
0: OFF (default)
1: ON
MOUT
RIN1M: RIN1 pin
0: OFF (default)
1: ON
MOUT
LIN2M: LIN2 pin
0: OFF (default)
1: ON
MOUT
RIN2M: RIN2 pin
0: OFF (default)
1: ON
MOUT
LIN3M: LIN3 pin
0: OFF (default)
1: ON
MOUT
RIN3M: RIN3 pin
0: OFF (default)
1: ON
MOUT
D5
RIN2M
R/W
0
MS0596-J-01
D4
LIN2M
R/W
0
D3
RIN1M
R/W
0
D2
LIN1M
R/W
0
D1
DARM
R/W
0
D0
DALM
R/W
0
2008/12
- 69 -
[AK4371]
Addr
13H
Register Name
MOUT ATT
R/W
Default
D7
0
RD
0
D6
PMMO
R/W
0
D5
MOG
R/W
0
D4
MMUTE
R/W
1
D3
ATTM3
R/W
0
D2
ATTM2
R/W
0
D1
ATTM1
R/W
0
D0
ATTM0
R/W
0
ATTM3-0: MOUT
(Table 27)
Default: MMUTE bit = “1”, ATTM3-0 bits = “0000” (MUTE)
ATTM3-0 bits
MMUTE bit
MMUTE: MOUT
0:
ATTM3-0 bits
1: Mute ATTM3-0 bits
“0”
(Table 27)
(default)
MOG: DAC Æ MOUT Gain
0: 0dB (default)
1: +6dB
PMMO:
0: Power OFF (default)
1: Power ON
Hi-Z
MS0596-J-01
2008/12
- 70 -
[AK4371]
Figure 57
Handsfree
Analog Supply
+
1.6∼3.6V
10µ
0.1µ
0.22µ
Speaker
2.2µ
0.1µ
23
22
21
20
19
18
17
AVDD
VCOM
VREF
ROUT
LOUT
MOUT
16Ω
HVDD
16Ω
24
+
220µ
VSS1
220µ
+
+
SPK-Amp
25 HPR
MUTET 16
26 HPL
I2C
15
27 RIN2
PDN
14
1µ
32 LIN1
VSS3
VSS2
9
8
VCOC
MCKO 10
7
31 RIN1
PVDD
11
6
CDTI
DVDD
30 LIN3
MCKI
12
5
CCLK
4
Top View
LRCK
29 RIN3
BICK
13
3
CSN
2
AK4371VN
SDATA
28 LIN2
1
Headphone
0.1u
1000p
Analog Ground
0.1u
Rp
10
Cp
Digital Ground
µP
Audio Controller
:
- AK4371
- EXT
- PLL
-
- AVDD
0.1μF
VSS1, VSS2, VSS3
(PMPLL bit = “0”)
(PMPLL bit = “1”)
10Ω
Figure 57.
VCOC pin
Cp Rp Table 4
M/S bit “1”
AK4371 LRCK, BICK pins
AK4371 LRCK, BICK pins 100kΩ
DVDD
(MCKI
AC
MS0596-J-01
DVDD
)
2008/12
- 71 -
[AK4371]
AVDD
AK4371
110k
LIN1 pin
HP-Amp
LIN1HL bit
100k
:
OFF
VCOM
(= 0.475 x AVDD)
Figure 58.
1.
AVDD, PVDD, HVDD
DVDD
AVDD
10Ω
AVDD
DVDD
OFF
AVDD
AVDD
HVDD
PVDD
1.6V
DVDD
AVDD
AVDD
OFF
DVDD
HVDD
HVDD
VSS1, VSS2, VSS3
PC
2.
PMVREF bit = “0”
0.1μF
AVDD
VREF
VSS1
0.22μF
AVDD
0.855 x AVDD
VSS1
PMVREF bit = “1”
VREF
(typ)
VCOM 0.475 x AVDD
(typ)
2.2μF
VSS1
VREF, VCOM pins
AVDD, VREF
VCOM pins
3.
DAC
VCOM
VCOM
0.48xAVDD(typ)@−3dBFS, PMVREF bit = “0” LOUT/ROUT/MOUT
0.61xAVDD(typ)@0dBFS, PMVREF bit = “0”
(2
)
7FFFFFH(@24bit)
800000H(@24bit)
000000H(@24bit)
VCOM
VCOM+
mV
DC
VCOM
2’s
DC
MS0596-J-01
2008/12
- 72 -
[AK4371]
32pin QFN (Unit: mm)
4.0 ± 0.1
2.4 ± 0.1
17
24
0.40 ± 0.10
25
2.4 ± 0.1
4.0 ± 0.1
16
A
Exposed
Pad
32
9
0.45 ± 0.10
8
1
0.22 ± 0.05
B
0.18 ± 0.05
0.05 M
C0.3
PIN #1 ID
0.4
:
0.65 MAX
0.00 MIN
0.05 MAX
0.08
(Exposed Pad)
■
:
:
:
MS0596-J-01
2008/12
- 73 -
[AK4371]
4371
XXXX
1
XXXX : Date code identifier (4 )
Date (YY/MM/DD)
07/04/13
08/12/19
Revision
00
01
Reason
Page
Contents
44-55
(PLL Slave
mode, PLL Master mode)
•
•
•
(
)
•
•
•
MS0596-J-01
2008/12
- 74 -