データシート

[AK4372]
AK4372
PLL & HP-AMP
AK4372
PLL &
24bit D/A
I/F
PLL
16Ω
ON/OFF
CSP
40mW
2.5mm×2.5mm
†
†
ΔΣ
DAC
24pin
DAC
- 8kHz ∼ 48kHz
† 8 FIR
: 20kHz
: ±0.02dB
: 54dB
†
: 32kHz, 44.1kHz, 48kHz
†
:
- PLL Mode (MCKI): 27MHz, 26MHz, 19.8MHz, 19.68MHz, 19.2MHz, 15.36MHz,
14.4MHz, 13MHz, 12MHz and 11.2896MHz
- PLL Mode (BICK or LRCK): 64fs, 32fs or fs
- EXT Mode: 256fs/384fs/512fs/768fs/1024fs
: AC
†
I/F
: MSB First, 2’s Complement
, 24bit/20bit/16bit
- I2S, 24bit
/
†
: LR, LL, RR, (L+R)/2
†
†
†
:3
or
†
- S/N: [email protected]
: +6 to –24dB (or 0 to –30dB), 2dB step
†
: 40mW x 2ch @16Ω, 3.3V
- S/N: [email protected]
ON/OFF
: 0 ∼ –63dB & +12/+6/0dB Gain
1.5dB step (0 ∼ –30dB), 3dB step (–30 ∼ –63dB)
†
:3
/I2C
†
: 1.6V ∼ 3.6V
†
: 3.8mA @1.8V (6.8mW, DAC+HP,
)
† AK4372ECB: Ta= −30 ∼ 85°C
AK4372VCB: Ta= −40 ∼ 85°C
†
: 24pin CSP (2.5mm x 2.5mm, 0.4mm pitch)
† AK4368
MS0684-J-02
2008/12
-1-
[AK4372]
■
MCKO
BICK
LRCK
SDATA
Audio
Interface
MCKI
LIN/IN−
MIN
AVDD
VSS1
PLL
VCOM
VCOM
DVDD
VSS2
VCOC
DAC
Digital
Volume
Deemphasis
Bass
Boost
Digital
Filter
LOUT
(Lch)
ROUT
DAC
(Rch)
PDN
I2C
HDP
Amp
MUTE
HPL
HDP
Amp
MUTE
HPR
CAD0/CSN
SCL/CCLK
Serial I/F
SDA/CDTI
RIN/IN+
MUTET
Figure 1.
MS0684-J-02
2008/12
-2-
[AK4372]
■
AK4372ECB
AK4372VCB
AKD4372
−30 ∼ +85°C
−40 ∼ +85°C
AK4372
24pin CSP (0.4mm pitch)
24pin CSP (0.4mm pitch)
■
5
4
3
Top View
2
1
A
B
C
D
E
5
VSS2
CCLK
CSN
PDN
MUTET
4
VCOC
MCKO
CDTI
LOUT
ROUT
3
MCKI
LRCK
DVDD
I2C
VCOM
BICK
LIN
HPR
AVDD
SDATA
RIN
MIN
HPL
VSS1
A
B
C
D
E
2
1
Top View
MS0684-J-02
2008/12
-3-
[AK4372]
■ AK4370/71
1. Function
Function
PLL
Internal VREF
Hands-free Amp
AK4370
2-Stereo
Single-ended Input
or Full-differential Input
No
No
No
AK4371
3-Stereo
Single-ended Input
or Full-differential Input
Yes
Yes
Yes
Ta
−30 ∼ +85°C
−30 ∼ +85°C
Package
24 pin QFN
(4mm x 4mm, 0.5mm pitch)
32 pin QFN
(4mm x 4mm, 0.4mm pitch)
Analog Mixing
2.
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
(AK4370/71
Register Name
Power Management 0
PLL Control
Clock Control
Mode Control 0
Mode Control 1
DAC Lch ATT
DAC Rch ATT
Headphone Out Select 0
Lineout Select 0
Lineout ATT
Reserved
Reserved
Reserved
Headphone Out Select 1
Headphone ATT
Lineout Select 1
Mono Mixing
Differential Select
Reserved
Reserved
AK4372
1-Stereo + 1-Mono
Single-ended Input
or Full-differential Input
Yes
No
No
AK4372ECB: −30 ∼ +85°C
AK4372VCB: −40 ∼ +85°C
24 pin CSP
(2.5mm x 2.5mm, 0.4mm pitch)
)
D7
PMVREF
FS3
PLL4
0
ATS
ATTL7
ATTR7
HPG1
0
0
0
0
0
RIN3HR
0
RIN3R
0
0
RIN3M
0
D6
D5
D4
PMPLL
PMLO
MUTEN
FS2
FS1
FS0
MCKAC
0
M/S
MONO1 MONO0
BCKP
DATTC LMUTE SMUTE
ATTL6
ATTL5
ATTL4
ATTR6
ATTR5
ATTR4
HPG0
MINHR MINHL
LOG
MINR
MINL
0
0
0
0
0
0
0
0
0
0
0
0
RIN3HL LIN3HR LIN3HL
HPZ
HMUTE ATTH4
RIN3L
LIN3R
LIN3L
0
L3M
L3HM
0
0
0
LIN3M
RIN2M
LIN2M
MMUTE
PMMO
MOG
AK4370/71
AK4372
AK4372
AK4370
MS0684-J-02
D3
PMHPR
PLL3
BF
LRP
BST1
ATTL3
ATTR3
RINHR
RINR
ATTS3
0
0
0
RIN2HR
ATTH3
RIN2R
L2M
0
RIN1M
ATTM3
D2
PMHPL
PLL2
PS0
DIF2
BST0
ATTL2
ATTR2
LINHL
LINL
ATTS2
0
0
0
RIN2HL
ATTH2
RIN2L
L2HM
LDIFM
LIN1M
ATTM2
D1
PMDAC
PLL1
PS1
DIF1
DEM1
ATTL1
ATTR1
DARHR
DARR
ATTS1
0
0
0
LINHR
ATTH1
LINR
LM
LDIFH
DARM
ATTM1
D0
PMVCM
PLL0
MCKO
DIF0
DEM0
ATTL0
ATTR0
DALHL
DALL
ATTS0
0
0
0
RINHL
ATTH0
RINL
LHM
LDIF
DALM
ATTM0
2008/12
-4-
[AK4372]
No.
I/O
A1
SDATA
B2
BICK
I/O
B3
LRCK
I/O
A3
C3
MCKI
DVDD
I
-
A4
VCOC
O
A5
B4
VSS2
MCKO
SDA
CDTI
SCL
CCLK
CAD0
CSN
O
I/O
I
I
I
I
I
C4
B5
C5
D5
PDN
I
L/R
, 1.6 ∼ 3.6V
PLL
VSS2
2
VSS1
(I2C
(3
0
(I2C
: I2C pin = “H”)
: I2C pin = “L”)
(I2C
: I2C pin = “H”)
(3
: I2C pin = “L”)
: I2C pin = “H”)
(3
: I2C pin = “L”)
&
“L”
I
“L”
D3
I2C
I
E5
MUTET
O
D4
E4
LOUT
ROUT
O
O
E3
VCOM
O
E2
E1
D2
D1
C1
AVDD
VSS1
HPR
HPL
MIN
RIN
IN+
LIN
IN−
O
O
I
I
I
I
I
B1
C2
Note 1.
“H”: I2C
, “L”: 3
VSS1 pin
Lch
Rch
VSS1 pin
& PLL
1
Rch HP-Amp
Lch HP-Amp
Rch
Lch
2.2μF
, 1.6 ∼ 3.6V
(LDIF bit = “0” :
(LDIF bit = “1” :
)
(LDIF bit = “0” :
(LDIF bit = “1” :
)
)
)
(I2C, SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN)
MCKI pin
PDN pin = “L”
MS0684-J-02
2008/12
-5-
[AK4372]
■
Analog
Digital
LOUT, ROUT, MUTET, HPR, HPL,
MIN, RIN/IN+, LIN/IN−
MCKI
MCKO
VSS2
(VSS1 = VSS2 =0V; Note 2, Note 3)
Parameter
Symbol
min
max
Units
Power Supplies Analog
AVDD
4.6
V
−0.3
Digital
DVDD
4.6
V
−0.3
Input Current (any pins except for supplies)
IIN
mA
±10
Analog Input Voltage (Note 4)
VINA
(AVDD+0.3) or 4.6
V
−0.3
Digital Input Voltage (Note 5)
VIND
(DVDD+0.3) or 4.6
V
−0.3
AK4372ECB
Ta
85
−30
°C
Ambient Temperature
AK4372VCB
Ta
85
−40
°C
Storage Temperature
Tstg
150
−65
°C
Note 2.
Note 3. VSS1, VSS2
Note 4. LIN/IN−, RIN/IN+ and MIN pins. Max (AVDD+0.3V)
4.6V
Note 5. SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN and I2C pins. Max (DVDD+0.3V)
4.6V
:
(VSS1=VSS2 =0V; Note 2)
Parameter
Symbol
Power Supplies Analog
AVDD
(Note 6)
Digital (Note 7)
DVDD
Note 2.
Note 6. AVDD DVDD
DVDD
OFF
AVDD
Note 7. Max (AVDD+0.2V)
3.6V
min
1.6
1.6
typ
2.4
2.4
1.6V
max
3.6
(AVDD+0.2) or 3.6
Units
V
V
AVDD
DVDD
:
MS0684-J-02
2008/12
-6-
[AK4372]
(
Ta=25°C; AVDD=DVDD=2.4V, VSS1=VSS2=0V; fs=44.1kHz; EXT mode; BOOST OFF; Slave
Mode; Signal Frequency =1kHz; Measurement band width=20Hz ∼ 20kHz; Headphone-Amp: RL =16Ω, CL=220μF
(Figure 50))
Parameter
min
typ
max
Units
24
bit
DAC Resolution
Headphone-Amp: (HPL/HPR pins) (Note 8)
Analog Output Characteristics
THD+N
dB
−3dBFS Output, 2.4V, Po=10mW@16Ω
−50
−40
dB
0dBFS Output, 3.3V, Po=40mW@16Ω
−20
82
90
dB
D-Range
−60dBFS Output, A-weighted, 2.4V
92
dB
−60dBFS Output, A-weighted, 3.3V
S/N
A-weighted, 2.4V
82
90
dB
A-weighted, 3.3V
92
dB
Interchannel Isolation
60
80
dB
DC Accuracy
Interchannel Gain Mismatch
0.3
0.8
Gain Drift
200
Load Resistance (Note 9)
16
Load Capacitance
300
1.04
1.16
1.28
Output Voltage −3dBFS Output (Note 10)
0dBFS Output, 3.3V,
0.8
Po=40mW@16Ω
Output Volume: (HPL/HPR pins)
Step Size
0.1
1.5
2.9
0 ∼ –30dB
(HPG1-0 bits = “00”)
0.1
3
5.9
–30 ∼ –63dB
Gain Control Range
Max (ATT4-0 bits = 00H)
0
(HPG1-0 bits = “00”)
Min (ATT4-0 bits = 1FH)
−63
Stereo Line Output: (LOUT/ROUT pins, RL=10kΩ) (Note 11)
Analog Output Characteristics:
THD+N (0dBFS Output)
−60
−50
S/N
A-weighted, 2.4V
80
87
A-weighted, 3.3V
90
DC Accuracy
Gain Drift
200
Load Resistance (Note 9)
10
Load Capacitance
25
Output Voltage (0dBFS Output) (Note 12)
1.32
1.47
1.61
Output Volume: (LOUT/ROUT pins)
Step Size
1
2
3
Gain Control Range
Max (ATTS3-0 bits = FH)
0
(LOG1-0 bit = “0”)
Min (ATTS3-0 bits = 0H)
−30
Note 8. DALHL=DARHR bits = “1”, LINHL=RINHL=MINHL=LINHR=RINHR=MINHR bits = “0”
Note 9. AC
Note 10.
AVDD
Vout = 0.48 x AVDD(typ)@−3dBFS.
Note 11. DALL=DARR bits = “1”, LINL=RINL=MINL=LINR=RINR=MINR bits = “0”
Note 12.
AVDD
Vout = 0.61 x AVDD(typ)@0dBFS.
MS0684-J-02
dB
ppm/°C
Ω
pF
Vpp
Vrms
dB
dB
dB
dB
dB
dB
dB
ppm/°C
kΩ
pF
Vpp
dB
dB
dB
2008/12
-7-
[AK4372]
Parameter
LINEIN: (LIN/RIN/MIN pins)
Analog Input Characteristics
Input Resistance (Figure 25, Figure 26 and Figure 27)
LIN pin
LINHL=LINHR=LINL=LINR= bits = “1”
LINHL bit = “1”, LINHR=LINL=LINR bits = “0”
LINHR bit = “1”, LINHL=LINL=LINR bits = “0”
LINL bit = “1”, LINHL=LINHR=LINR bits = “0”
LINR bit = “1”, LINHL=LINHR=LINL bits = “0”
RIN pin
RINHL=RINHR=RINL=RINR bits = “1”
RINHL bit = “1”, RINHR=RINL=RINR bits = “0”
RINHR bit = “1”, RINHL=RINL=RINR bits = “0”
RINL bit = “1”, RINHL=RINHR=RINR bits = “0”
RINR bit = “1”, RINHL=RINHR=RINL bits = “0”
MIN pin
MINHL=MINHR=MINL=MINR bits = “1”
MINHL bit = “1”, MINHR=MINL=MINR bits = “0”
MINHR bit = “1”, MINHL=MINL=MINR bits = “0”
MINL bit = “1”, MINHL=MINHR=MINR bits = “0”
MINR bit = “1”, MINHL=MINHR=MINL bits = “0”
Gain
LIN/RIN/MIN Æ LOUT/ROUT
LIN/RIN/MIN Æ HPL/HPR
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”) (Note 13)
AVDD+DVDD
Power-Down Mode (PDN pin = “L”) (Note 14)
min
typ
max
Units
14
-
25
100
100
100
100
-
kΩ
kΩ
kΩ
kΩ
kΩ
14
-
25
100
100
100
100
-
kΩ
kΩ
kΩ
kΩ
kΩ
14
-
25
100
100
100
100
-
kΩ
kΩ
kΩ
kΩ
kΩ
−1
−0.05
0
+0.95
+1
+1.95
dB
dB
-
5.0
1
8.0
100
mA
μA
Note 13. PMDAC=PMHPL=PMHPR=PMLO bits = “1”, MUTEN bit = “1”, MCKO bit = “0”, HP-Amp
PMDAC=PMHPL=PMHPR= “1”, PMLO bits = “0” , AVDD+DVDD=4.0mA (typ) @2.4V, 3.8mA (typ)
@1.8V.
Note 14.
(MCKI, BICK, LRCK)
VSS2
MS0684-J-02
2008/12
-8-
[AK4372]
(Ta=25°C; AVDD = DVDD=1.6 ∼ 3.6V; fs=44.1kHz; De-emphasis = OFF)
Parameter
Symbol
min
DAC Digital Filter: (Note 15)
Passband (Note 16)
PB
0
−0.05dB
−6.0dB
Stopband (Note 16)
SB
24.1
Passband Ripple
PR
Stopband Attenuation
SA
54
Group Delay (Note 17)
GD
Group Delay Distortion
ΔGD
DAC Digital Filter + Analog Filter: (Note 15) (Note 18)
Frequency Response
FR
0 ∼ 20.0kHz
Analog Filter: (Note 19)
Frequency Response
FR
0 ∼ 20.0kHz
BOOST Filter: (Note 18) (Note 20)
Frequency Response
20Hz
FR
MIN
100Hz
1kHz
20Hz
FR
MID
100Hz
1kHz
20Hz
FR
MAX 100Hz
1kHz
Note 15. BOOST OFF (BST1-0 bit = “00”)
Note 16.
fs (
)
PB=0.4535fs(@−0.05dB) SB=0.546fs(@−54dB)
Note 17.
typ
max
Units
22.05
22
0
20.0
±0.02
-
kHz
kHz
kHz
dB
dB
1/fs
µs
±0.5
-
dB
±1.0
-
dB
5.76
2.92
0.02
10.80
6.84
0.13
16.06
10.54
0.37
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
Note 18. DAC Æ HPL, HPR, LOUT, ROUT
Note 19. LIN/MIN Æ HPL/LOUT, RIN/MIN Æ HPR/ROUT
Note 20.
fs
Boost Filter (fs=44.1kHz)
20
MAX
15
Gain [dB]
MID
10
MIN
5
0
-5
10
100
1000
10000
Frequency [Hz]
Figure 2. Boost Frequency (fs=44.1kHz)
MS0684-J-02
2008/12
-9-
[AK4372]
DC
(Ta=25°C; AVDD = DVDD=1.6 ∼ 3.6V)
Parameter
High-Level Input Voltage
2.2V≤DVDD≤3.6V
1.6V≤DVDD<2.2V
Low-Level Input Voltage
2.2V≤DVDD≤3.6V
1.6V≤DVDD<2.2V
Input Voltage at AC Coupling (Note 21)
High-Level Output Voltage
(Iout=−200μA)
Low-Level Output Voltage
(Except SDA pin: Iout=200μA)
(SDA pin, 2.0V≤DVDD≤3.6V: Iout=3mA)
(SDA pin, 1.6V≤DVDD<2.0V: Iout=3mA)
Input Leakage Current
Note 21. MCKI pin
Symbol
VIH
VIH
VIL
VIL
VAC
VOH
min
70%DVDD
80%DVDD
0.4
DVDD−0.2
typ
-
max
30%DVDD
20%DVDD
-
Units
V
V
V
V
Vpp
V
VOL
VOL
VOL
Iin
-
-
0.2
0.4
20%DVDD
±10
V
V
V
μA
(Figure 50)
MS0684-J-02
2008/12
- 10 -
[AK4372]
(Ta=25°C; AVDD=DVDD=1.6 ∼ 3.6V; CL = 20pF; unless otherwise specified)
Parameter
Symbol
min
Master Clock Input Timing
Frequency (PLL mode)
fCLK
11.2896
(EXT mode)
fCLK
2.048
Pulse Width Low (Note 22)
tCLKL
0.4/fCLK
Pulse Width High (Note 22)
tCLKH
0.4/fCLK
AC Pulse Width (Note 23)
tACW
18.5
LRCK Timing
Frequency
fs
8
Duty Cycle: Slave Mode
Duty
45
Master Mode
Duty
MCKO Output Timing (PLL mode)
Frequency
fCLKO
0.256
Duty Cycle (Except fs=32kHz, PS1-0= “00”)
dMCK
40
(fs=32kHz, PS1-0= “00”)
dMCK
Serial Interface Timing (Note 24)
Slave Mode (M/S bit = “0”):
BICK Period (Note 25)
(Except PLL Mode,
tBCK
312.5 or 1/(64fs)
PLL4-0 bits =“01110”, “01111”)
tBCK
(PLL Mode, PLL4-0 bits = “01110”)
(PLL Mode, PLL4-0 bits = “01111”)
tBCK
BICK Pulse Width Low
(Except PLL Mode,
PLL4-0 bits = “01110”, “01111”)
tBCKL
100
(PLLMode,
PLL4-0bits = “01110”, “01111”)
tBCKL
0.4 x tBCK
BICK Pulse Width High
(Except PLL Mode,
PLL4-0 bits =“01110”, “01111”)
tBCKH
100
(PLL Mode,
PLL4-0 bits = “01110”, “01111”)
tBCKH
0.4 x tBCK
tLRB
50
LRCK Edge to BICK “↑” (Note 26)
tBLR
50
BICK “↑” to LRCK Edge (Note 26)
SDATA Hold Time
tSDH
50
SDATA Setup Time
tSDS
50
Master Mode (M/S bit = “1”):
BICK Frequency (BF bit = “1”)
fBCK
(BF bit = “0”)
fBCK
BICK Duty
dBCK
tMBLR
BICK “↓” to LRCK
−50
SDATA Hold Time
tSDH
50
SDATA Setup Time
tSDS
50
Control Interface Timing (3-wire Serial mode)
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
40
CSN “H” Time
tCSW
150
tCSS
50
CSN Edge to CCLK “↑” (Note 27)
tCSH
50
CCLK “↑” to CSN Edge (Note 27)
MS0684-J-02
typ
max
Units
-
27
24.576
-
MHz
MHz
ns
ns
ns
44.1
50
48
55
-
kHz
%
%
33
12.288
60
-
MHz
%
%
1/(32f)
1/(64f)
1/(32fs)
-
ns
ns
ns
-
-
ns
-
ns
-
-
ns
-
-
ns
ns
ns
ns
ns
64fs
32fs
50
-
50
-
Hz
Hz
%
ns
ns
ns
-
-
ns
ns
ns
ns
ns
ns
ns
ns
2008/12
- 11 -
[AK4372]
Parameter
Control Interface Timing (I2C Bus mode): (Note 28)
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 29)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Capacitive Load on Bus
Pulse Width of Spike Noise Suppressed by Input Filter
Power-down & Reset Timing
PDN Pulse Width (Note 30)
Symbol
min
typ
max
Units
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
Cb
tSP
1.3
0.6
1.3
0.6
0.6
0
0.1
0.6
0
-
400
0.3
0.3
400
50
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
tPD
150
-
-
ns
Note 22. AC
Note 23. MCKI
(Figure 3)
Note 24.
Note 25. PLL Mode, PLL4-0 bits = “01110”, “01111”
Note 26.
LRCK
BICK “↑”
Note 27
CSN
CCLK
CCLK “↑”
Note 28. I2C Philips Semiconductors
Note 29.
300ns (SCL
)
Note 30.
PDN pin “L”
“H”
MS0684-J-02
312.5
1/(64fs)
2008/12
- 12 -
[AK4372]
■
1/fCLK
tACW
1000pF
tACW
Measurement
Point
MCKI Input
100kΩ
VSS2
VAC
VSS2
Figure 3. MCKI AC Coupling Timing
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
MCKO
50%
DVDD
tH
tL
dMCK=tH/(tH+tL) or tL/(tH+tL)
Figure 4. Clock Timing
MS0684-J-02
2008/12
- 13 -
[AK4372]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDH
tSDS
VIH
SDATA
VIL
Figure 5. Serial Interface Timing (Slave Mode)
50%DVDD
LRCK
tMBLR
BICK
50%DVDD
tSDH
tSDS
VIH
SDATA
VIL
Figure 6. Serial Interface Timing (Master mode)
MS0684-J-02
2008/12
- 14 -
[AK4372]
VIH
CSN
VIL
tCSS
tCSH
tCCKL
tCCKH
VIH
CCLK
VIL
tCCK
tCDH
tCDS
CDTI
C1
C0
VIH
R/W
VIL
Figure 7. WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
tCSS
VIH
CCLK
CDTI
VIL
D2
D1
VIH
D0
VIL
Figure 8. WRITE Data Input Timing
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
Start
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Figure 9. I2C Bus Mode Timing
tPD
PDN
VIL
Figure 10. Power-down & Reset Timing
MS0684-J-02
2008/12
- 15 -
[AK4372]
■
I/F
6
Mode
PLL Master Mode
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
(PLL Reference Clock: BICK pin)
PLL Slave Mode 3
(PLL Reference Clock: LRCK pin)
EXT Master Mode
EXT Slave Mode
Mode
(Table 1 and Table 2.)
PMPLL bit
1
M/S bit
1
PLL4-0 bits
See Table 4
Figure
Figure 11
1
0
See Table 4
Figure 12
1
0
See Table 4
Figure 13
1
0
See Table 4
Figure 14
x
x
Figure 15
Figure 16
0
1
0
0
Table 1. Clock Mode Setting (x: Don’t care)
MCKO bit
0
PLL Master Mode
1
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
0
1
MCKO pin
L
PS1-0 bits
L
PS1-0 bits
MCKI pin
PLL4-0 bits
PLL4-0 bits
PLL Slave Mode 2
(PLL Reference Clock: BICK pin)
0
L
GND
PLL Slave Mode 3
(PLL Reference Clock: LRCK pin)
0
L
GND
EXT Master Mode
0
L
EXT Slave Mode
0
L
FS3-0 bits
FS3-0 bits
BICK pin
Output
(BF bit
)
LRCK pin
Input
(32fs ∼ 64fs)
Input
(1fs)
Input
(PLL4-0 bits
)
Input
(32fs ∼ 64fs)
Output
(BF bit
)
Input
(32fs ∼ 64fs)
Output
(1fs)
Input
(1fs)
Input
(1fs)
Output
(1fs)
Input
(1fs)
Table 2. Clock pins state in Clock Mode
■
M/S bit
(PDN pin = “L”)
AK4372
M/S bit
“1”
“0”
“1”
M/S bit “1”
AK4372 LRCK, BICK pin
AK4372
LRCK, BICK pin
100kΩ
M/S bit
Mode
0
Slave Mode
(default)
1
Master Mode
Table 3. Select Master/Slave Mode
MS0684-J-02
2008/12
- 16 -
[AK4372]
■ PLL
(PMPLL bit = “1”)
PMPLL bit = “1”
PLL
PLL
FS3-0 bit, PLL4-0 bit (Table 4, Table 5, Table 6)
PMPLL bit “0” Æ “1”
Table 4
1) PLL Mode
Mode
PLL4
PLL3
PLL2
PLL1
PLL0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Other
s
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Others
Reference Clock
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
MCKI
BICK
BICK
LRCK
N/A
fs
(Note 31)
11.2896MHz
14.4MHz
12MHz
19.2MHz
15.36MHz
13MHz
19.68MHz
19.8MHz
26MHz
27MHz
13MHz
26MHz
19.8MHz
27MHz
32fs
64fs
fs
Note 31. Type 1-4 Table 5
Note 32. Mode10 ~ 13 Mode5 /7 /8 /9
Note 33. Mode 14-16 Slave Mode
Table 4. PLL
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 1
Type 2
Type 2
Type 3
Type 4
Table 6
Table 6
Table 6
R,C at VCOC
C[F]
R[Ω]
10k
22n
10k
22n
10k
47n
10k
22n
10k
22n
15k
330n
10k
47n
10k
47n
15k
330n
10k
47n
10k
22n
10k
22n
10k
22n
10k
22n
6.8k
47n
6.8k
47n
6.8k
330n
PLL Lock
Time (typ
20ms
20ms
20ms
20ms
20ms
100ms
20ms
20ms
100ms
20ms
20ms
20ms
20ms
20ms
20ms
20ms
80ms
(default)
(PLL mode) (N/A: Not available)
2) PLL Mode
PLL
MCKI
Table 5
Mode
FS3
FS2
FS1
FS0
0
1
2
4
5
6
8
9
10
3, 7,
11-15
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
Others
Table 5.
fs
Type 1
48kHz
24kHz
12kHz
32kHz
16kHz
8kHz
44.1kHz
22.05kHz
11.025kHz
Type 2
48.0007kHz
24.0004kHz
12.0002kHz
32.0005kHz
16.0002kHz
8.0001kHz
44.0995kHz
22.0498kHz
11.0249kHz
Type 3
47.9992kHz
23.9996kHz
11.9998kHz
31.9994kHz
15.9997kHz
7.9999kHz
44.0995kHz
22.0498kHz
11.0249kHz
Type 4
47.9997kHz
23.9999kHz
11.9999kHz
31.9998kHz
15.9999kHz
7.9999kHz
44.0995kHz
22.0498kHz
11.0249kHz
N/A
N/A
N/A
N/A
(PLL mode,
(default)
=MCKI) (N/A: Not available)
MS0684-J-02
2008/12
- 17 -
[AK4372]
PLL
Mode
0
1
2
3
4
Others
Table 6.
BICK
FS3 bit
1
1
1
1
1
LRCK
Table 6
FS2 bit
FS1 bit
FS0 bit
0
0
0
0
1
0
0
0
1
0
1
1
1
0
0
Others
(PLL Mode,
Sampling Frequency Range
(default)
32kHz < fs ≤ 48kHz
24kHz < fs ≤ 32kHz
16kHz < fs ≤ 24kHz
12kHz < fs ≤ 16kHz
8kHz ≤ fs ≤ 12kHz
N/A
=BICK or LRCK) (N/A: Not availlable)
■ PLL
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
BICK
(M/S bit = “1”) PMPLL bit = “0” Æ “1”
PMDAC bit = “0” Æ “1”
LRCK BICK “L”
MCKO bit = “1”
MCKO pin
MCKO bit = “0”
MCKO pin
“L”
PLL
AK4372
(Table 7)
PLL
LRCK
Master Mode (M/S bit = “1”)
Power Up
Power Down
PLL Unlock
(PMDAC bit= PMPLL bit= “1”) (PMDAC bit= PMPLL bit= “0”)
Input or
MCKI pin Refer to Table 4.
Refer to Table 4.
fixed to “L” or “H” externally
MCKO bit = “0”: L
MCKO bit = “0”: L
MCKO pin
L
MCKO bit = “1”: Output
MCKO bit = “1”: Unsettling
BF bit = “1”: 64fs output
BICK pin
L
L
BF bit = “0”: 32fs output
LRCK pin
Output
L
L
Table 7. Clock Operation in Master mode (PLL mode)
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
MCKO bit = “0”
9
(M/S bit = “0”) PMPLL bit = “0” Æ “1”
MCKO bit = “1”
MCKO pin
MCKO pin “L”
PMDAC bit = “0” Æ “1”
PLL
Slave Mode (M/S bit = “0”)
Power Up
Power Down
(PMDAC bit= PMPLL bit= “1”) (PMDAC bit= PMPLL bit= “0”)
Input or
MCKI pin Refer to Table 4.
fixed to “L” or “H” externally
MCKO bit = “0”: L
MCKO pin
L
MCKO bit = “1”: Output
BICK pin
LRCK pin
PLL
MCKO pin
Table
PLL Unlock
Refer to Table 4.
MCKO bit = “0”: L
MCKO bit = “1”: Unsettling
Input or
Input
Fixed to “L” or “H” externally
Fixed to “L” or “H”
externally
Input or
Input
Fixed to “L” or “H” externally
Fixed to “L” or “H”
externally
Table 8. Clock Operation in Slave mode (PLL mode)
MS0684-J-02
2008/12
- 18 -
[AK4372]
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
26MHz, 27MHz
(Figure 11) MCKO
BICK
11.2896MHz, 12MHz, 13MHz, 14.4MHz, 15.36MHz, 19.2MHz, 19.68MHz, 19.8MHz,
PLL
MCKO, BICK, LRCK
PS1-0 bits (Table 9)
MCKO bit
ON/OFF
BF bit
32fs or 64fs
(Table 10)
27MHz,26MHz,19.8MHz,19.68MHz,
19.2MHz,15.36MHz,14.4MHz,13MHz,
12MHz,11.2896MHz
AK4372
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
32fs, 64fs
1fs
MCLK
BCLK
LRCK
SDTO
SDATA
Figure 11. PLL Master Mode
PS1
PS0
MCKO
0
0
256fs
(default)
0
1
128fs
1
0
64fs
1
1
32fs
Table 9. MCKO
(PLL mode, MCKO bit = “1”)
BF bit
BICK
0
32fs
(default)
1
64fs
Table 10. BICK Output Frequency at Master Mode
MS0684-J-02
2008/12
- 19 -
[AK4372]
■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
MCKI, BICK or LRCK pin
PLL
a) PLL
MCKO
bit
PLL
AK4372
(Table 4)
PLL4-0 bit
: MCKI pin
BICK, LRCK
MCKO LRCK
(MCKO pin) PS1-0 bit (Table 9)
FS3-0 bit
ON/OFF
(PMDAC bit = “1”)
MCKI, LRCK
MCKO
(Table 5)
BICK
(PMDAC bit = “0”)
27MHz,26MHz,19.8MHz,19.68MHz,
19.2MHz,15.36MHz,14.4MHz,13MHz,
12MHz,11.2896MHz
AK4372
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
32fs ~ 64fs
1fs
MCLK
BCLK
LRCK
SDTO
SDATA
Figure 12. PLL Slave Mode (PLL Reference Clock: MCKI pin)
b) PLL
FS3-0 bit
: BICK pin
8kHz ∼ 48kHz
(Table 6.)
AK4372
DSP or μP
MCKI
MCKO
BICK
LRCK
32fs or 64fs
1fs
BCLK
LRCK
SDTO
SDATA
Figure 13. PLL Slave Mode (PLL Reference Clock: BICK pin)
MS0684-J-02
2008/12
- 20 -
[AK4372]
c) PLL
FS3-0 bit
: LRCK pin
8kHz ∼ 48kHz
(Table 6.)
AK4372
DSP or μP
MCKI
MCKO
BICK
LRCK
32fs ∼ 64fs
1fs
BCLK
LRCK
SDTO
SDATA
Figure 14. PLL Slave Mode (PLL Reference Clock: LRCK pin)
MS0684-J-02
2008/12
- 21 -
[AK4372]
■ EXT Mode (PMPLL bit = “0”: Default)
PMPLL bit
“0”
DAC
(Table 11)
PS1-0 bit
PLL4-0 bits
(M/S bit = “1”)
“1”)
(EXT mode)
MCKI pin
MCKI pin
MCKO
MCKO bit
DAC
(PMDAC bit = “1”)
“0”
LRCK
BICK
AK4372
(Figure 15)
PLL
FS3-0 bits
ON/OFF
(PMDAC bit =
MCKI pin
DAC
(PMDAC bit = “0”)
AK4372
DSP or μP
MCKO
256fs, 384fs, 512fs,
768fs or 1024fs
MCKI
32fs, 64fs
BICK
1fs
LRCK
MCLK
BCLK
LRCK
SDTO
SDATA
Figure 15. EXT Master Mode
(M/S bit = “0”)
MCKI, BICK, LRCK
(Figure 16) MCKI
DAC
(PMDAC bit = “1”)
LRCK
(MCKI, BICK, LRCK)
DAC
(PMDAC bit = “0”)
AK4372
DSP or μP
MCKO
MCKI
BICK
LRCK
256fs, 384fs, 512fs,
768fs or 1024fs
32fs
64fs
1fs
MCLK
BCLK
LRCK
SDTO
SDATA
Figure 16. EXT Slave Mode
MS0684-J-02
2008/12
- 22 -
[AK4372]
Mode
FS3
0
0
1
0
2
0
4
0
5
0
6
0
8
1
9
1
10
1
12
1
13
1
Others
Table 11.
FS2
0
0
0
1
1
1
0
0
0
1
1
Others
FS1
0
0
1
0
0
1
0
0
1
0
0
FS0
0
1
0
0
1
0
0
1
0
0
1
fs
MCKI
256fs
8kHz ∼ 48kHz
512fs
8kHz ∼ 48kHz
1024fs
8kHz ∼ 24kHz
256fs
8kHz ∼ 48kHz
512fs
8kHz ∼ 48kHz
1024fs
8kHz ∼ 24kHz
256fs
(default)
8kHz ∼ 48kHz
512fs
8kHz ∼ 48kHz
1024fs
8kHz ∼ 24kHz
384fs
8kHz ∼ 48kHz
768fs
8kHz ∼ 24kHz
N/A
N/A
(EXT mode) (N/A: Not available)
MCKI
PS1
0
0
1
1
Table 12. MCKO
PS0
0
1
0
1
MCKO
256fs
(default)
128fs
64fs
32fs
(EXT mode, MCKO bit = “1”)
Master Mode (M/S bit = “1”)
Power Up (PMDAC bit = “1”)
Power Down (PMDAC bit = “0”)
Input or
MCKI pin Refer to Table 11.
fixed to “L” or “H” externally
MCKO bit = “0”: L
MCKO pin
L
MCKO bit = “1”: Output
BF bit = “1”: 64fs output
BICK pin
L
BF bit = “0”: 32fs output
LRCK pin
Output
L
Table 13. Clock Operation in Master mode (EXT mode)
Slave Mode (M/S bit = “0”)
Power Up (PMDAC bit = “1”)
Power Down (PMDAC bit = “0”)
Input or
MCKI pin Refer to Table 11.
fixed to “L” or “H” externally
MCKO bit = “0”: L
MCKO pin
L
MCKO bit = “1”: Output
BICK pin
Input
Fixed to “L” or “H” externally
LRCK pin
Input
Fixed to “L” or “H” externally
Table 14. Clock Operation in Slave mode (EXT mode)
DR, S/N
Table 15
DR, S/N
MCKI
DAC
DR,
S/N
MCKI
256fs/384fs/512fs
768fs/1024fs
Table 15. MCKI
DR, S/N (BW=20kHz, A-weight)
fs=8kHz
fs=16kHz
56dB
75dB
75dB
90dB
DR, S/N
(2.4V)
MS0684-J-02
2008/12
- 23 -
[AK4372]
■
SDATA, BICK, LRCK 3pin
(Table 16) DIF2-0 bits
Mode 1 Mode 0 20bit
DSP
Mode 2 3 16bit
LSB
21∼24bit
4
5
Mode 0
16bitDAC
Mode 4 Mode 0 24bit
Mode 3 I2S
LSB
17∼24bit
“0”
Mode 2
8
BICK=32fs(BF bit = “0”)
Mode
0
1
2
3
4
DIF2
0
0
0
0
1
DIF1
0
0
1
1
0
DIF0
0
1
0
1
0
ADC
BICK≥48fs
20bit
“0”
Mode 1, 2, 4
BICK
32fs ≤ BICK ≤ 64fs
40fs ≤ BICK ≤ 64fs
48fs ≤ BICK ≤ 64fs
BICK=32fs or 48fs ≤ BICK ≤ 64fs
48fs ≤ BICK ≤ 64fs
0: 16bit,
1: 20bit,
2: 24bit,
3: I2S
4: 24bit,
Table 16.
Figure 17
Figure 18
Figure 19
Figure 20
Figure 18
(default)
LRCK
BICK
(32fs)
SDATA
Mode 0
15
14
6
5
4
3
2
15
14
1
0
15
14
0
Don’t care
6
5
4
3
2
1
0
15
14
0
19
0
19
0
15
14
BICK
SDATA
Mode 0
Don’t care
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 17. Mode 0
(LRP = BCKP bits = “0”)
LRCK
BICK
SDATA
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19:MSB, 0:LSB
SDATA
Mode 4
Don’t care
23
22
21
20
23
22
21
20
23:MSB, 0:LSB
Lch Data
Figure 18. Mode 1, 4
Rch Data
(LRP = BCKP bits = “0”)
MS0684-J-02
2008/12
- 24 -
[AK4372]
Rch
Lch
LRCK
BICK
SDATA
15
14
0
19
18
4
1
0
23
22
8
3
4
Don’t
care
15
14
0
Don’t
care
19
18
4
1
0
Don’t
care
23
22
8
3
4
16bit
SDATA
Don’t
care
15
14
Don’t
care
19
18
Don’t
care
23
22
20bit
SDATA
1
0
1
0
24bit
Figure 19. Mode 2
(LRP = BCKP bits = “0”)
Lch
LRCK
Rch
BICK
SDATA
16bit
15
14
0
SDATA
20bit
19
18
4
1
0
SDATA
23
22
8
3
4
1
0
15
14
6
5
4
3
2
24bit
Don’t
care
15
14
0
Don’t
care
19
18
4
1
0
Don’t
care
23
22
8
3
4
1
15
14
6
5
4
3
Don’t
care
15
Don’t
care
19
0
Don’t
care
23
2
1
BICK
(32fs)
SDATA
16bit
0
Figure 20. Mode 3
1
0
0
15
(LRP = BCKP bits = “0”)
MS0684-J-02
2008/12
- 25 -
[AK4372]
■
AK4372
MUTE
0.5dB
256
DAC
(Table 17) DATTC bit “1”
ATTL7-0 bit
DATTC bit “0”
Lch, Rch
(DATT)
0dB
Lch, Rch
−127dB
ATTL7-0
Attenuation
ATTR7-0
FFH
0dB
FEH
−0.5dB
FDH
−1.0dB
FCH
−1.5dB
:
:
02H
−126.5dB
01H
−127.0dB
00H
(default)
MUTE (−∞)
Table 17. Digital Volume ATT
ATT7-0
ATT
@fs=44.1kHz)
“0”
00H
ATS bit 1061/fs 7424/fs
1062
FFH(0dB)
PDN pin “L”
ATT7-0 00H
PMDAC bit “1”
ATS
0
1
Table 18.
ATT speed
0dB to MUTE
1 step
1061/fs
4/fs
7424/fs
29/fs
ATT7-0
MS0684-J-02
(Table 18) ATS bit = “0”
00H(MUTE)
1061/fs (24ms
ATT7-0 PMDAC bit
(default)
2008/12
- 26 -
[AK4372]
■
×ATT
−∞
ATT
SMUTE bit
−∞ (“0”)
(Table 18)
×ATT
“1”
ATT
SMUTE bit
−∞
ATT
ATT
“0”
ATT
SMUTE bit
ATS bit
ATS bit
(1)
(1)
ATT Level
(3)
Attenuation
-∞
GD
(2)
GD
Analog Output
Figure 21.
Notes:
(1) ATT
3712/fs
(2)
(3)
×ATT
(Table 18)
ATS bit = “1”
ATT
“128”(−63.5dB)
(GD)
−∞
ATT
MS0684-J-02
2008/12
- 27 -
[AK4372]
■
IIR
3
DEM1-0 bit
(32kHz, 44.1kHz, 48kHz)
(50/15µs
(Table 19)
DEM1 bit
DEM0 bit
0
0
0
1
1
0
1
1
Table 19.
De-emphasis
44.1kHz
OFF
48kHz
32kHz
)
(default)
■
BST1-0 bit
DAC
(Table 20)
BST1 bit
0
0
1
1
BST0 bit
0
1
0
1
Table 20.
BOOST
OFF
MIN
MID
MAX
(default)
■
MONO1-0 bit
(Table 21)
DAC
MONO1 bit
0
0
1
1
Lch/Rch
MONO0 bit
0
1
0
1
Table 21.
Lch
L
L
R
(L+R)/2
Rch
R
L
R
(L+R)/2
(default)
■
PDN pin = “L”
PDN pin = “L”
AK4372
VCOM, DAC, HPL, HPR, LOUT, ROUT
DAC
PMDAC bit
“1”
150ns
PDN pin
MCKI
MCKI
MS0684-J-02
2008/12
- 28 -
[AK4372]
■
(HPL, HPR pins)
AVDD
PMHPL=PMHPR bits = “1”
MUTEN bit “0”
16Ω
tr:
tf:
(VCOM/2
(VCOM/2
Table 22.
: MUTET pin
MUTET pin
MUTEN bit
“1”
VCOM(=0.475 x AVDD)
VSS1
70k x C (typ)
60k x C (typ)
)
)
C=1μF
(VCOM/2
(VCOM/2
): tr = 70k x 1μ = 70ms(typ)
): tf = 60k x 1μ = 60ms(typ)
PMHPL, PMHPR bits “0”
HPL, HPR pins VSS1
PMHPL/R bit
MUTEN bit
HPL/R pin
VCOM
VCOM/2
tf
tr
(1) (2)
(3)
(4)
Figure 22.
(1)
(2)
(PMHPL, PMHPR bits = “1”)
VSS1
(MUTEN bit = “1”) MUTET
MUTET pin
“C”
(tr)
70k x C(typ)
(3)
VSS1
VCOM/2
(4)
VCOM/2
(tf)
(MUTEN bit = “0”) MUTET
MUTET pin
60k x C(typ)
(PMHPL, PMHPR bits = “0”)
VSS1
MS0684-J-02
“C”
2008/12
- 29 -
[AK4372]
(fc)
Table 23
(fc)
AVDD=2.4, 3.0, 3.3V
RL 16Ω
0.48 x AVDD (Vpp)
@−3dBFS
HP-AMP
R
C
Headphone
16Ω
AK4372
Figure 23.
R [Ω]
0
6.8
16
C [μF]
fc [Hz]
BOOST=OFF
fc [Hz]
BOOST=MIN
220
100
100
47
100
47
45
100
70
149
50
106
17
43
28
78
19
47
Table 23.
Output Power [mW]
,
2.4V
3.0V
3.3V
21
33
40
10
16
20
5
8
10
f
Wired OR
PMVCM=PMHPL=PMHPR bits = “0”, HPZ bit = “1”
200kΩ(typ) VSS1
OR
PMVCM
x
0
1
1
PMHPL/R
0
0
1
1
HP-Amp
AK4372 HP-Amp
HPMTN
HPZ
Mode
x
0
Power-down & Mute
x
1
Power-down
0
x
Mute
1
x
Normal Operation
Table 24. HP-Amp Mode Setting (x: Don’t care)
HPL, HPR pins
HP-Amp Wired
HPL/R pins
VSS1
Pull-down by 200kΩ
VSS1
Normal Operation
(default)
HPL pin
AK4372
Headphone
HPR pin
Another
HP-Amp
Figure 24.
Wired OR
MS0684-J-02
2008/12
- 30 -
[AK4372]
HPL
ON/OFF
DALHL, LINHL, RINHL, MINHL bits
HPR
ON/OFF
DARHR, LINHR, RINHR, MINHR bits
LHM bit = “0”, HPG1-0 bits =
“00” (R1H = R2H = RDH = 100k), ATTH4-0 bits = “00H”(0dB)
+0.95dB(typ)
HPG1-0 bit = “01” (RDH= 50k)
DAC
+6.95dB(typ)
HPG1-0 bit
= “10” (RDH= 25k)
DAC
+12.95dB(typ)
LHM bit
LIN/RIN
(L+R)/2
HPL/R
(R1H= 200k)
LDIF = LDIFH = LINL = RINR bits = “1”
HPL/R pins
LIN/RIN pins
IN−/+ pins
LINHL, RINHL, LINHR, RINHR bits
OFF
VCOM
“0”
(= 0.475 x AVDD)
Figure 51
100k(typ)
Figure 27
LDIFH bit
R1H
LIN pin
LINHL bit
R1H
RIN pin
RINHL bit
R2H
MIN pin
1.11RH
MINHL bit
RDH
DAC Lch
100k(typ)
DALHL bit
−
RH
+
−
HPL pin
+
HP-Amp
100k(typ)
Figure 27
LDIFH bit
R1H
LIN pin
LINHR bit
R1H
RIN pin
RINHR bit
R2H
MIN pin
1.11RH
MINHR bit
RDH
DAC Rch
100k(typ)
DARHR bit
−
RH
+
−
+
HPR pin
HP-Amp
Figure 25. HPL/R
MS0684-J-02
2008/12
- 31 -
[AK4372]
■
HPL/HPR
HMUTE bit = “0”
ATTH4-0 bit
+6dB ∼ −57dB or 0dB ∼ −63dB, 1.5dB or 3dB step, Table 25)
HMUTE
0
1
ATTH4-0
00H
01H
02H
03H
:
12H
13H
14H
15H
16H
:
1DH
1EH
1FH
x
HPG1-0 bits = “10”
HPG1-0 bits = “01”
HPG1-0 bits = “00”
(DAC Only)
(DAC Only)
+12dB
+6dB
0dB
+10.5dB
+4.5dB
−1.5dB
+9dB
+3dB
−3dB
+7.5dB
+1.5dB
−4.5dB
:
:
:
−15dB
−21dB
−27dB
−16.5dB
−22.5dB
−28.5dB
−18dB
−24dB
−30dB
−21dB
−27dB
−33dB
−24dB
−30dB
−36dB
:
:
:
−45dB
−51dB
−57dB
−48dB
−54dB
−60dB
−51dB
−57dB
−63dB
MUTE
MUTE
MUTE
Table 25. HPL/HPR Volume ATT values (x: Don’t care)
MS0684-J-02
(+12dB ∼ −51dB or
STEP
(default)
1.5dB
3dB
2008/12
- 32 -
[AK4372]
■
(LOUT, ROUT pins)
0.475 x AVDD
10kΩ
PMLO bit = “1”
LOUT
ON/OFF
DALL, LINL, RINL, MINL bits
ROUT
ON/OFF
DARR, LINR, RINR, MINR bits
LM bit = “0”, LOG bit = “0” (R1L = R2L = RDL =
100k), ATTS3-0 bits = “0FH”(0dB)
0dB(typ)
LOG bit = “1” (RDL= 50k)
DAC
+6dB
LM bit
LIN/RIN
(L+R)/2
LOUT/ROUT
(R1L = 200k)
OFF
VCOM
(= 0.475 x AVDD)
Figure 51
R1L
LIN pin
LINL bit
R1L
RIN pin
RINL bit
R2L
MIN pin
RL
MINL bit
RDL
DAC Lch
100k(typ)
DALL bit
−
RL
+
−
LOUT pin
+
R1L
LIN pin
LINR bit
R1L
RIN pin
RINR bit
R2L
MIN pin
RL
MINR bit
RDL
DAC Rch
100k(typ)
DARR bit
−
RL
+
−
+
ROUT pin
Figure 26. LOUT/ROUT
MS0684-J-02
2008/12
- 33 -
[AK4372]
LDIF=LINL=RINR bits = “1”
pins
LIN/RIN pins
IN−/+ pins
LOUT/ROUT
LOUT/ROUT pins
OFF
VCOM
(= 0.475 x AVDD)
Figure 51
Figure 25
HPL/R pins
LDIFH bit
R2L
IN− pin
100k(typ)
RL
LINL bit
100k(typ)
LDIF bit
−
RL
+
R2L
IN+ pin
−
LOUT pin
+
100k(typ)
RL
RINR bit
−
RL
+
−
ROUT pin
+
Figure 27. LOUT/ROUT
(
)
■
(+6dB ∼ −24dB or
LOUT/ROUT
LMUTE bit = “0”
ATTS3-0 bit
0dB ∼ −30dB, 2dB step, Table 26) LOUT/ROUT
LMUTE
0
1
LOG bit = “1”
(DAC Only)
FH
+6dB
EH
+4dB
DH
+2dB
CH
0dB
:
:
1H
−22dB
0H
−24dB
x
MUTE
Table 26. LOUT/ROUT Volume ATT
ATTS3-0
MS0684-J-02
LOG bit = “0”
0dB
−2dB
−4dB
−6dB
:
−28dB
−30dB
MUTE
(x: Don’t care)
(default)
2008/12
- 34 -
[AK4372]
■
(EXT mode)
1) DAC → HP-Amp
Power Supply
(10)
(1)
>150ns
PDN pin
Don’t care
(2) >0s
PMVCM bit
Don’t care
(3)
Don’t care
Don’t care
Clock Input
PMDAC bit
DAC Internal
State
PD
Normal Operation
PD
Normal Operation
PD
SDTI pin
DALHL,
DARHR bits
(4) >0s
PMHPL,
PMHPR bits
(4) >0s
(5) >2ms
(5) >2ms
MUTEN bit
ATTL7-0
ATTR7-0 bits
00H(MUTE)
FFH(0dB)
(8) GD (9) 1061/fs
(6)
FFH(0dB)
00H(MUTE)
(8)
(8) (9)
(9)
00H(MUTE)
(8) (9)
(6)
(7)
(7)
HPL/R pin
Figure 28. DAC
(1) AVDD
(2) PDN pin
(3) DAC
DVDD
“H”
HP-amp
(Don’t care: Hi-Z
DVDD 1.6V
150ns
PDN pin
PMVCM, PMDAC bit “1”
(MCKI, BICK, LRCK)
(4) PMVCM, PMDAC bits “1”
(5) DALHL, DARHR bits “1”
PMHPL, PMHPR, MUTEN bits “1”
(6)
(tr) 70k x C(typ)
C=1μF
(7)
(tf) 60k x C(typ)
C=1μF
DARHR bits
2ms
)
AVDD
“H”
PMDAC bit = “0”
DALHL, DARHR bits
(VCOM pin
“1”
MUTET pin
(C)
tr 70ms(typ)
MUTET pin
(C)
tf 60ms(typ)
PMHPL, PMHPR “0”
2.2μF
)
VCOM/2
VCOM/2
DALHL,
“0”
(8)
(9)
(10)
AVDD
22/fs(=499µs@fs=44.1kHz)
ATS bit
OFF
DVDD
MS0684-J-02
(GD)
1061/fs(=24ms@fs=44.1kHz)
AVDD DVDD
2008/12
- 35 -
[AK4372]
2) DAC → Lineout
Power Supply
(1) >150ns
PDN pin
(2)
>0s
PMVCM bit
Don’t care
(5)
Clock Input
Don’t care
(4) >0s
PMDAC bit
DAC Internal
State
Don’t care
PD
Normal Operation
PD(Power-down)
Normal Operation
SDTI pin
DALL,
DARR bits
(3) >0s
PMLO bit
ATTL/R7-0 bits
FFH(0dB)
00H(MUTE)
LMUTE,
ATTS3-0 bits
(2)
(3)
(4)
(5)
PDN pin “H”
PMVCM bit “1”
DALL, DARR bits
DAC
(6) PMLO bit
(7)
(8)
(8)
(7)
(8)
(6)
(6)
(Hi-Z)
Figure 29. DAC
DVDD
(8) 1061/fs (7)
(6)
LOUT/ROUT pins
FFH(0dB)
0FH(0dB)
10H(MUTE)
(7) GD
(1) AVDD
00H(MUTE)
(Hi-Z)
Lineout
(Don’t care: Hi-Z
)
DVDD 1.6V
AVDD
150ns
PDN pin “H”
PMVCM bit “1”
DALL, DARR bits “1”
“1”
PMDAC, PMLO bits “1”
(MCKI, BICK, LRCK)
PMDAC bit = “0”
LOUT/ROUT
LOUT, ROUT pins
22/fs(=499µs@fs=44.1kHz)
(GD)
ATS bit
1061/fs(=24ms@fs=44.1kHz)
MS0684-J-02
2008/12
- 36 -
[AK4372]
3) LIN/RIN/MIN → HP-Amp
Power Supply
(1) >150ns
PDN pin
(2) >0s
PMVCM bit
Don’t care
LINHL, MINHL,
RINHR, MINHR bits
(3) >0s
PMHPL/R bits
(5) >2ms
(5) >2ms
MUTEN bit
(Hi-Z)
(4)
LIN/RIN/MIN pins
(Hi-Z)
(7)
(6)
(6)
HPL/R pins
Figure 30. LIN/RIN
(1) AVDD
HP-amp
DVDD
DVDD 1.6V
150ns
PDN pin “H”
(MCKI, BICK, LRCK)
(2) PDN pin “H”
PMVCM bit “1”
(3) PMVCM bit “1”
LINHL, MINHL, RINHR, MINHR bits
(4) LINHL, MINHL, RINHR, MINHR bits “1”
LIN, RIN, MIN
AVDD
DAC
“1”
pin 0.475 x AVDD
(5) LINHL, MINHL, RINHR, MINHR bits “1”
2ms
(VCOM pin
PMHPL, PMHPR, MUTEN bits “1”
(6)
MUTET pin
(C)
(tr) 70k x C(typ)
C=1μF
tr 70ms(typ)
(7)
MUTET pin
(C)
(tf) 60k x C(typ)
C=1μF
tf 60ms(typ)
PMHPL, PMHPR bits “0”
MINHL, RINHR, MINHR bits “0”
MS0684-J-02
2.2μF
)
VCOM/2
VCOM/2
LINHL,
2008/12
- 37 -
[AK4372]
4) LIN/RIN/MIN → Lineout
Power Supply
(1) >150ns
PDN pin
(2) >0s
PMVCM bit
Don’t care
LINL, MINL,
RINR, MINR bits
(3) >0s
PMLO bit
(5) >2ms
(5) >2ms
(Hi-Z)
(4)
LIN/RIN/MIN pins
LMUTE,
ATTS3-0 bits
LOUT/ROUT pins
(Hi-Z)
DVDD
(6)
(6)
(Hi-Z)
Figure 31. LIN/RIN
(1) AVDD
0FH(0dB)
10H(MUTE)
(6)
(Hi-Z)
LOUT/ROUT
DVDD 1.6V
PDN pin
150ns
“H”
(MCKI, BICK, LRCK)
(2) PDN pin “H”
PMVCM bit “1”
(3) PMVCM bit “1”
LINL, MINL, RINR, MINR bits
(4) LINL, MINL, RINR, MINR bits “1”
LIN, RIN, MIN
(5) LINL, MINL, RINR, MINR bits “1”
PMLO bit “1”
(6) PMLO bit
LOUT, ROUT pins
2ms
MS0684-J-02
AVDD
DAC
“1”
pin 0.475 x AVDD
(VCOM pin
2.2μF
)
2008/12
- 38 -
[AK4372]
(PLL Slave mode)
„
1) DAC → HP-Amp
Power Supply
(12)
(1)
>150ns
PDN pin
Don’t care
(2) >0s
PMVCM, PMPLL,
PMDAC, MCKO bits
Don’t care
(3)
Don’t care
Don’t care
MCKI pin
Unstable
(4) ~20ms
Don’t care
(5)
Unstable
(4) ~20ms
MCKO pin
Unstable
Don’t care
(5)
BICK,
LRCK pins
Unstable
Unstable
DAC Internal
State
PD
Don’t care
Normal Operation
PD
Unstable
Normal Operation
PD
Don’t care
SDTI pin
Unstable
DALHL,
DARHR bits
(6) >0s
PMHPL,
PMHPR bits
(6) >0s
(7) >2ms
(7) >2ms
MUTEN bit
ATTL7-0
ATTR7-0 bits
FFH(0dB)
00H(MUTE)
FFH(0dB)
00H(MUTE)
(10) GD (11) 1061/fs (10) (11)
(8)
(9)
00H(MUTE)
(10) (11) (10) (11)
(8)
(9)
HPL/R pin
Figure 32. DAC
(1) AVDD
(2)
(3)
(4)
(5)
HP-amp
(Don’t care: Hi-Z
DVDD
DVDD 1.6V
150ns
PDN pin “H”
PDN pin “H”
PMVCM, PMPLL, PMDAC, MCKO bits “1”
MCKI pin
PLL
PLL
Table 4
PLL
MCKO pin
DAC
MCKO
(BICK, LRCK)
)
AVDD
PMDAC bit = “0”
DALHL, DARHR bits “1”
(6) PLL
2ms
(VCOM pin
2.2μF
)
(7) DALHL, DARHR bits “1”
PMHPL, PMHPR, MUTEN bits “1”
MUTET pin
(C)
VCOM/2
(8)
C=1μF
tr 70ms(typ)
(tr) 70k x C(typ)
MUTET pin
(C)
VCOM/2
(9)
C=1μF
tf 60ms(typ)
(tf) 60k x C(typ)
PMHPL, PMHPR “0”
DALHL,
DARHR bits “0” 3D1-0bits “00”
22/fs(=499µs@fs=44.1kHz)
(GD)
(10)
ATS bit
1061/fs(=24ms@fs=44.1kHz)
(11)
OFF
AVDD DVDD
(12)
AVDD
DVDD
MS0684-J-02
2008/12
- 39 -
[AK4372]
2) DAC → Lineout
Power Supply
(1) >150ns
PDN pin
(2)>0s
PMVCM, PMPLL,
PMDAC, MCKO bits
Don’t care
Don’t care
Don’t care
(3)
MCKI pin
(4) ~20ms
Unstable
MCKO pin
Don’t care
Unstable
Unstable (5)
(4) ~20ms
Unstable
(5)
BICK, LRCK pins
Unstable
DAC Internal
State
Unstable
PD
Normal Operation
Don’t care
PD
Normal Operation
Unstable
Unstable
SDTI pin
DALL,
DARR bits
(6) >0s
(6) >0s
(7) >0s
(7) >0s
PMLO bit
ATTL/R7-0 bits
LMUTE,
ATTS3-0 bits
00H(MUTE)
FFH(0dB)
10H(MUTE)
Figure 33. DAC
(1) AVDD
(2)
(3)
(4)
(5)
(8)
(9) (10)
(9)
(Hi-Z)
(Hi-Z)
Lineout
(Don’t care: Hi-Z
DVDD 1.6V
150ns
PDN pin “H”
PDN pin “H”
PMVCM, PMPLL, PMDAC, MCKO bits “1”
MCKI pin
PLL
PLL
Table 4
PLL
MCKO pin
DAC
MCKO
(BICK, LRCK)
LOUT/ROUT
DALL, DARR bits
(10)
(8)
(8)
DVDD
(6) PLL
(7) PMLO bit
(8) PMLO bit
(9)
(10)
FFH(0dB)
0FH(0dB)
(9) GD (10) 1061/fs
LOUT/ROUT pins
00H(MUTE)
)
AVDD
PMDAC bit = “0”
“1”
“1”
LOUT, ROUT pins
22/fs(=499µs@fs=44.1kHz)
ATS bit
MS0684-J-02
(GD)
1061/fs(=24ms@fs=44.1kHz)
2008/12
- 40 -
[AK4372]
LIN/RIN/MIN → HP-Amp
Power Supply
(1) >150ns
PDN pin
(2) >0s
PMVCM bit
Don’t care
LINHL, MINHL,
RINHR, MINHR bits
(3) >0s
PMHPL/R bits
(5) >2ms
(5) >2ms
MUTEN bit
(Hi-Z)
(4)
LIN/RIN/MIN pins
(Hi-Z)
(7)
(6)
(6)
HPL/R pins
Figure 34. LIN/RIN
(1) AVDD
HP-amp
DVDD
DVDD 1.6V
150ns
PDN pin “H”
(MCKI, BICK, LRCK)
(2) PDN pin “H”
PMVCM bit “1”
(3) PMVCM bit “1”
LINHL, MINHL, RINHR, MINHR bits
(4) LINHL, MINHL, RINHR, MINHR bits “1”
LIN, RIN, MIN
AVDD
DAC
“1”
pin 0.475 x AVDD
(5) LINHL, MINHL, RINHR, MINHR bits “1”
2ms
(VCOM pin
PMHPL, PMHPR, MUTEN bits “1”
(6)
MUTET pin
(C)
(tr) 70k x C(typ)
C=1μF
tr 70ms(typ)
(7)
MUTET pin
(C)
(tf) 60k x C(typ)
C=1μF
tf 60ms(typ)
PMHPL, PMHPR bits “0”
MINHL, RINHR, MINHR bits “0”
MS0684-J-02
2.2μF
)
VCOM/2
VCOM/2
LINHL,
2008/12
- 41 -
[AK4372]
4) LIN/RIN/MIN → Lineout
Power Supply
(1) >150ns
PDN pin
(2) >0s
PMVCM bit
Don’t care
LINL, MINL,
RINR, MINR bits
(3) >0s
PMLO bit
(5) >2ms
(5) >2ms
(Hi-Z)
(4)
LIN/RIN/MIN pins
LMUTE,
ATTS3-0 bits
LOUT/ROUT pins
(Hi-Z)
DVDD
(6)
(6)
(Hi-Z)
Figure 35. LIN/RIN
(1) AVDD
0FH(0dB)
10H(MUTE)
(6)
(Hi-Z)
LOUT/ROUT
DVDD 1.6V
PDN pin
150ns
“H”
(MCKI, BICK, LRCK)
(2) PDN pin “H”
PMVCM bit “1”
(3) PMVCM bit “1”
LINL, MINL, RINR, MINR bits
(4) LINL, MINL, RINR, MINR bits “1”
LIN, RIN, MIN
(5) LINL, MINL, RINR, MINR bits “1”
PMLO bit “1”
(6) PMLO bit
LOUT, ROUT pins
2ms
MS0684-J-02
AVDD
DAC
“1”
pin 0.475 x AVDD
(VCOM pin
2.2μF
)
2008/12
- 42 -
[AK4372]
(PLL Master Mode)
„
1) DAC → HP-Amp
Power Supply
(11)
(1)
>150ns
PDN pin
Don’t care
(2) >0
M/S, PMVCM, PMPLL,
PMDAC, MCKO bits
Don’t care (3)
Don’t care
Don’t care
MCKI pin
(4) ~20ms
Unstable
Unstable
(4) ~20ms
MCKO pin
Don’t care “L”
Don’t care
Unstable
BICK, LRCK pins
Unstable
Unstable
DAC Internal
State
PD
Don’t care
Normal Operation
PD
Unstable
Normal Operation
PD
Don’t care
SDTI pin
Unstable
DALHL,
DARHR bits
(5) >0
PMHPL,
PMHPR bits
(5) >0
(6) >2ms
(6) >2ms
MUTEN bit
ATTL7-0
ATTR7-0 bits
FFH(0dB)
00H(MUTE)
(9) GD (10) 1061/fs (9)
FFH(0dB)
00H(MUTE)
(10)
(7)
(8)
(9) (10) (9)
00H(MUTE)
(10)
(7)
(8)
HPL/R pin
Figure 36. DAC
(1) AVDD
DVDD
(2) PDN pin "H"
(3) MCKI pin
(4) PLL
HP-amp
(Don’t care: Hi-Z
)
DVDD 1.6V
AVDD
150ns
PDN pin "H"
PMVCM, PMPLL, PMDAC, MCKO, M/S bits “1”
PLL
Table 4
PLL
BICK, LRCK, MCKO pins
(5) PLL
DALHL, DARHR bits “1”
(6) DALHL, DARHR bits “1”
2ms
(VCOM pin
2.2µF
)
PMHPL, PMHPR, MUTEN bits “1”
(7)
MUTET pin
(C)
VCOM/2
(tr) 70k x C(typ)
C=1µF
tr 70ms(typ)
(8)
MUTET pin
(C)
VCOM/2
(tf) 60k x C(typ)
C=1µF
tf 60ms(typ)
PMHPL, PMHPR bits “0”
DALHL,
DARHR bits “0”
(9)
22/fs(=499µs@fs=44.1kHz)
(GD)
(10)
ATS bit
1061/fs(=24ms@fs=44.1kHz)
(11)
OFF
AVDD DVDD
AVDD
DVDD
MS0684-J-02
2008/12
- 43 -
[AK4372]
2) DAC → Lineout
Power Supply
(1) >150ns
PDN pin
(2)
>0
M/S, PMVCM, PMPLL,
PMDAC, MCKO bits
Don’t care
Don’t care
Don’t care
(3)
MCKI pin
(4) ~20ms
Unstable
MCKO pin
Don’t care
Unstable
“L”
(4) ~20ms
Unstable
BICK, LRCK pins
Unstable
DAC Internal
State
Unstable
PD
Normal Operation
Don’t care
PD
Unstable
Normal Operation
Unstable
SDTI pin
DALL,
DARR bits
(5) >0
(5) >0
(6) >0
(6) >0
PMLO bit
ATTL/R7-0 bits
LMUTE,
ATTS3-0 bits
FFH(0dB)
00H(MUTE)
10H(MUTE)
(7)
(1) AVDD
DVDD
(2) PDN pin “H”
(3) MCKI pin
(4) PLL
(5) PLL
(6) PMLO bit
(7) PMLO bit
(8)
(9)
(8) (9)
(8)
(9)
(7)
(8)
(Hi-Z)
Figure 37. DAC
FFH(0dB)
0FH(0dB)
(8) GD (9) 1061/fs
LOUT/ROUT pins
00H(MUTE)
(Hi-Z)
Lineout
(Don’t care: Hi-Z
)
DVDD 1.6V
AVDD
150ns
PDN pin “H”
PMVCM, PMPLL, PMDAC, MCKO, M/S bits “1”
PLL
Table 4
PLL
BICK, LRCK, MCKO pins
DALL, DARR bits
“1”
“1”
LOUT, ROUT pins
22/fs(=499μs@fs=44.1kHz)
ATS bit
MS0684-J-02
(GD)
1061/fs(=24ms@fs=44.1kHz)
2008/12
- 44 -
[AK4372]
LIN/RIN/MIN → HP-Amp
Power Supply
(1) >150ns
PDN pin
(2) >0s
PMVCM bit
Don’t care
LINHL, MINHL,
RINHR, MINHR bits
(3) >0s
PMHPL/R bits
(5) >2ms
(5) >2ms
MUTEN bit
(Hi-Z)
(4)
LIN/RIN/MIN pins
(Hi-Z)
(7)
(6)
(6)
HPL/R pins
Figure 38. LIN/RIN
(1) AVDD
HP-amp
DVDD
DVDD 1.6V
150ns
PDN pin “H”
(MCKI, BICK, LRCK)
(2) PDN pin “H”
PMVCM bit “1”
(3) PMVCM bit “1”
LINHL, MINHL, RINHR, MINHR bits
(4) LINHL, MINHL, RINHR, MINHR bits “1”
LIN, RIN, MIN
AVDD
DAC
“1”
pin 0.475 x AVDD
(5) LINHL, MINHL, RINHR, MINHR bits “1”
2ms
(VCOM pin
PMHPL, PMHPR, MUTEN bits “1”
(6)
MUTET pin
(C)
(tr) 70k x C(typ)
C=1μF
tr 70ms(typ)
(7)
MUTET pin
(C)
(tf) 60k x C(typ)
C=1μF
tf 60ms(typ)
PMHPL, PMHPR bits “0”
MINHL, RINHR, MINHR bits “0”
MS0684-J-02
2.2μF
)
VCOM/2
VCOM/2
LINHL,
2008/12
- 45 -
[AK4372]
4) LIN/RIN/MIN → Lineout
Power Supply
(1) >150ns
PDN pin
(2) >0s
PMVCM bit
Don’t care
LINL, MINL,
RINR, MINR bits
(3) >0s
PMLO bit
(5) >2ms
(5) >2ms
(Hi-Z)
(4)
LIN/RIN/MIN pins
LMUTE,
ATTS3-0 bits
LOUT/ROUT pins
(Hi-Z)
DVDD
(6)
(6)
(Hi-Z)
Figure 39. LIN/RIN
(1) AVDD
0FH(0dB)
10H(MUTE)
(6)
(Hi-Z)
LOUT/ROUT
DVDD 1.6V
PDN pin “H”
150ns
(MCKI, BICK, LRCK)
(2) PDN pin “H”
PMVCM bit “1”
(3) PMVCM bit “1”
LINL, MINL, RINR, MINR bits
(4) LINL, MINL, RINR, MINR bits “1”
LIN, RIN, MIN
(5) LINL, MINL, RINR, MINR bits “1”
PMLO bit “1”
(6) PMLO bit
LOUT, ROUT pins
2ms
MS0684-J-02
AVDD
DAC
“1”
pin 0.475 x AVDD
(VCOM pin
2.2μF
)
2008/12
- 46 -
[AK4372]
■
(1) 3
(I2C pin = “L”)
3
I/F
: CSN, CCLK, CDTI
I/F
Chip
address(2bits, “01”
), Read/Write(1bit, Fixed to “1”, Write only), Register address(MSB first, 5bits), Control
data(MSB first, 8bits)
CCLK
CCLK 16
1
CSN
“H”
CCLK
5MHz(max)
PDN pin = “L”
CSN
0
CCLK
Clock, “H” or “L”
CDTI
“H” or “L”
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Clock, “H” or “L”
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
“H” or “L”
Chip Address (Fixed to “01”)
READ/WRITE (Fixed to “1”, Write only)
Register Address
Control Data
Figure 40. 3
I/F
MS0684-J-02
2008/12
- 47 -
[AK4372]
(2) I2C
AK4372
(I2C pin = “H”)
Fast-mode (max:400kHz, Ver1.0)
I 2C
(2)-1. WRITE
I2C
(Start Condition)
(Figure 47)
8bit
IC
AK4372
SCL
2
“L”
7bit
6bit
“001000”
(Figure 42)
1bit
(Acknowledge)
(Figure 48) R/W
(
(Figure 43)
3
(Figure 44) AK4372
“L”
IC
“H”
SDA
(R/W)
CAD0 pin
SDA
“1”
R/W
Figure 41
“H”
)
8bit MSB first
8bit
(Stop Condition)
(Figure 47)
“H”
“0”
SCL
AK4372
“H”
3bit “0”
MSB first
SDA
1
“13H”
“00H”
“H”
SDA
SCL
“L”
(Figure 49)
“H”
SCL
“L”
“H”
SDA
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “0”
Slave
Address
Sub
Address(n)
A
C
K
Data(n)
Data(n+x)
Data(n+1)
A
C
K
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 41. I2C
0
0
1
0
0
0
CAD0
R/W
A3
A2
A1
A0
D3
D2
D1
D0
(CAD0 pin
Figure 42. 1
0
0
0
A4
Figure 43.
D7
D6
D5
Figure 44.
)
2
D4
3
MS0684-J-02
2008/12
- 48 -
[AK4372]
(2)-2. READ
R/W
“1”
AK4372
READ
“13H”
“00H”
AK4372
2
READ
(2)-2-1.
AK4372
AK4372
(READ
WRITE
“n+1”
(R/W = “1”)
READ
)
“n”
1
READ
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
Data(n+2)
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 45. CURRENT ADDRESS READ
(2)-2-2.
READ
(R/W bit= “1”)
“0”)
WRITE
WRITE
AK4372
(R/W bit= “1”)
READ
(R/W =
AK4372
1
READ
S
T
A
R
T
SDA
S
S
T
A
R
T
R/W= “0”
Sub
Address(n)
Slave
Address
A
C
K
S
A
C
K
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+x)
Data(n+1)
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 46. RANDOM ADDRESS READ
MS0684-J-02
2008/12
- 49 -
[AK4372]
SDA
SCL
S
P
start condition
stop condition
Figure 47.
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 48. I2C
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 49. I2C
MS0684-J-02
2008/12
- 50 -
[AK4372]
■
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
Register Name
Power Management 0
PLL Control
Clock Control
Mode Control 0
Mode Control 1
DAC Lch ATT
DAC Rch ATT
Headphone Out Select 0
Lineout Select 0
Lineout ATT
Reserved
Reserved
Reserved
Headphone Out Select 1
Headphone ATT
Lineout Select 1
Mono Mixing
Differential Select
Reserved
Reserved
PDN pin = “L”
PDN pin “L”
14H
1FH
“0”
“1”
D7
0
FS3
PLL4
0
ATS
ATTL7
ATTR7
HPG1
0
0
0
0
0
0
0
0
0
0
0
0
D6
PMPLL
FS2
0
MONO1
DATTC
ATTL6
ATTR6
HPG0
LOG
0
0
0
0
0
HPZ
0
0
0
0
0
D5
PMLO
FS1
M/S
MONO0
LMUTE
ATTL5
ATTR5
MINHR
MINR
0
0
0
0
0
HMUTE
0
0
0
0
0
D4
MUTEN
FS0
MCKAC
BCKP
SMUTE
ATTL4
ATTR4
MINHL
MINL
0
0
0
0
0
ATTH4
0
0
0
0
1
D3
PMHPR
PLL3
BF
LRP
BST1
ATTL3
ATTR3
RINHR
RINR
ATTS3
0
0
0
0
ATTH3
0
0
0
0
0
D2
PMHPL
PLL2
PS0
DIF2
BST0
ATTL2
ATTR2
LINHL
LINL
ATTS2
0
0
0
0
ATTH2
0
0
0
0
0
D1
PMDAC
PLL1
PS1
DIF1
DEM1
ATTL1
ATTR1
DARHR
DARR
ATTS1
0
0
0
LINHR
ATTH1
LINR
LM
LDIFH
0
0
D0
PMVCM
PLL0
MCKO
DIF0
DEM0
ATTL0
ATTR0
DALHL
DALL
ATTS0
0
0
0
RINHL
ATTH0
RINL
LHM
LDIF
0
0
“1”
“0”
MS0684-J-02
2008/12
- 51 -
[AK4372]
■
Addr
00H
Register Name
Power Management 0
R/W
Default
D7
0
RD
0
D6
PMPLL
R/W
0
D5
PMLO
R/W
0
D4
MUTEN
R/W
0
D3
PMHPR
R/W
0
D2
PMHPL
R/W
0
D1
PMDAC
R/W
0
D0
PMVCM
R/W
0
PMVCM: VCOM
0: Power OFF (default)
1: Power ON
PMDAC: DAC
0: Power OFF (default)
1: Power ON
OFF
ON
ATT
PMHPL: Lch
0: Power OFF (default)
1: Power ON
HPL pin
VSS1 (0V)
PMHPR: Rch
0: Power OFF (default)
1: Power ON
HPR pin
VSS1 (0V)
MUTEN:
0:
1:
(default)
DC
VSS1 (0V)
0.475 x AVDD
PMLO:
0: Power OFF (default)
1: Power ON
Hi-Z
PMPLL: PLL
0: Power OFF: EXT mode (default)
1: Power ON: PLL mode
ON/OFF “1” /“0”
PDN pin
“L”
PMVCM, PMDAC, PMHPL, PMHPR, PMLO, PMPLL, MCKO bits
20μA(typ)
(typ. 1μA)
MS0684-J-02
“0”
PDN pin = “L”
2008/12
- 52 -
[AK4372]
Addr
01H
Register Name
PLL Control
R/W
Default
D7
FS3
R/W
1
D6
FS2
R/W
0
D5
FS1
R/W
0
D4
FS0
R/W
0
D3
PLL3
R/W
0
D2
PLL2
R/W
0
D1
PLL1
R/W
0
D0
PLL0
R/W
0
D6
0
RD
0
D5
M/S
R/W
0
D4
MCKAC
R/W
0
D3
BF
R/W
0
D2
PS0
R/W
0
D1
PS1
R/W
0
D0
MCKO
R/W
0
FS3-0:
PLL mode: Table 5
EXT mode: Table 11
PLL4-0: PLL
PLL mode: Table 4
EXT mode:
PLL4 bit Addr=02H, D7
Addr
02H
Register Name
Clock Control
R/W
Default
D7
PLL4
R/W
0
MCKO: MCKO
0: Disable (default)
1: Enable
PS1-0: MCKO
PLL mode: Table 9
EXT mode: Table 12
BF:
BICK
0: 32fs (default)
1: 64fs
MCKAC: MCKI
0: CMOS
1: AC
M/S:
(default)
/
0:
1:
PLL4: PLL
PLL3-0 bits
(default)
Addr=01H, D3-0
MS0684-J-02
2008/12
- 53 -
[AK4372]
Addr
03H
Register Name
Mode Control 0
R/W
Default
D7
0
RD
0
D6
D5
MONO1
MONO0
R/W
0
R/W
0
DIF2-0:
D4
BCKP
R/W
0
D3
LRP
R/W
0
D2
DIF2
R/W
0
D1
DIF1
R/W
1
D0
DIF0
R/W
0
D2
BST0
R/W
0
D1
DEM1
R/W
0
D0
DEM0
R/W
1
(Table 16)
Default: “010” (Mode 2)
LRP: LRCK
0:
1:
(
(default)
)
BCKP: BICK
(
0:
(default)
1:
)
MONO1-0:
Default: “00” (LR)
Addr
04H
Register Name
Mode Control 1
R/W
Default
(Table 21)
D7
ATS
R/W
0
D6
DATTC
R/W
0
DEM1-0:
Default: “01” (OFF)
D5
LMUTE
R/W
1
D4
SMUTE
R/W
0
D3
BST1
R/W
0
(Table 19)
BST1-0:
(Table 20)
Default: “00” (OFF)
SMUTE: DAC
0:
1: DAC
(default)
LMUTE: LOUT/ROUT
0:
ATTS3-0 bits
1: Mute ATTS3-0 bits
(Table 26)
(default)
DATTC:
0: Independent (default)
1: Dependent
“0” Lch, Rch
DATTC bit = “1”
ATS:
“1” Lch ATT
ATTR7-0 bit
ATTL7-0 bit
Rch
ATT
(Table 18)
0: 1061/fs (default)
1: 7424/fs
MS0684-J-02
2008/12
- 54 -
[AK4372]
Addr
05H
06H
Register Name
DAC Lch ATT
DAC Rch ATT
R/W
Default
D7
ATTL7
ATTR7
R/W
0
D6
ATTL6
ATTR6
R/W
0
D5
ATTL5
ATTR5
R/W
0
ATTL7-0: DAC Lch
ATTR7-0: DAC Rch
Default: “00H” (MUTE)
Addr
07H
Register Name
Headphone Out Select 0
R/W
Default
D4
ATTL4
ATTR4
R/W
0
D3
ATTL3
ATTR3
R/W
0
D2
ATTL2
ATTR2
R/W
0
D1
ATTL1
ATTR1
R/W
0
D0
ATTL0
ATTR0
R/W
0
D3
RINHR
R/W
0
D2
LINHL
R/W
0
D1
DARHR
R/W
0
D0
DALHL
R/W
0
(Table 17)
(Table 17)
D7
HPG1
R/W
0
D6
HPG0
R/W
0
D5
MINHR
R/W
0
DALHL: DAC Lch
0: OFF (default)
1: ON
Lch
DARHR: DAC Rch
0: OFF (default)
1: ON
Rch
D4
MINHL
R/W
0
LINHL: LIN pin
0: OFF (default)
1: ON
Lch
RINHR: RIN pin
0: OFF (default)
1: ON
Rch
MINHL: MIN pin
0: OFF (default)
1: ON
Lch
MINHR: MIN pin
0: OFF (default)
1: ON
Rch
HPG1-0: DACÆHPL/R Gain (Table 25)
Default: “00”: +0.95dB
MS0684-J-02
2008/12
- 55 -
[AK4372]
Addr
08H
Register Name
Lineout Select 0
R/W
Default
D7
0
D6
LOG
R/W
0
RD
0
DALL: DAC Lch
0: OFF (default)
1: ON
LOUT
DARR: DAC Rch
0: OFF (default)
1: ON
ROUT
LINL: LIN pin
0: OFF (default)
1: ON
LOUT
RINR: RIN pin
0: OFF (default)
1: ON
ROUT
MINL: MIN pin
0: OFF (default)
1: ON
LOUT
MINR: MIN pin
0: OFF (default)
1: ON
ROUT
D5
MINR
R/W
0
D4
MINL
R/W
0
D3
RINR
R/W
0
D2
LINL
R/W
0
D1
DARR
R/W
0
D0
DALL
R/W
0
D5
0
RD
0
D4
0
RD
0
D3
ATTS3
R/W
0
D2
ATTS2
R/W
0
D1
ATTS1
R/W
0
D0
ATTS0
R/W
0
LOG: DAC Æ LOUT/ROUT Gain
0: 0dB (default)
1: +6dB
Addr
09H
Register Name
Lineout ATT
R/W
Default
D7
0
RD
0
D6
0
RD
0
ATTS3-0: LOUT/ROUT
(Table 26)
Default: LMUTE bit = “1”, ATTS3-0 bits = “0000” (MUTE)
ATTS3-0 bits
LMUTE bit
“0”
MS0684-J-02
2008/12
- 56 -
[AK4372]
Addr
0DH
Register Name
Headphone Out Select
R/W
Default
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
RD
RD
RD
RD
RD
RD
0
0
0
0
0
D4
ATTH4
R/W
0
D3
ATTH3
R/W
0
RINHL: RIN pin
0: OFF (default)
1: ON
Lch
LINHR: LIN pin
0: OFF (default)
1: ON
Rch
Addr
0EH
Register Name
Headphone ATT
R/W
Default
D7
0
RD
0
D6
HPZ
R/W
0
D5
HMUTE
R/W
0
0
D1
LINHR
R/W
0
D0
RINHL
R/W
0
D2
ATTH2
R/W
0
D1
ATTH1
R/W
0
D0
ATTH0
R/W
0
ATTH4-0: HPL/HPR
(Table 25)
Default: HMUTE bit = “0”, ATTH4-0 bits = “00H” (0dB)
ATTH4-0 bits
HMUTE bit
HMUTE: HPL/HPR
0:
ATTH4-0 bits
1: Mute ATTH4-0 bits
HPZ: HP-Amp
0:
1: 200kΩ(typ)
“0”
(Table 25)
(default)
(default)
MS0684-J-02
2008/12
- 57 -
[AK4372]
Addr
0FH
Register Name
Lineout Select
R/W
Default
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
RD
RD
RD
RD
RD
RD
0
0
0
0
0
0
RINL: RIN pin
0: OFF (default)
1: ON
LOUT
LINR: LIN pin
0: OFF (default)
1: ON
ROUT
Addr
10H
Register Name
Mono Mixing
R/W
Default
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
RD
RD
RD
RD
RD
RD
0
0
0
0
0
0
LHM: LIN/RIN pins
0: OFF (default)
1: ON
(L+R)/2
LM: LIN/RIN pins
0: OFF (default)
1: ON
Addr
11H
Register Name
Differential Select
R/W
Default
LDIF: IN+/− pins
0: OFF (default)
1: ON
LDIF bit = “1”
LDIFH: IN+/− pins
0: OFF (default)
1: ON
D1
LINR
R/W
0
D0
RINL
R/W
0
D1
LM
R/W
0
D0
LHM
R/W
0
D1
LDIFH
R/W
0
D0
LDIF
R/W
0
HPL/R
(L+R)/2
LOUT/ROUT
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
RD
RD
RD
RD
RD
RD
0
0
0
0
0
0
LOUT/ROUT
LIN/RIN
IN+/IN−
HPL/R
(LDIF bit = “1”
MS0684-J-02
)
2008/12
- 58 -
[AK4372]
Figure 50
Digital Ground
Analog Ground
µP
Cp Rp
VSS2
CCLK
CSN
PDN
MUTET
VCOC
MCKO
CDTI
LOUT
ROUT
AK4372ECB
1000p
Audio
MCKI
LRCK
DVDD
1µ
I2C
VCOM
2.2µ
Top View
Controller
SDATA
SPK-Amp
+
Analog Supply
10
BICK
LIN
HPR
AVDD
RIN
MIN
HPL
VSS1
+
220µ
+
10µ
1.6∼3.6V
0.1µ
0.1µ
+
220µ
16Ω
16Ω
Headphone
:
- AK4372
- EXT
- PLL
-
- AVDD
0.1μF
VSS1, VSS2
(PMPLL bit = “0”)
(PMPLL bit = “1”)
10Ω
Figure 50.
VCOC pin
Cp Rp Table 4
M/S bit “1”
AK4372 LRCK, BICK pins
AK4372 LRCK, BICK pins 100kΩ
DVDD
(MCKI
AC
MS0684-J-02
DVDD
)
2008/12
- 59 -
[AK4372]
AVDD
AK4372
110k
LIN1 pin
HP-Amp
LIN1HL bit
100k
:
OFF
VCOM
(= 0.475 x AVDD)
Figure 51.
1.
AVDD
AVDD
10Ω
DVDD
DVDD
OFF
AVDD
DVDD
1.6V
DVDD
AVDD
AVDD
VSS1, VSS2
PC
2.
AVDD
AVDD
VCOM
0.475 x AVDD
VSS1
0.1μF
(typ)
2.2μF
VSS1
VCOM pins
AVDD
VCOM pins
3.
DAC
VCOM
0.48xAVDD(typ)@−3dBFS
0.61xAVDD(typ)@0dBFS
7FFFFFH(@24bit)
000000H(@24bit)
VCOM
VCOM+
mV
VCOM
LOUT/ROUT
2’s
800000H(@24bit)
DC
VCOM
(2
)
DC
MS0684-J-02
2008/12
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[AK4372]
24
CSP (Unit: mm)
Top View
Bottom View
2.50 ± 0.05
A
0.4
5
5
4372
4
3
2.50 ± 0.05
3
XXXX
2
B
4
2
1
1
A
B
C
D
E
E
D
C
B
A
φ 0.25 ± 0.05
φ 0.05
M
S AB
0.20 ± 0.05
0.65
S
0.08
S
■
:
: SnAgCu
(
)
MS0684-J-02
2008/12
- 61 -
[AK4372]
4372
XXXX
1
A
XXXX : Date code identifier (4 )
Date (YY/MM/DD)
07/10/30
08/12/04
Revision
00
01
08/12/19
02
Reason
Page
Contents
1, 3, 4, 6 AK4372VCB
Ambient Temperature
AK4372ECB: −30 ∼ 85°C
AK4372VCB: −40 ∼ 85°C
53
39-42
mode, PLL Master mode)
(PLL Slave
•
•
•
(
)
•
•
•
MS0684-J-02
2008/12
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