ASAHI KASEI [AK4396] AK4396 Advanced Multi-Bit 192kHz 24-Bit ΔΣ DAC AK4396 DVD-Audio 192kHz 24 DAC ΔΣ (SCF) 192kHz PCM DSDDVD-Audio, SACD AK4396 AK4393/4/5 • 128 • : 30kHz ∼ 216kHz • 24 8 ( - Ripple: ±0.005dB, Attenuation: 75dB • • • DSD • 32, 44.1, 48kHz • • ATT( 256 ) • THD+N: −100dB • DR, S/N: 120dB • I/F : 24 , 16/20/24 • : 256fs, 384fs, 512fs, 768fs or 1152fs 2 : 128fs, 192fs, 256fs or 384fs 4 : 128fs or 192fs DSD : 512fs or 768fs • : 5V ± 5%( ), 3.0 ∼ 5.25V( ) • : CMOS or TTL • : 28VSOP • AK4393/4/5 MS0336-J-00 ) , I2S, DSD 2004/08 -1- ASAHI KASEI [AK4396] AVDD AVSS DVDD DVSS VCOM PDN TTL SMUTE DFS0 ACKS DZFL BICK/DCLK LRCK/DSDR PCM Data Interface SDATA/DSDL 8X Interpolator ΔΣ Modulator SCF 8X Interpolator ΔΣ Modulator SCF AOUTLAOUTR+ AOUTRDZFR DIF0/DCLK DSD Data Interface DIF1/DSDL DIF2/DSDR CAD0 CAD1 AOUTL+ Control Register CSN CCLK CDTI P/S Clock Divider MCLK De-emphasis Control DEM0 DEM1 VREFH VREFL Block Diagram MS0336-J-00 2004/08 -2- ASAHI KASEI [AK4396] AK4396VF AKD4396 −40 ∼ +85°C AK4396 28pin VSOP (0.65mm pitch) DVSS 1 28 ACKS/DZFR DVDD 2 27 TST2/CAD1 MCLK 3 26 TST1/DZFL PDN 4 25 P/S BICK/DCLK 5 24 VCOM SDATA/DSDL 6 23 AOUTL+ LRCK/DSDR 7 22 AOUTL- SMUTE/CSN 8 21 AOUTR+ DFS0/CAD0 9 20 AOUTR- DEM0/CCLK 10 19 AVSS DEM1/CDTI 11 18 AVDD DIF0/DCLK 12 17 VREFH DIF1/DSDL 13 16 VREFL DIF2/DSDR 14 15 TTL Top View MS0336-J-00 2004/08 -3- ASAHI KASEI [AK4396] AK4393/4/5 1. Function & Performance fs (max) DVDD Power Dissipation Digital Input Level DF Stopband Attenuation Digital Volume μP I/F Address Pin De-emphasis Filter Optional DF Zero Detection Pin DSD Mode Pin #15 Pin #26 (Serial mode) Pin #28 (Serial mode) AK4393 108kHz 3 ~ 5.25V 310mW CMOS 75dB AK4394 216kHz 4.75 ~ 5.25V 325mW TTL 75dB Not available Not available Not available Not available 32k, 44.1k, 48k, 96k 32k, 44.1k, 48k, 96k Not available Slow Roll-off Not available DZFL/R No No BVSS BVSS CKS0 DZFL CKS2 DZFR AK4395 216kHz 4.75 ~ 5.25V 335mW TTL 110dB 256 levels, 0.5dB CAD0/1 32k, 44.1k, 48k Slow Roll-off DZFL/R No BVSS DZFL DZFR AK4396 216kHz 3 ~ 5.25V 200mW CMOS/TTL 75dB 256 levels, Linear CAD0/1 32k, 44.1k, 48k Slow Roll-off DZFL/R Yes TTL DZFL DZFR 2. Pin Configuration Pin # AK4393 1 DVSS 2 DVDD 3 MCLK 4 PDN 5 BICK 6 SDATA 7 LRCK 8 SMUTE/CSN 9 DFS0 10 DEM0/CCLK 11 DEM1/CDTI 12 DIF0 13 DIF1 14 DIF2 15 BVSS 16 VREFL 17 VFEFH 18 AVDD 19 AVSS 20 AOUTR− 21 AOUTR+ 22 AOUTL− 23 AOUTL+ 24 VCOM 25 P/S 26 CKS0 27 CKS1 28 CKS2 TST1-2: AK4394 DVSS DVDD MCLK PDN BICK SDATA LRCK SMUTE/CSN DFS0 DEM0/CCLK DEM1/CDTI DIF0 DIF1 DIF2 BVSS VREFL VFEFH AVDD AVSS AOUTR− AOUTR+ AOUTL− AOUTL+ VCOM P/S CKS0/DZFL CKS1 CKS2/DZFR Don’t care. AK4395 DVSS DVDD MCLK PDN BICK SDATA LRCK SMUTE/CSN DFS0/CAD0 DEM0/CCLK DEM1/CDTI DIF0 DIF1 DIF2 BVSS VREFL VFEFH AVDD AVSS AOUTR− AOUTR+ AOUTL− AOUTL+ VCOM P/S CKS0/DZFL CKS1/CAD1 ACKS/DZFR MS0336-J-00 AK4396 DVSS DVDD MCLK PDN BICK SDATA LRCK SMUTE/CSN DFS0/CAD0 DEM0/CCLK DEM1/CDTI DIF0 DIF1 DIF2 TTL VREFL VFEFH AVDD AVSS AOUTR− AOUTR+ AOUTL− AOUTL+ VCOM P/S TST1/DZFL TST2/CAD1 ACKS/DZFR 2004/08 -4- ASAHI KASEI [AK4396] 3. CKS2-0 AK4393/4/5 CKS2 0 0 0 0 1 1 1 1 CKS1 0 0 1 1 0 0 1 1 CKS0 0 1 0 1 0 1 0 1 DFS0=0 256fs 256fs 384fs 384fs 512fs 512fs 768fs 768fs AK4396 DFS0=1 128fs 256fs 192fs 384fs 256fs N/A 384fs N/A : DFS0 ACKS 0 0 0 0 1 1 1 1 DFS0=0 256fs 256fs 384fs 384fs 512fs 512fs 768fs 768fs DFS0=1 128fs 256fs 192fs 384fs 256fs N/A 384fs N/A 4. Register map Addr 00H 01H 02H 03H 04H Register Name Control 1 Control 2 Control 3 Lch ATT Control Rch ATT Control D7 ACKS DZFE D/P ATT7 ATT7 D6 D5 D4 D3 D2 0 0 0 DIF2 DIF1 DZFM SLOW DFS1 DFS0 DEM1 DSDM DCKS DCKB 0 DZFB ATT6 ATT5 ATT4 ATT3 ATT2 ATT6 ATT5 ATT4 ATT3 ATT2 : Changing points from AK4393’s register. Italic means the default value differs from AK4393. D1 DIF0 DEM0 0 ATT1 ATT1 D0 RSTN SMUTE 0 ATT0 ATT0 Addr 00H 01H 02H 03H 04H Register Name Control 1 Control 2 Control 3 Lch ATT Control Rch ATT Control D7 ACKS DZFE D/P ATT7 ATT7 D6 0 DZFM DSDM ATT6 ATT6 D1 DIF0 DEM0 0 ATT1 ATT1 D0 RSTN SMUTE 0 ATT0 ATT0 D1 DIF0 DEM0 0 ATT1 ATT1 D0 RSTN SMUTE 0 ATT0 ATT0 D5 0 SLOW DCKS ATT5 ATT5 D4 0 DFS1 DCKB ATT4 ATT4 D3 DIF2 DFS0 0 ATT3 ATT3 D2 DIF1 DEM1 DZFB ATT2 ATT2 : Changing points from AK4394’s register. Italic means the default value differs from AK4394. Addr 00H 01H 02H 03H 04H Register Name Control 1 Control 2 Control 3 Lch ATT Control Rch ATT Control D7 ACKS DZFE D/P ATT7 ATT7 D6 D5 D4 D3 D2 0 0 0 DIF2 DIF1 DZFM SLOW DFS1 DFS0 DEM1 DSDM DCKS DCKB 0 DZFB ATT6 ATT5 ATT4 ATT3 ATT2 ATT6 ATT5 ATT4 ATT3 ATT2 : Changing points from AK4395’s register. Italic means the default value differs from AK4395. MS0336-J-00 2004/08 -5- ASAHI KASEI No. Pin Name [AK4396] I/O 1 2 3 DVSS DVDD MCLK I 4 PDN I BICK DCLK SDATA DSDL LRCK DSDR I I I I I I SMUTE I CSN DFS0 CAD0 DEM0 CCLK DEM1 CDTI DIF0 DCLK DIF1 DSDL DIF2 DSDR I I I I I I I I I I I I I 5 6 7 8 9 10 11 12 13 14 Function Digital Ground Pin Digital Power Supply Pin, 3.3V or 5.0V Master Clock Input Pin Power-Down Mode Pin When at “L”, the AK4396 is in power-down mode and is held in reset. The AK4396 should always be reset upon power-up. Audio Serial Data Clock Pin in PCM mode DSD Clock Pin in DSD mode Audio Serial Data Input Pin in PCM mode DSD Lch Data Input Pin in DSD mode L/R Clock Pin in PCM mode DSD Rch Data Input Pin in DSD mode Soft Mute Pin in parallel mode When this pin goes “H”, soft mute cycle is initiated. When returning “L”, the output mute releases. Chip Select Pin in serial mode Sampling Speed Mode Select Pin in parallel mode (Internal pull-down pin) Chip Address 0 Pin in serial mode (Internal pull-down pin) De-emphasis Enable 0 Pin in parallel mode Control Data Clock Pin in serial mode De-emphasis Enable 1 Pin in parallel mode Control Data Input Pin in serial mode Digital Input Format 0 Pin in PCM mode DSD Clock Pin in DSD mode Digital Input Format 1 Pin in PCM mode DSD Lch Data Input Pin in DSD mode Digital Input Format 2 Pin in PCM mode DSD Rch Data Input Pin in DSD mode Note: All input pins except internal pull-up/down pins should not be left floating. MS0336-J-00 2004/08 -6- ASAHI KASEI [AK4396] 15 TTL I 16 17 18 19 20 21 22 23 24 VREFL VREFH AVDD AVSS AOUTR− AOUTR+ AOUTL− AOUTL+ VCOM I I O O O O O 25 P/S I TST1 DZFL TST2 CAD1 ACKS DZFR O O I I I O 26 27 28 CMOS/TTL Level Select Pin (Internal pull-up pin) “L”: CMOS Level, “H”: TTL Level Low Level Voltage Reference Input Pin High Level Voltage Reference Input Pin Analog Power Supply Pin, 5.0V Analog Ground Pin Rch Negative Analog Output Pin Rch Positive Analog Output Pin Lch Negative Analog Output Pin Lch Positive Analog Output Pin Common Voltage Output Pin, AVDD/2 Parallel/Serial Select Pin (Internal pull-up pin) “L”: Serial Mode, “H”: Parallel Mode Test 1 Pin in parallel mode (Don’t Care) Lch Zero Input Detect Pin in serial mode Test 2 Pin in parallel mode (Internal pull-down pin) Chip Address 1 Pin in serial mode (Internal pull-down pin) Master Clock Auto Setting Mode Pin in parallel mode Rch Zero Input Detect Pin in serial mode Note: All input pins except internal pull-up/down pins should not be left floating. Note: TST1 pinHi-Z MS0336-J-00 2004/08 -7- ASAHI KASEI [AK4396] (1) (PCM ) AOUTL+, AOUTL− AOUTR+, AOUTR− SMUTE TST1 TST2 Analog Digital DVSS DVSS (2) 1. PCM AOUTL+, AOUTL− AOUTR+, AOUTR− DIF2, DIF1, DIF0 DZFL, DZFR Analog Digital DVSS 2. DSD #5, #6, #7 DCLK, DSDL, DSDR Analog Digital AOUTL+, AOUTL− AOUTR+, AOUTR− DCLK(#12), DSDL(#13), DSDR(#14) DZFL, DZFR DVSS #12, #13, #14DCLK, DSDL, DSDR Analog Digital AOUTL+, AOUTL− AOUTR+, AOUTR− DCLK(#5), DSDL(#6), DSDR(#7) DZFL, DZFR MS0336-J-00 DVSS 2004/08 -8- ASAHI KASEI (AVSS, DVSS=0V; Note 1) Parameter Power Supplies: Analog Digital |AVSS − DVSS| [AK4396] (Note 2) Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Temperature (Power applied) Storage Temperature Symbol AVDD DVDD ΔGND IIN VIND Ta Tstg min −0.3 −0.3 −0.3 −40 −65 max 6.0 6.0 0.3 ±10 DVDD+0.3 85 150 Units V V V max 5.25 5.25 AVDD AVDD Units V V V V V mA V °C °C Note 1. Note 2. AVSS, DVSS : (AVSS, DVSS=0V; Note 1) Parameter Power Supplies Analog (Note 3) Digital Voltage Reference “H” voltage reference (Note 4) “L” voltage reference VREFH − VREFL Symbol AVDD DVDD VREFH VREFL ΔVREF min 4.75 3.0 AVDD−0.5 AVSS 3.0 typ 5.0 5.0 - Note 1. Note 3. AVDD DVDD Note 4. (VREFH − VREFL) AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.8Vpp × (VREFH − VREFL)/5. : MS0336-J-00 2004/08 -9- ASAHI KASEI [AK4396] (Ta=25°C; AVDD=DVDD=5.0V; AVSS=DVSS=0V; VREFH=AVDD, VREFL=AVSS; Input data = 24bit; RL ≥ 1kΩ; BICK=64fs; Signal Frequency = 1kHz; Sampling Frequency = 44.1kHz; Measurement bandwidth = 20Hz ~ 20kHz; External Circuit: Figure 17; unless otherwise specified.) Parameter min typ max Units Resolution 24 Bits Dynamic Characteristics (Note 5) 0dBFS −100 -90 dB fs=44.1kHz THD+N BW=20kHz −60dBFS −57 dB 0dBFS −97 dB fs=96kHz BW=40kHz −60dBFS −54 dB 0dBFS −97 dB fs=192kHz BW=40kHz −60dBFS −54 dB BW=80kHz −51 dB −60dBFS Dynamic Range (−60dBFS with A-weighted) (Note 6) 114 120 dB S/N (A-weighted) (Note 7) 114 120 dB Interchannel Isolation (1kHz) 100 120 dB DC Accuracy Interchannel Gain Mismatch 0.15 0.3 dB Gain Drift (Note 8) 20 ppm/°C Output Voltage (Note 9) ±2.65 ±2.8 ±2.95 Vpp Load Capacitance 25 pF Load Resistance (Note 10) 1 kΩ Power Supplies Power Supply Current Normal operation (PDN pin = “H”) AVDD DVDD (fs ≤ 96kHz) DVDD (fs = 192kHz) Power down (PDN pin = “L”) AVDD+DVDD Power Supply Rejection (Note 11) 32 8 13 47 19 mA mA mA 10 50 100 μA dB (Note 12) (Note 13) Note 5. Audio Precision System Two Note 6. Figure 17 ( 2) 101dB at 16bit data and 118dB at 20bit data. Note 7. Figure 17 ( 2) S/N Note 8. (VREFH − VREFL) +5V Note 9. (0dB) (VREFH − VREFL) AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.8Vpp × (VREFH − VREFL)/5. Note 10. ACDC 1.5k Note 11. DVDD=3.3V typ. 5mA ( @ fs ≤ 96kHz), typ. 8mA (@ fs = 192kHz) Note 12. P/S pin = TTL pin = DVDD (MCLK, BICK, LRCK) DVSS Note 13. VREFH pin +5V AVDD, DVDD 1kHz, 100mVpp MS0336-J-00 2004/08 - 10 - ASAHI KASEI [AK4396] (fs = 44.1kHz) (Ta=25°C; AVDD=4.75 ∼ 5.25V, DVDD=3.0 ∼ 5.25V; Normal Speed Mode; DEM=OFF; SLOW bit=“0”) Parameter Symbol min typ max Digital Filter Passband (Note 14) ±0.01dB PB 0 20.0 −6.0dB 22.05 Stopband (Note 14) SB 24.1 Passband Ripple PR ±0.005 Stopband Attenuation SA 75 Group Delay (Note 15) GD 28 Digital Filter + SCF Frequency Response: 0 ∼ 20.0kHz ±0.2 - (fs = 96kHz) (Ta=25°C; AVDD=4.75 ∼ 5.25V, DVDD=3.0 ∼ 5.25V; Double Speed Mode; DEM=OFF; SLOW bit=“0”) Parameter Symbol min typ max Digital Filter Passband (Note 14) ±0.01dB PB 0 43.5 −6.0dB 48.0 Stopband (Note 14) SB 52.5 Passband Ripple PR ±0.005 Stopband Attenuation SA 75 Group Delay (Note 15) GD 28 Digital Filter + SCF Frequency Response: 0 ∼ 40.0kHz ±0.3 - (fs = 192kHz) (Ta=25°C; AVDD=4.75 ∼ 5.25V, DVDD=3.0 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SLOW bit=“0”) Parameter Symbol min typ max Digital Filter Passband (Note 14) ±0.01dB PB 0 87.0 −6.0dB 96.0 Stopband (Note 14) SB 105 Passband Ripple PR ±0.005 Stopband Attenuation SA 75 Group Delay (Note 15) GD 28 Digital Filter + SCF Frequency Response: 0 ∼ 80.0kHz +0/−1 Note 14. fs( ) Units kHz kHz kHz dB dB 1/fs dB Units kHz kHz kHz dB dB 1/fs dB Units kHz kHz kHz dB dB 1/fs dB PB = 0.4535 × fs(@±0.01dB) SB = 0.546 × fs Note 15. 16/20/24 MS0336-J-00 2004/08 - 11 - ASAHI KASEI [AK4396] (fs = 44.1kHz) (Ta=25°C; AVDD=4.75 ∼ 5.25V, DVDD=3.0 ∼ 5.25V; Normal Speed Mode; DEM=OFF; SLOW bit=“1”) Parameter Symbol min typ max Digital Filter Passband (Note 16) ±0.04dB PB 0 8.1 −3.0dB 18.2 Stopband (Note 16) SB 39.2 Passband Ripple PR ±0.005 Stopband Attenuation SA 72 Group Delay (Note 15) GD 28 Digital Filter + SCF Frequency Response: 0 ∼ 20.0kHz +0/−5 - (fs = 96kHz) (Ta=25°C; AVDD=4.75 ∼ 5.25V, DVDD=3.0 ∼ 5.25V; DEM=OFF; SLOW bit=“1”) Parameter Symbol min typ Digital Filter Passband (Note 16) ±0.04dB PB 0 −3.0dB 39.6 Stopband (Note 16) SB 85.3 Passband Ripple PR Stopband Attenuation SA 72 Group Delay (Note 15) GD 28 Digital Filter + SCF Frequency Response: 0 ∼ 40.0kHz +0/−4 fs( ) kHz kHz kHz dB dB 1/fs dB max Units 17.7 - - kHz kHz kHz dB dB 1/fs - dB ±0.005 (fs = 192kHz) (Ta=25°C; AVDD=4.75 ∼ 5.25V, DVDD=3.0 ∼ 5.25V; Quad Speed Mode; DEM=OFF; SLOW bit=“1”) Parameter Symbol min typ max Digital Filter Passband (Note 16) ±0.04dB PB 0 35.5 −3.0dB 79.1 Stopband (Note 16) SB 171 Passband Ripple PR ±0.005 Stopband Attenuation SA 72 Group Delay (Note 15) GD 28 Digital Filter + SCF Frequency Response: 0 ∼ 80.0kHz +0/−5 Note 16. Units Units kHz kHz kHz dB dB 1/fs dB PB = 0.185 × fs(@±0.04dB) SB = 0.888 × fs MS0336-J-00 2004/08 - 12 - ASAHI KASEI [AK4396] DC (CMOS Level Mode) (Ta=25°C; AVDD=4.75 ∼ 5.25V, DVDD=3.0 ∼ 5.25V, TTL pin=“L”) Parameter Symbol min High-Level Input Voltage VIH 70%DVDD Low-Level Input Voltage VIL High-Level Output Voltage (Iout=−100μA) VOH DVDD−0.5 Low-Level Output Voltage (Iout=100μA) VOL Input Leakage Current (Note 17) Iin - typ - max 30%DVDD 0.5 ±10 Units V V V V μA DC (TTL Level Mode) (Ta=25°C; AVDD=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V; TTL pin=“H”) Parameter Symbol min High-Level Input Voltage (TTL pin) VIH 70%DVDD (All pins except TTL pin) VIH 2.2 Low-Level Input Voltage (TTL pin) VIL (All pins except TTL pin) VIL High-Level Output Voltage (Iout=−100μA) VOH DVDD−0.5 Low-Level Output Voltage (Iout=100μA) VOL Input Leakage Current (Note 17) Iin - typ - max 30%DVDD 0.8 0.5 ±10 Units V V V V V V μA Note 17. DFS0, TTL, P/S, TST2 pin (typ. 100kΩ) MS0336-J-00 2004/08 - 13 - ASAHI KASEI [AK4396] (Ta=25°C; AVDD=4.75 ∼ 5.25V, DVDD=3.0 ∼ 5.25V) Parameter Symbol Master Clock Timing Frequency fCLK Duty Cycle dCLK LRCK Frequency (Note 18) Normal Speed Mode fsn Double Speed Mode fsd Quad Speed Mode fsq Duty Cycle Duty PCM Audio Interface Timing BICK Period tBCK Normal Speed Mode tBCK Double Speed Mode tBCK Quad Speed Mode tBCKL BICK Pulse Width Low tBCKH BICK Pulse Width High tBLR BICK “↑” to LRCK Edge (Note 19) tLRB LRCK Edge to BICK “↑” (Note 19) tSDH SDATA Hold Time tSDS SDATA Setup Time DSD Audio Interface Timing DCLK Period DCLK Pulse Width Low DCLK Pulse Width High DCLK Edge to DSDL/R (Note 20) Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN High Time CSN “↓” to CCLK “↑” CCLK “↑” to CSN “↑” Reset Timing PDN Pulse Width Note 18. Note 19. Note 20. Note 21. RSTN bit 2 LRCK PDN pin “L” (Note 21) min typ max Units 7.7 40 41.472 60 MHz % 30 54 108 45 54 108 216 55 kHz kHz kHz % 1/128fsn 1/64fsd 1/64fsq 30 30 20 20 20 20 ns ns ns ns ns ns ns ns ns tDCK tDCKL tDCKH tDDD 1/64fs 160 160 −20 ns ns ns ns tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 200 80 80 50 50 150 50 50 ns ns ns ns ns ns ns ns tPD 150 ns 4 PDN pin 20 RSTN bit BICK “↑” “H” DFS1-0 bit MS0336-J-00 2004/08 - 14 - ASAHI KASEI [AK4396] 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDS tSDH VIH SDATA VIL Audio Interface Timing (PCM Mode) MS0336-J-00 2004/08 - 15 - ASAHI KASEI [AK4396] tDCK tDCKL tDCKH VIH DCLK VIL tDDD VIH DSDL DSDR VIL Audio Serial Interface Timing (DSD Normal Mode, DCKB bit = “0”) tDCK tDCKL tDCKH VIH DCLK VIL tDDD tDDD VIH DSDL DSDR VIL Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”) VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS CDTI C1 tCDH C0 R/W A4 VIH VIL WRITE Command Input Timing MS0336-J-00 2004/08 - 16 - ASAHI KASEI [AK4396] tCSW VIH CSN VIL tCSH VIH CCLK CDTI VIL D3 D2 D1 D0 VIH VIL WRITE Data Input Timing tPD PDN VIL Power Down & Reset Timing MS0336-J-00 2004/08 - 17 - ASAHI KASEI [AK4396] D/A AK4396 PCMDSD DSDRDSD D/P bit 2 ~ 3/fs D/A PCM DSDDCLK, DSDL, BICK, LRCK, SDATA PCM D/P bit PCM/DSDRSTN bit D/P bit Interface 0 PCM 1 DSD Table 1. PCM/DSD Mode Control [1] PCM AK4396MCLK, BICK, LRCK MCLK LRCK MCLKΔΣ PDN pin RSTN bit (PDN pin = “H”) (MCLK, BICK, LRCK) (PDN pin = “L”) “0”)ON(PDN pin = “L” → “H”) (RSTN bit = MCLK (1) (P/S pin = “H”) 1. Manual Setting Mode (ACKS pin = “L”) MCLK MCLK pinPDN pin DFS0 pin( Table 2) “0”DFS0 Table 3DFS1 bit 4 DFS0 pin Sampling Rate (fs) L Normal Speed Mode 30kHz ∼ 54kHz H Double Speed Mode 54kHz ∼ 108kHz Table 2. Sampling Speed (Manual Setting Mode @Parallel Mode) LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 128fs N/A N/A N/A 11.2896 12.2880 MCLK (MHz) 192fs 256fs 384fs 512fs 768fs 1152fs N/A 8.1920 12.2880 16.3840 24.5760 36.8640 N/A 11.2896 16.9344 22.5792 33.8688 N/A N/A 12.2880 18.4320 24.5760 36.8640 N/A 16.9344 22.5792 33.8688 N/A N/A N/A 18.4320 24.5760 36.8640 N/A N/A N/A Table 3. System Clock Example (Manual Setting Mode @Parallel Mode) MS0336-J-00 BICK 64fs 2.0480MHz 2.8224MHz 3.0720MHz 5.6448MHz 6.1440MHz 2004/08 - 18 - ASAHI KASEI [AK4396] 2. Auto Setting Mode (ACKS pin = “H”) MCLK( MCLK Table 4) DFS0 pin Table 5DFS0 pin DVSSDVDD MCLK 1152fs Sampling Speed Normal (fs≤32kHz) 512fs 768fs Normal 256fs 384fs Double 128fs 192fs Quad Table 4. Sampling Speed (Auto Setting Mode @Parallel Mode) LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz 128fs N/A N/A N/A N/A N/A 22.5792 24.5760 MCLK (MHz) 192fs 256fs 384fs 512fs 768fs 1152fs N/A N/A N/A 16.3840 24.5760 36.8640 N/A N/A N/A 22.5792 33.8688 N/A N/A N/A N/A 24.5760 36.8640 N/A N/A 22.5792 33.8688 N/A N/A N/A N/A 24.5760 36.8640 N/A N/A N/A 33.8688 N/A N/A N/A N/A N/A 36.8640 N/A N/A N/A N/A N/A Table 5. System Clock Example (Auto Setting Mode @Parallel Mode) Sampling Speed Normal Double Quad (2) (P/S pin = “L”) 1. Manual Setting Mode (ACKS bit = “0”) MCLKDFS1-0 bit MCLK Table 7 → “H”) Manual Setting Mode ( Table 6) (PDN pin = “L” DFS1-0 bitRSTN bit DFS1 bit DFS0 bit Sampling Rate (fs) Default 0 0 Normal Speed Mode 30kHz ∼ 54kHz 0 1 Double Speed Mode 54kHz ∼ 108kHz 1 0 Quad Speed Mode 120kHz ∼ 216kHz Table 6. Sampling Speed (Manual Setting Mode @Serial Mode) LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz 128fs N/A N/A N/A 11.2896 12.2880 22.5792 24.5760 MCLK (MHz) 192fs 256fs 384fs 512fs 768fs 1152fs N/A 8.1920 12.2880 16.3840 24.5760 36.8640 N/A 11.2896 16.9344 22.5792 33.8688 N/A N/A 12.2880 18.4320 24.5760 36.8640 N/A 16.9344 22.5792 33.8688 N/A N/A N/A 18.4320 24.5760 36.8640 N/A N/A N/A 33.8688 N/A N/A N/A N/A N/A 36.8640 N/A N/A N/A N/A N/A Table 7. System Clock Example (Manual Setting Mode @Serial Mode) MS0336-J-00 BICK 64fs 2.0480MHz 2.8224MHz 3.0720MHz 5.6448MHz 6.1440MHz 11.2896MHz 12.2880MHz 2004/08 - 19 - ASAHI KASEI [AK4396] 2. Auto Setting Mode (ACKS bit = “1”) MCLK( MCLK Table 8)DFS1-0 bit Table 9 MCLK 1152fs Sampling Speed Normal (fs≤32kHz) 512fs 768fs Normal 256fs 384fs Double 128fs 192fs Quad Table 8. Sampling Speed (Auto Setting Mode @Serial Mode) LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz 128fs N/A N/A N/A N/A N/A 22.5792 24.5760 MCLK (MHz) 192fs 256fs 384fs 512fs 768fs 1152fs N/A N/A N/A 16.3840 24.5760 36.8640 N/A N/A N/A 22.5792 33.8688 N/A N/A N/A N/A 24.5760 36.8640 N/A N/A 22.5792 33.8688 N/A N/A N/A N/A 24.5760 36.8640 N/A N/A N/A 33.8688 N/A N/A N/A N/A N/A 36.8640 N/A N/A N/A N/A N/A Table 9. System Clock Example (Auto Setting Mode @Serial Mode) Sampling Speed Normal Double Quad [2] DSD MCLK, DCLK MCLKDCKS bit (PDN pin = “H”) (PDN pin = “L”) (PDN pin = “L” MCLK DCLK (MCLK, DCLK) ON → “H”) MCLK DCKS bit 0 1 MCLK Frequency DCLK Frequency 512fs 64fs 768fs 64fs Table 10. System Clock (DSD Mode) MS0336-J-00 Default 2004/08 - 20 - ASAHI KASEI [AK4396] [1] PCM BICK DIF2-0 pin 2’sBICK 20LSB Mode 0 1 2 3 4 LRCK SDATA 5 DIF2-0 bitMSB ( Table 11) Mode 2 16 “0” DIF2 0 0 0 0 1 DIF1 0 0 1 1 0 DIF0 Input Format BICK 0 16bit ≥ 32fs 1 20bit ≥ 48fs 0 24bit ≥ 48fs 1 24bit I2S ≥ 48fs 0 24bit ≥ 48fs Table 11. Audio Interface Format Figure Figure 1 Figure 2 Figure 3 Figure 4 Figure 2 Default LRCK 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 BICK (32fs) SDATA Mode 0 15 0 14 6 1 5 14 4 15 3 2 16 17 1 0 31 15 0 14 6 5 14 1 4 15 3 16 2 17 1 0 31 15 14 0 1 0 1 BICK (64fs) SDATA Mode 0 Don’t care 15 14 Don’t care 0 15 14 0 15:MSB, 0:LSB Lch Data Rch Data Figure 1. Mode 0 Timing LRCK 0 1 8 9 10 11 12 31 0 1 8 9 10 11 12 31 BICK (64fs) SDATA Mode 1 Don’t care 19 0 Don’t care 19 0 Don’t care 19 0 19 0 19:MSB, 0:LSB SDATA Mode 4 Don’t care 23 22 21 20 23 22 21 20 23:MSB, 0:LSB Lch Data Rch Data Figure 2. Mode 1, 4 Timing MS0336-J-00 2004/08 - 21 - ASAHI KASEI [AK4396] LRCK 0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 0 1 BICK (64fs) SDATA 23 22 1 0 Don’t care 23 22 0 1 Don’t care 23 22 0 1 23:MSB, 0:LSB Lch Data Rch Data Figure 3. Mode 2 Timing LRCK 0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 BICK (64fs) SDATA 1 23 22 0 Don’t care 23 22 1 0 Don’t care 23 23:MSB, 0:LSB Lch Data Rch Data Figure 4. Mode 3 Timing [2] DSD DSD DCKB bit DIF2-0 pinDIF2-0 bit DCLK64fs DCLK DCLK (64fs) DCKB=1 DCLK (64fs) DCKB=0 DSDL,DSDR Normal D0 DSDL,DSDR Phase Modulation D0 D1 D1 D2 D1 D2 D3 D2 D3 Figure 5. DSD Mode Timing MS0336-J-00 2004/08 - 22 - ASAHI KASEI [AK4396] D/A RSTN bit ≥4/fs D/A Mode PCM Mode DSD Mode ≥0 D/A Data PCM Data DSD Data Figure 6. D/A Mode Switching Timing (PCM to DSD) RSTN bit D/A Mode DSD Mode PCM Mode ≥4/fs D/A Data DSD Data PCM Data Figure 7. D/A Mode Switching Timing (DSD to PCM) Note. DSD25% DSD 75% SACD(Scarlet Book) IIR3 (32kHz, 44.1kHz, 48kHz) 4OFF DSD 2 bitPCM (50/15μ s ) DSDDEM1-0 DEM1 DEM0 Mode 0 0 44.1kHz 0 1 OFF Default 1 0 48kHz 1 1 32kHz Table 12. De-emphasis Control (Normal Speed Mode) AK4396 DAC MUTE 256(ATT) − 0dB 48dB 1 256 Table 13 Sampling Speed 1 Level 255 to 0 Normal Speed Mode 4LRCK 1020LRCK Double Speed Mode 8LRCK 2040LRCK Quad Speed Mode 16LRCK 4080LRCK Table 13. ATT Transition Time MS0336-J-00 2004/08 - 23 - ASAHI KASEI [AK4396] AK43968192 “0” DZF pin“H” “0” DZF pin “L” RSTN bit “0”DZF pin “1”“0”DZF pin “L” DZFM bit “1”8192“0” DZF pin “H”DZFE bit pin“L” DZF pin DZFB bit “H” RSTN bit ∼ 5LRCK 4 DZF ATTATT × ATT(Table 13) SMUTE pin“L” SMUTE bit “0”−∞ ATT ATT SMUTE pin −∞ −∞ −∞ “H”SMUTE bit (“0”) ATT “1” × ATT SM U T E pin or SM U T E bit (1) (1) AT T _Level (3) Attenuation -∞ GD (2) GD (2) AO U T (4) 8192/fs D Z F pin (1) ATT × ATT 1020LRCK (2) (GD) (3) −∞ ATT (4) (Table 13) 8192 “0” Normal Speed Mode “0”DZF pin DZF pin ATT “255” “H” “L” Figure 8. Soft Mute Function ON PDN pin“L” MCLK MCLK4/fs MS0336-J-00 2004/08 - 24 - ASAHI KASEI [AK4396] PDN pin Figure 9 “L”(Hi-Z) PDN Internal State Normal Operation Power-down D/A In (Digital) Normal Operation “0” data GD D/A Out (Analog) (1) GD (3) (2) (3) (1) (4) Clock In Don’t care MCLK, BICK, LRCK DZFL/DZFR External MUTE (1) (GD) (2) Hi-Z (3) PDN(“ (6) (5) Mute ON ↓ ↑”) “0” (4) (PDN pin = “L”) (MCLK, BICK, LRCK) (5) (3) (6) (PDN pin = “L”) DZF pin “L” Æ “H”)AOUT pin (PDN pin: “L” (VA/2) VCOM pin C = 10 μF 1 τ (typ) = 10μF x 0.75kΩ = 7.5ms, 5τ (typ) = 37.5ms 1 τ (max) = 10μF x 0.975kΩ = 9.75ms, 5τ (max) = 48.75ms Figure 9. Power-down/up sequence example MS0336-J-00 2004/08 - 25 - ASAHI KASEI [AK4396] RSTN bit “0”DAC VCOM DZFL/DZFR pin “H” Figure 10RSTN bit RSTN bit 3~4/fs (6) 2~3/fs (6) Internal RSTN Timing Internal State Normal Operation Normal Operation Digital Block P D/A In (Digital) d “0” data (1) GD GD (3) D/A Out (Analog) (2) (3) (1) (4) Clock In Don’t care MCLK, BICK, LRCK 2/fs(5) DZFL/DZFR (1) (GD) (2) RSTN bit = “0”VCOM (3) RSTN (“ (AVDD/2) ↓ ↑”)“0” (4) (RSTN bit = “0”)(MCLK, BICK, LRCK) (5) DZF pin RSTN bit “H”LSI “L” (6) RSTN bit LSIRSTN bit 2 ~ 3/fs RSTN bit2/fs 3 ~ 4/fs Figure 10. Reset sequence example MS0336-J-00 2004/08 - 26 - ASAHI KASEI [AK4396] AK4396( P/S pin ) ( ) PDN pinAK4396 P/S pin “L” 3 I/F : CSN, CCLK, CDTI I/F Chip address (2bit, C1/0), Read/Write (1bit, “1”, Write only), Register address (MSB first, 5bit) Control data (MSB first, 8bit)CCLK “↓” “ ↑”CSN “↑” CCLK 5MHz (max) Function Parallel mode Serial mode Auto Setting Mode O O Manual Setting Mode O O Audio Format O O De-emphasis O O SMUTE O O DSD Mode X O Zero Detection X O Slow roll-off response X O Digital Attenuator X O Table 14. Function List (O: Available, X: Not available) PDN pin“L” RSTN bit “0” CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1-C0: Chip Address (C1=CAD1, C0=CAD0) R/W: READ/WRITE (Fixed to “1”, Write only) A4-A0: Register Address D7-D0: Control Data Figure 11. Control I/F Timing *AK4396 *PDN pin = “L” *CSN “L”CCLK “↑”1517 MS0336-J-00 2004/08 - 27 - ASAHI KASEI [AK4396] Addr 00H 01H 02H 03H 04H Register Name Control 1 Control 2 Control 3 Lch ATT Rch ATT D7 ACKS DZFE D/P ATT7 ATT7 D6 0 DZFM DSDM ATT6 ATT6 D5 0 SLOW DCKS ATT5 ATT5 D4 0 DFS1 DCKB ATT4 ATT4 D3 DIF2 DFS0 0 ATT3 ATT3 D2 DIF1 DEM1 DZFB ATT2 ATT2 D1 DIF0 DEM0 0 ATT1 ATT1 D0 RSTN SMUTE 0 ATT0 ATT0 Note. 05H ∼ 1FH Note. PDN pin “L” Note. RSTN bit “0” Note. P/S pin PDN pinAK4396 Addr Register Name 00H Control 1 Default D7 ACKS 0 D6 0 0 D5 0 0 D4 0 0 D3 DIF2 0 D2 DIF1 1 D1 DIF0 0 D0 RSTN 1 RSTN: Internal Timing Reset 0 : Reset. 1 : Normal operation (Default) “0” DIF2-0: Audio Data Interface Modes (Table 11) “010” (Mode2 : 24bit ) ACKS: Master Clock Frequency Auto Setting Mode Enable (PCM only) 0 : Disable : Manual setting mode (Default) 1 : Enable : Auto setting mode ACKS bit “1”MCLK MS0336-J-00 2004/08 - 28 - ASAHI KASEI Addr Register Name 01H Control 2 Default [AK4396] D7 DZFE 0 D6 DZFM 0 D5 SLOW 0 D4 DFS1 0 D3 DFS0 0 D2 DEM1 0 D1 DEM0 1 D0 SMUTE 0 SMUTE: Soft Mute Enable 0 : Normal operation (Default) 1 : DAC outputs soft-muted. DEM1-0: De-emphasis response (Table 12) “01” (OFF) DFS1-0: Sampling Speed Control (Table 6) “00” (Normal speed) DFS1-0 bit SLOW: Slow Roll-off Filter Enable 0 : Sharp roll-off filter (Default) 1 : Slow roll-off filter DZFM: Data Zero Detect Mode 0 : Channel separated mode (Default) 1 : Channel ANDed mode DZFM bit “1”8192 DZF pin “H” DZFE: “0” Data Zero Detect Enable 0 : Disable (Default) 1 : Enable DZFE bit DZF pin MS0336-J-00 “L” 2004/08 - 29 - ASAHI KASEI Addr Register Name 02H Control 3 Default [AK4396] D7 D/P 0 DZFB: Inverting Enable of DZF 0 : DZF pin 1 : DZF pin D6 DSDM 0 D5 DCKS 0 D4 DCKB 0 D3 0 0 D2 DZFB 0 D1 0 0 D0 0 0 D4 ATT4 ATT4 1 D3 ATT3 ATT3 1 D2 ATT2 ATT2 1 D1 ATT1 ATT1 1 D0 ATT0 ATT0 1 “H”(Default) “L” DCKB: Polarity of DCLK (DSD Only) 0 : DSD data is output from DCLK falling edge. (Default) 1 : DSD data is output from DCLK rising edge. DCKS: Master Clock Frequency Select at DSD mode (DSD only) 0 : 512fs (Default) 1 : 768fs DSDM: DSD Input Select 0 : Input pin : No.5, 6, 7 (Default) 1 : Input pin : No. 12, 13, 14 DSDM bitRSTN bitAK4396 D/P: DSD/PCM Mode Select 0 : PCM mode (Default) 1 : DSD mode D/P bitRSTN bit Addr Register Name 03H Lch ATT 04H Rch ATT Default AK4396 D7 ATT7 ATT7 1 D6 ATT6 ATT6 1 D5 ATT5 ATT5 1 ATT7-0: Attenuation Level ATT = 20 log10 (ATT_DATA / 255) [dB] FFH : 0dB (Default) 00H : Mute MS0336-J-00 2004/08 - 30 - ASAHI KASEI [AK4396] Figure 12, Figure 13 Figure 14 Figure 16, Figure 17 Figure 18 (AKD4396) Digital Supply 3.3V 10u 0.1u + 1 DVSS DZFR 28 2 DVDD CAD1 27 Master Clock 3 MCLK DZFL 26 Reset & Power down 4 PDN P/S 25 64fs 5 BICK VCOM 24 24bit Audio Data 6 SDATA AOUTL+ 23 Lch Lch 7 LRCK AOUTL- 22 LPF Mute 8 CSN AOUTR+ 21 Micro- 9 CAD0 AOUTR- 20 Rch LPF Rch Mute controller 10 CCLK AVSS 11 CDTI AVDD 12 DIF0 VREFH 13 DIF1 VREFL 14 DIF2 TTL fs Digital Ground AK4396 0.1u 19 0.1u 18 10u + 17 0.1u 16 + 10u 10u + Lch Out Rch Out Analog Supply 5V 15 Analog Ground : - Chip Address = “00”. BICK = 64fs, LRCK = fs. - AVDDDVDD - AVSSDVSS - AOUT / Figure 12. Typical Connection Diagram (AVDD=5V, DVDD=3.3V, Serial mode) MS0336-J-00 2004/08 - 31 - ASAHI KASEI [AK4396] Digital Supply 3.3V 10u 0.1u + 1 DVSS ACKS 28 2 DVDD TST2 27 Master Clock 3 MCLK TST1 26 Reset & Power down 4 PDN P/S 25 64fs 5 BICK VCOM 24 24bit Audio Data 6 SDATA AOUTL+ 23 Lch AOUTL- 22 LPF Rch LPF fs Mode setting Digital Ground AK4396 7 LRCK 8 SMUTE AOUTR+ 21 9 DFS0 AOUTR- 20 10 DEM0 AVSS 11 DEM1 AVDD 12 DIF0 VREFH 13 DIF1 VREFL 14 DIF2 TTL 19 0.1u 18 17 0.1u 16 0.1u + 10u + Lch Out Rch Out 10u + 10u Analog Supply 5V 15 Analog Ground : - BICK = 64fs, LRCK = fs. - AVDDDVDD - AVSSDVSS - AOUT / Figure 13. Typical Connection Diagram (AVDD=5V, DVDD=3.3V, Parallel mode, AK4393 MS0336-J-00 ) 2004/08 - 32 - ASAHI KASEI [AK4396] Digital Supply 5.0V 10u 0.1u + 1 DVSS DZFR 28 2 DVDD CAD1 27 Master Clock 3 MCLK DZFL 26 Reset & Power down 4 PDN P/S 25 64fs 5 BICK VCOM 24 24bit Audio Data 6 SDATA AOUTL+ 23 Lch Lch Mute Rch Mute AK4396 0.1u 7 LRCK AOUTL- 22 LPF 8 CSN AOUTR+ 21 Micro- 9 CAD0 AOUTR- 20 Rch LPF controller 10 CCLK AVSS 11 CDTI AVDD 12 DIF0 VREFH 13 DIF1 VREFL 14 DIF2 TTL fs Digital Ground 19 0.1u 18 10u + 17 0.1u 16 + 10u 10u + Lch Out Rch Out Analog Supply 5V 15 Analog Ground : - Chip Address = “00”. BICK = 64fs, LRCK = fs. - TTL pin (AK4394/5BVSS pin) - AVDDDVDD - AVSSDVSS - AOUT / Figure 14. Typical Connection Diagram (AVDD=5V, DVDD=5V, Serial mode, AK4394/5 Digital Ground ) Analog Ground System Controller 1 DVSS DZFR 28 2 DVDD CAD1 27 3 MCLK DZFL 26 4 PDN P/S 25 5 BICK VCOM 24 6 SDATA AOUTL+ 23 7 LRCK AOUTL- 22 8 CSN AOUTR+ 21 9 CAD0 AOUTR- 20 10 CCLK AVSS 19 11 CDTI AVDD 18 12 DIF0 VREFH 17 13 DIF1 VREFR 16 14 DIF2 TTL 15 AK4396 Figure 15. Ground Layout MS0336-J-00 2004/08 - 33 - ASAHI KASEI [AK4396] 1. AK4396AVDD AVDD DVDD AVDDDVDD AVDDDVDD AK4396 DVDD AVSS DVSS 2. VREFH pin VREFL pinVREFH pin AVDD VREFL pinAVSS VCOM 10µF0.1µF VCOM pin AK4396VREFH/VREFL pin VREFH pin VREFL pin0.1µF AVSS 3. 2.8Vpp (typ, VREFH − VREFL = 5V) AOUT+, AOUT−V AOUT = (AOUT+)−(AOUT−) 5.6Vpp (typ, VREFH − VREFL = 5V) 2’s compliment (2 ) 7FFFFFH(@24bit) 800000H(@24bit) 000000H(@24bit) V AOUT0V VCOM ΔΣ ( Figure 161 ) (SCF) LPF LPF Figure 17 3 AK4396 AOUT- 2.4k 2.4k 150 680p +Vop AOUT+ 3.3n 2.4k 2.4k Analog Out 150 680p -Vop Figure 16. External LPF Circuit Example 1 for PCM (fc = 125kHz, Q=0.692) Frequency Response Gain 20kHz −0.012dB 40kHz −0.083dB 80kHz −0.799dB Table 15. Frequency Response of External LPF Circuit Example 1 for PCM MS0336-J-00 2004/08 - 34 - ASAHI KASEI [AK4396] +15 3.3n + 10k 330 180 0.1u 7 3 2 + 4 3.9n 6 NJM5534D + 10u 0.1u 620 620 3.3n + 100u 3.9n 100 6 Lch 1.0n NJM5534D 10u 6 NJM5534D 1.2k 330 2 - 4 + 3 7 0.1u 7 3 + 2 4 + 10k AOUTL+ 180 +10u 1.0n 1.2k 680 0.1u 560 560 100u AOUTL- + -15 10u 680 + 0.1u 10u + 10u 0.1u Figure 17. External LPF Circuit Example 2 for PCM 2nd Stage Total 1st Stage Cut-off Frequency 182kHz 284kHz Q 0.637 Gain +3.9dB -0.88dB +3.02dB 20kHz -0.025 -0.021 -0.046dB Frequency 40kHz -0.106 -0.085 -0.191dB Response 80kHz -0.517 -0.331 -0.848dB Table 16. Frequency Response of External LPF Circuit Example 2 for PCM MS0336-J-00 2004/08 - 35 - ASAHI KASEI SACD − 30dB/oct ( Figure 18) [AK4396] (Scarlet Book) SACD50kHz AK4396( Table 17) Frequency Gain 20kHz −0.4dB 50kHz −2.8dB 100kHz −15.5dB Table 17. Internal Filter Response at DSD mode 2.0k 1.8k 4.3k AOUT1.0k 270p 2.8Vpp 2200p +Vop 3300p 2.0k 1.8k 1.0k AOUT+ + 2.8Vpp 4.3k 270p Analog Out 6.34Vpp -Vop Figure 18. External 3rd order LPF Circuit Example for DSD Frequency Gain 20kHz −0.05dB 50kHz −0.51dB 100kHz −16.8dB DC gain = 1.07dB Table 16. 3rd order LPF (Figure 18) Response MS0336-J-00 2004/08 - 36 - ASAHI KASEI [AK4396] 28pin VSOP (Unit: mm ) *9.8±0.2 1.25±0.2 0.675 28 A 7.6±0.2 *5.6±0.2 15 14 1 0.65 0.22±0.1 +0.1 0.15-0.05 0.1±0.1 0.5±0.2 Detail A Seating Plane | 0.10 NOTE: Dimension "*" does not include mold flash. 0-10° Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate MS0336-J-00 2004/08 - 37 - ASAHI KASEI [AK4396] AKM AK4396VF XXXBYYYYC XXXBYYYC: Date code identifier XXXB: YYYYC: Date (YY/MM/DD) 04/08/31 Revision 00 Lot number (X : Digit number, B : Alpha character ) Assembly date (Y : Digit number, C : Alpha character) Reason Page Contents • • • • • • MS0336-J-00 2004/08 - 38 -