ASAHI KASEI [AK4348] AK4348 3.3V 192kHz 24-Bit 8-Channel DAC AK4348 +3.3V 8 24 8kHz DAC 192kHz (SCF) : ∆Σ 2 8kHz LPF 192kHz Slow roll-off 24 8 DR, S/N: 104dB THD+N: -90dB SCF 2 LPF (32kHz, 44.1kHz, 48kHz ) ATT ( 256 ) 2 µP I/F: 3 ,I C I/F : , (16/20/24bit), I2S, TDM : 256fs, 384fs, 512fs, 768fs or 1152fs 128fs, 192fs, 256fs or 384fs 2 128fs or 192fs 4 : 2.7 3.6V : Ta = −20 ∼ 85°C (EF), −40 ∼ 85°C (VF) 30pin VSOP AK4359 DZF Audio I/F LOUT1 LPF SCF DAC DATT ROUT1 LPF SCF DAC DATT LOUT2 LPF SCF DAC DATT ROUT2 LPF SCF DAC DATT LOUT3 LPF SCF DAC DATT ROUT3 LPF SCF DAC DATT LOUT4 LPF SCF DAC DATT ROUT4 LPF SCF DAC DATT MS0532-J-00 MCLK LRCK BICK SDTI1 SDTI2 SDTI3 SDTI4 PCM Control Register 3-wire or I2C AK4348 2006/07 -1- ASAHI KASEI [AK4348] -20 ∼ +85°C -40 ∼ +85°C AK4348EF AK4348VF AKD4348 30pin VSOP 30pin VSOP MCLK 1 30 DZF1 BICK 2 29 TDM0/DZF2 SDTI1 3 28 AVDD LRCK 4 27 AVSS RSTB 5 26 VCOM SMUTE/CSN/CAD0 6 25 LOUT1 ACKS/CCLK/SCL 7 24 ROUT1 DIF0/CDTI/SDA 8 23 P/S SDTI2 9 22 LOUT2 SDTI3 10 21 ROUT2 SDTI4 11 20 LOUT3 DIF1 12 19 ROUT3 DEM0/CAD1 13 18 LOUT4 DVDD 14 17 ROUT4 DVSS 15 16 DEM1/I2C AK4348 Top View Compatibility with AK4359 Function Power supply voltage #29 pin function in parallel control mode Chip address for 3-wire uP I/F Chip address for I2C uP I/F AK4359 4.5 to 5.5V “L” output AK4348 2.7 to 3.6V TDM0 pin (pull-down pin) N/A CAD0 CAD1 (CAD0 is fixed.) CAD0, CAD1 MS0532-J-00 2006/07 -2- ASAHI KASEI No. 1 Pin Name MCLK [AK4348] I/O I Function Master Clock Input An external TTL clock should be input on this pin. 2 BICK I Audio Serial Data Clock 3 SDTI1 I DAC1 Audio Serial Data Input 4 LRCK I L/R Clock 5 RSTB I Reset Mode When at “L”, the AK4348 is in reset mode. The AK4348 must be reset once upon power-up. 6 SMUTE I Soft Mute in parallel control mode “H”: Enable, “L”: Disable CSN I Chip Select in serial 3-wire mode CAD0 I Chip Address in serial I2C mode 7 ACKS I Auto Setting Mode in parallel control mode “L”: Manual Setting Mode, “H”: Auto Setting Mode CCLK I Control Data Clock in serial 3-wire control mode SCL Control Data Clock in serial I2C control mode 8 DIF0 I Audio Data Interface Format in parallel control mode CDTI I Control Data Input in serial 3-wire control mode SDA I/O Control Data in serial I2C control mode 9 SDTI2 I DAC2 Audio Serial Data Input 10 SDTI3 I DAC3 Audio Serial Data Input 11 SDTI4 I DAC4 Audio Serial Data Input 12 DIF1 I Audio Data Interface Format 13 CAD1 I Chip Address in serial control mode DEM0 I De-emphasis Filter Enable 14 DVDD Digital Power Supply, +2.7∼+3.6V 15 DVSS Digital Ground 16 I2C I µP I/F Mode Select in serial control mode “L”: 3-wire Serial, “H”: I2C Bus DEM1 I De-emphasis Filter Enable in parallel control mode 17 ROUT4 O DAC4 Right Channel Analog Output 18 LOUT4 O DAC4 Left Channel Analog Output 19 ROUT3 O DAC3 Right Channel Analog Output 20 LOUT3 O DAC3 Left Channel Analog Output 21 ROUT2 O DAC2 Right Channel Analog Output 22 LOUT2 O DAC2 Left Channel Analog Output 23 P/S I Parallel/Serial Control Mode Select (Internal pull-up pin) “L”: Serial control mode, “H”: Parallel control mode 24 ROUT1 O DAC1 Right Channel Analog Output 25 LOUT1 O DAC1 Left Channel Analog Output 26 VCOM O Common Voltage, AVDD/2 Normally connected to AVSS with a 0.1µF ceramic capacitor in parallel with a 10µF electrolytic cap. 27 AVSS Analog Ground 28 AVDD Analog Power Supply, +2.7∼+3.6V 29 TDM0 I TDM I/F Format Mode in parallel control mode (Internal pull-down pin) “L”: Normal mode, “H”: TDM 256 mode DZF2 O Data Zero Input Detect in serial control mode 30 DZF1 O Data Zero Input Detect Note: All input pins except P/S and TDM0 pins should not be left floating. MS0532-J-00 2006/07 -3- ASAHI KASEI Classificatio n Analog Digital [AK4348] Setting Pin Name LOUT4-1, ROUT4-1 DZF2-1 SDTI4-1 SMUTE (Parallel control mode) DEM0, DIF1 (Serial control mode) (AVSS, DVSS=0V; Note 1) Parameter Power Supplies Analog Digital |AVSS-DVSS| (Note 2) Input Current (any pins except for supplies) Analog Input Voltage Digital Input Voltage Ambient Operating Temperature AK4348EF AK4348VF Storage Temperature Leave open. Leave open. Connect to DVSS. Connect to DVDD or DVSS. Symbol AVDD DVDD ∆GND IIN VINA VIND Ta Ta Tstg Min -0.3 -0.3 -0.3 -0.3 -20 -40 -65 Max 4.6 4.6 0.3 ±10 AVDD+0.3 DVDD+0.3 85 85 150 Units V V V mA V V °C °C °C Max 3.6 3.6 Units V V Note 1. Note 2. AVSS DVSS : (AVSS, DVSS=0V; Note 1) Parameter Power Supplies Analog (Note 3) Digital Symbol AVDD DVDD Min 2.7 2.7 Typ 3.3 3.3 Note 3. AVDD DVDD : MS0532-J-00 2006/07 -4- ASAHI KASEI [AK4348] ( Ta = 25°C; AVDD,DVDD=3.3V; fs = 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥5kΩ) Parameter Min Typ Max Resolution 24 Dynamic Characteristics (Note 4) THD+N fs=44.1kHz 0dBFS -90 -80 BW=20kHz -60dBFS -40 fs=96kHz 0dBFS -86 BW=40kHz -60dBFS -37 fs=192kHz 0dBFS -86 BW=40kHz -60dBFS -37 Dynamic Range (-60dBFS with A-weighted) (Note 5) 96 104 S/N (A-weighted) (Note 6) 96 104 Interchannel Isolation (1kHz) 80 100 Interchannel Gain Mismatch 0.2 0.5 DC Accuracy Gain Drift 100 Output Voltage (Note 7) 2.09 2.24 2.39 Load Resistance (Note 8) 5 Load Capacitance 25 Power Supplies Power Supply Current (AVDD+DVDD) 45 72 Normal Operation (RSTB pin = “H”, fs≤96kHz) 52 78 Normal Operation (RSTB pin = “H”, fs=192kHz) 33 133 Reset Mode (RSTB pin = “L”) (Note 9) Note 4. Audio Precision (System Two) Note 5. 100dB when using 16bit data. Note 6. S/N Note 7. (0dB) AVDD AOUT (Typ.@0dB) = 2.24Vpp×AVDD/3.3 Note 8. AC Note 9. P/S pin DVDD (MCLK, BICK, LRCK) MS0532-J-00 Units Bits dB dB dB dB dB dB dB dB dB dB ppm/°C Vpp kΩ pF mA mA µA DVSS 2006/07 -5- ASAHI KASEI [AK4348] (Ta = 25°C; AVDD, DVDD = 2.7 ∼ 3.6V; fs = 44.1kHz; DEM = OFF; SLOW = “0”) Parameter Symbol Min Typ Digital filter PB 0 Passband ±0.05dB (Note 10) 22.05 -6.0dB Stopband (Note 10) SB 24.1 Passband Ripple PR Stopband Attenuation SA 54 Group Delay (Note 11) GD 19.3 Digital Filter + SCF Frequency Response 20.0kHz Fs=44.1kHz FR + 0.06/-0.10 40.0kHz Fs=96kHz FR + 0.06/-0.13 80.0kHz Fs=192kHz FR + 0.06/-0.51 Note 10. fs ( ) Max Units 20.0 - - kHz kHz kHz dB dB 1/fs - dB dB dB ± 0.02 PB=0.4535×fs(@±0.05dB) SB=0.546×fs Note 11. 16/24 (Ta = 25°C; AVDD, DVDD = 2.7~3.6V; fs = 44.1kHz; DEM = OFF; SLOW = “1”) Parameter Symbol Min Typ Max Units PB 0 39.2 18.2 8.1 - Digital Filter Passband ±0.04dB -3.0dB Stopband Passband Ripple Stopband Attenuation Group Delay (Note 12) (Note 12) (Note 11) SB PR SA GD 72 - 19.3 - kHz kHz kHz dB dB 1/fs - +0.1/-4.3 +0.1/-3.3 +0.1/-3.7 - dB dB dB ± 0.005 Digital Filter + SCF Frequency Response Note 12. 20.0kHz 40.0kHz 80.0kHz fs=44.kHz fs=96kHz fs=192kHz FR FR FR fs ( ) PB = 0.185×fs (@±0.04dB), SB = 0.888×fs. DC (Ta = 25°C; AVDD, DVDD = 2.7 ∼ 3.6V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Iout = -80µA) Low-Level Output Voltage (Iout = 80µA) Input Leakage Current (Note 13) Symbol VIH VIL VOH VOL Iin Min 70%DVDD DVDD-0.4 - Typ - Max 30%DVDD 0.4 ± 10 Units V V V V µA Note 13. P/S pin has an internal pull-up device and TDM0 pin has an internal pull-down device, nominally 100kΩ. MS0532-J-00 2006/07 -6- ASAHI KASEI [AK4348] (Ta = 25°C; AVDD, DVDD = 2.7 ∼ 3.6V; CL = 20pF) Parameter Master Clock Frequency Duty Cycle LRCK Frequency Normal Mode (TDM0= “0”, TDM1= “0”) Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle TDM256 mode (TDM0= “1”, TDM1= “0”) Normal Speed Mode High time Low time TDM128 mode (TDM0= “1”, TDM1= “1”) Normal Speed Mode Double Speed Mode High time Low time Audio Interface Timing BICK Period BICK Pulse Width Low Pulse Width High BICK “↑” to LRCK Edge (Note 14) LRCK Edge to BICK “↑” (Note 14) SDTI Hold Time SDTI Setup Time Control Interface Timing (3-wire Serial mode): CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN High Time CSN “↓” to CCLK “↑” CCLK “↑” to CSN “↑” Control Interface Timing (I2C Bus mode): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 15) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter Capacitive load on bus Reset Timing RSTB Pulse Width (Note 16) MS0532-J-00 Symbol fCLK dCLK Min 2.048 40 fsn fsd fsq Duty Typ 11.2896 Max 36.864 60 Units MHz % 8 60 120 45 48 96 192 55 kHz kHz kHz % fsn tLRH tLRL 8 1/256fs 1/256fs 48 kHz ns ns fsn fsd tLRH tLRL 8 60 1/128fs 1/128fs 48 96 kHz kHz ns ns tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 81 30 30 20 20 10 10 ns ns ns ns ns ns ns tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 200 80 80 40 40 150 50 50 ns ns ns ns ns ns ns ns fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP Cb 1.3 0.6 1.3 0.6 0.6 0 0.1 0.6 0 - tRST 150 400 0.3 0.3 50 400 kHz µs µs µs µs µs µs µs µs µs µs ns pF ns 2006/07 -7- ASAHI KASEI [AK4348] Note 14. LRCK BICK Note 15. 300ns(SCL Note 16. RSTB pin “L” 2 Note 17. I C Philips Semiconductors “↑” ) 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDS tSDH VIH SDTI VIL Audio Serial Interface Timing MS0532-J-00 2006/07 -8- ASAHI KASEI [AK4348] VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS CDTI C1 tCDH C0 R/W VIH A4 VIL WRITE Command Input Timing tCSW VIH CSN VIL tCSH VIH CCLK VIL D3 CDTI D2 D1 VIH D0 VIL WRITE Data Input Timing VIH SDA VIL tLOW tBUF tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT tSU:STA tSU:STO Start Stop Start I2C Bus mode Timing tRST RSTB VIL Reset Timing MS0532-J-00 2006/07 -9- ASAHI KASEI [AK4348] MCLK, LRCK, BICK (MCLK) (LRCK) MCLK ∆Σ MCLK (Manual Setting Mode) (Auto Setting Mode) 2 Manual Setting Mode (ACKS bit = “0”: Register 00H) DFS0/1 bit (Table 1) MCLK (Table 2~Table 4) Auto Setting Mode (ACKS bit = “1”: Default) MCLK (Table 5) (Table 6) DFS0/1 bit Normal Speed Mode ACKS pin Double Speed Mode 128fs 192fs (RSTB pin = “H”) ACKS pin Auto Setting Mode “H” ACKS pin “L” (MCLK, BICK, LRCK) (RSTB pin = “L”) ON (RSTB = “↑”) MCLK DFS1 DFS0 Sampling Rate (fs) 0 0 Normal Speed Mode 8kHz~48kHz 0 1 Double Speed Mode 60kHz~96kHz 1 0 Quad Speed Mode Table 1. LRCK fs 32.0kHz 44.1kHz 48.0kHz 256fs 8.1920MHz 11.2896MHz 12.2880MHz LRCK fs 88.2kHz 96.0kHz 120kHz~192kHz (Manual Setting Mode) 384fs 12.2880MHz 16.9344MHz 18.4320MHz Table 2. MCLK 512fs 16.3840MHz 22.5792MHz 24.5760MHz 768fs 24.5760MHz 33.8688MHz 36.8640MHz (Normal Speed Mode 128fs 11.2896MHz 12.2880MHz Table 3. LRCK fs 176.4kHz 192.0kHz Table 4. Default MCLK 192fs 256fs 16.9344MHz 22.5792MHz 18.4320MHz 24.5760MHz (Double Speed Mode MCLK 128fs 192fs 22.5792MHz 33.8688MHz 24.5760MHz 36.8640MHz (Quad Speed Mode MS0532-J-00 1152fs 36.8640MHz N/A N/A BICK 64fs 2.0480MHz 2.8224MHz 3.0720MHz Manual Setting Mode) 384fs 33.8688MHz 36.8640MHz BICK 64fs 5.6448MHz 6.1440MHz Manual Setting Mode) BICK 64fs 11.2896MHz 12.2880MHz Manual Setting Mode) 2006/07 - 10 - ASAHI KASEI [AK4348] MCLK 1152fs 512fs 256fs 128fs Sampling Speed Normal (fs≤32kHz) Normal Double Quad 768fs 384fs 192fs Table 5. LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz 128fs 22.5792 24.5760 192fs 33.8688 36.8640 (Auto Setting Mode) 256fs 22.5792 24.5760 - MCLK (MHz) 384fs 512fs 16.3840 22.5792 24.5760 33.8688 36.8640 - Table 6. 768fs 24.5760 33.8688 36.8640 - 1152fs 36.8640 - Sampling Speed Normal Double Quad (Auto Setting Mode) MS0532-J-00 2006/07 - 11 - ASAHI KASEI [AK4348] (Table 7) TDM0 bit TDM0-1 bit MSB Mode 2 16/20 DIF0-1, TDM0 pin DIF0-1, 11 (Table 8) DIF0-2, Mode 2 (24bit MSB justified format in normal mode) DIF1 pin 2’s Complement BICK LSB “0” TDM0 pin “H” DAC(8ch) “H” “L” 1/256fs(min) BICK SDTI1 pin 256fs LRCK complement SDTI1 I/F TDM256 (Table 7) BICK 2’s SDTI2-4 MSB TDM0 bit “1” TDM1 bit “0” TDM256 (Table 8) SDTI1 pin DAC(8ch) SDTI2-4 BICK 256fs LRCK “H” “L” 1/256fs(min) MSB 2’s complement SDTI1 BICK TDM128 (TDM0 bit = “1”, TDM1 bit = “1”,Table 8) SDTI1 pin DAC (L1,R1,L2,R2) SDTI2 pin DAC (L3,R3,L4,R4) 4ch SDTI3-4 BICK 128fs Mode Normal TDM256 TDM0 L L L L H H H H 0 1 2 3 5 6 DIF1 L L H H L L H H DIF0 L H L H L H L H SDTI Format 16-bit LSB Justified 20-bit LSB Justified 24-bit MSB Justified 24-bit I2S Compatible N/A N/A 24-bit MSB Justified 24-bit I2S Compatible Table 7. Mode Normal 0 1 2 3 4 TDM256 5 6 7 TDM128 8 9 10 TDM1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 Table 8. TDM0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 LRCK H/L H/L H/L L/H BICK ≥32fs ≥40fs ≥48fs ≥48fs Figure Figure 1 Figure 2 Figure 3 Figure 4 ↑ ↓ 256fs 256fs Figure 5 Figure 6 (Parallel control mode) DIF2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 DIF1 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 DIF0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 SDTI Format 16-bit LSB Justified 20-bit LSB Justified 24-bit MSB Justified 24-bit I2S Compatible 24-bit LSB Justified N/A N/A 24-bit MSB Justified 24-bit I2S Compatible 24-bit LSB Justified N/A N/A 24-bit MSB Justified 24-bit I2S Compatible 24-bit LSB Justified LRCK H/L H/L H/L L/H H/L BICK ≥32fs ≥40fs ≥48fs ≥48fs ≥48fs Figure Figure 1 Figure 2 Figure 3 Figure 4 Figure 2 ↑ ↓ ↑ 256fs 256fs 256fs Figure 5 Figure 6 Figure 7 ↑ ↓ ↑ 128fs 128fs 128fs Figure 8 Figure 9 Figure 10 (Serial control mode, Default: Mode 2) MS0532-J-00 2006/07 - 12 - ASAHI KASEI [AK4348] LRCK 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 BICK (32fs) SDTI Mode 0 15 14 6 5 1 0 14 4 15 3 2 16 1 17 0 31 15 0 14 6 5 14 1 4 3 15 2 16 1 17 0 31 15 0 14 1 BICK (64fs) SDTI Mode 0 Don’t care 15 14 15 Don’t care 0 14 0 15:MSB, 0:LSB Lch Data Rch Data Figure 1. Mode 0 Timing LRCK 0 1 8 9 10 11 12 31 0 1 8 9 10 11 12 31 0 1 BICK (64fs) SDTI Mode 1 Don’t care 19 0 Don’t care 19 0 Don’t care 19 0 20 19 0 19:MSB, 0:LSB SDTI Mode 4 Don’t care 23 22 21 20 23 22 21 23:MSB, 0:LSB Lch Data Rch Data Figure 2. Mode 1,4 Timing LRCK 0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 0 1 BICK (64fs) SDTI 23 22 1 0 Don’t care 23 22 1 0 Don’t care 23 22 23:MSB, 0:LSB Lch Data Rch Data Figure 3. Mode 2 Timing MS0532-J-00 2006/07 - 13 - ASAHI KASEI [AK4348] LRCK 0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 0 1 BICK (64fs) SDTI 23 0 1 22 Don’t care 23 22 1 0 Don’t care 23 23:MSB, 0:LSB Lch Data Rch Data Figure 4. Mode 3 Timing 256 BICK LRCK BICK(256fs) SDTI1(i) 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 L1 R1 L2 R2 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK Figure 5. Mode 5 Timing 256 BICK LRCK BICK(256fs) SDTI1(i) 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 L1 R1 L2 R2 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 23 Figure 6. Mode 6 Timing 256 BICK LRCK BICK(256fs) SDTI1(i) 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 L1 R1 L2 R2 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 0 23 Figure 7. Mode 7 Timing MS0532-J-00 2006/07 - 14 - ASAHI KASEI [AK4348] 128 BICK LRCK BICK(128fs) SDTI1(i) SDTI2(i) 23 22 23 22 0 0 23 22 23 22 0 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 23 22 23 22 0 0 23 22 23 22 0 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 0 23 22 0 23 22 0 23 0 23 Figure 8. Mode 8 Timing 128 BICK LRCK BICK(128fs) SDTI1(i) SDTI2(i) 23 22 0 23 22 0 0 23 22 23 22 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 23 22 0 23 22 0 23 22 0 23 22 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK Figure 9. Mode 9 Timing 128 BICK LRCK BICK(128fs) SDTI1(i) SDTI2(i) 23 22 0 23 22 0 23 22 0 23 22 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 23 22 0 23 22 0 23 22 0 23 22 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 0 19 0 19 Figure 10. Mode 10 Timing MS0532-J-00 2006/07 - 15 - ASAHI KASEI [AK4348] IIR 3 (32kHz, 44.1kHz, 48kHz) Double Speed Mode, Quad Speed Mode DEM0-1 bit DEMA-D bit DEM0-1 pin (50/15µs DAC DEM1 DEM0 Mode 0 0 1 1 0 1 0 1 44.1kHz OFF 48kHz 32kHz Table 9. AK4348 (Normal Speed Mode) MUTE DAC 256 ATT 0dB 256 ATT_DATA = “0” ) OFF -48dB 1 ATT = 20 log10 (ATT_DATA / 255) [dB] (Table 10) MUTE Sampling Speed Normal Speed Mode Double Speed Mode Quad Speed Mode 1 Level 4LRCK 8LRCK 16LRCK 255 to 0 1020LRCK 2040LRCK 4080LRCK Table 10. ATT pin 8192/fs “0” “H” “H” RSTN bit “1” PW1-4 bit “0” DAC “0” DZF pin DZFB bit DZF1 pin “L” DZF pin DZF1 DZF2 0CH 0DH “1” “1” AK4348 Table 11 “0” DZF pin “0” PW1-4 bit DAC DAC “L” “0” DZF RSTN bit “0” DZF DZF pin 4~5LRCK “L” PW bit “0” DZF pin “L” AND AND Table 11. DZF pin MS0532-J-00 2006/07 - 16 - ASAHI KASEI [AK4348] ×ATT -∞ (Table 10) ATT SMUTE bit -∞ (“0”) ATT ×ATT “1” ATT SMUTE bit ATT “0” -∞ -∞ ATT SMUTE (1) (1) ATT Level (3) Attenuation -∞ GD GD (2) AOUT (4) 8192/fs DZF pin : (1) ATT ×ATT 1020LRCK (2) (3) 0dB (4) (Table 10) Normal Speed Mode ATT “255” (GD) -∞ 8192 “0” “0” DZF pin SMUTE pin Figure 11. DZF pin “H” “L” DZF pin “L” (DZFB bit = “0”) MS0532-J-00 2006/07 - 17 - ASAHI KASEI ON “↑” [AK4348] RSTB pin AK4348 RSTB pin VCOM “L” “L” RSTB DAC MCLK LRCK LRCK DAC (PW1-4 bit) “0” VCOM Power RSTB pin Internal State DAC In (Digital) Normal Operation (2) Reset “0”data “0”data GD (1) GD (3) DAC Out (Analog) (2) (3) (4) Clock In MCLK,LRCK,BICK Don’t care Don’t care (6) DZF1/DZF2 External Mute (1) (2) (3) RSTB (4) (5) (6) (5) Mute ON Mute ON (GD) VCOM (“↑ ↓”) “0” (RSTB pin = “L”) (3) (RSTB pin= “L”) DZF pin Figure 12. (MCLK, BICK, LRCK) “L” (DZFB bit = “0”) ON/OFF MS0532-J-00 2006/07 - 18 - ASAHI KASEI [AK4348] RSTN bit RSTN bit “0” DAC VCOM RSTN bit DZF pin “0” “H” (DZFB bit = “0”) Figure 13 RSTN bit RSTN bit 3~4/fs (6) 2~3/fs (6) Internal RSTN bit Internal State Normal Operation Normal Operation Digital Block P D/A In (Digital) d “0” data (1) GD GD (3) D/A Out (Analog) (2) (3) (1) (4) Clock In Don’t care MCLK,LRCK,BICK 2/fs(5) DZF (1) (2) RSTN bit = “0” (3) RSTN (GD) VCOM (“↓ ↑”) (4) (RSTN bit = “0”) (5) DZF pin RSTN bit (6) RSTN bit LSI “0” “H” (MCLK, BICK, LRCK) LSI RSTN bit RSTN bit 2/fs “L” 3 ~4/fs 2 ~ 3/fs Figure 13. (DZFB bit = “0”) MS0532-J-00 2006/07 - 19 - ASAHI KASEI [AK4348] 2 pin “L” ) I2 C CAD1 pin RSTN bit “0” (3 3 I2 C CAD0-1 RSTB pin * AK4348 * RSTB pin = “L” * * P/S pin RSTB pin Function Parallel control mode Serial control mode O O O - O O O O O O O Double sampling mode at 128/192fs De-emphasis SMUTE Zero Detection 24bit LSB justified format TDM256 mode TDM128 mode Table 12. (1) 3 (O: , -: ) (I2C pin = “L”) 3 I/F (2bit, C1/0, C1=CAD1, C0 “1” Control data (MSB first, 8bit) “↑” CCLK : CSN, CCLK, CDTI ), Read/Write (1bit, “1” CCLK 5MHz (max) I/F Chip address , Write only), Register address (MSB first, 5bit) “↑” CSN CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1-C0: R/W: A4-A0: D7-D0: Chip Address (C1=CAD1, C0=“1”) READ/WRITE (Fixed to “1”, Write only) Register Address Control Data Figure 14. Control I/F Timing MS0532-J-00 2006/07 - 20 - ASAHI KASEI [AK4348] 2 (2) I C AK4348 (I2C pin = “H”) I2 C (max:400kHz) I2 C (Start Condition) SCL (Figure 19) (R/W) (Figure 16) CAD0-1 pin (Acknowledge) Write (Not Acknowledge) (Figure 20) 2 ( Figure 15 “H” SDA 5 IC “L” “H” 7 2 R/W bit “0” “1” AK4348 8 IC “00100” R/W bit AK4348 SDA ) 8 (Figure 17) 3 (Figure 18) AK4348 (Stop Condition) (Figure 19) MSB first 8 SCL “H” 3 MSB first SDA AK4348 “0” “L” “H” 1 “0EH” “00H” “H” SCL SDA “L” S T A R T SDA S “H” “L” “H” SDA (Figure 21) SCL S T O P R/W Slave Address Sub Address(n) A C K Data(n) Data(n+x) Data(n+1) A C K A C K A C K A C K P A C K Figure 15. I2C 0 0 1 0 0 (CAD0-1 0 0 D6 D5 Figure 18. R/W 1 A4 Figure 17. D7 CAD0 ) Figure 16. 0 CAD1 A3 A2 A1 A0 D3 D2 D1 D0 2 D4 3 MS0532-J-00 2006/07 - 21 - ASAHI KASEI [AK4348] SDA SCL S P start condition stop condition Figure 19. DATA OUTPUT BY MASTER not acknowledge DATA OUTPUT BY SLAVE(AK4359) acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION Figure 20. I2C SDA SCL data line stable; data valid change of data allowed Figure 21. I2C MS0532-J-00 2006/07 - 22 - ASAHI KASEI [AK4348] Register Map Addr Register Name 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH Control 1 Control 2 Control 3 LOUT1 ATT Control ROUT1 ATT Control LOUT2 ATT Control ROUT2 ATT Control LOUT3 ATT Control ROUT3 ATT Control LOUT4 ATT Control ROUT4 ATT Control Invert Output Signal DZF1 Control DZF2 Control DEM Control D7 D6 D5 D4 D3 D2 D1 D0 ACKS 0 PW4 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 INVL1 L1 L1 0 TDM1 0 PW3 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 INVR1 R1 R1 0 TDM0 SLOW PW2 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 INVL2 L2 L2 0 DIF2 DFS1 0 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 INVR2 R2 R2 0 DIF1 DFS0 0 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 INVL3 L3 L3 DEMA DIF0 DEM1 DZFB ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 INVR3 R3 R3 DEMB PW1 DEM0 PW1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 INVL4 L4 L4 DEMC RSTN SMUTE 0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 INVR4 R4 R4 DEMD Note: For addresses from 0FH to 1FH, data must not be written. When RSTB pin goes to “L”, the registers are initialized to their default values. When RSTN bit goes to “0”, the only internal timing is reset, and the registers are not initialized to their default values. All data can be written to the registers even if PW1-4 or RSTN bit is “0”. Register Definitions Addr 00H Register Name Control 1 Default D7 D6 D5 D4 D3 D2 D1 D0 ACKS TDM1 TDM0 DIF2 DIF1 DIF0 PW1 RSTN 1 0 0 0 1 0 1 1 RSTN: Internal timing reset 0: Reset. All DZF pins go to “H” and any registers are not initialized. 1: Normal operation When MCLK frequency or DFS changes, the click noise can be reduced by RSTN bit. PW1: Power-down control (0: Power-down, 1: Power-up) PW1: Power down control of DAC1 This bit is duplicated into D1 of 02H. DIF2-0: Audio data interface modes (See Table 7, Table 8) Initial: “010”, Mode 2 TDM0-1: TDM Mode Select Mode Normal TDM256 TDM128 TDM1 0 0 1 TDM0 0 1 1 BICK 32fs∼ 256fs fixed 128fs fixed SDTI 1-4 1 1-2 Sampling Speed Normal, Double, Quad Speed Normal Speed Normal, Double Speed ACKS: Master Clock Frequency Auto Setting Mode Enable 0: Disable, Manual Setting Mode 1: Enable, Auto Setting Mode Master clock frequency is detected automatically when the ACKS bit = “1”. In this case, the setting of DFS1-0 bits is ignored. When this bit is “0”, DFS1-0 bits set the sampling speed mode. MS0532-J-00 2006/07 - 23 - ASAHI KASEI Addr 01H [AK4348] Register Name Control 2 Default D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 SLOW DFS1 DFS0 DEM1 DEM0 SMUTE 0 0 0 0 1 0 SMUTE: Soft Mute Enable 0: Normal operation 1: DAC outputs soft-muted DEM1-0: De-emphasis Response (See Table 9) Initial: “01”, OFF DFS1-0: Sampling speed control (See Table 1) 00: Normal speed 01: Double speed 10: Quad speed When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise occurs. SLOW: Slow Roll-off Filter Enable 0: Sharp Roll-off Filter 1: Slow Roll-off Filter Adr 02H Register Name Speed & Power Down Control Default D7 PW4 1 D6 PW3 1 D5 PW2 1 D4 0 0 D3 0 0 D2 DZFB 0 D1 PW1 1 D0 0 0 PW1: Power-down control (0: Power-down, 1: Power-up) PW1: Power down control of DAC1 This bit is duplicated into D1 of 00H. DZFB: Inverting Enable of DZF 0: DZF goes “H” at Zero Detection 1: DZF goes “L” at Zero Detection PW4-2: Power-down control (0: Power-down, 1: Power-up) PW2: Power down control of DAC2 PW3: Power down control of DAC3 PW4: Power down control of DAC4 All sections are powered-down by PW1=PW2=PW3=PW4=0. MS0532-J-00 2006/07 - 24 - ASAHI KASEI Addr 03H 04H 05H 06H 07H 08H 09H 0AH Register Name LOUT1 ATT Control ROUT1 ATT Control LOUT2 ATT Control ROUT2 ATT Control LOUT3 ATT Control ROUT3 ATT Control LOUT4 ATT Control ROUT4 ATT Control Default [AK4348] D7 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 1 D6 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 1 D5 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 1 D4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 1 D3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 1 D2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 1 D1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 1 D0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 1 D6 INVR1 0 D5 INVL2 0 D4 INVR2 0 D3 INVL3 0 D2 INVR3 0 D1 INVL4 0 D0 INVR4 0 D5 L2 L2 0 D4 R2 R2 0 D3 L3 L3 0 D2 R3 R3 0 D1 L4 L4 0 D0 R4 R4 0 D5 0 0 D4 0 0 D3 DEMA 0 D2 DEMB 0 D1 DEMC 0 D0 DEMD 0 ATT = 20 log10 (ATT_DATA / 255) [dB] 00H: Mute Addr 0BH Register Name Invert Output Signal Default D7 INVL1 0 INVL1-4, INVR1-4: Inverting Output Polarity 0: Normal Output 1: Inverted Output Addr 0CH 0DH Register Name DZF1 Control DZF2 Control Default D7 L1 L1 0 D6 R1 R1 0 L1-4, R1-4: Zero Detect Flag Enable for DZF1/2 pins 0: Disable 1: Enable Addr 0EH Register Name DEM Control Default D7 0 0 D6 0 0 DEMA-D: De-emphasis Enable of DAC1/2/3/4 0: Disable 1: Enable MS0532-J-00 2006/07 - 25 - ASAHI KASEI [AK4348] Figure 22, 23 (AKD4348) Master Clock 1 MCLK DZF1 30 64fs 2 BICK TDM0 29 24bit Audio Data 3 SDTI1 AVDD 28 fs 4 LRCK AVSS 27 Reset 5 RSTB VCOM 26 6 SMUTE LOUT1 25 MUTE L1ch Out 7 ACKS ROUT1 24 MUTE R1ch Out Microcontroller AK4348 Mute Signal TDM Mode 0.1u 10u Analog 3.3V + + 0.1u 10u 8 DIF0 P/S 23 24bit Audio Data 9 SDTI2 LOUT2 22 MUTE L2ch Out 24bit Audio Data 10 SDTI3 ROUT2 21 MUTE R2ch Out 24bit Audio Data 11 SDTI4 LOUT3 20 MUTE L3ch Out Micro- 12 DIF1 ROUT3 19 MUTE R3ch Out controller 13 DEM0 LOUT4 18 MUTE L4ch Out 14 DVDD ROUT4 17 MUTE R4ch Out 15 DVSS DEM1 16 Micro-controller 10u + 0.1u Digital 3.3V Digital Ground Analog Ground Figure 22. Typical Connection Diagram (Parallel Control Mode) Notes: - LRCK = fs, BICK=64fs. - LOUT/ROUT - P/S, TDM0 pin MS0532-J-00 2006/07 - 26 - ASAHI KASEI [AK4348] Master Clock 1 MCLK DZF1 30 64fs 2 BICK DZF2 29 24bit Audio Data 3 SDTI1 AVDD 28 fs 4 LRCK AVSS 27 Reset 5 RSTB VCOM 26 6 CSN 7 CCLK Microcontroller AK4348 0.1u 10u Analog 3.3V + + 0.1u 10u LOUT1 25 MUTE L1ch Out ROUT1 24 MUTE R1ch Out 8 CDTI P/S 23 24bit Audio Data 9 SDTI2 LOUT2 22 MUTE L2ch Out 24bit Audio Data 10 SDTI3 ROUT2 21 MUTE R2ch Out 24bit Audio Data 11 SDTI4 LOUT3 20 MUTE L3ch Out Micro- 12 DIF1 ROUT3 19 MUTE R3ch Out controller 13 CAD0 LOUT4 18 MUTE L4ch Out 14 DVDD ROUT4 17 MUTE R4ch Out 15 DVSS I2C 16 10u + 0.1u Digital 3.3V Digital Ground Analog Ground Figure 23. Typical Connection Diagram (3-wire Serial Control Mode) Notes: - LRCK = fs, BICK=64fs. - LOUT/ROUT - P/S pin - DZF1 pin 0CH MS0532-J-00 2006/07 - 27 - ASAHI KASEI [AK4348] Analog Ground Digital Ground System Controller 1 MCLK 2 BICK 3 SDTI1 4 DZF1 30 TDM0/DZF2 29 AK4348 AVDD 28 LRCK AVSS 27 5 RSTB VCOM 26 6 SMUTE/CSN/CAD0 LOUT1 25 7 ACKS/CCLK/CSL ROUT1 24 8 DFS0/CDT/SDA P/S 23 9 SDTI2 LOUT2 22 10 SDTI3 ROUT2 21 11 SDTI4 LOUT3 20 12 DIF1 ROUT3 19 13 DEM0/CAD1 LOUT4 18 14 DVDD ROUT4 17 15 DVSS DEM1/I2 16 Figure 24. : AVSS DVSS 1. AVDD DVDD AVDD DVDD AVSS DVSS PC (0.1µF) 2. ( 800000H(@24bit) VCOM + VCOM 2.24Vpp(typ@AVDD=3.3V) INVL/INVR bit L/R ∆Σ ) (SCF) (CTF) 2’s Complement (2 ) 7FFFFFH(@24bit) 000000H(@24bit) VAOUT VCOM mV DC DC MS0532-J-00 2006/07 - 28 - ASAHI KASEI [AK4348] 30pin VSOP (Unit: mm) *9.7±0.1 1.5MAX 0.3 30 16 15 1 0.22±0.1 7.6±0.2 5.6±0.1 A 0.15 +0.10 -0.05 0.65 0.12 M 0.45±0.2 +0.10 0.10 -0.05 1.2±0.10 Detail A 0.08 NOTE: Dimension "*" does not include mold flash. : : : ( ) MS0532-J-00 2006/07 - 29 - ASAHI KASEI [AK4348] (AK4348EF) AKM AK4348EF XXXBYYYYC XXXBYYYYC Date code identifier XXXB: Lot number (X: Digit number, B: Alpha character) YYYYC: Assembly date (Y: Digit number, C: Alpha character) MS0532-J-00 2006/07 - 30 - ASAHI KASEI [AK4348] (AK4348VF) AKM AK4348VF XXXBYYYYC XXXBYYYYC Date code identifier XXXB: Lot number (X: Digit number, B: Alpha character) YYYYC: Assembly date (Y: Digit number, C: Alpha character) Date (YY/MM/DD) 06/07/28 Revision 00 Reason Page Contents • • • • • • MS0532-J-00 2006/07 - 31 -