データシート

ASAHI KASEI
[AK5700]
AK5700
PLL & MIC-AMP
AK5700
16-Bit ΔΣ Mono ADC
16bit A/D
ALC(Auto Level Control)
PLL
AK5700 24pin QFN
AK5701
AK5700
1.
2.
AK5700
DSP
: 16bits
- ADC
2
or
(+30dB/+15dB or 0dB)
: 1.8Vpp @AVDD =3.0V (= 0.6 x AVDD)
: S/(N+D): 78dB, DR, S/N: 89dB@MGAIN=0dB
S/(N+D): 77dB, DR, S/N: 87dB@MGAIN=+15dB
S/(N+D): 72dB, DR, S/N: 77dB@MGAIN=+30dB
HPF
(fc=3.4Hz@fs=44.1kHz)
- Digital ALC (Automatic Level Control)
(+36dB ∼ −54dB, 0.375dB Step, Mute)
3.
:
- PLL Slave Mode (EXLRCK pin): 7.35kHz ∼ 48kHz
- PLL Slave Mode (EXBCLK pin): 7.35kHz ∼ 48kHz
- PLL Slave Mode (MCKI pin):
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
- PLL Master Mode:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
- EXT Master/Slave Mode:
7.35kHz ∼ 48kHz (256fs), 7.35kHz ∼ 26kHz (512fs), 7.35kHz ∼ 13kHz (1024fs)
4. PLL
:
- MCKI pin:
27MHz, 26MHz, 24MHz, 19.2MHz, 13.5MHz, 13MHz, 12.288MHz, 12MHz,
11.2896MHz
- EXLRCK pin: 1fs
- EXBCLK pin: 32fs/64fs
5.
6.
: MSB First, 2’s complement
- DSP Mode, 16bit
, I2S
7.
μP
:3
8.
:
- AVDD: 2.4 ∼ 3.6V
- DVDD: 1.6 ∼ 3.6V
9.
: 6mA
10. Ta = −30 ∼ 85°C
11.
: 24pin QFN (4mm x 4mm)
12. AK5701
MS0569-J-01
2006/12
-1-
ASAHI KASEI
[AK5700]
„
DVDD
DVSS
PDN
AIN1/AIN+
AIN−
S
E
L
ADC
ALC
HPF or
IVOL
AIN2
LRCK
Audio I/F
Controller
BCLK
S
E
L
SDTO
MPWR
VCOM
AVDD
AVSS
VCOC
Control
Register
PLL
MCKO MCKI
CSP
EXLRCK
EXBCLK
EXSDTI
CSN CCLK CDTI
Figure 1.
MS0569-J-01
2006/12
-2-
ASAHI KASEI
[AK5700]
„
−30 ∼ +85°C
AK5700
AK5700VN
AKD5700
24pin QFN (0.5mm pitch)
PDN
CSN
CCLK
CDTI
MCKI
EXBCLK
18
17
16
15
14
13
„
MCKO
AIN -
22
Top View
9
CSP
23
8
SDTO
24
7
LRCK
AIN1 / AIN+
VCOC
6
10
BCLK
AK5700VN
5
21
DVSS
AIN2
4
EXSDTI
DVDD
11
3
20
AVDD
TEST
2
EXLRCK
AVSS
12
1
19
VCOM
MPWR
„ AK5701VN
ADC
AK5701VN
2
2
DSP Mode 0, DSP Mode 1,
Left justified, I2S
MS0569-J-01
AK5700VN
1
2
DSP Mode 0,
Left justified, I2S
2006/12
-3-
ASAHI KASEI
No.
Pin Name
[AK5700]
I/O
1
VCOM
O
2
3
4
5
6
7
8
AVSS
AVDD
DVDD
DVSS
BCLK
LRCK
SDTO
O
O
O
9
CSP
I
10
11
12
13
14
15
16
17
MCKO
EXSDTI
EXLRCK
EXBCLK
MCKI
CDTI
CCLK
CSN
O
I
I
I
I
I
I
I
18
PDN
I
19
MPWR
O
20
TEST
-
21
22
AIN2
AIN−
AIN1
AIN+
I
I
I
I
23
24
VCOC
Note 1.
Function
, 0.5 x AVDD
ADC
“H”: CSN pin = “H” active, C1-0 = “01”
“L”: CSN pin = “L” active, C1-0 = “10”
(CSP pin = “H”
)
“H”:
“L”:
2
(MDIF1 bit = “0”: Single-ended Input)
(MDIF1 bit = “1”: Full-differential Input)
1
PLL
AVSS
(AIN1, AIN1−, AIN2)
O
„
Analog
Digital
MPWR, VCOC, AIN1/AIN+, AIN−, AIN2
BCLK, LRCK, SDTO, MCKO
MCKI, EXBCLK, EXLRCK, EXSDTI
MS0569-J-01
DVSS
2006/12
-4-
ASAHI KASEI
(AVSS, DVSS=0V; Note 2)
Parameter
Power Supplies:
Analog
Digital
|AVSS – DVSS| (Note 3)
Input Current, Any Pin Except Supplies
Analog Input Voltage (Note 4)
Digital Input Voltage (Note 5)
Ambient Temperature (powered applied)
Storage Temperature
[AK5700]
Symbol
AVDD
DVDD
ΔGND
IIN
VINA
VIND
Ta
Tstg
min
−0.3
−0.3
−0.3
−0.3
−30
−65
max
4.6
4.6
0.3
±10
AVDD+0.3
DVDD+0.3
85
150
Units
V
V
V
mA
V
V
°C
°C
Note 2.
Note 3. AVSS DVSS
Note 4. AIN1/AIN+, AIN−, AIN2 pins
Note 5. PDN, CSN, CCLK, CDTI, CSP, MCKI, EXSDTI, EXLRCK, EXBCLK pins
:
(AVSS, DVSS=0V; Note 2)
Parameter
Power Supplies
Analog
(Note 6)
Digital
Symbol
AVDD
DVDD
Note 2.
Note 6. AVDD, DVDD
DVDD
min
2.4
1.6
DVDD
OFF
typ
3.0
3.0
Max
3.6
AVDD
AVDD
AVDD
Units
V
V
OFF
OFF
:
MS0569-J-01
2006/12
-5-
ASAHI KASEI
[AK5700]
(Ta=25°C; AVDD, DVDD=3.0V; AVSS=DVSS=0V; PLL Master Mode; MCKI=12MHz, fs=44.0995kHz, BCLK=64fs;
Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified)
Min
Typ
max
Units
Parameter
MIC Amplifier: AIN1, AIN2 pins; MDIF1 bit = “0” (Single-ended inputs)
Input
MGAIN1-0 bits = “00”
40
60
80
kΩ
Resistance MGAIN1-0 bits = “01” or “10”
20
30
40
kΩ
MGAIN1-0 bits = “00”
0
dB
Gain
MGAIN1-0 bits = “01”
+15
dB
MGAIN1-0 bits = “10”
+30
dB
MIC Amplifier: AIN+, AIN− pins; MDIF1 bit = “1” (Full-differential input)
Input Voltage (Note 7)
MGAIN1-0 bits = “01”
0.37
Vpp
MGAIN1-0 bits = “10”
0.066
Vpp
MIC Power Supply: MPWR pin
Output Voltage (Note 8)
2.02
2.25
2.48
V
Load Resistance
1.0
kΩ
Load Capacitance
30
pF
ADC Analog Input Characteristics: AIN1/AIN2 pins (Single-ended inputs) → ADC → IVOL,
MGAIN=+15dB, IVOL=0dB, ALC=OFF
Resolution
16
Bits
MGAIN=+30dB
0.057
Vpp
Input Voltage (Note 9)
MGAIN=+15dB
0.27
0.32
0.37
Vpp
MGAIN=0dB
1.53
1.80
2.07
Vpp
67
77
dB
S/(N+D) (−0.5dBFS) (Note 10)
79
87
dB
D-Range (−60dBFS, A-weighted) (Note 11)
S/N (A-weighted) (Note 11)
79
87
dB
Power Supplies:
Power Supply Current: AVDD+DVDD
Power Up (PDN pin = “H”) (Note 12)
6
12
mA
Power Down (PDN pin = “L”) (Note 13)
1
20
μA
Note 7.
AC
MGAIN1-0 bits = “00”
AIN+, AIN− pin
AVDD
Vin = |(AIN+) − (AIN−)| = 0.123 x AVDD (max)@MGAIN1-0 bits
= “01”, 0.022 x AVDD (max)@MGAIN1-0 bits = “10”.
ADC
Note 8.
AVDD
Vout = 0.75 x AVDD (typ)
Note 9.
AVDD
Vin = 0.107 x AVDD (typ)@MGAIN1-0 bits = “01” (+15dB), Vin = 0.6 x
AVDD(typ)@MGAIN1-0 bits = “00” (0dB)
Note 10. 78dB(typ)@MGAIN=0dB, 72dB(typ)@MGAIN=+30dB
Note 11. 89dB(typ)@MGAIN=0dB, 77dB(typ)@MGAIN=+30dB
Note 12. PLL Master Mode (MCKI=12MHz)
PMADC = PMVCM = PMPLL = PMMP = M/S bits = “1”, MCKO =
“0”
MPWR pin
0mA
AVDD=4.5mA(typ), DVDD=1.5mA(typ).
EXT Slave Mode (PMPLL = M/S = MCKO bits = “0”)
: AVDD=3.8mA(typ), DVDD=1.2mA(typ).
Bypass Mode (THR bit = “1”, PMADC = M/S bits = “0”), fs=8kHz
: AVDD=1μA(typ),
DVDD=150μA(typ).
Note 13.
DVDD
DVSS
MS0569-J-01
2006/12
-6-
ASAHI KASEI
[AK5700]
(Ta=25°C; AVDD=2.4 ∼ 3.6V; DVDD=1.6 ∼ 3.6V; fs=44.1kHz)
Parameter
Symbol
ADC Digital Filter (Decimation LPF):
Passband (Note 14)
PB
±0.1dB
−1.0dB
−3.0dB
Stopband (Note 14)
SB
Passband Ripple
PR
Stopband Attenuation
SA
Group Delay (Note 15)
GD
Group Delay Distortion
ΔGD
ADC Digital Filter (HPF): HPF1-0 bits = “00”
Frequency Response (Note 14) −3.0dB
FR
−0.5dB
−0.1dB
Note 14.
fs (
PB=20.0kHz(@−1.0dB)
min
typ
max
Units
0
25.7
65
-
20.0
21.1
18
0
17.4
±0.1
-
kHz
kHz
kHz
kHz
dB
dB
1/fs
μs
-
3.4
10
22
-
Hz
Hz
Hz
)
0.454 x fs
(ADC)
1kHz
Note 15.
16
DC
(Ta=25°C; AVDD=2.4 ∼ 3.6V; DVDD=1.6 ∼ 3.6V)
Parameter
Symbol
High-Level Input Voltage
Except CSP pin; 2.2V≤ DVDD ≤3.6V
VIH
Except CSP pin; 1.6V≤ DVDD <2.2V
VIH
CSP pin
VIH
Low-Level Input Voltage
Except CSP pin; 2.2V≤ DVDD ≤3.6V
VIL
Except CSP pin; 1.6V≤ DVDD <2.2V
VIL
CSP pin
VIL
High-Level Output Voltage
(Iout= −200μA)
VOH
Low-Level Output Voltage
(Iout= 200μA)
VOL
Input Leakage Current (Note 16)
Iin
Note 16. CSP pin = “H”
CCLK pin
min
typ
max
Units
70%DVDD
80%DVDD
90%DVDD
-
-
V
V
V
DVDD−0.2
-
-
30%DVDD
20%DVDD
10%DVDD
0.2
±10
V
V
V
V
V
μA
(typ. 100kΩ)
MS0569-J-01
2006/12
-7-
ASAHI KASEI
[AK5700]
(Ta=25°C; AVDD=2.4 ∼ 3.6V; DVDD=1.6 ∼ 3.6V; CL=20pF; unless otherwise specified)
Parameter
Symbol
min
typ
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
MCKO Output Timing
Frequency
fMCK
0.2352
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
256fs at fs=32kHz, 29.4kHz
dMCK
33
LRCK Output Timing
Frequency
fs
7.35
DSP Mode: Pulse Width High
tLRCKH
tBCK
Except DSP Mode: Duty Cycle
Duty
50
BCLK Output Timing
Period
BCKO1-0 bit = “01”
tBCK
1/(32fs)
BCKO1-0 bit = “10”
tBCK
1/(64fs)
Duty Cycle
dBCK
50
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
MCKO Output Timing
Frequency
fMCK
0.2352
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
256fs at fs=32kHz, 29.4kHz
dMCK
33
EXLRCK Input Timing
Frequency
fs
7.35
DSP Mode: Pulse Width High
tLRCKH
tBCK−60
Except DSP Mode: Duty Cycle
Duty
45
EXBCLK Input Timing
Period
tBCK
1/(64fs)
Pulse Width Low
tBCKL
0.4 x tBCK
Pulse Width High
tBCKH
0.4 x tBCK
PLL Slave Mode (PLL Reference Clock = EXLRCK pin)
EXLRCK Input Timing
Frequency
fs
7.35
DSP Mode: Pulse Width High
tLRCKH
tBCK−60
Except DSP Mode: Duty Cycle
Duty
45
EXBCLK Input Timing
Period
tBCK
1/(64fs)
Pulse Width Low
tBCKL
0.4 x tBCK
Pulse Width High
tBCKH
0.4 x tBCK
-
MS0569-J-01
max
Units
27
-
MHz
ns
ns
12.288
MHz
60
-
%
%
48
-
kHz
ns
%
-
ns
ns
%
27
-
MHz
ns
ns
12.288
MHz
60
-
%
%
48
1/fs − tBCK
55
kHz
ns
%
1/(32fs)
-
ns
ns
ns
48
1/fs − tBCK
55
kHz
ns
%
1/(32fs)
-
ns
ns
ns
2006/12
-8-
ASAHI KASEI
[AK5700]
Parameter
Symbol
PLL Slave Mode (PLL Reference Clock = EXBCLK pin)
EXLRCK Input Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
EXBCLK Input Timing
Period
PLL3-0 bits = “0010”
tBCK
PLL3-0 bits = “0011”
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Slave Mode
MCKI Input Timing
Frequency
256fs
fCLK
512fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
EXLRCK Input Timing
Frequency
256fs
fs
512fs
fs
1024fs
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
EXBCLK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Master Mode
MCKI Input Timing
Frequency
256fs
fCLK
512fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Output Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BCLK Output Timing
Period
BCKO1-0 bit = “01”
tBCK
BCKO1-0 bit = “10”
tBCK
Duty Cycle
dBCK
MS0569-J-01
min
typ
max
Units
7.35
tBCK−60
45
-
48
1/fs − tBCK
55
kHz
ns
%
0.4 x tBCK
0.4 x tBCK
1/(32fs)
1/(64fs)
-
-
ns
ns
ns
ns
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
-
12.288
13.312
13.312
-
MHz
MHz
MHz
ns
ns
7.35
7.35
7.35
tBCK−60
45
-
48
26
13
1/fs − tBCK
55
kHz
kHz
kHz
ns
%
312.5
130
130
-
-
ns
ns
ns
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
-
12.288
13.312
13.312
-
MHz
MHz
MHz
ns
ns
7.35
-
tBCK
50
48
-
kHz
ns
%
-
1/(32fs)
1/(64fs)
50
-
ns
ns
%
2006/12
-9-
ASAHI KASEI
[AK5700]
Parameter
Audio Interface Timing (DSP Mode)
Master Mode
LRCK “↑” to BCLK “↑” (Note 17)
LRCK “↑” to BCLK “↓” (Note 18)
BCLK “↑” to SDTO (BCKP bit = “0”)
BCLK “↓” to SDTO (BCKP bit = “1”)
Slave Mode
EXLRCK “↑” to EXBCLK “↑” (Note 17)
EXLRCK “↑” to EXBCLK “↓” (Note 18)
EXBCLK “↑” to EXLRCK “↑” (Note 17)
EXBCLK “↓” to EXLRCK “↑” (Note 18)
EXBCLK “↑” to SDTO (BCKP bit = “0”)
EXBCLK “↓” to SDTO (BCKP bit = “1”)
Audio Interface Timing (Left justified & I2S)
Master Mode
BCLK “↓” to LRCK Edge (Note 19)
LRCK Edge to SDTO (MSB)
(Except I2S mode)
BCLK “↓” to SDTO
Slave Mode
EXLRCK Edge to EXBCLK “↑” (Note 19)
EXBCLK “↑” to EXLRCK Edge (Note 19)
EXLRCK Edge to SDTO (MSB)
(Except I2S mode)
EXBCLK “↓” to SDTO
Note 17. MSBS, BCKP bits = “00” or “11”
Note 18. MSBS, BCKP bits = “01” or “10”
Note 19.
EXLRCK
Symbol
min
typ
Max
Units
tDBF
tDBF
tBSD
tBSD
0.5 x tBCK − 40
0.5 x tBCK − 40
−70
−70
0.5 x tBCK
0.5 x tBCK
-
0.5 x tBCK + 40
0.5 x tBCK + 40
70
70
ns
ns
ns
ns
tLRB
tLRB
tBLR
tBLR
tBSD
tBSD
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
-
-
80
80
ns
ns
ns
ns
ns
ns
tMBLR
tLRD
−40
−70
-
40
70
ns
ns
tBSD
−70
-
70
ns
tLRB
tBLR
tLRD
50
50
-
-
80
ns
ns
ns
tBSD
-
-
80
ns
EXBCLK
“↑”
MS0569-J-01
2006/12
- 10 -
ASAHI KASEI
[AK5700]
Parameter
Control Interface Timing (CSP pin = “L”)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Control Interface Timing (CSP pin = “H”)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “L” Time
CSN “↑” to CCLK “↑”
CCLK “↑” to CSN “↓”
Power-down & Reset Timing
PDN Pulse Width (Note 20)
PMADC “↑” to SDTO valid (Note 21)
HPF1-0 bits = “00”
HPF1-0 bits = “01”
HPF1-0 bits = “10”
Note 20. AK5700 PDN pin = “L”
Note 21. PMADC bit
Symbol
min
typ
max
Units
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
142
56
56
28
28
150
50
50
-
-
ns
ns
ns
ns
ns
ns
ns
ns
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
142
56
56
28
28
150
50
50
-
-
ns
ns
ns
ns
ns
ns
ns
ns
tPD
150
-
-
ns
tPDV
tPDV
tPDV
-
3088
1552
784
-
1/fs
1/fs
1/fs
LRCK
“↑”
MS0569-J-01
2006/12
- 11 -
ASAHI KASEI
[AK5700]
„
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
50%DVDD
LRCK
tLRCKH
tLRCKL
tBCK
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
50%DVDD
BCLK
tBCKH
tBCKL
1/fMCK
dBCK = tBCKH / tBCK x 100
tBCKL / tBCK x 100
MCKO
50%DVDD
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 2. Clock Timing (PLL/EXT Master mode)
tLRCKH
LRCK
50%DVDD
tBCK
tDBF
dBCK
BCLK
(BCKP = "0")
50%DVDD
BCLK
(BCKP = "1")
50%DVDD
tBSD
SDTO
MSB
50%DVDD
Figure 3. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “0”)
MS0569-J-01
2006/12
- 12 -
ASAHI KASEI
[AK5700]
tLRCKH
LRCK
50%DVDD
tBCK
tDBF
dBCK
BCLK
(BCKP = "1")
50%DVDD
BCLK
(BCKP = "0")
50%DVDD
tBSD
SDTO
MSB
50%DVDD
Figure 4. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “1”)
50%DVDD
LRCK
tMBLR
tBCKL
BCLK
50%DVDD
tLRD
tBSD
SDTO
50%DVDD
Figure 5. Audio Interface Timing (PLL/EXT Master mode & Except DSP mode)
MS0569-J-01
2006/12
- 13 -
ASAHI KASEI
[AK5700]
1/fs
VIH
EXLRCK
VIL
tLRCKH
tBLR
tBCK
VIH
EXBCLK
(BCKP = "0")
VIL
tBCKH
tBCKL
VIH
EXBCLK
(BCKP = "1")
VIL
Figure 6. Clock Timing (PLL Slave mode; PLL Reference Clock = EXLRCK or EXBCLK pin & DSP mode; MSBS = 0)
1/fs
VIH
EXLRCK
VIL
tLRCKH
tBLR
tBCK
VIH
EXBCLK
(BCKP = "1")
VIL
tBCKH
tBCKL
VIH
EXBCLK
(BCKP = "0")
VIL
Figure 7. Clock Timing (PLL Slave mode; PLL Reference Clock = EXLRCK or EXBCLK pin & DSP mode; MSBS = 1)
MS0569-J-01
2006/12
- 14 -
ASAHI KASEI
[AK5700]
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
EXLRCK
VIL
tLRCKH
tLRCKL
tBCK
Duty = tLRCKH x fs x 100
= tLRCKL x fs x 100
VIH
EXBCLK
VIL
tBCKH
tBCKL
fMCK
50%DVDD
MCKO
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin & Except DSP mode)
tLRCKH
VIH
EXLRCK
VIL
tLRB
VIH
EXBCLK
VIL
(BCKP = "0")
VIH
EXBCLK
(BCKP = "1")
VIL
tBSD
SDTO
MSB
50%DVDD
Figure 9. Audio Interface Timing (PLL Slave mode & DSP mode; MSBS = 0)
MS0569-J-01
2006/12
- 15 -
ASAHI KASEI
[AK5700]
tLRCKH
VIH
EXLRCK
VIL
tLRB
VIH
EXBCLK
VIL
(BCKP = "1")
VIH
EXBCLK
(BCKP = "0")
VIL
tBSD
SDTO
50%DVDD
MSB
Figure 10. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = 1)
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
EXLRCK
VIL
tLRCKH
tLRCKL
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tBCK
VIH
EXBCLK
VIL
tBCKH
tBCKL
Figure 11. Clock Timing (EXT Slave mode)
MS0569-J-01
2006/12
- 16 -
ASAHI KASEI
[AK5700]
VIH
EXLRCK
VIL
tBLR
tLRB
VIH
EXBCLK
VIL
tLRD
SDTO
tBSD
MSB
50%DVDD
Figure 12. Audio Interface Timing (PLL/EXT Slave mode)
MS0569-J-01
2006/12
- 17 -
ASAHI KASEI
[AK5700]
VIH
CSN
VIL
tCCKL
tCSS
tCCKH
VIH
CCLK
VIL
tCCK
tCDH
tCDS
VIH
CDTI
C1
C0
R/W
VIL
Figure 13. WRITE Command Input Timing (CSP pin = “L”)
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
D2
D1
D0
VIL
Figure 14. WRITE Data Input Timing (CSP pin = “L”)
MS0569-J-01
2006/12
- 18 -
ASAHI KASEI
[AK5700]
VIH
CSN
VIL
tCSS
tCCKL
tCCKH
VIH
CCLK
VIL
tCCK
tCDH
tCDS
VIH
CDTI
C1
C0
R/W
VIL
Figure 15. WRITE Command Input Timing (CSP pin = “H”)
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
D2
D1
D0
VIL
Figure 16. WRITE Data Input Timing (CSP pin = “H”)
MS0569-J-01
2006/12
- 19 -
ASAHI KASEI
[AK5700]
PMADC
tPDV
SDTO
50%DVDD
Figure 17. Power Down & Reset Timing 1
tPD
PDN
VIL
Figure 18. Power Down & Reset Timing 2
MS0569-J-01
2006/12
- 20 -
ASAHI KASEI
[AK5700]
„
I/F
5
(See Table 1 and Table 2.)
Mode
PMPLL bit
M/S bit
PLL3-0 bits
PLL Master Mode (Note 22)
1
1
See Table 4
PLL Slave Mode 1
1
0
See Table 4
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
1
0
See Table 4
(PLL Reference Clock: EXLRCK or EXBCLK pin)
EXT Slave Mode
0
0
x
EXT Master Mode (Note 23)
0
1
x
Note 22. PLL Master Mode
M/S bit = “1”, PMPLL bit = “0”, MCKO bit = “1”
Note 23. EXT Master Mode
Figure
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
MCKO pin
Figure 45
Table 1. Clock Mode Setting (x: Don’t care)
Mode
MCKO bit
0
PLL Master Mode
1
PLL Slave Mode
(PLL Reference Clock: MCKI pin)
0
1
MCKO pin
MCKI pin
“L”
PS1-0 bits
PLL3-0 bits
“L”
PS1-0 bits
PLL3-0 bits
PLL Slave Mode
(PLL Reference Clock: EXLRCK
or EXBCLK pin)
0
“L”
EXT Slave Mode
0
“L”
EXT Master Mode
0
“L”
GND
FS1-0 bits
FS1-0 bits
BCLK pin,
LRCK pin,
EXBCLK pin EXLRCK pin
BCLK pin
LRCK pin
(BCKO1-0
(1fs)
bits
)
EXBCLK pin EXLRCK pin
(1fs)
(≥ 32fs)
EXBCLK pin
EXLRCK pin
(PLL3-0 bits
(1fs)
)
EXBCLK pin EXLRCK pin
(1fs)
(≥ 32fs)
BCLK pin
LRCK pin
(BCKO1-0
(1fs)
bits
)
Table 2. Clock pins state in Clock Mode
„
M/S bit
(PDN pin = “L”)
AK5700
M/S bit
“1”
“0”
“1”
M/S bit
0
1
Mode
Slave Mode
EXBCLK, EXLRCK
Master Mode
BCLK, LRCK
Table 3. Select Master/Salve Mode
MS0569-J-01
Default
2006/12
- 21 -
ASAHI KASEI
[AK5700]
„ PLL
PMPLL bit = “1”
PLL
PLL FS3-0 bit, PLL3-0 bit
PMPLL bit “0” Æ “1”
Table 4
1) PLL Mode
PLL
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
0
2
0
0
0
0
0
1
0
0
EXLRCK pin
EXBCLK pin
1fs
32fs
3
0
0
1
1
EXBCLK pin
64fs
4
5
6
7
8
9
12
13
14
15
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
Mode
Others
Others
Note 24. PLL3-0 bits = “0110”
MCKI pin
11.2896MHz
MCKI pin
12.288MHz
MCKI pin
12MHz
MCKI pin
24MHz
MCKI pin
19.2MHz
MCKI pin
12MHz (Note 24)
MCKI pin
13.5MHz
MCKI pin
27MHz
MCKI pin
13MHz
MCKI pin
26MHz
N/A
“1001”
Table 5
VCOC pin
R,C
R[Ω] C[F]
6.8k
220n
10k
4.7n
10k
10n
10k
4.7n
10k
10n
10k
4.7n
10k
4.7n
10k
4.7n
10k
4.7n
10k
4.7n
10k
4.7n
10k
10n
10k
10n
10k
220n
10k
220n
PLL
(max)
80ms
2ms
4ms
2ms
4ms
40ms
40ms
40ms
40ms
40ms
40ms
40ms
40ms
60ms
60ms
Default
Mode6
Table 4. Setting of PLL Mode (fs: Sampling Frequency)
2) PLL Mode
MCKI
Mode
0
1
2
3
4
Table 5
FS3 bit
0
0
0
0
0
FS2 bit
0
0
0
0
1
FS1 bit
0
0
1
1
0
FS0 bit
0
1
0
1
0
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
10
11
0
0
1
1
0
1
14
1
1
1
1
1
0
15
1
1
1
1
Sampling Frequency
8kHz
12kHz
16kHz
24kHz
7.35kHz
7.349918kHz (Note 25)
11.025kHz
11.024877kHz (Note 25)
14.7kHz
14.69984kHz (Note 25)
22.05kHz
22.04975kHz (Note 25)
32kHz
48kHz
29.4kHz
29.39967kHz (Note 25)
44.1kHz
44.0995kHz (Note 25)
N/A
Default
Others
Others
Note 25. PLL3-0 bits = “1001”
Table 5. Setting of Sampling Frequency at PMPLL bit = “1” and Reference Clock=MCKI pin
MS0569-J-01
2006/12
- 22 -
ASAHI KASEI
[AK5700]
EXLRCK or EXBCLK
FS3 bit
Mode
FS3, FS2 bit
(Table 6)
Sampling Frequency
FS1 bit
FS0 bit
Range
0
0
Don’t care
Don’t care
7.35kHz ≤ fs ≤ 12kHz
0
0
1
Don’t care
Don’t care
12kHz < fs ≤ 24kHz
1
1
Don’t care
Don’t care
Don’t care
24kHz < fs ≤ 48kHz
2
Default
Others
Others
N/A
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” and Reference=EXLRCK/EXBCLK
FS2 bit
„ PLL
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
PMPLL bit = “0” Æ “1”
PLL
MCKO pin
“L”
(See Table 7)
bit = “1”
MCKO pin
DSP Mode 0
“0”
BCLK
BCLK
PMPLL bit = “0” Æ “1”
PLL
DSP Mode 0 MSBS bit = “0”, BCKP bit = “1”
1
“H”
2
1/(256fs)
LRCK “L”
MCKO bit = “0”
BCLK LRCK Ach
MSBS bit = “1”, BCKP bit =
PMPLL bit = “0”
LRCK
MCKO
BCLK,
“L”
MCKO pin
BCLK pin
LRCK pin
MCKO bit = “0”
MCKO bit = “1”
“L” Output
“L” Output
“L” Output
PMPLL bit “0” Æ “1”
“L” Output
PLL Unlock (
)
“L” Output
1fs Output
See Table 9
See Table 10
PLL Lock
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
PLL State
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
PMPLL bit = “0” Æ “1”
PLL
PLL
PLL
MCKO pin
MCKO
Table 9
ADC
MCKO pin
MCKO bit = “0” MCKO bit = “1”
“L” Output
PMPLL bit “0” Æ “1”
“L” Output
PLL Unlock (
)
“L” Output
See Table 9
PLL Lock
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
PLL State
MS0569-J-01
2006/12
- 23 -
ASAHI KASEI
[AK5700]
„ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
11.2896MHz, 12MHz , 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz
PLL
MCKO, BCLK, LRCK
(MCKO)
PS1-0 bit (Table 9)
MCKO bit ON/OFF
BCLK
BCKO1-0 bits
32fs or 64fs
(See Table 10)
11.2896MHz, 12MHz, 12.288MHz, 13MHz
13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz
DSP or μP
AK5700
MCKI
256fs/128fs/64fs/32fs
MCKO
32fs, 64fs
BCLK
1fs
LRCK
MCLK
BCLK
LRCK
SDTI
SDTO
Figure 19. PLL Master Mode
Mode
0
1
2
3
PS1 bit
0
0
1
1
Table 9. MCKO
PS0 bit
0
1
0
1
(PLL
MCKO pin
256fs
Default
128fs
64fs
32fs
, MCKO bit = “1”)
BCKO1 bit
BCKO0 bit
BCLK
0
0
N/A
0
1
32fs
Default
1
0
64fs
1
1
N/A
Table 10. BCLK Output Frequency at Master Mode
MS0569-J-01
2006/12
- 24 -
ASAHI KASEI
[AK5700]
„ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
MCKI, EXBCLK or EXLRCK pin
PLL
a) PLL
MCKO
MCKO bit
PLL
PLL3-0 bit
AK5700
(Table 4)
: MCKI pin
EXBCLK, EXLRCK
MCKO EXLRCK
(MCKO pin) PS1-0 bit (Table 9)
FS3-0 bit
ON/OFF
(SeeTable 5)
11.2896MHz, 12MHz, 12.288MHz, 13MHz
13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz
AK5700
DSP or μP
MCKI
MCKO
256fs/128fs/64fs/32fs
EXBCLK
EXLRCK
≥ 32fs
1fs
MCLK
BCLK
LRCK
SDTI
SDTO
Figure 20. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
ADC
(PMADC bit = “1”)
(MCKI, EXBCLK, EXLRCK)
(PMADC bit = “0”)
b) PLL
FS3-0 bit
: EXBCLK or EXLRCK pin
7.35kHz ∼ 48kHz
(See Table 6.)
AK5700
DSP or μP
MCKI
EXBCLK
EXLRCK
32fs, 64fs
1fs
BCLK
LRCK
SDTI
SDTO
Figure 21. PLL Slave Mode 2 (PLL Reference Clock: EXLRCK or EXBCLK pin)
MS0569-J-01
2006/12
- 25 -
ASAHI KASEI
[AK5700]
„ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
PMPLL bit
“0”
(EXT Slave Mode)
MCKI pin
PLL
CODEC
I/F
MCKI (256fs, 512fs or 1024fs), EXBCLK (≥32fs), EXLRCK(fs)
MCKI
(See Table 11)
ADC
MCKI EXLRCK
FS1-0 bit
Mode
0
1
2
3
ADC
MCKI Input
Sampling Frequency
Frequency
Range
Don’t care
0
0
256fs
7.35kHz ∼ 48kHz
Don’t care
0
1
1024fs
7.35kHz ∼ 13kHz
Don’t care
1
0
512fs
7.35kHz ∼ 26kHz
Don’t care
1
1
256fs
7.35kHz ∼ 48kHz
Table 11. EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
MCKI
FS3-2 bits
FS1 bit
FS0 bit
(PMADC bit = “1”)
Default
(MCKI, EXBCLK, EXLRCK)
(PMADC bit = “0”)
AK5700
DSP or μP
MCKO
256fs, 512fs or 1024fs
MCKI
MCLK
EXBCLK
EXLRCK
≥ 32fs
1fs
BCLK
LRCK
SDTI
SDTO
Figure 22. EXT Slave Mode
MS0569-J-01
2006/12
- 26 -
ASAHI KASEI
[AK5700]
„ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”, TE3-0 bits = “0101”, TMASTER bit = “1”)
Figure 45
MCKI pin
PLL
(256fs, 512fs or 1024fs)
MCKI
Mode
FS3-2 bits
0
1
2
3
Don’t care
Don’t care
Don’t care
Don’t care
ADC
(EXT Master Mode)
MCKI
(See Table 12)
ADC
FS1-0 bit
MCKI Input
Frequency
0
0
256fs
0
1
1024fs
1
0
512fs
1
1
256fs
Table 12. EXT Master Mode
MCKI
FS1 bit
(PMADC bit = “1”)
Sampling Frequency
Range
7.35kHz ∼ 48kHz
7.35kHz ∼ 13kHz
7.35kHz ∼ 26kHz
7.35kHz ∼ 48kHz
FS0 bit
MCKI
Default
MCKI
MCKI
(PMADC bit = “0”)
AK5700
DSP or μP
MCKO
256fs, 512fs or 1024fs
MCKI
BCLK
LRCK
MCLK
32fs or 64fs
1fs
BCLK
LRCK
SDTI
SDTO
Figure 23. EXT Master Mode
BCKO1 bit
BCKO0 bit
BCLK
0
0
N/A
0
1
32fs
Default
1
0
64fs
1
1
N/A
Table 13. BCLK Output Frequency at Master Mode
MS0569-J-01
2006/12
- 27 -
ASAHI KASEI
[AK5700]
„
THR bit = “1”, M/S bit = “0”, PMADC bit = “0”
LRCK, BCLK, SDTO pins
EXLRCK, EXBCLK, EXSDTI pins
THR bit = “1”, M/S bit = “0” PMADC bit = “1”
SDTO pin
ADC
THR bit
M/S bit
0
0
1
0
1
1
PMADC bit
0
1
0
1
0
1
0
1
DSP or μP
EXLRCK, EXBCLK pins
BCLK/LRCK
SDTO
“L”
“L”
“L”
ADC data
Output
“L”
Output
ADC data
EXBCLK/EXLRCK
EXSDTI
EXBCLK/EXLRCK ADC data
N/A
N/A
Output
ADC data
Table 14. Bypass Mode Select
Mode
Power down
Slave mode
Power down
Master mode
Bypass mode
Slave & Bypass
N/A
Master mode
BCLK
1fs
SDTI
Figure
Default
Figure 24
Figure 25
DSP or μP
AK5700
≥ 32fs
LRCK
LRCK, BCLK pins
≥ 32fs
BCLK
EXBCLK
LRCK
EXLRCK
SDTO
EXSDTI
BCLK
1fs
LRCK
SDTO
Figure 24. Bypass Mode
DSP or μP
DSP or μP
AK5700
≥ 32fs
BCLK
LRCK
SDTI
1fs
≥ 32fs
BCLK
EXBCLK
LRCK
EXLRCK
SDTO
AIN
BCLK
1fs
LRCK
Analog In
Figure 25. Slave & Bypass Mode
MS0569-J-01
2006/12
- 28 -
ASAHI KASEI
[AK5700]
„
3
(Table 15)
DIF1 bit
0
0
1
1
DIF0 bit
0
1
0
1
Mode 0 (DSP Mode 0)
DIF1
0
SDTO
SDTO
MSB
DIF0
0
ADC
“−1”
SDTO
DSP Mode 0
Reserved
BCLK, EXBCLK
32fs
≥ 32fs
I2S
≥ 32fs
Table 15. Audio Interface Format
BCLK/EXBCLK
BCLK/EXBCLK
2’s
EXLRCK, EXBCLK, SDTO
LRCK/EXLRCK 1
“↓”
BCKP, MSBS bit
BCKP bit = “0”
BCKP bit = “1”
MSBS bit
MSB
LRCK, BCLK, SDTO
Mode 3
SDTO BCLK/EXBCLK
SDTO
Mode 2
Mode
0
1
2
3
DIF1-0 bit
Figure
See Table 16
Figure 30
Figure 31
Default
I/F
“↑”
“↓”
BCLK/EXBCLK
MSBS
BCKP
0
0
0
1
1
0
1
1
16bit
8bit
“–256”
Audio Interface Format
SDTO MSB
LRCK/EXLRCK “↑”
1
BCLK/EXBCLK “↑”
(Figure 26)
SDTO MSB
LRCK/EXLRCK “↑”
1
BCLK/EXBCLK “↓”
(Figure 27)
SDTO MSB
LRCK/EXLRCK “↑”
1
BCLK/EXBCLK “↓”
BCLK/EXBCLK “↑”
(Figure 28)
SDTO MSB
LRCK/EXLRCK “↑”
1
BCLK/EXBCLK “↑”
BCLK/EXBCLK “↓”
(Figure 29)
Table 16. Audio Interface Format in Mode 0
8bit
“−1”
8bit
8bit
16bit
“−1”
16bit
16bit
DAC
16bit
(128)
MS0569-J-01
2006/12
- 29 -
ASAHI KASEI
[AK5700]
EXLRCK / LRCK
(M/S=0)
EXLRCK / LRCK
(M/S=1)
15
0
1
8
2
14
15
16
17
18
29
30
31
0
1
8
2
14
15
16
17
18
13
30
31
EXBCLK(32fs)
BCLK(32fs)
SDTO(o)
8
15 14
2
0
1
15 14
2
1
8
15 14
0
2
0
1
2
15 14
1
0
1/fs
1/fs
15:MSB, 0:LSB
Figure 26. Mode 0 Timing (BCKP = “0”, MSBS = “0”, M/S = “0” or “1”)
EXLRCK / LRCK
(M/S=0)
EXLRCK / LRCK
(M/S=1)
15
0
1
8
2
14
15
16
17
18
29
30
31
0
1
8
2
14
15
16
17
18
13
30
31
EXBCLK(32fs)
BCLK(32fs)
SDTO(o)
8
15 14
2
1
0
15 14
2
1
0
8
15 14
2
1
0
2
15 14
1
0
1/fs
1/fs
15:MSB, 0:LSB
Figure 27. Mode 0 Timing (BCKP = “1”, MSBS = “0”, M/S = “0” or “1”)
EXLRCK / LRCK
(M/S=0)
EXLRCK / LRCK
(M/S=1)
15
0
1
8
2
14
15
16
17
18
29
30
31
0
1
8
2
14
15
16
17
18
13
30
31
EXBCLK(32fs)
BCLK(32fs)
SDTO(o)
15 14
8
2
2
15 14
0
1
1
0
15 14
8
2
0
1
1/fs
15 14
2
1
0
1/fs
15:MSB, 0:LSB
Figure 28. Mode 0 Timing (BCKP = “0”, MSBS = “1”, M/S = “0” or “1”)
EXLRCK / LRCK
(M/S=0)
EXLRCK / LRCK
(M/S=1)
15
0
1
8
2
14
15
16
17
18
29
30
31
0
1
8
2
14
15
16
17
18
13
30
31
EXBCLK(32fs)
BCLK(32fs)
SDTO(o)
15 14
8
2
1
0
15 14
2
1
0
15 14
8
2
1
0
15 14
2
1
0
1/fs
1/fs
15:MSB, 0:LSB
Figure 29. Mode 0 Timing (BCKP = “1”, MSBS = “1”, M/S = “0” or “1”)
Note : Figure 26,Figure 27,Figure 28,Figure 29
0bit 15bit
16bit 31bit
MS0569-J-01
2006/12
- 30 -
ASAHI KASEI
[AK5700]
EXLRCK
LRCK
0
1
2
8
3
9
10
11
12
13
14
15
0
1
2
8
3
9
10
11
12
13
14
15
0
1
EXBCLK(32fs)
BCLK(32fs)
15 14 13
SDTO(o)
0
1
2
8
7
3
6
14
5
15
4
16
3
17
2
1
0
18
15 14 13
31
0
1
2
8
7
3
6
5
14
15
4
16
3
17
2
1
18
0
31
15
0
1
EXBCLK(64fs)
BCLK(64fs)
15 14 13
SDTO(o)
13 2
1
0
15 14 13
1
2
2
1
0
15
15:MSB, 0:LSB
1/fs
Figure 30. Mode 2 Timing (MSB justified, M/S = “0” or “1”)
EXLRCK
LRCK
0
1
2
3
4
9
10
11
12
13
14
15
0
1
2
3
4
9
10
11
12
13
14
15
0
1
EXBCLK(32fs)
BCLK(32fs)
0
SDTO(o)
0
15
1
14 13
2
3
4
7
7
14
6
15
5
16
4
17
3
18
2
1
31
0
0
15 14 13
1
2
3
7
4
7
14
6
15
5
16
4
17
3
18
2
1
31
0
0
1
EXBCLK(64fs)
BCLK(64fs)
SDTO(o)
15 14 13
2
1
0
15 14 13
2
2
1
0
15:MSB, 0:LSB
1/fs
Figure 31. Mode 3 Timing (I2S, M/S = “0” or “1”)
Note : Figure 30,Figure 31
LRCK “L”
0bit
LRCK
15bit
MS0569-J-01
“H”
0bit
15bit
2006/12
- 31 -
ASAHI KASEI
„
AK5700
[AK5700]
HPF
DC
HPF
HPF
HPF1-0 bits
3.4Hz (@fs= 44.1kHz)
(fs)
fc
fs=44.1kHz
fs=22.05kHz
3.4Hz
1.7Hz
6.8Hz
3.4Hz
13.6Hz
6.8Hz
N/A
N/A
Table 17.
HPF
HPF1 bit
HPF0 bit
0
0
1
1
0
1
0
1
fs=11.025kHz
0.85Hz
1.7Hz
3.4Hz
N/A
Default
„
AK5700
MDIF1 bit = “1”
Table 19 “X”
MDIF1 bit
0
1
MDIF1 bit = “0”
AIN bit
AIN1 pin AIN+ pin
Ach
AIN1
0
AIN1
AIN2
1
AIN2
0
AIN1
1
N/A
N/A
x
AIN+/−
x
AIN+/−
Table 18. MIC/Line In Path Select
AIN1, AIN2
(Figure 33)
AIN bit
Default
Register
Pin
AIN1
MDIF1 bit
AIN2
AIN1−
AIN1+
0
O
O
1
O
X
O
Table 19. Handling of MIC/Line Input Pins (“-“: N/A; “X”: Signal should not be input.)
AK5700
AIN bit
AIN1/AIN+ pin
ADC
AIN− pin
MDIF1 bit
AIN2 pin
Figure 32.
MS0569-J-01
2006/12
- 32 -
ASAHI KASEI
[AK5700]
AK5700
MPWR pin
1k
MIC-Amp
AIN+ pin
AIN− pin
1k
Figure 33.
(MDIF1 bit = “1”)
„
AK5700
(Table 20)
30kΩ
MGAIN1-0 bit
MGAIN1-0 bits = “00”
typ. 60kΩ MGAIN1-0 bits = “01”, “10”
MGAIN1 bit
0
0
1
1
MGAIN0 bit
0
1
0
1
Table 20.
Input Gain
0dB
+15dB
+30dB
N/A
typ.
Default
„
PMMP bit = “1”
AVDD)V (typ)
MPWR pin
MPWR pin
min. 1.0kΩ
(0.75 x
min. 2.0kΩ
2
(Figure 34
PMMP bit
MPWR pin
0
Hi-Z
1
Output
Table 21.
)
Default
MIC Power
≥ 2kΩ
≥ 2kΩ
MPWR pin
Microphone
AIN1 pin
Microphone
AIN2 pin
Figure 34. MIC Block Circuit
MS0569-J-01
2006/12
- 33 -
ASAHI KASEI
[AK5700]
„ ALC
ALC bit = “1”
1.
ALC
ALC
ALC
ALC
ALC
(Table 23)
(Table 22)
LMAT1-0 bit
IVL
ZELMN bit = “0”(
)
ALC
IVL
ALC
ZTM1-0 bit
(Table 24)
ZELMN bit = “1”(
)
LMAT1-0 bit
ALC bit
LMTH1
0
0
1
1
ALC
“0”
0
1
ZTM1
ZTM0
0
0
1
1
0
1
0
1
LMAT1
LMAT0
0
0
0
1
1
0
1
1
x
x
Table 23. ALC
128/fs
256/fs
512/fs
1024/fs
Table 24. ALC
(
: 1/fs)
ALC
LMTH0 ALC
0
ALC Output ≥ −2.5dBFS
1
ALC Output ≥ −4.1dBFS
0
ALC Output ≥ −6.0dBFS
1
ALC Output ≥ −8.5dBFS
Table 22. ALC
ZELMN
IVL
1 step
ALC
−2.5dBFS > ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
ALC
1 step
2 step
4 step
8 step
1step
ATT
8kHz
16ms
32ms
64ms
128ms
MS0569-J-01
ATT
0.375dB
0.750dB
1.500dB
3.000dB
0.375dB
16kHz
8ms
16ms
32ms
64ms
Default
Default
44.1kHz
2.9ms
5.8ms
11.6ms
23.2ms
Default
2006/12
- 34 -
ASAHI KASEI
2.
[AK5700]
ALC
ALC
WTM1-0
(Table 25)
(Table 22)
ALC
(Table 27)
ZTM1-0
RGAIN1-0 bit
(Table 26)
IVL
WTM1-0
WTM1-0
ZTM1-0
ALC
IVL
32H
IVL
30H
ALC
ALC
(Table 24)
ALC
ZTM1-0
RGAIN1-0 bit = “01”(2 steps)
0.75dB(0.375dB x 2)
IVL
ALC
(REF7-0)
IVL
ALC
(
) ≤ Output Signal < (
(
) > Output Signal
ALC
)
ALC
WTM1
WTM0
0
0
1
1
0
1
0
1
RGAIN1
0
0
1
1
ALC
8kHz
128/fs
16ms
256/fs
32ms
512/fs
64ms
1024/fs
128ms
Table 25. ALC
RGAIN0
0
1
0
1
Table 26. ALC
16kHz
8ms
16ms
32ms
64ms
GAIN STEP
1 step
0.375dB
2 step
0.750dB
3 step
1.125dB
4 step
1.500dB
REF7-0
GAIN(dB)
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
E2H
+30.375
E1H
+30.0
E0H
+29.625
:
:
03H
−53.25
02H
−53.625
01H
−54.0
00H
MUTE
Table 27. ALC
MS0569-J-01
44.1kHz
2.9ms
5.8ms
11.6ms
23.2ms
Default
Default
Step
0.375dB
Default
2006/12
- 35 -
ASAHI KASEI
3.
[AK5700]
ALC
Table 28
ALC
Register Name
Comment
LMTH
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM1-0 bits should be the same data
00
as ZTM1-0 bits
Maximum gain at recovery operation
E1H
Gain of IVOL
91H
Limiter ATT step
00
Recovery GAIN step
00
ALC enable
1
Table 28. ALC
WTM1-0
REF7-0
IVL7-0
LMAT1-0
RGAIN1-0
ALC
ALC
bit = “0”
Data
01
0
00
fs=8kHz
Operation
−4.1dBFS
Enable
16ms
Data
01
0
10
fs=44.1kHz
Operation
−4.1dBFS
Enable
11.6ms
16ms
10
11.6ms
+30dB
0dB
1 step
1 step
Enable
E1H
91H
00
00
1
+30dB
0dB
1 step
1 step
Enable
ALC
(ALC
PMADC bit = “0”)
LMTH, LMAT1-0, WTM1-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 16ms@8kHz
Limiter and Recovery Step = 1
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
Manual Mode
WR (IVL7-0)
ALC bit = “1”
* The value of IVOL should be
(1) Addr=18H&19H, Data=91H
the same or smaller than REF’s
WR (ZTM1-0, WTM1-0)
(2) Addr=1AH, Data=00H
WR (REF7-0)
(3) Addr=1BH, Data=E1H
WR (LMAT1-0, RGAIN1-0, ZELMN, LMTH1-0; ALC= “1”)
(4) Addr=1CH, Data=81H
ALC Operation
Note : WR : Write
Figure 35. ALC
MS0569-J-01
2006/12
- 36 -
ASAHI KASEI
„
[AK5700]
(
)
ALC bit = “0”
1.
2.
ALC
(ZTM1-0, LMTH
)
ALC
3.
IVL7-0 bit
PMADC bit = “0”
(Table 29)
ZTM1-0 bit
IVL7-0 bit
IVOL
IVL7-0
F1H
F0H
EFH
:
92H
91H
90H
:
03H
02H
01H
00H
Table 29.
PMADC bit = “1”
GAIN (dB)
+36.0
+35.625
+35.25
:
+0.375
0.0
−0.375
:
−53.25
−53.625
−54
MUTE
MS0569-J-01
ADC
Step
0.375dB
Default
2006/12
- 37 -
ASAHI KASEI
[AK5700]
IVL7-0 bit
ALC bit
ALC Status
Disable
Enable
IVL7-0 bits
Disable
E1H(+30dB)
(1)
Internal IVL
E1H(+30dB)
(2)
E1(+30dB) --> F1(+36dB)
Figure 36. ALC
(1) ALC bit = “1”
(WTM1-0 bits) +
(2) ALC
IVL
IVL7-0 bits
E1(+30dB)
IVOL
ALC
(ZTM1-0 bits)
(18H)
ALC Disable
ALC Enable
ALC bit = “1”
bit = “0”
ALC
„
PDN pin
“L”
AK5700
PMAL bit = “0”
ADC
PMADC bit
HPF1-0 bits = “00”
2’s
“0” → “1”
ADC
3088/fs=70.0ms@fs=44.1kHz
(Table 30)
“0”
ADC
HPF1 bit
HPF0 bit
0
0
3088/fs
0
1
1552/fs
1
0
784/fs
1
1
Cycle
Init Cycle
fs=44.1kHz
fs=22.05kHz
70.0ms
140.0ms
(
)
70.4ms
35.2ms
(
)
17.8ms
N/A
N/A
Table 30. ADC
MS0569-J-01
35.6ms
N/A
fs=11.025kHz
280.1ms
Default
140.8ms
71.1ms
(
)
N/A
2006/12
- 38 -
ASAHI KASEI
[AK5700]
„
pin
3
Chip address
I/F
(CSN, CCLK, CDTI)
CSP pin
CSN
1) CSP pin = “L”
I/F
Chip address (2bits, “10”
), Read/Write (1bit, “1”
), Register address (MSB first, 5bits)
Control Data (MSB first, 8bits)
CCLK “↓”
“↑”
CSN “↓” 16
CCLK “↑”
CCLK
7MHz (max)
PDN pin = “L”
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
“1” “0” “1”
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (C1 = “1”, C0 = “0”); Fixed to “10”
READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1”
Register Address
Control data
Figure 37.
(CSP pin = “L”)
2) CSP pin = “H”
I/F
Chip address (2bits, “01”
), Read/Write (1bit, “1”
), Register address (MSB first, 5bits)
Control Data (MSB first, 8bits)
CCLK “↓”
“↑”
CSN “↑” 16
CCLK “↑”
CCLK
7MHz (max)
PDN pin = “L”
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
“0” “1” “1”
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (C1 = “0”, C0 = “1”); Fixed to “01”
READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1”
Register Address
Control data
Figure 38.
(CSP pin = “H”)
MS0569-J-01
2006/12
- 39 -
ASAHI KASEI
[AK5700]
„
Addr
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
Register Name
Power Management
PLL Control
Signal Select
Mic Gain Control
Audio Format Select
fs Select
Clock Output Select
Reserved
Input Volume Control
Reserved
Timer Select
ALC Mode Control 1
ALC Mode Control 2
Mode Control 1
Mode Control 2
Note 26. PDN pin
Note 27. “0”
D7
0
0
0
0
0
HPF1
0
0
IVL7
1
0
REF7
ALC
TE3
0
D6
0
0
0
0
0
HPF0
0
0
IVL6
0
0
REF6
ZELMN
TE2
0
D5
0
PLL3
0
0
1
BCKO1
0
0
IVL5
0
0
REF5
LMAT1
TE1
0
D4
0
PLL2
PMMP
0
0
BCKO0
0
0
IVL4
1
0
REF4
LMAT0
TE0
0
D3
0
PLL1
0
0
MSBS
FS3
THR
0
IVL3
0
ZTM1
REF3
RGAIN1
0
0
D2
PMVCM
PLL0
MDIF1
0
BCKP
FS2
MCKO
0
IVL2
0
ZTM0
REF2
RGAIN0
0
0
D1
0
M/S
0
D0
PMADC
PMPLL
AIN
MGAIN1
MGAIN0
DIF1
FS1
PS1
0
IVL1
0
WTM1
REF1
LMTH1
0
DIF0
FS0
PS0
1
IVL0
1
WTM0
REF0
LMTH0
0
0
TMASTER
“L”
“1”
10H-1EH
“1”
MS0569-J-01
“0”
2006/12
- 40 -
ASAHI KASEI
[AK5700]
„
Addr
10H
Register Name
Power Management
Default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
PMVCM
0
D1
0
0
D0
PMADC
0
PMADC: MIC-Amp, ADC
0: Power down (Default)
1: Power up
PMADC bit
“00”)
“0”
“1”
(3088/fs=70.0ms@fs= 44.1kHz, HPF1-0 bits =
ADC
PMVCM: VCOM
0: Power down (Default)
1: Power up
PMVCM bit “1”
PMADC, PMPLL, PMMP, MCKO bits
“0”
PMVCM bit
“0”
ON/OFF (“1”/“0”)
PDN pin
“L”
PMVCM, PMADC, PMPLL, MCKO bits
“0”
20μA(typ)
(typ. 1μA)
PDN pin = “L”
ADC
Addr
11H
ADC
Register Name
PLL Control
Default
D7
0
0
D6
0
0
D5
PLL3
1
D4
PLL2
0
D3
PLL1
0
D2
PLL0
1
D1
M/S
0
D0
PMPLL
0
PMPLL: PLL
0: EXT Mode and Power Down (Default)
1: PLL Mode and Power up
M/S: Master / Slave Mode
0: Slave Mode (Default)
1: Master Mode
PLL3-0: PLL
(See Table 4)
Default: “1001”(MCKI pin=12MHz)
MS0569-J-01
2006/12
- 41 -
ASAHI KASEI
Addr
12H
[AK5700]
Register Name
Signal Select
Default
D7
0
0
D6
0
0
D5
0
0
D4
PMMP
0
D3
0
0
D2
MDIF1
0
D1
0
0
D0
AIN
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
D1
D0
MGAIN1
MGAIN0
0
1
D1
DIF1
1
D0
DIF0
1
AIN: ADC
0: AIN1 pin (Default)
1: AIN2 pin
MDIF1: ADC
0:
(AIN1/AIN2 pin: Default)
1:
(AIN+/AIN− pin)
PMMP: MPWR pin
0: Power down: Hi-Z (Default)
1: Power up
Addr
13H
Register Name
Mic Gain Control
Default
D7
0
0
D6
0
0
MGAIN1-0:
Default: “01”(+15dB)
Addr
14H
Register Name
Audio Format Select
Default
(See Table 20)
D7
0
0
DIF1-0:
Default: “11” (I2S)
BCKP: DSP Mode
“0”: “↑” SDTO
“1”: “↓” SDTO
D6
0
0
D5
1
1
D4
0
0
D3
MSBS
0
D2
BCKP
0
(See Table 15)
BCLK/EXBCLK
(Default)
MSBS: DSP Mode
LRCK/EXLRCK
“0”: LRCK/EXLRCK “↑”
“1”: LRCK/EXLRCK “↑”
(See Table 16)
(See Table 16)
BCLK/EXBCLK
BCLK/EXBCLK 1
MS0569-J-01
(Default)
2006/12
- 42 -
ASAHI KASEI
Addr
15H
Register Name
fs Select
Default
[AK5700]
D7
HPF1
0
D6
HPF0
0
D5
BCKO1
0
FS3-0:
(See Table 5 and Table 6)
Default: “1111” (44.1kHz)
PLL
BCKO1-0:
Default: “01” (32fs)
PS1-0: MCKO
Default: “00”(256fs)
D2
FS2
1
BCLK
D1
FS1
1
D0
FS0
1
(See Table 11)
EXT
MCKI
(See Table 10)
HPF
(See Table 17, Table 30)
Default: “00” (fc=3.4Hz@fs=44.1kHz, Init Cycle=3088/fs)
Register Name
Clock Output Select
Default
D3
FS3
1
MCKI
HPF1-0:
Addr
16H
D4
BCKO0
1
D7
0
0
D6
0
0
ADC
D5
0
0
D4
0
0
D3
THR
0
D2
MCKO
0
D1
PS1
0
D0
PS0
0
D5
IVL5
0
D4
IVL4
1
D3
IVL3
0
D2
IVL2
0
D1
IVL1
0
D0
IVL0
1
(See Table 9)
MCKO: MCKO
0: Disable: MCKO pin = “L” (Default)
1: Enable: Output frequency is selected by PS1-0 bits.
THR:
0: OFF (Default)
1: ON
Addr
18H
Register Name
Input Volume Control
Default
IVL7-0:
Default: “91H” (0dB)
(Table 14)
D7
IVL7
1
D6
IVL6
0
; 0.375dB step, 242 Level (See Table 29)
MS0569-J-01
2006/12
- 43 -
ASAHI KASEI
Addr
1AH
[AK5700]
Register Name
Timer Select
Default
D7
0
0
WTM1-0: ALC
Default: “00” (128/fs)
ALC
D6
0
0
D5
0
0
D4
0
0
D3
ZTM1
0
D2
ZTM0
0
D1
WTM1
0
D0
WTM0
0
D3
REF3
0
D2
REF2
0
D1
REF1
0
D0
REF0
1
D1
LMTH1
0
D0
LMTH0
0
(see Table 25)
ZTM1-0: ALC
Default: “00” (128/fs)
(see Table 24)
ALC
Addr
1BH
Register Name
ALC Mode Control 1
Default
D7
REF7
1
D6
REF6
1
REF7-0: ALC
Default: “E1H” (+30.0dB)
Addr
1CH
Register Name
ALC Mode Control 2
Default
LMAT1-0: ALC
Default: “00”
D6
ZELMN
0
D5
LMAT1
0
/
RGAIN1-0: ALC
Default: “00”
D4
REF4
0
0.375dB step, 242 Level (See Table 27)
D7
ALC
0
LMTH1-0: ALC
Default: “00”
D5
REF5
1
D4
LMAT0
0
D3
D2
RGAIN1
RGAIN0
0
0
(see Table 22)
(see Table 26)
ATT
(see Table 23)
ZELMN: ALC
0: Enable (Default)
1: Disable
ALC: ALC
0: ALC Disable (Default)
1: ALC Enable
MS0569-J-01
2006/12
- 44 -
ASAHI KASEI
Addr
1DH
Register Name
Mode Control 1
Default
[AK5700]
D7
TE3
1
TE3-0: EXT Master Mode Enable
“0101”
1EH
EXT Master Mode
“1010”, “0101”
Default: “1010”
Addr
1EH
Register Name
Mode Control 2
Default
D6
TE2
0
D5
TE1
1
D4
TE0
0
D3
0
0
D2
0
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
D1
0
0
D0
0
0
D1
D0
0
0
“1010”
D7
0
0
D6
0
0
TMASTER
0
TMASTER: EXT Master Mode
TE3-0 bits = “0101”
0: Except EXT Master Mode (Default)
1: EXT Master Mode
MS0569-J-01
2006/12
- 45 -
ASAHI KASEI
Figure 39
[AK5700]
Figure 40
(AKD5700)
17
16
15
14
CSN
CCLK
CDTI
MCKI
21 AIN2
AK5700VN
22 AIN
Top View
MCKO 10
BCLK
DSP
10u 0.1u
10u 0.1u
2.2u
0.1u
Cp
6
7
DVSS
LRCK
DVDD
24 VCOC
5
8
4
SDTO
AVDD
23 AIN1
3
9
Power Supply
2.4 ∼ 3.6V
Note:
- AK5700
- EXT
- PLL
Cp
- 100ms
11
CSP
Rp
0.1 x Cp
(Note)
EXBCLK 13
18
PDN
EXSDTI
AVSS
≤ 1u
20 TEST
2
Internal MIC
EXLRCK 12
VCOM
≤ 1u
DSP
19 MPWR
1
External MIC
2.2k
2.2k
μP
Power Supply
1.6 ∼ 3.6V
Analog Ground
Digital Ground
AVSS, DVSS
(PMPLL bit = “0”)
(PMPLL bit = “1”)
VCOC pin
Cp Rp Table 4
Cp+Rp
AC
Figure 39.
(
MS0569-J-01
0.1 x
1μF
)
2006/12
- 46 -
ASAHI KASEI
[AK5700]
17
16
15
14
CSN
CCLK
CDTI
MCKI
20 TEST
EXSDTI
21 AIN2
AK5700VN
22 AIN
Top View
11
MCKO 10
DVSS
BCLK
6
DSP
10u 0.1u
2.2u
0.1u
Cp
10u 0.1u
DVDD
7
5
LRCK
4
24 VCOC
AVDD
8
3
SDTO
AVSS
23 AIN1
2
9
VCOM
CSP
Power Supply
2.4 ∼ 3.6V
Note:
- AK5700
- EXT
- PLL
Cp
EXBCLK 13
18
EXLRCK 12
Rp
0.1 x Cp
(Note)
DSP
19 MPWR
1
Line In
PDN
μP
Power Supply
1.6 ∼ 3.6V
Analog Ground
Digital Ground
AVSS, DVSS
(PMPLL bit = “0”)
(PMPLL bit = “1”)
VCOC pin
Cp Rp Table 4
Figure 40.
(
MS0569-J-01
Cp+Rp
0.1 x
)
2006/12
- 47 -
ASAHI KASEI
[AK5700]
1.
AVDD, DVDD
AVDD, DVDD
AVSS, DVSS
PC
2.
AVDD pin
AVDD
AVSS
0.1μF
VCOM
2.2μF
0.1μF
AVSS
VCOM pin
VCOM pin
3.
“00”, 30kΩ (typ)@MGAIN1-0 bits = “01” or “10”
x AVDD Vpp(typ)@MGAIN 1-0 bits = “00”
fc=1/(2πRC)
DC
(ADC
DC
AK5700
60kΩ (typ)@MGAIN1-0 bits =
(0.5 x AVDD)
0.6
DC
2’s
(2
)
HPF(fc=3.4Hz@HPF1-0 bits = “00”, fs=44.1kHz)
AVSS
AVDD
)
MS0569-J-01
2006/12
- 48 -
ASAHI KASEI
[AK5700]
„
ADC
Power-up
1. PLL
Example:
Audio I/F Format: I2S
BCLK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
Power Supply
(1)
PDN pin
(2)
(3)
PMVCM bit
(Addr:10H, D2)
(1) Power Supply & PDN pin = “L” Æ “H”
(4)
MCKO bit
(Addr:16H, D2)
(2)Addr:11H, Data:12H
Addr:14H, Data:23H
Addr:15H, Data:2FH
PMPLL bit
(Addr:11H, D0)
(5)
MCKI pin
Input
(3)Addr:10H, Data:04H
M/S bit
(Addr:11H, D1)
40msec(max)
(6)
BCLK pin
LRCK pin
Output
(4)Addr:16H, Data:04H
Addr:11H, Data:13H
Output
MCKO, BCLK and LRCK output
40msec(max)
(8)
MCKO pin
(7)
Figure 41. Clock Set Up Sequence (1)
<
>
PDN pin “L” Æ “H”
AK5700
150ns
“L”
(2)
DIF1-0, PLL3-0, FS3-0, BCKO1-0, M/S bits
(2a) M/S bit = “1” , PLL3-0, FS3-0, BCKO1-0
(2b) DIF1-0
(3) VCOM
: PMVCM bit = “0” Æ “1”
VCOM
(4) MCKO
: MCKO bit = “1”
MCKO
: MCKO bit = “0”
(5) PMPLL bit = “0” Æ “1”
MCKI pin
PLL
MCKI=12MHz
40ms(max)
(Table 4)
(6) PLL
BCLK, LRCK
(7) MCKO bit = “1”
MCKO pin
(8) MCKO bit = “1”
PLL
MCKO pin
(1)
MS0569-J-01
PLL
2006/12
- 49 -
ASAHI KASEI
[AK5700]
2. PLL
(EXLRCK or EXBCLK pin)
Example:
Audio I/F Format : I2S
PLL Reference clock: EXBCLK
EXBCLK frequency: 64fs
Sampling Frequency: 44.1kHz
Power Supply
(1)
PDN pin
(2)
4fs
(1)ofPower Supply & PDN pin = “L” Æ “H”
(3)
PMVCM bit
(Addr:10H, D2)
(2) Addr:11H, Data:0CH
Addr:14H, Data:23H
Addr:15H, Data:2FH
PMPLL bit
(Addr:11H, D0)
EXLRCK pin
EXBCLK pin
Input
(3) Addr:10H, Data:04H
(4)
Internal Clock
(5)
(4) Addr:11H, Data:0DH
Figure 42. Clock Set Up Sequence (2)
<
>
PDN pin “L” Æ “H”
AK5700
150ns
“L”
(2)
DIF1-0, FS3-0, PLL3-0 bits
(3) VCOM
: PMVCM bit = “0” Æ “1”
VCOM
(4) PMPLL bit = “0” Æ “1”
PLL
(EXLRCK or EXBCLK pin)
PLL
EXLRCK PLL
EXBCLK PLL
VCOC pin
10k+4.7nF
2ms(max)
(5) PLL
(1)
MS0569-J-01
PLL
160ms(max),
(Table 4)
2006/12
- 50 -
ASAHI KASEI
[AK5700]
3. PLL
(MCKI pin)
Example:
Audio I/F Format: I2S
BCLK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
Power Supply
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(2)
(2)Addr:11H, Data:10H
Addr:14H, Data:23H
Addr:15H, Data:2FH
(3)
PMVCM bit
(Addr:10H, D2)
(4)
MCKO bit
(Addr:16H, D2)
(3)Addr:10H, Data:04H
PMPLL bit
(Addr:11H, D0)
(5)
MCKI pin
(4)Addr:16H, Data:04H
Addr:11H, Data:11H
Input
40msec(max)
(6)
MCKO pin
MCKO output start
Output
(7)
(8)
EXBCLK pin
EXLRCK pin
Input
EXBCLK and EXLRCK input start
Figure 43. Clock Set Up Sequence (3)
<
>
PDN pin “L” Æ “H”
AK5700
150ns
“L”
(2)
DIF1-0, PLL3-0, FS3-0, BCKO1-0, M/S bits
(3) VCOM
PMVCM bit = “0” Æ “1”
VCOM
(4) MCKO
: MCKO bit = “1”
(5) PMPLL bit = “0” Æ “1”
MCKI pin
PLL
MCKI=12MHz
40ms(max)
(Table 4)
(6) PLL
MCKO pin
(7)
MCKO pin
(8) MCKO
EXBCLK, EXLRCK
(1)
MS0569-J-01
PLL
2006/12
- 51 -
ASAHI KASEI
[AK5700]
4.
(
)
Example:
Audio I/F Format: I2S
Input MCKI frequency: 256fs
Sampling Frequency: 44.1kHz
MCKO: Disable
(1) Power Supply & PDN pin = “L” Æ “H”
Power Supply
(1)
PDN pin
(2)
(2) Addr:11H, Data:00H
Addr:14H, Data:23H
Addr:15H, Data:2FH
(3)
PMVCM bit
(Addr:10H, D2)
(4)
MCKI pin
Input
(3) Addr:10H, Data:04H
(4)
EXLRCK pin
EXBCLK pin
Input
MCKI, EXBCLK and EXLRCK input
Figure 44. Clock Set Up Sequence (4)
<
>
PDN pin “L” Æ “H”
AK5700
150ns
(2)
DIF1-0, FS1-0 bits
(3) VCOM
PMVCM bit = “0” Æ “1”
VCOM
(4) MCKI, EXLRCK, EXBCLK
(1)
MS0569-J-01
“L”
2006/12
- 52 -
ASAHI KASEI
[AK5700]
5.
(
)
Power Supply
(1)
Example:
PDN pin
(2)
Audio I/F Format: I2S
BCLK frequency at Master Mode: 64fs
Input Master Clock Select: 256fs
Sampling Frequency: 44.1kHz
(3)
PMVCM bit
(Addr:10H, D2)
MCKI pin
(1) Power Supply & PDN pin = “L” Æ “H”
Input
M/S bit
(Addr:11H, D1)
TE3-0 bits
"1010"
(Addr:1DH, D7-4)
(2)Addr:11H, Data:26H
Addr:14H, Data:23H
Addr:15H, Data:2FH
Addr:1DH, Data:50H
Addr:1EH, Data:02H
BCLK and LRCK output
"0101"
TMASTER bit
(Addr:1EH, D1)
BCLK pin
LRCK pin
Output
(3)Addr:10H, Data:04H
Figure 45. Clock Set Up Sequence (5)
<
>
(1)
(2)
PDN pin “L” Æ “H”
AK5700
150ns
“L”
DIF1-0, FS1-0, BCKO1-0, M/S, TE3-0, TMASTER bits
(2a) M/S bit = “1”, FS3-0, BCKO1-0
(2b) DIF1-0
(2c) TE3-0 bits = “0101”
(2d) TMASTER bit = “1”: BCLK, LRCK
(3) VCOM
PMVCM bit = “0” Æ “1”
VCOM
EXT Master Mode
“1010”
PDN pin = “L” Æ “H”
TE3-0 bits =
Table 1
MS0569-J-01
2006/12
- 53 -
ASAHI KASEI
6.
[AK5700]
&
Example:
Audio I/F Format : I2S
PLL Reference clock: EXBCLK
EXBCLK frequency: 64fs
Sampling Frequency: 44.1kHz
Power Supply
(1)
4fs
(1)ofPower Supply & PDN pin = “L” Æ “H”
PDN pin
(2)
(3)
PMVCM bit
(2) Addr:11H, Data:0CH
Addr:14H, Data:23H
Addr:15H, Data:2FH
Addr:16H, Data:08H
(Addr:10H, D2)
PMPLL bit
(Addr:11H, D0)
EXLRCK pin
EXBCLK pin
Input
(3) Addr:10H, Data:04H
(4)
Internal Clock
(5)
(4) Addr:11H, Data:0DH
Figure 46. Clock Set Up Sequence (6)
<
>
PDN pin “L” Æ “H”
AK5700
150ns
“L”
(2)
THR bit = “1”
DIF1-0, FS3-0, PLL3-0 bits
(3) VCOM
: PMVCM bit = “0” Æ “1”
VCOM
(4) PMPLL bit = “0” Æ “1”
PLL
(EXLRCK or EXBCLK pin)
PLL
EXLRCK PLL
EXBCLK PLL
VCOC pin
10k+4.7nF
2ms(max)
(5) PLL
(1)
MS0569-J-01
PLL
160ms(max),
(Table 4)
2006/12
- 54 -
ASAHI KASEI
[AK5700]
7.
Power Supply
(1)
(1) Power Supply & PDN pin = “L” Æ “H”
PDN pin
(2)
THR bit
(2) Addr:16H, Data:08H
(Addr:16H, D3)
(3)
EXLRCK pin
EXBCLK pin
EXSDTI pin
Input
MCKI, EXBCLK and EXLRCK input
Figure 47. Clock Set Up Sequence (7)
<
>
PDN pin “L” Æ “H”
AK5700
150ns
“L”
(2) THR bit = “1”
(3) EXLRCK, EXBCLK, EXSDTI
LRCK, BCLK, SDTO
(1)
MS0569-J-01
2006/12
- 55 -
ASAHI KASEI
[AK5700]
„
Example:
PLL Master Mode
Audio I/F Format:I2S
Sampling Frequency:44.1kHz
Pre MIC AMP:+15dB
MIC Power On
ALC setting:Refer to Figrure 37
ALC bit = “1”
(1) Addr:15H, Data:2FH
FS3-0 bits
(Addr:15H, D3-0)
X,XXX
1111
(2) Addr:12H, Data:10H
Addr:13H, Data:01H
(1)
MIC Control
(Addr:12H, D4
& Addr:13H, D1-0)
Timer Control
(Addr:1AH)
ALC Control 1
(Addr:1BH)
ALC Control 2
(Addr:1CH)
0, 01
1, 01
(3) Addr:1AH, Data:0AH
(2)
XXH
0AH
(4) Addr:1BH, Data:E1H
(3)
XXH
E1H
(5) Addr:1CH, Data:81H
(4)
XXH
81H
01H
ALC State
(6) Addr:10H, Data:05H
(8)
(5)
ALC Disable
ALC Enable
ALC Disable
Recording
PMADC bit
(Addr:10H, D0)
3088 / fs
(7) Addr:10H, Data:04H
(7)
(6)
ADC Internal
State
Power Down
Initialize Normal State Power Down
(8) Addr:1CH, Data:01H
Figure 48. MIC Input Recording Sequence
<
>
fs=44.1kHz
”
(1)
ALC
ALC
“Figure 35. ALC
(FS3-0 bits)
PLL
ADC
PLL
(6)
(2)
(
12H&13H)
(3) ALC Timer (
1AH)
(4) ALC REF (
1BH)
(5) LMTH1-0, RGAIN1-0, LMAT1-0, ALC bits
(
1CH)
(6)
ADC
: PMADC bit = “0” → “1”
ADC
3088/fs=70.0ms@fs=44.1kHz, HPF1-0 bits = “00”
ALC
(IVL7-0 bits)
(0dB)
100ms
PMVCM=PMMP bits = “1”
2ms PMPLL bit = “1”
6ms
PMADC bit = “1”
(7)
ADC
: PMADC bit = “1” → “0”
ADC
ALC Disable
ALC
(ALC bit = “0”)
(PMADC bit = “0”)
PMADC bit = “0”
(IVL7-0 bits)
ADC
(8) ALC Disable: ALC bit = “1” → “0”
MS0569-J-01
2006/12
- 56 -
ASAHI KASEI
[AK5700]
„
ADC
1. PLL
Example:
(1)
Audio I/F Format: I2S
BCLK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
Sampling Frequency: 44.1kHz
PMPLL bit
(Addr:11H, D0)
M/S bit
(Addr:11H, D1)
(1) Addr:11H, Data:10H
(2)
MCKO bit
"H" or "L"
(2) Addr:16H, Data:00H
(Addr:16H, D2)
(3)
External MCKI
Input
(3) Stop an external MCKI
Figure 49. Clock Stopping Sequence (1)
<
>
(1) PLL
(2) MCKO
(3)
: PMPLL=M/S bits = “1” → “0”
: MCKO bit = “1” → “0”
2. PLL
(EXLRCK, EXBCLK pin)
Example
Audio I/F Format : I2S
PLL Reference clock: EXBCLK
BCLK frequency: 64fs
Sampling Frequency: 44.1kHz
(1)
PMPLL bit
(Addr:11H, D0)
(2)
EXBCLK
Input
(1) Addr:11H, Data:0CH
(2)
EXLRCK
Input
(2) Stop the external clocks
Figure 50. Clock Stopping Sequence (2)
<
>
(1) PLL
(2)
*
: PMPLL bit = “1” → “0”
&
MS0569-J-01
2006/12
- 57 -
ASAHI KASEI
[AK5700]
3. PLL
(MCKI pin)
Example
Audio I/F Format: I2S
PLL Reference clock: MCKI=11.2896MHz
EXBCLK frequency: 64fs
Sampling Frequency: 44.1kHz
(1)
PMPLL bit
(1) Addr:11H, Data:10H
(Addr:11H, D0)
(2)
MCKO bit
(2) Addr:16H, Data:00H
(Addr:16H, D2)
(3)
External MCKI
Input
(3) Stop the external clocks
Figure 51. Clock Stopping Sequence (3)
<
>
(1) PLL
(2) MCKO
(3)
: PMPLL bit = “1” → “0”
: MCKO bit = “1” → “0”
4.
(
)
(1)
External MCKI
Input
Example
(1)
EXBCLK
Input
EXLRCK
Input
Audio I/F Format :I2S
Input MCKI frequency:256fs
Sampling Frequency:44.1kHz
(1)
(1) Stop the external clocks
Figure 52. Clock Stopping Sequence (4)
<
>
(1)
*
5.
(
)
(1)
External MCKI
Input
Example
BCLK
Output
"H" or "L"
LRCK
Output
"H" or "L"
Audio I/F Format :I2S
Input MCKI frequency:256fs
Sampling Frequency:44.1kHz
(1) Stop MCKI
Figure 53. Clock Stopping Sequence (5)
<
>
(1) MCKI
BCLK
LRCK
“H”
MS0569-J-01
“L”
2006/12
- 58 -
ASAHI KASEI
[AK5700]
„
(typ. 1μA)
PMVCM bit = “0”
PDN pin = “L”
MS0569-J-01
20μA(typ)
2006/12
- 59 -
ASAHI KASEI
[AK5700]
24pin QFN (Unit: mm)
4.0 ± 0.1
2.4 ± 0.15
13
18
19
2.4± 0.15
4.0 ± 0.1
12
A
Exposed
Pad
24
7
0.40 ± 0.1
6
1
B
0.2
0.08
0.5
:
0.10 M
PIN #1 ID
(0.35 x 45 )
0.75± 0.05
0.23 ± 0.05
(Exposed Pad)
„
:
:
:
MS0569-J-01
2006/12
- 60 -
ASAHI KASEI
[AK5700]
5700
XXXX
1
XXXX : Date code identifier (4
Date (YY/MM/DD)
06/11/16
06/12/25
Revision
00
01
)
Reason
Page
Contents
Error correct
40
Register Map (Addr=17H)
Bit (D0) value was changed: 0 → 1
•
•
•
•
•
•
MS0569-J-01
2006/12
- 61 -