データシート

ASAHI KASEI
[AK4647]
AK4647
Stereo CODEC with MIC/HP-AMP
AK4647
CODEC
AK4647
PLL
48pin
LQFP
1.
2.
•
(
or
)
•
•
(+32dB/+26dB/+20dB or 0dB)
• Digital ALC (Automatic Level Control)
(+36dB ∼ −54dB, 0.375dB Step, Mute)
• ADC
: S/(N+D): 83dB, DR, S/N: 86dB (MIC-Amp=+20dB)
S/(N+D): 88dB, DR, S/N: 95dB (MIC-Amp=0dB)
•
•
• Programmable EQ
•
(tc=50/15μs, fs=32kHz, 44.1kHz, 48kHz)
•
•
•
(+12dB ∼ −115.0dB, 0.5dB Step, Mute)
• Digital ALC (Automatic Level Control)
(+36dB ∼ −54dB, 0.375dB Step, Mute)
•
• Programmable EQ
•
: S/(N+D): 88dB, S/N: 92dB
•
- HP-AMP
: S/(N+D): 70dB, S/N: 90dB
: 62mW@16Ω (HVDD=3.3V)
ON/OFF
•
:
3.
4.
:
(1) PLL
•
(2)
5.
•
: 11.2896MHz,12MHz,12.288MHz,13.5MHz,24MHz,27MHz (MCKI pin)
1fs (LRCK pin)
32fs or 64fs (BICK pin)
: 256fs, 512fs or 1024fs (MCKI pin)
: 32fs/64fs/128fs/256fs
MS0566-J-00
2006/11
-1-
ASAHI KASEI
6.
7.
8.
9.
[AK4647]
:
• PLL Slave Mode (LRCK pin): 7.35kHz ∼ 48kHz
• PLL Slave Mode (BICK pin): 7.35kHz ∼ 48kHz
• PLL Slave Mode (MCKI pin):
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• PLL Master Mode:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• EXT Slave Mode:
7.35kHz ∼ 48kHz (256fs), 7.35kHz ∼ 26kHz (512fs), 7.35kHz ∼ 13kHz (1024fs)
(Ver 1.0, 400kHz
)
μP
:3
, I2C
: MSB First, 2’s complement
• ADC : 16bit
, I2S
• DAC : 16bit
, 16bit
, 16-24bit I2S
10. Ta = −40 ∼ 85°C
11.
:
• AVDD, DVDD: 2.6 ∼ 3.6V (typ. 3.3V)
• HVDD: 2.6 ∼ 5.25V (typ. 3.3V/5.0V)
12.
: 48pin LQFP
„
AVDD
AVSS
VCOM
DVDD
DVSS
PMMP
MPWR
CSN
CCLK
CDTI
PMADL or PMADR
RIN1
MIC-Amp
LIN2
External
MIC
Control
Register
PMADL
LIN1
Internal
MIC
I2C
MIC Power
Supply
A/D
Wind-Noise
Reduction
HPF
Stereo
Separation
PDN
ALC
PMADR
BICK
RIN2
LRCK
or
SDTO
Audio
I/F
SDTI
Line In
PMLO
LOUT
Line Out
ROUT
PMHPL
PMDAC
D/A
HPL
Headphone
Stereo
DATT Bass ALC
Separation
SMUTE Boost
HPF
PMHPR
HPR
MCKO
PMPLL
MUTET
PLL
MCKI
VCOC
PMBP
HVDD
HVSS
MIN
Figure 1.
MS0566-J-00
2006/11
-2-
ASAHI KASEI
[AK4647]
„
−40 ∼ +85°C
AK4647
AK4647VQ
AKD4647
48pin LQFP (0.5mm pitch)
MUTET
HPL
HPR
HVSS
HVDD
TEST2
TEST1
NC
NC
MCKO
MCKI
NC
36
35
34
33
32
31
30
29
28
27
26
25
„
NC
37
24
NC
NC
38
23
DVSS
ROUT
39
22
DVDD
LOUT
40
21
BICK
NC
41
20
LRCK
MIN
42
19
NC
NC
43
18
SDTO
RIN2/IN2−
44
17
SDTI
LIN2/IN2+
45
16
CDTI/SDA
LIN1/IN1−
46
15
CCLK/SCL
RIN1/IN1+
47
14
CSN/CAD0
MPWR
48
13
NC
AK4647VQ
1
2
3
4
5
6
7
8
9
10
11
12
NC
VCOM
AVSS
NC
AVDD
VCOC
I2C
NC
PDN
NC
NC
NC
Top View
MS0566-J-00
2006/11
-3-
ASAHI KASEI
No.
Pin Name
[AK4647]
I/O
1
NC
-
2
VCOM
O
3
AVSS
-
4
NC
-
5
AVDD
-
6
VCOC
O
7
I2C
I
8
NC
-
9
PDN
I
10
NC
-
11
NC
-
12
NC
-
13
NC
-
17
18
CSN
CAD0
CCLK
SCL
CDTI
SDA
SDTI
SDTO
19
NC
20
21
22
23
LRCK
BICK
DVDD
DVSS
24
NC
14
15
16
Function
NC
, 0.45 x AVDD
ADC
NC
PLL
AVSS
“H”: I2C
NC
, “L”: 3
“H”:
“L”:
NC
NC
NC
NC
I
I
I
I
I
I/O
I
O
-
DAC
0
(I2C pin = “L” : 3
(I2C pin = “H” : I2C
)
(I2C pin = “L” : 3
(I2C pin = “H” : I2C
(I2C pin = “L” : 3
(I2C pin = “H” : I2C
)
)
)
)
)
NC
I/O
I/O
-
NC
MS0566-J-00
2006/11
-4-
ASAHI KASEI
[AK4647]
No.
Pin Name
25
NC
-
26
27
MCKI
MCKO
I
O
28
NC
-
29
NC
-
30
TEST1
-
31
TEST2
-
32
33
34
35
HVDD
HVSS
HPR
HPL
O
O
36
MUTET
O
37
NC
-
38
NC
-
39
40
ROUT
LOUT
O
O
41
NC
-
42
MIN
I
43
NC
-
44
45
46
47
48
Note 1.
I/O
RIN2
IN2−
LIN2
IN2+
LIN1
IN1−
RIN1
IN1+
MPWR
Note 2. I2C pin
Function
NC
NC
NC
1
2
Rch
Lch
HVSS
NC
NC
Rch
Lch
NC
NC
I
Rch
2
(MDIF2 bit = “0” :
I
2
(MDIF2 bit = “1” :
I
Lch
2
(MDIF2 bit = “0” :
I
2
(MDIF2 bit = “1” :
I
Lch
1
(MDIF1 bit = “0” :
I
1
(MDIF1 bit = “1” :
I
Rch
1
(MDIF1 bit = “0” :
I
1
(MDIF1 bit = “1” :
O
(MIN, LIN1, RIN1, LIN2, RIN2)
AVDD
)
)
)
)
)
)
)
)
AVSS
MS0566-J-00
2006/11
-5-
ASAHI KASEI
[AK4647]
„
Analog
Digital
MPWR, VCOC, HPR, HPL, MUTET, ROUT, LOUT,
MIN, RIN2/IN2−, LIN2/IN2+, LIN1/IN1−,
RIN1/IN1+
MCKO
MCKI
DVSS
(AVSS, DVSS, HVSS=0V; Note 3)
Parameter
Power Supplies:
Analog
Digital
Headphone-Amp
|AVSS – DVSS|
|AVSS – HVSS|
Input Current, Any Pin Except Supplies
Analog Input Voltage (Note 5)
Digital Input Voltage (Note 6)
Ambient Temperature (powered applied)
Storage Temperature
(Note 4)
(Note 4)
Symbol
AVDD
DVDD
HVDD
ΔGND1
ΔGND2
IIN
VINA
VIND
Ta
Tstg
min
−0.3
−0.3
−0.3
−0.3
−0.3
−30
−65
max
6.0
6.0
6.0
0.3
0.3
±10
AVDD+0.3
DVDD+0.3
85
150
Units
V
V
V
V
V
mA
V
V
°C
°C
Max
3.6
3.6
5.25
+0.3
Units
V
V
V
V
Note 3.
Note 4. AVSS DVSS, HVSS
Note 5. I2C, MIN, RIN2/IN2−, LIN2/IN2+, LIN1/IN1−, RIN1/IN1+ pins
Note 6. PDN, CSN/CAD0, CCLK/SCL, CDTI/SDA, SDTI, LRCK, BICK, MCKI pins
SDA, SCL pins
(DVDD+0.3)V
:
(AVSS, DVSS, HVSS=0V; Note 3)
Parameter
Power Supplies Analog
(Note 7) Digital
HP-Amp
Difference
Note 3.
Note 7. AVDD, DVDD, HVDD
OFF
DVDD
HVDD OFF
Symbol
AVDD
DVDD
HVDD
AVDD−DVDD
ON
min
2.6
2.6
2.6
−0.3
typ
3.3
3.3
3.3 / 5.0
0
PDN pin = “L”
DVDD
AVDD, HVDD
OFF
OFF
AVDD,
:
MS0566-J-00
2006/11
-6-
ASAHI KASEI
[AK4647]
(Ta=25°C; AVDD, DVDD, HVDD=3.3V; AVSS=DVSS=HVSS=0V; fs=44.1kHz, BICK=64fs;
Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified)
min
typ
max
Parameter
MIC Amplifier: LIN1, RIN1, LIN2, RIN2 pins; MDIF1 = MDIF2 bits = “0” (Single-ended inputs)
Input
MGAIN1-0 bits = “00”
40
60
80
Resistance MGAIN1-0 bits = “01”, “10”or “11”
20
30
40
MGAIN1-0 bits = “00”
0
MGAIN1-0 bits = “01”
+20
Gain
MGAIN1-0 bits = “10”
+26
MGAIN1-0 bits = “11”
+32
MIC Amplifier: IN1+, IN1−, IN2+, IN2− pins; MDIF1 = MDIF2 bits = “1” (Full-differential input)
Input Voltage (Note 8)
MGAIN1-0 bits = “01”
0.228
MGAIN1-0 bits = “10”
0.114
MGAIN1-0 bits = “11”
0.057
MIC Power Supply: MPWR pin
Output Voltage (Note 9)
2.22
2.47
2.72
Load Resistance
0.5
Load Capacitance
30
ADC Analog Input Characteristics: LIN1/RIN1/LIN2/RIN2 pins → ADC → IVOL, IVOL=0dB, ALC=OFF
Resolution
16
(Note 11)
0.168
0.198
0.228
Input Voltage (Note 10)
(Note 12)
1.68
1.98
2.28
(Note 11)
71
83
S/(N+D) (−1dBFS)
(Note 12)
88
(Note 11)
76
86
D-Range (−60dBFS, A-weighted)
(Note 12)
95
(Note 11)
76
86
S/N
(A-weighted)
(Note 12)
95
(Note 11)
75
90
Interchannel Isolation
(Note 12)
100
(Note 11)
0.1
0.8
Interchannel Gain Mismatch
(Note 12)
0.1
0.8
Units
kΩ
kΩ
dB
dB
dB
dB
Vpp
Vpp
Vpp
V
kΩ
pF
Bits
Vpp
Vpp
dBFS
dBFS
dB
dB
dB
dB
dB
dB
dB
dB
Note 8.
AC
MGAIN1-0 bits = “00”
IN1+, IN1−, IN2+, IN2− pin
AVDD
Vin = |(IN+) − (IN−)| = 0.069 x AVDD
(max)@MGAIN1-0 bits = “01”, 0.035 x AVDD (max)@MGAIN1-0 bits = “10”, 0.017 x AVDD
(max)@MGAIN1-0 bits = “11”.
ADC
Note 9.
AVDD
Vout = 0.75 x AVDD (typ)
Note 10.
AVDD
Vin = 0.06 x AVDD (typ)@MGAIN1-0 bits = “01” (+20dB), Vin = 0.6 x
AVDD(typ)@MGAIN1-0 bits = “00” (0dB)
Note 11. MGAIN1-0 bits = “01” (+20dB)
Note 12. MGAIN1-0 bits = “00” (0dB)
MS0566-J-00
2006/11
-7-
ASAHI KASEI
[AK4647]
min
typ
max
Units
Parameter
DAC Characteristics:
Resolution
16
Bits
Stereo Line Output Characteristics: DAC → LOUT, ROUT pins, ALC=OFF, IVOL=0dB, DVOL=0dB, LOVL bit =
“0”, RL=10kΩ
Output Voltage (Note 13)
LOVL bit = “0”
1.78
1.98
2.18
Vpp
LOVL bit = “1”
2.25
2.50
2.75
Vpp
S/(N+D) (−3dBFS)
78
88
dBFS
S/N
(A-weighted)
82
92
dB
Interchannel Isolation
80
100
dB
Interchannel Gain Mismatch
0.1
0.5
dB
Load Resistance
10
kΩ
Load Capacitance
30
pF
Headphone-Amp Characteristics: DAC → HPL/HPR pins, ALC=OFF, IVOL=0dB, DVOL=0dB
Output Voltage (Note 14)
1.58
1.98
2.38
Vpp
HPG bit = “0”, 0dBFS, HVDD=3.3V, RL=22.8Ω
2.40
3.00
3.60
Vpp
HPG bit = “1”, 0dBFS, HVDD=5V, RL=100Ω
HPG bit = “1”, 0dBFS, HVDD=3.3V, RL=16Ω (Po=62mW)
1.0
Vrms
S/(N+D)
60
70
dBFS
HPG bit = “0”, −3dBFS, HVDD=3.3V, RL=22.8Ω
80
dBFS
HPG bit = “1”, −3dBFS, HVDD=5V, RL=100Ω
HPG bit = “1”, 0dBFS, HVDD=3.3V, RL=16Ω (Po=62mW)
20
dBFS
(Note 15)
80
90
dB
S/N
(A-weighted)
(Note 16)
90
dB
(Note 15)
65
75
dB
Interchannel Isolation
(Note 16)
80
dB
(Note 15)
0.1
0.8
dB
Interchannel Gain Mismatch
(Note 16)
0.1
0.8
dB
Load Resistance
16
Ω
30
pF
Figure 2 C1
Load Capacitance
300
pF
Figure 2 C2
Note 13.
Note 14.
AVDD
Vout = 0.6 x AVDD (typ)@LOVL bit = “0”.
AVDD
Vout = 0.6 x AVDD(typ)@HPG bit = “0”, 0.91 x AVDD(typ)@HPG bit = “1”.
Note 15. HPG bit = “0”, HVDD=3.3V, RL=22.8Ω.
Note 16. HPG bit = “1”, HVDD=5V, RL=100Ω.
HP-Amp
HPL/HPR pin
Measurement Point
47μF
C1
0.22μF
6.8Ω
C2
16Ω
10Ω
Figure 2.
MS0566-J-00
2006/11
-8-
ASAHI KASEI
[AK4647]
min
Parameter
Mono Input: MIN pin (External Input Resistance=20kΩ)
Maximum Input Voltage (Note 17)
Gain (Note 18)
MIN Æ LOUT/ROUT
LOVL bit = “0”
−4.5
LOVL bit = “1”
MIN Æ HPL/HPR
HPG bit = “0”
−24.5
HPG bit = “1”
Power Supplies:
Power Up (PDN pin = “H”)
All Circuit Power-up:
AVDD+DVDD
(Note 19)
HVDD: HP-Amp Normal Operation
No Output
(Note 20)
Power Down (PDN pin = “L”) (Note 21)
AVDD+DVDD+HVDD
-
typ
max
Units
1.98
-
Vpp
0
+2
−20
−16.4
+4.5
−15.5
-
dB
dB
dB
dB
15
23
mA
5
8
mA
10
100
μA
Note 17.
AVDD
(Rin)
Vin = 0.6 x AVDD x Rin / 20kΩ (typ).
Note 18.
Note 19. PLL Master Mode (MCKI=12.288MHz)
PMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR =
PMVCM = PMPLL = MCKO = PMBP = PMMP = M/S bits = “1”
MPWR pin
0mA
AVDD=11mA(typ), DVDD=4mA(typ).
EXT Slave Mode (PMPLL = M/S = MCKO bits = “0”)
: AVDD=10mA(typ), DVDD=3mA(typ).
Note 20. PMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR = PMVCM = PMPLL = PMBP bits = “1”
Note 21.
DVDD
DVSS
MS0566-J-00
2006/11
-9-
ASAHI KASEI
[AK4647]
(Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V; fs=44.1kHz; DEM=OFF; FIL1=FIL3=EQ=OFF)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
Passband (Note 22)
PB
0
17.3
kHz
±0.16dB
19.4
kHz
−0.66dB
19.9
kHz
−1.1dB
22.1
kHz
−6.9dB
Stopband
SB
26.1
kHz
Passband Ripple
PR
dB
±0.1
Stopband Attenuation
SA
73
dB
Group Delay (Note 23)
GD
19
1/fs
Group Delay Distortion
0
ΔGD
μs
ADC Digital Filter (HPF): (Note 24)
Frequency Response (Note 22) −3.0dB
FR
0.9
Hz
2.7
Hz
−0.5dB
6.0
Hz
−0.1dB
DAC Digital Filter (LPF):
Passband (Note 22)
PB
0
19.6
kHz
±0.1dB
20.0
kHz
−0.7dB
22.05
kHz
−6.0dB
Stopband
SB
25.2
kHz
Passband Ripple
PR
dB
±0.01
Stopband Attenuation
SA
59
dB
Group Delay (Note 23)
GD
22
1/fs
DAC Digital Filter (LPF) + SCF:
FR
dB
Frequency Response: 0 ∼ 20.0kHz
±1.0
DAC Digital Filter (HPF): (Note 24)
Frequency Response (Note 22) −3.0dB
FR
0.9
Hz
2.7
Hz
−0.5dB
6.0
Hz
−0.1dB
BOOST Filter: (Note 25)
Frequency Response
MIN
FR
20Hz
dB
5.76
100Hz
dB
2.92
1kHz
dB
0.02
MID
FR
20Hz
dB
10.80
100Hz
dB
6.84
1kHz
dB
0.13
MAX 20Hz
FR
dB
16.06
100Hz
dB
10.54
1kHz
dB
0.37
Note 22.
Note 23.
fs (
PB=20.0kHz(@−0.7dB)
)
0.454 x fs
(DAC)
ADC
1kHz
16
PMADL=PMADR bits = “0”
DAC
Group Delay 22/fs(typ)
Note 24. PMADL bit = “1” or PMADR bit = “1”
ADC HPF ON DAC HPF OFF
PMADL=PMADR bits = “0”, PMDAC bit = “1”
DAC HPF ON ADC HPF
Note 25.
16
DAC
MS0566-J-00
OFF
2006/11
- 10 -
ASAHI KASEI
[AK4647]
DC
(Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V)
Parameter
Symbol
VIH
High-Level Input Voltage
2.2V≤DVDD≤3.6V
Low-Level Input Voltage
VIH
2.2V≤DVDD≤3.6V
High-Level Output Voltage
VOH
(Iout=−200μA)
Low-Level Output Voltage
VOL
(Except SDA pin: Iout=200μA)
(SDA pin: Iout=3mA)
VOL
Input Leakage Current
Iin
min
70%DVDD
DVDD−0.2
typ
-
Max
30%DVDD
-
Units
V
V
V
-
-
0.2
0.4
±10
V
V
μA
(Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V; CL=20pF; unless otherwise specified)
Parameter
Symbol
min
typ
max
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
27
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
MCKO Output Timing
Frequency
fMCK
0.2352
12.288
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
256fs at fs=32kHz, 29.4kHz
dMCK
33
LRCK Output Timing
Frequency
fs
7.35
48
Duty Cycle
Duty
50
BICK Output Timing
Period
BCKO bit = “0”
tBCK
1/(32fs)
BCKO bit = “1”
tBCK
1/(64fs)
Duty Cycle
dBCK
50
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
27
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
MCKO Output Timing
Frequency
fMCK
0.2352
12.288
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
256fs at fs=32kHz, 29.4kHz
dMCK
33
LRCK Input Timing
Frequency
fs
7.35
48
Duty
Duty
45
55
BICK Input Timing
Period
tBCK
1/(64fs)
1/(32fs)
Pulse Width Low
tBCKL
0.4 x tBCK
Pulse Width High
tBCKH
0.4 x tBCK
-
MS0566-J-00
Units
MHz
ns
ns
MHz
%
%
kHz
%
ns
ns
%
MHz
ns
ns
MHz
%
%
kHz
%
ns
ns
ns
2006/11
- 11 -
ASAHI KASEI
[AK4647]
Parameter
Symbol
PLL Slave Mode (PLL Reference Clock = LRCK pin)
LRCK Input Timing
Frequency
fs
Duty
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
fs
Duty
Duty
BICK Input Timing
Period
PLL3-0 bits = “0010”
tBCK
PLL3-0 bits = “0011”
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
External Slave Mode
MCKI Input Timing
Frequency
256fs
fCLK
512fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Input Timing
Frequency
256fs
fs
512fs
fs
1024fs
fs
Duty
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
Audio Interface Timing
Master Mode
tMBLR
BICK “↓” to LRCK Edge (Note 26)
tLRD
LRCK Edge to SDTO (MSB)
(Except I2S mode)
tBSD
BICK “↓” to SDTO
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Slave Mode
tLRB
LRCK Edge to BICK “↑” (Note 26)
tBLR
BICK “↑” to LRCK Edge (Note 26)
tLRD
LRCK Edge to SDTO (MSB)
(Except I2S mode)
tBSD
BICK “↓” to SDTO
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Note 26.
LRCK
BICK “↑”
MS0566-J-00
min
typ
max
Units
7.35
45
-
48
55
kHz
%
1/(64fs)
130
130
-
1/(32fs)
-
ns
ns
ns
7.35
45
-
48
55
kHz
%
0.4 x tBCK
0.4 x tBCK
1/(32fs)
1/(64fs)
-
-
ns
ns
ns
ns
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
-
12.288
13.312
13.312
-
MHz
MHz
MHz
ns
ns
7.35
7.35
7.35
45
-
48
26
13
55
kHz
kHz
kHz
%
312.5
130
130
-
-
ns
ns
ns
−40
−70
-
40
70
ns
ns
−70
50
50
-
70
-
ns
ns
ns
50
50
-
-
80
ns
ns
ns
50
50
-
80
-
ns
ns
ns
2006/11
- 12 -
ASAHI KASEI
[AK4647]
Parameter
Control Interface Timing (3-wire Serial mode)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 28)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Capacitive Load on Bus
Pulse Width of Spike Noise Suppressed by Input Filter
Power-down & Reset Timing
PDN Pulse Width
(Note 29)
PMADL or PMADR “↑” to SDTO valid (Note 30)
Note 27. I2C Philips Semiconductors
Note 28.
300ns (SCL
Note 29. AK4647 PDN pin = “L”
Note 30. PMADL bit
PMADR bit
Symbol
min
typ
max
Units
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
40
40
150
50
50
-
-
ns
ns
ns
ns
ns
ns
ns
ns
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
Cb
tSP
1.3
0.6
1.3
0.6
0.6
0
0.1
0.6
0
-
400
0.3
0.3
400
50
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
tPD
tPDV
150
-
1059
-
ns
1/fs
)
LRCK
MS0566-J-00
“↑”
2006/11
- 13 -
ASAHI KASEI
[AK4647]
„
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
50%DVDD
LRCK
tLRCKH
tLRCKL
1/fMCK
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
50%DVDD
MCKO
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 3. Clock Timing (PLL Master mode)
50%DVDD
LRCK
tBLR
tBCKL
BICK
50%DVDD
tLRD
tBSD
SDTO
50%DVDD
tSDH
tSDS
VIH
SDTI
VIL
Figure 4. Audio Interface Timing (PLL Master mode)
MS0566-J-00
2006/11
- 14 -
ASAHI KASEI
[AK4647]
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRCKH
tLRCKL
tBCK
Duty = tLRCKH x fs x 100
= tLRCKL x fs x 100
VIH
BICK
VIL
tBCKH
tBCKL
fMCK
50%DVDD
MCKO
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 5. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin)
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRCKH
tLRCKL
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 6. Clock Timing (EXT Slave mode)
MS0566-J-00
2006/11
- 15 -
ASAHI KASEI
[AK4647]
VIH
LRCK
VIL
tLRB
tBLR
VIH
BICK
VIL
tLRD
tBSD
SDTO
50%DVDD
MSB
tSDH
tSDS
VIH
SDTI
VIL
Figure 7. Audio Interface Timing (PLL/EXT Slave mode)
VIH
CSN
VIL
tCCKL
tCSS
tCCKH
VIH
CCLK
VIL
tCCK
tCDH
tCDS
VIH
CDTI
C1
C0
R/W
VIL
Figure 8. WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
D2
D1
D0
VIL
Figure 9. WRITE Data Input Timing
MS0566-J-00
2006/11
- 16 -
ASAHI KASEI
[AK4647]
VIH
SDA
VIL
tBUF
tLOW
tHIGH
tR
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
tSU:STO
Start
Stop
Figure 10. I2C
PMADL bit
or
PMADR bit
tPDV
SDTO
50%DVDD
Figure 11. Power Down & Reset Timing 1
tPD
PDN
VIL
Figure 12. Power Down & Reset Timing 2
MS0566-J-00
2006/11
- 17 -
ASAHI KASEI
[AK4647]
„
I/F
4
(See Table 1 and Table 2.)
Mode
PLL Master Mode
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
(PLL Reference Clock: LRCK or BICK pin)
EXT Slave Mode
Don’t Care (Note 31)
Note 31.
PMPLL bit
1
M/S bit
1
PLL3-0 bits
See Table 4
Figure
Figure 13
1
0
See Table 4
Figure 14
1
0
See Table 4
0
0
0
1
x
x
MCKO bit = “1”
Figure 15
Figure 16
Figure 17
MCKO pin
Table 1. Clock Mode Setting (x: Don’t care)
Mode
MCKO bit
0
PLL Master Mode
1
0
PLL Slave Mode
(PLL Reference Clock: MCKI pin)
1
MCKO pin
“L”
PS1-0 bits
MCKI pin
PLL3-0 bits
“L”
PS1-0 bits
PLL3-0 bits
GND
PLL Slave Mode
(PLL Reference Clock: LRCK or BICK pin)
0
“L”
EXT Slave Mode
0
“L”
FS3-0 bits
BICK pin
Output
(BCKO bit
)
Input
(BCKO bit
)
Input
(BCKO bit
)
Input
(≥ 32fs)
LRCK pin
Output
(1fs)
Input
(1fs)
Input
(1fs)
Input
(1fs)
Table 2. Clock pins state in Clock Mode
„
M/S bit
(PDN pin = “L”)
AK4647
M/S bit
“1”
“0”
“1”
M/S bit “1”
AK4647 LRCK, BICK pin
AK4647
LRCK, BICK pin
100kΩ
M/S bit
Mode
0
Slave Mode
1
Master Mode
Table 3. Select Master/Slave Mode
MS0566-J-00
Default
2006/11
- 18 -
ASAHI KASEI
[AK4647]
„ PLL
PMPLL bit = “1”
PLL
PLL FS3-0 bits, PLL3-0 bits
PMPLL bit “0” Æ “1”
Table 4
1) PLL Mode
PLL
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
0
2
0
0
0
0
0
1
0
0
LRCK pin
BICK pin
1fs
32fs
3
0
0
1
1
BICK pin
64fs
4
5
6
7
12
13
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Mode
Others
Others
VCOC pin
R,C
R[Ω] C[F]
6.8k
220n
10k
4.7n
10k
10n
10k
4.7n
10k
10n
10k
4.7n
10k
4.7n
10k
4.7n
10k
4.7n
10k
10n
10k
10n
MCKI pin
11.2896MHz
MCKI pin
12.288MHz
MCKI pin
12MHz
MCKI pin
24MHz
MCKI pin
13.5MHz
MCKI pin
27MHz
N/A
Table 4. Setting of PLL Mode (*fs: Sampling Frequency)
PLL
(max)
160ms
2ms
4ms
2ms
4ms
40ms
40ms
40ms
40ms
40ms
40ms
Default
2) PLL Mode
MCKI
Table 5
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
0
0
0
0
0
8kHz
Default
1
0
0
0
1
12kHz
2
0
0
1
0
16kHz
3
0
0
1
1
24kHz
4
0
1
0
0
7.35kHz
5
0
1
0
1
11.025kHz
6
0
1
1
0
14.7kHz
7
0
1
1
1
22.05kHz
10
1
0
1
0
32kHz
11
1
0
1
1
48kHz
14
1
1
1
0
29.4kHz
15
1
1
1
1
44.1kHz
Others
Others
N/A
Table 5. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = MCKI pin)
LRCK or BICK
FS3, FS1-0 bits
(Table 6)
Mode
FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency Range
0
Don’t care
0
0
0
Default
7.35kHz ≤ fs ≤ 8kHz
0
Don’t care
1
1
0
8kHz < fs ≤ 12kHz
0
Don’t care
0
2
1
12kHz < fs ≤ 16kHz
0
Don’t care
1
3
1
16kHz < fs ≤ 24kHz
1
Don’t care
0
6
1
24kHz < fs ≤ 32kHz
1
Don’t care
1
7
1
32kHz < fs ≤ 48kHz
Others
Others
N/A
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = LRCK or BICK pin)
MS0566-J-00
2006/11
- 19 -
ASAHI KASEI
[AK4647]
„ PLL
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
bit = “1”
MCKO pin
PLL
PMPLL bit = “0” Æ “1”
PLL
MCKO pin
“L”
(See Table 7)
BICK
LRCK
BICK
“L”
1fs
LRCK “L”
MCKO bit = “0”
1
PMPLL bit = “0”
LRCK
MCKO
LRCK, BICK
BICK,
“L”
MCKO pin
BICK pin
LRCK pin
MCKO bit = “0”
MCKO bit = “1”
“L” Output
“L” Output
“L” Output
PMPLL bit “0” Æ “1”
“L” Output
PLL Unlock (
)
“L” Output
1fs Output
See Table 9
See Table 10
PLL Lock
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
PLL State
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
PMPLL bit = “0” Æ “1”
PLL
PLL
DACL, DACH bits “0”
PLL
ADC
MCKO pin
DAC
MCKO
Table 9
DAC
MCKO pin
MCKO bit = “0” MCKO bit = “1”
“L” Output
PMPLL bit “0” Æ “1”
“L”
Output
PLL Unlock (
)
“L” Output
Output
PLL Lock
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
PLL State
MS0566-J-00
2006/11
- 20 -
ASAHI KASEI
[AK4647]
„ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
11.2896MHz, 12MHz , 12.288MHz, 13.5MHz, 24MHz or 27MHz
MCKO, BICK, LRCK
(MCKO)
MCKO bit ON/OFF
BICK
BCKO bit
(See Table 10)
PLL
PS1-0 bits (Table 9)
32fs or 64fs
11.2896MHz, 12MHz, 12.288MHz
13.5MHz, 24MHz, 27MHz
DSP or μP
AK4647
MCKI
256fs/128fs/64fs/32fs
MCKO
32fs, 64fs
BICK
1fs
LRCK
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 13. PLL Master Mode
Mode
0
1
2
3
PS1 bit
0
0
1
1
Table 9. MCKO
PS0 bit
0
1
0
1
(PLL
MCKO pin
256fs
Default
128fs
64fs
32fs
, MCKO bit = “1”)
BCKO bit
BICK
0
32fs
Default
1
64fs
Table 10. BICK Output Frequency at Master Mode
MS0566-J-00
2006/11
- 21 -
ASAHI KASEI
[AK4647]
„ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
MCKI, BICK or LRCK pin
PLL
PLL
a) PLL
: MCKI pin
MCKO
BICK, LRCK
bit
AK4647
(Table 4)
PLL3-0 bits
MCKO LRCK
(MCKO pin) PS1-0 bits (Table 9)
FS3-0 bits
ON/OFF
MCKO
(See Table 5)
11.2896MHz, 12MHz, 12.288MHz
13.5MHz, 24MHz, 27MHz
AK4647
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
≥ 32fs
1fs
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 14. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
MS0566-J-00
2006/11
- 22 -
ASAHI KASEI
b) PLL
FS3-0 bits
[AK4647]
: BICK or LRCK pin
7.35kHz ∼ 48kHz
(See Table 6.)
AK4647
DSP or μP
MCKO
MCKI
BICK
LRCK
32fs, 64fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 15. PLL Slave Mode 2 (PLL Reference Clock: BICK pin)
AK4647
DSP or μP
MCKO
MCKI
BICK
LRCK
≥ 32fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 16. PLL Slave Mode 2 (PLL Reference Clock: LRCK pin)
ADC or DAC
LRCK)
(PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”)
(MCKI, BICK,
(PMADL=PMADR=PMDAC bits = “0”)
MS0566-J-00
2006/11
- 23 -
ASAHI KASEI
[AK4647]
„ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
PMPLL bit “0”
ADC, DAC
Mode
0
1
2
3
Others
(EXT Mode)
MCKI pin
PLL
CODEC
I/F
MCKI (256fs, 512fs or 1024fs), BICK (≥32fs), LRCK(fs)
MCKI
MCKI
FS1-0 bit
(See Table 11)
MCKI Input
Sampling Frequency
Frequency
Range
Don’t care
0
0
256fs
7.35kHz ∼ 48kHz
Don’t care
0
1
1024fs
7.35kHz ∼ 13kHz
Don’t care
1
0
256fs
7.35kHz ∼ 48kHz
Don’t care
1
1
512fs
7.35kHz ∼ 26kHz
Others
N/A
N/A
Table 11. EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
MCKI
FS3-2 bits
FS1 bit
LRCK
FS0 bit
DAC
S/N
S/N
Table 12 DAC
Default
MCKI
LOUT/ROUT pins
S/N
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
83dB
512fs
93dB
1024fs
93dB
Table 12. Relationship between MCKI and S/N of LOUT/ROUT pins
MCKI
ADC or DAC
LRCK)
(PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”)
(MCKI, BICK,
(PMADL=PMADR=PMDAC bits = “0”
AK4647
DSP or μP
MCKO
256fs, 512fs or 1024fs
MCKI
BICK
LRCK
MCLK
≥ 32fs
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 17. EXT Slave Mode
MS0566-J-00
2006/11
- 24 -
ASAHI KASEI
[AK4647]
„
PDN pin
“L”
AK4647
PMADR bit “0” → “1”
1059/fs=24ms@fs=44.1kHz
“0”
ADC
PMDAC bit = “1”
ADC
PMDAC bit = “0”
PMADL bit
2’s
PMADL=PMADR bits = “0” PMDAC bit = “0” Æ “1”
1059/fs=24ms@fs=44.1kHz
“0”
DAC
DAC
ADC
ADC
DAC
DAC
2’s
DAC
(22/fs=0.5ms@fs=44.1kHz)
PMADL bit
PMADR bit “1”
„
3
(Table 13)
“↓”
SDTI
Mode
0
1
2
3
DIF1 bit
0
0
1
1
ADC
“−1”
DIF1-0 bits
2’s
LRCK BICK
BICK “↑”
DIF0 bit
0
1
0
1
16bit
8bit
“–256”
MSB
SDTO
SDTO (ADC)
N/A
SDTI (DAC)
N/A
2
2
IS
IS
Table 13. Audio Interface Format
8bit
“−1”
BICK
N/A
≥ 32fs
≥ 32fs
≥ 32fs
16bit
“−1”
8bit
8bit
Figure
Figure 18
Figure 19
Figure 20
BICK
Default
16bit
16bit
DAC
16bit
(128)
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
0 1 2 3
15 16 17 18
31 0 1 2 3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
SDTI(i)
1 0
15 14 13
Don't Care
15 14 13
15 14
1 0
1 0
Don't Care
15
15 14
2 1 0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 18. Mode 1
MS0566-J-00
2006/11
- 25 -
ASAHI KASEI
[AK4647]
LRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
7 6 5 4 3 2 1 0 15
0 1 2 3
15 16 17 18
31 0 1 2 3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
15 14 13
1 0
SDTI(i)
15 14 13
1 0
Don't Care
15 14 13
1 0
15 14 13
1 0
15
Don't Care
15
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 19. Mode 2
LRCK
9 10 11 12 13 14 15 0 1 2 3
0 1 2 3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTO(o)
0 15 14
8 7 6 5 4 3 2 1 0 15 14
8 7 6 5 4 3 2 1 0
SDTI(i)
0 15 14
8 7 6 5 4 3 2 1 0 15 14
8 7 6 5 4 3 2 1 0
0 1 2 3
15 16 17 18
31 0 1 2 3
15 16 17 18
31 0 1
BICK(64fs)
SDTO(o)
15 14
2 1 0
SDTI(i)
15 14
2 1 0
Don't Care
15 14
2 1 0
15 14
2 1 0
Don't Care
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 20. Mode 3
„
PMADL, PMADR bits
PMADL bit
0
0
1
1
ADC
PMADR bit
0
1
0
1
Table 14.
ADC Lch data
All “0”
Rch Input Signal
Lch Input Signal
Lch Input Signal
MS0566-J-00
ADC Rch data
All “0”
Rch Input Signal
Lch Input Signal
Rch Input Signal
Default
2006/11
- 26 -
ASAHI KASEI
„
[AK4647]
HPF
AK4647 DC
44.1kHz)
ADC HPF ON DAC HPF
ON ADC HPF OFF
OFF
HPF
HPF
0.9Hz (@fs=
(fs)
PMADL bit = “1” or PMADR bit = “1”
PMADL=PMADR bits = “0”, PMDAC bit = “1”
DAC HPF
„
AK4647
LIN1/LIN2, RIN1/RIN2
RIN1, LIN2, RIN2 pins
IN1−, IN1+, IN2+, IN2− pins
Table 16 “X”
MDIF1 bit
0
0
0
0
0
1
1
Others
MDIF2 bit
0
0
0
0
1
0
1
INL bit
0
0
1
0
0
0
0
INR bit
0
1
0
1
0
1
0
MDIF1, MDIF2 bits = “0”
INL, INR bits
MDIF1, MDIF2 bits = “1”
LIN1,
(Figure 22)
Lch
LIN1
LIN1
LIN2
LIN2
LIN1
IN1+/−
IN1+/−
N/A
Table 15. MIC/Line In Path Select
Rch
RIN1
RIN2
RIN1
RIN2
IN2+/−
RIN2
IN2+/−
N/A
Default
Register
Pin
LIN1
RIN2
RIN1
LIN2
MDIF1 bit MDIF2 bit
IN1+
IN2+
IN1−
IN2−
0
0
O
O
O
O
0
1
O
X
O
O
1
0
O
O
X
O
1
1
O
O
O
O
Table 16. Handling of MIC/Line Input Pins (“-“: N/A; “X”: Signal should not be input.)
MS0566-J-00
2006/11
- 27 -
ASAHI KASEI
[AK4647]
AK4647
INL bit
LIN1/IN1− pin
ADC Lch
RIN1/IN1+ pin
MDIF1 bit
INR bit
RIN2/IN2− pin
ADC Rch
LIN2/IN2+ pin
MDIF2 bit
Figure 21.
AK4647
MPWR pin
1k
IN1− pin
MIC-Amp
IN1+ pin
A/D
SDTO pin
1k
Figure 22.
IN1+/− pins
MDIF1 bit
1
0
(MDIF1/2 bits = “1”)
LIN2/RIN2 pins
MDIF2 bit
0
0
2
INL1 bit
INL0 bit
INR1 bit
INR0 bit
0
0
0
1
0
1
0
1
Table 17. MIC/Line In Path Select Example
MS0566-J-00
Lch
IN1+/−
LIN2
Rch
RIN2
RIN2
2006/11
- 28 -
ASAHI KASEI
[AK4647]
„
AK4647
(Table 18)
typ. 30kΩ
MGAIN1-0 bits
MGAIN1-0 bits = “00”
typ. 60kΩ
MGAIN1 bit
0
0
1
1
MGAIN0 bit
0
1
0
1
Table 18.
MGAIN1-0 bits = “01”, “10”, “11”
Input Gain
0dB
+20dB
+26dB
+32dB
Default
„
PMMP bit = “1”
AVDD)V (typ)
MPWR pin
MPWR pin
min. 0.5kΩ
(0.75 x
min. 2kΩ
2
(Figure 23
PMMP bit
MPWR pin
0
Hi-Z
1
Output
Table 19.
)
Default
MIC Power
≥ 2kΩ
≥ 2kΩ
≥ 2kΩ
≥ 2kΩ
MPWR pin
Microphone
LIN1 pin
Microphone
RIN1 pin
Microphone
LIN2 pin
Microphone
RIN2 pin
Figure 23. MIC Block Circuit
MS0566-J-00
2006/11
- 29 -
ASAHI KASEI
[AK4647]
„ Digital EQ/HPF/LPF
AK4647
A/D
ALC
(Figure 24
) FIL1, FIL3, EQ
“ALC
”
ALC
DAC
1
IIR
Digital EQ/HPF/LPF
ADC
ADC
DAC
Digital EQ/HPF/LPF
FIL3, EQ, FIL1, GN1-0 bits
“0”
PMADL bit, PMADR bit
“00”
PMDAC bit
0
1
0
“01”, “10” or “11”
LOOP bit
x
x
x
0
1
1
Digital EQ/HPF/LPF
Default
,
Note 32.
Table 20. Digital EQ/HPF/LPF
ATT
FIL3
GN1-0 bits(Table 21
FIL1, FIL3
FIL3
F1AS, F3AS bits
OFF(MUTE)
(x: Don’t care)
EQ, FIL1
“0”
)
EQ
HPF
F1AS, F3AS bits
0dB
(FIL3
FIL1
F1A13-0
F1B13-0
F1AS
FIL3
F3A13-0
F3B13-0
F3AS
0dB ∼ -10dB
MUTE
(FIL3
FIL3, EQ, FIL1 bits
MUTE)
EQ
)
“1”
EQA15-0
EQB13-0
EQC15-0
+12dB ∼ 0dB
Gain
LPF
“0”
ALC
GN1-0
+24/+12/0dB
Figure 24. Digital EQ/HPF/LPF
GN1
GN0
0
0
0
1
1
x
Table 21. Gain
Gain
0dB
Default
+12dB
+24dB
(x: Don’t care)
MS0566-J-00
2006/11
- 30 -
ASAHI KASEI
[AK4647]
[
]
1) FIL1, FIL3
fs:
fc:
f:
K:
HPF
[dB] (FIL1
0dB
)
FIL1: F1AS bit = “0”, F1A[13:0] bits =A, F1B[13:0] bits =B
FIL3: F3AS bit = “0”, F3A[13:0] bits =A, F3B[13:0] bits =B
(MSB=F1A13, F1B13, F3A13, F3B13; LSB=F1A0, F1B0, F3A0, F3B0)
1 / tan (πfc/fs)
A = 10K/20 x
1 − 1 / tan (πfc/fs)
,
B=
1 + 1 / tan (πfc/fs)
1 + 1 / tan (πfc/fs)
1 − z −1
H(z) = A
2) FIL1, FIL3
fs:
fc:
f:
K:
2 − 2cos (2πf/fs)
M(f) = A
1 + Bz −1
1 + B2 + 2Bcos (2πf/fs)
θ(f) = tan −1
(B+1)sin (2πf/fs)
1 - B + (B−1)cos (2πf/fs)
LPF
[dB] (FIL1
0dB
)
FIL1: F1AS bit = “1”, F1A[13:0] bits =A, F1B[13:0] bits =B
FIL3: F3AS bit = “1”, F3A[13:0] bits =A, F3B[13:0] bits =B
(MSB=F1A13, F1B13, F3A13, F3B13; LSB=F1A0, F1B0, F3A0, F3B0)
1 − 1 / tan (πfc/fs)
1
A = 10K/20 x
,
1 + 1 / tan (πfc/fs)
1 + z −1
H(z) = A
1 + Bz −1
B=
1 + 1 / tan (πfc/fs)
2 + 2cos (2πf/fs)
M(f) = A
1 + B2 + 2Bcos (2πf/fs)
MS0566-J-00
θ(f) = tan −1
(B−1)sin (2πf/fs)
1 + B + (B+1)cos (2πf/fs)
2006/11
- 31 -
ASAHI KASEI
[AK4647]
3) EQ
fs:
fc1:
fc2:
f:
K:
[dB] (
+12dB
)
EQA[15:0] bits =A, EQB[13:0] bits =B, EQC[15:0] bits =C
(MSB=EQA15, EQB13, EQC15; LSB=EQA0, EQB0, EQC0)
A = 10K/20 x
1 + 1 / tan (πfc2/fs)
1 − 1 / tan (πfc1/fs)
,
B=
,
1 + 1 / tan (πfc1/fs)
A + Cz −1
H(z) =
1 + 1 / tan (πfc1/fs)
A2 + C2 + 2ACcos (2πf/fs)
1 + B2 + 2Bcos (2πf/fs)
[
2
(2
) x 213
X=(
X
2
1 − 1 / tan (πfc2/fs)
1 + 1 / tan (πfc1/fs)
(AB−C)sin (2πf/fs)
θ(f) = tan −1
M(f) =
1 + Bz −1
C =10K/20 x
A + BC + (AB+C)cos (2πf/fs)
)
(2
]
)
MSB
[
]
1) FIL1
: fs=44.1kHz, fc=100Hz HPF
F1AS bit = “0”
F1A[13:0] bits = 01 1111 1100 0110
F1B[13:0] bits = 10 0000 0111 0100
2) EQ
: fs=44.1kHz, fc1=300Hz, fc2=3000Hz, Gain=+8dB
Gain[dB]
+8dB
fc1
fc2
Frequency
EQA[15:0] bits = 0000 1001 0110 1110
EQB[13:0] bits = 10 0001 0101 1001
EQC[15:0] bits = 1111 1001 1110 1111
MS0566-J-00
2006/11
- 32 -
ASAHI KASEI
[AK4647]
„ ALC
ALC bit = “1”
ALC
ALC
PMADL bit, PMADR bit
“00”
ALC
PMDAC bit
0
1
0
“01”, “10” or “11”
1.
DAC
ALC
1
LOOP bit
x
x
x
0
1
Table 22. ALC
ALC
Default
,
(x: Don’t care)
ALC
ALC
Lch, Rch
LMAT1-0 bits
ZELMN bit = “0”(
(Table 24)
)
ALC
ALC
IVL, IVR (L/R
IVL, IVR
LMTH1
0
0
1
1
LMAT1
0
0
0
1
1
1
x
Table 24. ALC
ZTM0
0
0
1
1
0
1
0
1
128/fs
256/fs
512/fs
1024/fs
Table 25. ALC
(
: 1/fs)
ALC
LMTH0 ALC
0
ALC Output ≥ −2.5dBFS
1
ALC Output ≥ −4.1dBFS
0
ALC Output ≥ −6.0dBFS
1
ALC Output ≥ −8.5dBFS
Table 23. ALC
ZTM1
IVL, IVR
1 step
“0”
ZELMN
L/R
(Table 25)
)
ALC
LMAT1-0 bits
ALC bit
)
ALC
ZTM1-0 bits
ZELMN bit = “1”(
(Table 23)
ALC
−2.5dBFS > ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
LMAT0 ALC
0
1 step
1
2 step
0
4 step
1
8 step
x
1step
ATT
8kHz
16ms
32ms
64ms
128ms
MS0566-J-00
Default
ATT
0.375dB
Default
0.750dB
1.500dB
3.000dB
0.375dB
(x: Don’t care)
16kHz
8ms
16ms
32ms
64ms
44.1kHz
2.9ms
5.8ms
11.6ms
23.2ms
Default
2006/11
- 33 -
ASAHI KASEI
2.
[AK4647]
ALC
ALC
WTM1-0 bits
(Table 26)
(Table 23)
ALC
(Table 28)
ZTM1-0 bits
RGAIN1-0 bits
(Table 27)
IVL, IVR (L/R
WTM1-0 bits
ALC
IVL, IVR
30H
IVL, IVR
32H
IVL, IVR
bits)
RGAIN1-0 bits = “01”(2 steps)
0.75dB(0.375dB x 2)
ALC
ALC
(Table 25)
)
ALC
IVL, IVR
(REF7-0
ALC
(
) ≤ Output Signal < (
(
) > Output Signal
ALC
)
ALC
WTM1
WTM0
0
0
1
1
0
1
0
1
RGAIN1
0
0
1
1
ALC
8kHz
128/fs
16ms
256/fs
32ms
512/fs
64ms
1024/fs
128ms
Table 26. ALC
RGAIN0
0
1
0
1
Table 27. ALC
16kHz
8ms
16ms
32ms
64ms
GAIN STEP
1 step
0.375dB
2 step
0.750dB
3 step
1.125dB
4 step
1.500dB
REF7-0
GAIN(dB)
F1H
+36.0
F0H
+35.625
EFH
+35.25
:
:
E2H
+30.375
E1H
+30.0
E0H
+29.625
:
:
03H
−53.25
02H
−53.625
01H
−54.0
00H
MUTE
Table 28. ALC
MS0566-J-00
44.1kHz
2.9ms
5.8ms
11.6ms
23.2ms
Default
Default
Step
0.375dB
Default
2006/11
- 34 -
ASAHI KASEI
3.
[AK4647]
ALC
Table 29
ALC
Register Name
Comment
LMTH
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM1-0 bits should be the same or
longer data as ZTM1-0 bits
Maximum gain at recovery operation
WTM1-0
REF7-0
IVL7-0,
IVR7-0
LMAT1-0
RGAIN1-0
ALC
ALC
bit = “0”
Gain of IVOL
Limiter ATT step
Recovery GAIN step
ALC enable
Data
01
0
01
fs=8kHz
Operation
−4.1dBFS
Enable
32ms
Data
01
0
11
fs=44.1kHz
Operation
−4.1dBFS
Enable
23.2ms
01
32ms
11
23.2ms
E1H
+30dB
E1H
+30dB
E1H
+30dB
E1H
+30dB
1 step
1 step
Enable
00
00
1
1 step
1 step
Enable
00
00
1
Table 29. ALC
ALC
(ALC
PMADL = PMADR bits = “0”)
LMTH, LMAT1-0, WTM1-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 32ms@8kHz
Zero Crossing Timeout Period = 32ms@8kHz
Limiter and Recovery Step = 1
Gain of IVOL = +30dB
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
ALC bit = “1”
Manual Mode
WR (ZTM1-0, WTM2-0)
(1) Addr=06H, Data=14H
WR (REF7-0)
(2) Addr=08H, Data=E1H
WR (IVL/R7-0)
* The value of IVOL should be
(3) Addr=09H&0CH, Data=E1H
the same or smaller than REF’s
WR (RGAIN1, LMTH1)
(4) Addr=0BH, Data=00H
WR (LMAT1-0, RGAIN0, ZELMN, LMTH0; ALC= “1”)
(5) Addr=07H, Data=21H
ALC Operation
Note : WR : Write
Figure 25. ALC
MS0566-J-00
2006/11
- 35 -
ASAHI KASEI
[AK4647]
„
(
)
ALC bit = “0”
1.
2.
ALC
(ZTM1-0, LMTH bits
ALC
)
3.
IVL7-0, IVR7-0 bits
PMADL = PMADR bits = “0”
= “1”
ADC
(Table 30)
ZTM1-0 bits
IVL7-0, IVR7-0 bits
L/R
PMADL bit = “1” or PMADR bit
IVOL
IVL7-0 = IVR7-0 bits = “91H” (0dB)
IVL7-0
IVR7-0
F1H
F0H
EFH
:
E2H
E1H
E0H
:
03H
02H
01H
00H
Table 30.
GAIN (dB)
+36.0
+35.625
+35.25
:
+30.375
+30.0
+29.625
:
−53.25
−53.625
−54
MUTE
MS0566-J-00
Step
0.375dB
Default
2006/11
- 36 -
ASAHI KASEI
[AK4647]
IVL7-0, IVR7-0 bits
ALC bit
ALC Status
Disable
Enable
IVL7-0 bits
E1H(+30dB)
IVR7-0 bits
C6H(+20dB)
Internal IVL
E1H(+30dB)
Internal IVR
C6H(+20dB)
E1(+30dB) --> F1(+36dB)
(1)
E1(+30dB)
(2)
E1(+30dB) --> F1(+36dB)
Figure 26. ALC
IVL IVR
IVL7-0 bits
(WTM1-0 bits) +
(2) ALC
IVL, IVR
Disable
C6H(+20dB)
IVOL
(1) ALC
IVL
ALC bit = “1”
ALC
(ZTM1-0 bits)
(09H, 0CH)
ALC bit = “0”
MS0566-J-00
ALC Disable
ALC Enable
ALC bit = “1”
2006/11
- 37 -
ASAHI KASEI
[AK4647]
„
IIR
3
(32kHz, 44.1kHz, 48kHz)
DEM1-0 bit
(tc=50/15μs
)
(Table 31)
DEM1
DEM0
0
0
0
1
1
0
1
1
Table 31.
Mode
44.1kHz
OFF
48kHz
32kHz
Default
„
BST1-0 bits
32)
BST1-0 bits = “01”(MIN)
DAC
(Table
47μF
DC
DAC
Figure 27
−20dB
Boost Filter (fs=44.1kHz)
0
MAX
Gain [dB]
-5
MID
-10
MIN
-15
-20
-25
10
100
1000
10000
Frequency [Hz]
Figure 27.
(fs=44.1kHz)
BST1
BST0
0
0
0
1
1
0
1
1
Table 32.
Mode
OFF
MIN
MID
MAX
MS0566-J-00
Default
2006/11
- 38 -
ASAHI KASEI
[AK4647]
„
AK4647
MUTE
0.5dB
DAC
DVOLC bit “1”
bit “0”
Lch, Rch
256/fs
00H(+12dB)
FFH(MUTE)
256
+12dB
DVL7-0 bits
0
1
−115dB
Lch, Rch
DVOLC
ATT
1061
DVTM bit = “0”
DVTM bit
1061/fs(24ms@fs=44.1kHz)
DVL/R7-0
00H
01H
02H
:
18H
:
FDH
FEH
FFH
DVTM bit
(DATT)
Gain
Step
+12.0dB
+11.5dB
+11.0dB
:
0.5dB
0dB
:
−114.5dB
−115.0dB
MUTE (−∞)
Table 33. Digital Volume Code Table
DVL/R7-0 bits = 00H
FFH
fs=8kHz
1061/fs
133ms
256/fs
32ms
Table 34.
MS0566-J-00
Default
fs=44.1kHz
24ms
6ms
Default
2006/11
- 39 -
ASAHI KASEI
[AK4647]
„
DAC
SMUTE bit “1”
SMUTE bit “0”
SMUTE bit
−∞(“0”)
DVTM bit
−∞
−∞
bits
DVTM bit
DVTM bit
DVL/R7-0 bits
DVL/R7-0
(Figure 28)
S M U T E bit
D VTM bit
D VL/R 7-0 bits
D VTM bit
(1)
(3)
A ttenuation
-∞
GD
(2)
GD
A nalog O utput
Figure 28.
(1) DVTM bit
(2)
(3)
−∞(“0”)
(GD)
DVTM bit
DVL/R7-0 bits
MS0566-J-00
2006/11
- 40 -
ASAHI KASEI
[AK4647]
„
:
PMBP bit = “1”
BEEPH bit
“1”
BEEPL bit
Ri
(typ)
Table 35, Table 36
“1”
Ri = 20kΩ
Ri
Ri
BEEPL
MIN
LOUT/ROUT pin
BEEPH
HPL/HPR pin
Figure 29. Block Diagram of MIN pin
LOVL bit
0
1
Table 35. Ri = 20kΩ
MIN Æ LOUT/ROUT
0dB
+2dB
MIN
Æ LOUT/ROUT
HPG bit
0
1
Table 36. Ri = 20kΩ
MIN Æ HPL/HPR
−20dB
−16.4dB
MIN
Æ
MS0566-J-00
Default
(typ)
Default
(typ)
2006/11
- 41 -
ASAHI KASEI
[AK4647]
„
(LOUT, ROUT pin)
DACL bit “1”
DACL bit
“0”
DAC
Lch, Rch
OFF
min. 10kΩ
LOUT, ROUT pins
LOUT, ROUT pins VCOM
PMLO bit = LOPS bit = “0”
LOPS bit = “1”
PMLO bit
ON/OFF
ON/OFF
Figure 31
C
C=1μF, AVDD=3.3V
PMLO bit = “1”
LOPS bit = “0”
AVSS 100kΩ(typ)
LOPS bit = “1”
20kΩ
300ms
LOVL bit
“DACL”
“LOVL”
LOUT pin
DAC
ROUT pin
Figure 30.
LOPS
0
1
PMLO
0
1
0
1
Table 37.
Mode
LOUT/ROUT pin
Pull-down to AVSS
Default
Fall down to AVSS
Rise up to VCOM
(x: Don’t care)
LOVL
Gain
0
0dB
1
+2dB
Table 38.
(typ)
0.6 x AVDD
0.757 x AVDD
LOUT
ROUT
1μF
Default
220Ω
20kΩ
Figure 31.
(
MS0566-J-00
)
2006/11
- 42 -
ASAHI KASEI
[AK4647]
[
(
)]
(2 )
(5 )
P M L O b it
(1 )
(3 )
(4 )
(6 )
L O P S b it
L O U T , R O U T p in s
N o r m a l O u tp u t
≥ 300 m s
≥ 300 m s
Figure 32.
(1)
(2)
ON
)
C=1μF, AVDD=3.3V
200ms (max
LOPS bit = “1”
PMLO bit = “1”
LOUT, ROUT pins
300ms)
(3) LOUT, ROUT pins
(4)
(5)
(
LOPS bit = “0”
ON
LOPS bit = “1”
PMLO bit = “0”
LOUT, ROUT pins
300ms)
(6) LOUT, ROUT pins
C=1μF, AVDD=3.3V
200ms (max
LOPS bit = “0”
MS0566-J-00
2006/11
- 43 -
ASAHI KASEI
[AK4647]
„
(HPL/HPR pins)
HVDD
HVDD/2
HPG bit
16Ω (min)
(Table 39)
HPG bit
Output Voltage [Vpp]
0
0.6 x AVDD
1
0.91 x AVDD
Table 39.
HPMTN bit
“0”
HVSS
HVDD/2
HVDD
: MUTET pin
HPMTN bit
“1”
MUTET pin
MUTET pin
C=1μF, HVDD=3.3V
: 100ms(typ), 250ms(max)
: 500ms(max)
PMHPL, PMHPR bits “0”
HPL, HPR pins “L” (HVSS)
PMHPL bit,
PMHPR bit
HPMTN bit
HPL pin,
HPR pin
(1) (2)
(3)
(4)
Figure 33.
(1)
(2)
(3)
(4)
(PMHPL, PMHPR bits = “1”)
(HPMTN bit = “1”)
(HPMTN bit = “0”)
(PMHPL, PMHPR bits = “0”)
MS0566-J-00
HVSS
HVSS
2006/11
- 44 -
ASAHI KASEI
[AK4647]
BOOST=OFF
(fc)
Table 40
(fc)
HVDD=2.7, 3.0, 3.3, 5V
(Vpp)@HPG bit = “0”, 0.91 x AVDD (Vpp)@HPG bit = “1”
R 12Ω
(0.22μF±20%
10Ω±20%
)
HP-AMP
AK4647
RL 16Ω
0.6 x AVDD
R
C
Headphone
16Ω
0.22μ
10Ω
Figure 34.
HPG bit
R [Ω]
6.8
0
16
0
1
100
C [μF]
100
47
100
47
220
100
22
10
fc [Hz]
BOOST=OFF
70
149
50
106
45
100
62
137
Table 40.
fc [Hz]
BOOST=MIN
@fs=44.1kHz
28
78
19
47
17
43
25
69
MS0566-J-00
Output Power [mW]@0dBFS
2.7V
3.0V
3.3V
10.1
12.5
15.1
5.1
6.3
7.7
33
41
50
0.9
1.1
1.3
2006/11
- 45 -
ASAHI KASEI
[AK4647]
„
(1) 3
(I2C pin = “L”)
3
I/F
(CSN, CCLK, CDTI)
I/F
Chip
address (2bits, “10”
), Read/Write (1bit, “1”
), Register address (MSB first, 5bits)
Control Data (MSB first,
8bits)
CCLK “↓”
“↑”
CSN “↓” 16
CCLK “↑”
CCLK
5MHz
(max)
PDN pin = “L”
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
“1” “0” “1”
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (C1 = “1”, C0 = “0”); Fixed to “10”
READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1”
Register Address
Control data
Figure 35.
MS0566-J-00
2006/11
- 46 -
ASAHI KASEI
(2) I2C
AK4647
[AK4647]
(I2C pin = “H”)
I 2C
(max:400kHz)
SDA, SCL pins
(DVDD+0.3)V
(2)-1. WRITE
I2C
(Start Condition)
(Figure 42)
8
IC
AK4647
SDA
R/W bit “1”
2
MSB first
“L”
IC
“H”
SDA
“L”
7
(R/W)
6
“001001”
(Figure 37)
CAD0 pin
1
(Acknowledge)
(Figure 43)
(
)
(Figure 38)
3
(Figure 39) AK4647
“0”
SDA
Figure 36
“H”
SCL
8
“0”
MSB first
2
8
(Stop Condition)
(Figure 42)
“H”
R/W bit
AK4647
SCL
“H”
1
“H”
SDA
SCL
“L”
(Figure 44)
“H”
SCL
“L”
“H”
SDA
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Sub
Address(n)
Data(n)
A
C
K
A
C
K
A
C
K
Data(n+1)
Data(n+x)
A
C
K
P
A
C
K
A
C
K
Figure 36. I2C
0
0
1
0
0
(CAD0
Figure 37.
0
0
0
D6
D5
Figure 39.
CAD0
R/W
A3
A2
A1
A0
D3
D2
D1
D0
)
1
A4
Figure 38.
D7
1
2
D4
3
MS0566-J-00
2006/11
- 47 -
ASAHI KASEI
[AK4647]
(2)-2. READ
R/W bit “1”
AK4647
READ
“1FH”
“00H”
AK4647
2
READ
(2)-2-1.
AK4647
AK4647
(READ
WRITE
“n+1”
(R/W bit = “1”)
READ
)
“n”
1
READ
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
A
C
K
Data(n+1)
Data(n+2)
A
C
K
A
C
K
Data(n+x)
A
C
K
P
A
C
K
A
C
K
Figure 40.
(2)-2-2.
READ
(R/W bit = “1”)
WRITE
WRITE
= “0”)
AK4647
(R/W bit= “1”)
READ
(R/W bit
AK4647
1
READ
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Sub
Address(n)
Slave
S Address
A
C
K
Slave
S Address
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 41.
MS0566-J-00
2006/11
- 48 -
ASAHI KASEI
[AK4647]
SDA
SCL
S
P
start condition
stop condition
Figure 42.
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 43. I2C
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 44. I2C
MS0566-J-00
2006/11
- 49 -
ASAHI KASEI
[AK4647]
„
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Register Name
Power Management 1
Power Management 2
Signal Select 1
Signal Select 2
Mode Control 1
Mode Control 2
Timer Select
ALC Mode Control 1
ALC Mode Control 2
Lch Input Volume Control
Lch Digital Volume Control
ALC Mode Control 3
Rch Input Volume Control
Rch Digital Volume Control
Mode Control 3
Mode Control 4
Power Management 3
Digital Filter Select
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ Co-efficient 0
EQ Co-efficient 1
EQ Co-efficient 2
EQ Co-efficient 3
EQ Co-efficient 4
EQ Co-efficient 5
FIL1 Co-efficient 0
FIL1 Co-efficient 1
FIL1 Co-efficient 2
FIL1 Co-efficient 3
Note 33. PDN pin
Note 34. “0”
D7
0
0
0
LOVL
PLL3
PS1
DVTM
0
REF7
D6
PMVCM
HPMTN
0
LOPS
PLL2
PS0
0
0
REF6
D5
PMBP
PMHPL
0
MGAIN1
PLL1
FS3
ZTM1
ALC
REF5
D4
0
PMHPR
DACL
0
PLL0
0
ZTM0
ZELMN
REF4
D3
PMLO
M/S
0
0
BCKO
0
WTM1
LMAT1
REF3
D2
PMDAC
0
PMMP
BEEPL
0
FS2
WTM0
LMAT0
REF2
D1
0
MCKO
0
0
DIF1
FS1
0
RGAIN0
REF1
D0
PMADL
PMPLL
MGAIN0
0
DIF0
FS0
0
LMTH0
REF0
IVL7
IVL6
IVL5
IVL4
IVL3
IVL2
IVL1
IVL0
DVL7
RGAIN1
IVR7
DVR7
0
0
0
GN1
F3A7
F3AS
F3B7
0
EQA7
EQA15
EQB7
0
EQC7
EQC15
F1A7
F1AS
F1B7
0
DVL6
LMTH1
IVR6
DVR6
LOOP
0
0
GN0
F3A6
0
F3B6
0
EQA6
EQA14
EQB6
0
EQC6
EQC14
F1A6
0
F1B6
0
DVL5
0
IVR5
DVR5
SMUTE
0
HPG
0
F3A5
F3A13
F3B5
F3B13
EQA5
EQA13
EQB5
EQB13
EQC5
EQC13
F1A5
F1A13
F1B5
F1B13
DVL4
0
IVR4
DVR4
DVOLC
0
MDIF2
FIL1
F3A4
F3A12
F3B4
F3B12
EQA4
EQA12
EQB4
EQB12
EQC4
EQC12
F1A4
F1A12
F1B4
F1B12
DVL3
0
IVR3
DVR3
BST1
IVOLC
MDIF1
EQ
F3A3
F3A11
F3B3
F3B11
EQA3
EQA11
EQB3
EQB11
EQC3
EQC11
F1A3
F1A11
F1B3
F1B11
DVL2
0
IVR2
DVR2
BST0
HPM
INR
FIL3
F3A2
F3A10
F3B2
F3B10
EQA2
EQA10
EQB2
EQB10
EQC2
EQC10
F1A2
F1A10
F1B2
F1B10
DVL1
0
IVR1
DVR1
DEM1
BEEPH
INL
0
F3A1
F3A9
F3B1
F3B9
EQA1
EQA9
EQB1
EQB9
EQC1
EQC9
F1A1
F1A9
F1B1
F1B9
DVL0
0
IVR0
DVR0
DEM0
DACH
PMADR
0
F3A0
F3A8
F3B0
F3B8
EQA0
EQA8
EQB0
EQB8
EQC0
EQC8
F1A0
F1A8
F1B0
F1B8
“L”
“1”
MS0566-J-00
2006/11
- 50 -
ASAHI KASEI
[AK4647]
„
Addr
00H
Register Name
Power Management 1
Default
D7
0
0
PMADL: MIC-Amp Lch, ADC Lch
0: Power down (Default)
1: Power up
PMADL
PMADR bit
D6
PMVCM
0
“0”
D5
PMBP
0
D4
0
0
D3
PMLO
0
D2
PMDAC
0
“1”
D1
0
0
D0
PMADL
0
(1059/[email protected])
ADC
PMDAC: DAC
0: Power down (Default)
1: Power up
PMLO:
0: Power down (Default)
1: Power up
PMBP:
0: Power down (Default)
1: Power up
PMBP bit = “1”
PMVCM: VCOM
0: Power down (Default)
1: Power up
“0”
MCKO bit
PMVCM bit “1”
00H, 01H, 02H, 10H
PMVCM bit
“0”
ON/OFF (“1”/“0”)
PDN pin
“L”
00H, 01H, 02H, 10H
ADC
DAC
MS0566-J-00
MCKO bit
“0”
ADC
DAC
2006/11
- 51 -
ASAHI KASEI
Addr
01H
[AK4647]
Register Name
Power Management 2
Default
D7
0
0
D6
HPMTN
0
D5
PMHPL
0
D4
PMHPR
0
D3
M/S
0
D2
0
0
D1
MCKO
0
D4
DACL
0
D3
0
0
D2
PMMP
0
D1
0
0
D0
PMPLL
0
PMPLL: PLL
0: EXT Mode and Power Down (Default)
1: PLL Mode and Power up
MCKO: MCKO
0: Disable: MCKO pin = “L” (Default)
1: Enable: Output frequency is selected by PS1-0 bits.
M/S: Master / Slave Mode
0: Slave Mode (Default)
1: Master Mode
PMHPR: Rch
0: Power down (Default)
1: Power up
PMHPL: Lch
0: Power down (Default)
1: Power up
HPMTN:
0: Mute (Default)
1: Normal operation
Addr
02H
Register Name
Signal Select 1
Default
MGAIN1-0:
MGAIN1 bit
D7
0
0
D6
0
0
D5
0
0
D0
MGAIN0
1
(See Table 18)
03H
D5 bit
PMMP: MPWR pin
0: Power down: Hi-Z (Default)
1: Power up
DACL: DAC
0: OFF (Default)
1: ON
PMLO bit = “1”
PMLO bit = “0”
MS0566-J-00
LOUT, ROUT pins
AVSS
2006/11
- 52 -
ASAHI KASEI
Addr
03H
[AK4647]
Register Name
Signal Select 2
Default
D7
LOVL
0
BEEPL:
0: OFF (Default)
1: ON
PMLO bit = “1”
D6
LOPS
0
D5
MGAIN1
0
D4
0
0
D3
0
0
D2
BEEPL
0
D1
0
0
D0
0
0
MIN
PMLO bit = “0”
MGAIN1:
LOUT, ROUT pins
AVSS
(See Table 18)
LOPS:
0: Normal Operation (Default)
1: Power Save Mode
LOVL:
0: 0dB (Default)
1: +2dB
Addr
04H
(Table 38)
Register Name
Mode Control 1
Default
DIF1-0:
Default: “10” (
BCKO:
D7
PLL3
0
FS3-0:
D3
BCKO
0
D2
0
0
D1
DIF1
1
D0
DIF0
0
D3
0
0
D2
FS2
0
D1
FS1
0
D0
FS0
0
(See Table 10)
(See Table 4)
D7
PS1
0
D6
PS0
0
D5
FS3
0
(See Table 5 and Table 6)
PLL
PS1-0: MCKO
Default: “00”(256fs)
D4
PLL0
0
)
BICK
Register Name
Mode Control 2
Default
D5
PLL1
0
(See Table 13)
PLL3-0: PLL
Default: “0000”(LRCK pin)
Addr
05H
D6
PLL2
0
D4
0
0
MCKI
EXT
(See Table 11)
MCKI
(Table 9)
MS0566-J-00
2006/11
- 53 -
ASAHI KASEI
Addr
06H
[AK4647]
Register Name
Timer Select
Default
D7
DVTM
0
WTM1-0: ALC
ALC
“00” (128/fs)
D6
0
0
D5
ZTM1
0
D4
ZTM0
0
D3
WTM1
0
D2
WTM0
0
D1
0
0
D0
0
0
D3
LMAT1
0
D2
LMAT0
0
D1
RGAIN0
D0
LMTH0
0
(see Table 26)
ZTM1-0: ALC
(see Table 25)
ALC
“00” (128/fs)
DVTM: Digital Volume
0: 1061/fs (Default)
1: 256/fs
DVL7-0, DVR7-0 bits
Addr
07H
Register Name
ALC Mode Control 1
Default
LMTH1-0: ALC
Default: “00”
LMTH1 bit
RGAIN1-0: ALC
Default: “00”
RGAIN1 bit
D7
0
0
D6
0
0
00H
D5
ALC
0
FFH
D4
ZELMN
0
/
0BH
0
(see Table 23)
D6 bit
(see Table 27)
03H
LMAT1-0: ALC
Default: “00”
D7 bit
ATT
(see Table 24)
ZELMN: ALC
0: Enable (Default)
1: Disable
ALC: ALC
0: ALC Disable (Default)
1: ALC Enable
Addr
08H
Register Name
ALC Mode Control 2
Default
REF7-0: ALC
Default: “E1H” (+30.0dB)
D7
REF7
1
D6
REF6
1
D5
REF5
1
D4
REF4
0
D3
REF3
0
D2
REF2
0
D1
REF1
0
D0
REF0
1
0.375dB step, 242 Level (Table 28)
MS0566-J-00
2006/11
- 54 -
ASAHI KASEI
Addr
09H
0CH
[AK4647]
Register Name
Lch Input Volume Control
Rch Input Volume Control
Default
D7
IVL7
IVR7
1
D6
IVL6
IVR6
1
IVL7-0, IVR7-0:
Default: “E1H” (+30.0dB)
Addr
0AH
0DH
Register Name
Lch Digital Volume Control
Rch Digital Volume Control
Default
Register Name
ALC Mode Control 3
Default
D7
DVL7
DVR7
0
D3
IVL3
IVR3
0
D2
IVL2
IVR2
0
D1
IVL1
IVR1
0
D0
IVL0
IVR0
1
D6
DVL6
DVR6
0
D5
DVL5
DVR5
0
D4
DVL4
DVR4
1
D3
DVL3
DVR3
1
D2
DVL2
DVR2
0
D1
DVL1
DVR1
0
D0
DVL0
DVR0
0
D4
0
0
D3
0
0
D2
0
0
D1
0
0
D0
0
0
D1
DEM1
0
D0
DEM0
1
(see Table 33)
D7
RGAIN1
0
LMTH1: ALC
Register Name
Mode Control 3
Default
DEM1-0:
Default: “01” (OFF)
BST1-0:
Default: “00” (OFF)
DVOLC:
0: Independent
1: Dependent (Default)
DVOLC bit = “1”
DVR7-0 bit DVL7-0 bit
D6
LMTH1
0
D5
0
0
/
RGAIN1: ALC
Addr
0EH
D4
IVL4
IVR4
0
; 0.375dB step, 242 Level (Table 30)
DVL7-0, DVR7-0:
Default: “18H” (0dB)
Addr
0BH
D5
IVL5
IVR5
1
(see Table 23)
(see Table 27)
D7
0
0
D6
LOOP
0
D5
SMUTE
0
D4
DVOLC
1
D3
BST1
0
D2
BST0
0
(Table 31)
(Table 32)
DVL7-0 bit
SMUTE:
0: Normal Operation (Default)
1: DAC outputs soft-muted
LOOP:
0: SDTI → DAC (Default)
1: SDTO → DAC
MS0566-J-00
2006/11
- 55 -
ASAHI KASEI
Addr
0FH
[AK4647]
Register Name
Mode Control 4
Default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
IVOLC
1
D2
HPM
0
D1
BEEPH
0
D0
DACH
0
DACH: DAC
0: OFF (Default)
1: ON
BEEPH: MIN pin
0: OFF (Default)
1: ON
HPM:
0:
1:
(Default)
HPM bit = “1”
DAC
IVOLC: IVOL
0: Independent
1: Dependent (Default)
IVOLC bit = “1”
Addr
10H
(L+R)/2
IVL7-0 bit
Register Name
Power Management 3
Default
D7
0
0
IVOL
D6
0
0
D5
HPG
0
D4
MDIF2
0
IVR7-0 bit
D3
MDIF1
0
D2
INR
0
D1
INL
0
IVL7-0 bit
D0
PMADR
0
PMADR: MIC-Amp Rch, ADC Rch
0: Power down (Default)
1: Power up
INL: ADC Lch
0: LIN1 pin (Default)
1: LIN2 pin
INR: ADC Rch
0: RIN1 pin (Default)
1: RIN2 pin
MDIF1:
0:
1:
MDIF2:
0:
1:
/
1
(LIN1/RIN1 pin: Default)
(IN1+/IN1− pin)
Pin#46 #47
2
(LIN2/RIN2 pin: Default)
(IN2+/IN2− pin)
Pin#45 #44
HPG:
0: 0dB (Default)
1: +3.6dB
/
(Table 39)
MS0566-J-00
2006/11
- 56 -
ASAHI KASEI
Addr
11H
Register Name
Digital Filter Select
Default
GN1-0: Gain
Default: “00” (0dB)
FIL3:
0:
1:
[AK4647]
D7
GN1
0
D6
GN0
0
D5
0
0
D2
FIL3
0
D1
0
0
D0
0
0
FIL3
(Default)
FIL3 bit = “0”
FIL3
(Default)
EQ bit = “1”
EQ
FIL1:
0:
1:
D3
EQ
0
(Table 21)
FIL3 bit = “1”
F3A13-0, F3B13-0 bit
OFF(MUTE)
EQ:
0:
1:
D4
FIL1
0
EQA15-0, EQB13-0, EQC15-0 bit
(0dB)
EQ bit = “0”
FIL1
(Default)
FIL1 bit = “1”
F1A13-0, F1B13-0 bit
FIL1 bit = “0”
FIL1
(0dB)
MS0566-J-00
2006/11
- 57 -
ASAHI KASEI
Addr
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
[AK4647]
Register Name
FIL3 Co-efficient 0
FIL3 Co-efficient 1
FIL3 Co-efficient 2
FIL3 Co-efficient 3
EQ Co-efficient 0
EQ Co-efficient 1
EQ Co-efficient 2
EQ Co-efficient 3
EQ Co-efficient 4
EQ Co-efficient 5
FIL1 Co-efficient 0
FIL1 Co-efficient 1
FIL1 Co-efficient 2
FIL1 Co-efficient 3
Default
D7
F3A7
F3AS
F3B7
0
EQA7
EQA15
EQB7
0
EQC7
EQC15
F1A7
F1AS
F1B7
0
0
F3A13-0, F3B13-0:
Default: “0000H”
F3AS:
0: HPF (Default)
1: LPF
D6
F3A6
0
F3B6
0
EQA6
EQA14
EQB6
0
EQC6
EQC14
F1A6
0
F1B6
0
0
FIL3
D5
F3A5
F3A13
F3B5
F3B13
EQA5
EQA13
EQB5
EQB13
EQC5
EQC13
F1A5
F1A13
F1B5
F1B13
0
D3
F3A3
F3A11
F3B3
F3B11
EQA3
EQA11
EQB3
EQB11
EQC3
EQC11
F1A3
F1A11
F1B3
F1B11
0
D2
F3A2
F3A10
F3B2
F3B10
EQA2
EQA10
EQB2
EQB10
EQC2
EQC10
F1A2
F1A10
F1B2
F1B10
0
D1
F3A1
F3A9
F3B1
F3B9
EQA1
EQA9
EQB1
EQB9
EQC1
EQC9
F1A1
F1A9
F1B1
F1B9
0
D0
F3A0
F3A8
F3B0
F3B8
EQA0
EQA8
EQB0
EQB8
EQC0
EQC8
F1A0
F1A8
F1B0
F1B8
0
(14bit x 2)
FIL3
EQA15-0, EQB13-0, EQC15-C0:
Default: “0000H”
F1A13-0, F1B13-B0:
Default: “0000H”
F1AS:
0: HPF (Default)
1: LPF
D4
F3A4
F3A12
F3B4
F3B12
EQA4
EQA12
EQB4
EQB12
EQC4
EQC12
F1A4
F1A12
F1B4
F1B12
0
(14bit x 2 + 16bit x 1)
FIL1
(14bit x 2)
FIL1
MS0566-J-00
2006/11
- 58 -
ASAHI KASEI
Figure 45
[AK4647]
Figure 46
(AKD4647)
Headphone
0.22u
10
0.22u
10
47u
0.1u
10
6.8
47u
10u
6.8
Power Supply
2.6 ∼ 3.6V
37 NC
200
Line Out
1u
1u
200
External MIC
Internal MIC
NC 25
MCKI 26
MCKO 27
NC 28
NC 29
TEST1 30
TEST2 31
HVSS 33
NC 24
38 NC
DVSS 23
39 ROUT
DVDD 22
40 LOUT
42 MIN
AK4647VQ
43 NC
Top View
LRCK 20
DSP
NC 19
SDTO 18
44 RIN2/IN2−
SDTI 17
45 LIN2/IN2+
CDTI/SDA 16
46 LIN1/IN1−
CCLK/SCL 15
47 RIN1/IN1+
CSN/CAD0 14
μP
NC 13
12 NC
11 NC
10 NC
9 PDN
8 NC
7 I2C
6 VCOC
Rp
0.1u
5 AVDD
4 NC
3 AVSS
2.2u
0.1u
2 VCOM
1 NC
48 MPWR
2.2k
2.2k
2.2k
2.2k
0.1u
BICK 21
41 NC
Mono In
HVDD 32
HPR 34
HPL 35
20k
20k
MUTET 36
1u
Cp
Analog Ground
:
- AK4647
- EXT
- PLL
-
Digital Ground
AVSS, DVSS, HVSS
(PMPLL bit = “0”)
(PMPLL bit = “1”)
VCOC pin
Cp Rp Table 4
M/S bit “1”
AK4647
AK4647 LRCK, BICK pin 100kΩ
Figure 45.
(
MS0566-J-00
LRCK, BICK pin
)
2006/11
- 59 -
ASAHI KASEI
[AK4647]
Headphone
0.22u
10
0.22u
10
47u
0.1u
10
6.8
47u
10u
6.8
Power Supply
2.6 ∼ 3.6V
37 NC
200
Line Out
1u
1u
200
Line In
NC 25
MCKI 26
MCKO 27
NC 28
NC 29
TEST1 30
TEST2 31
HVSS 33
NC 24
38 NC
DVSS 23
39 ROUT
DVDD 22
40 LOUT
0.1u
BICK 21
41 NC
Mono In
HVDD 32
HPR 34
HPL 35
20k
20k
MUTET 36
1u
42 MIN
AK4647VQ
43 NC
Top View
LRCK 20
DSP
NC 19
SDTO 18
44 RIN2/IN2−
SDTI 17
45 LIN2/IN2+
CDTI/SDA 16
46 LIN1/IN1−
CCLK/SCL 15
47 RIN1/IN1+
CSN/CAD0 14
μP
NC 13
2.2u
12 NC
11 NC
10 NC
9 PDN
8 NC
7 I2C
6 VCOC
Rp
0.1u
5 AVDD
4 NC
3 AVSS
2 VCOM
0.1u
1 NC
48 MPWR
Cp
Analog Ground
:
- AK4647
- EXT
- PLL
-
Digital Ground
AVSS, DVSS, HVSS
(PMPLL bit = “0”)
(PMPLL bit = “1”)
VCOC pin
Cp Rp Table 4
M/S bit “1”
AK4647
AK4647 LRCK, BICK pin 100kΩ
Figure 46.
(
MS0566-J-00
LRCK, BICK pin
)
2006/11
- 60 -
ASAHI KASEI
[AK4647]
1.
AVDD, DVDD, HVDD
AVDD, DVDD, HVDD
AVSS, DVSS, HVSS
PC
2.
VCOM
2.2μF
0.1μF
AVSS
VCOM pin
VCOM pin
3.
MIN
(0.45 x AVDD)
0.06 x AVDD Vpp(typ)@MGAIN1-0 bits = “01”, 0.03 x AVDD
Vpp(typ)@MGAIN1-0 bits = “10”, 0.015 x AVDD Vpp(typ)@MGAIN1-0 bits = “11”
0.6 x AVDD
Vpp(typ)@MGAIN1-0 bits = “00”
MIN
(0.45 x AVDD)
0.6 x AVDD Vpp(typ)
DC
fc=1/(2πRC)
AK4647 AVSS
AVDD
4.
DAC
8000H(@16bit)
2’s
0000H(@16bit)
0.45 x AVDD (typ)
MS0566-J-00
7FFFH(@16bit)
VCOM
VCOM
HVDD/2
2006/11
- 61 -
ASAHI KASEI
[AK4647]
„
ADC
DAC
Power-up
1. PLL
Example:
Power Supply
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
(1)
PDN pin
(2)
(3)
PMVCM bit
(Addr:00H, D6)
(4)
(1) Power Supply & PDN pin = “L” Æ “H”
MCKO bit
(Addr:01H, D1)
PMPLL bit
(2)Addr:01H, Data:08H
Addr:04H, Data:4AH
Addr:05H, Data:27H
(Addr:01H, D0)
(5)
MCKI pin
Input
M/S bit
(3)Addr:00H, Data:40H
(Addr:01H, D3)
40msec(max)
(6)
BICK pin
LRCK pin
Output
(4)Addr:01H, Data:0BH
Output
MCKO, BICK and LRCK output
40msec(max)
(8)
MCKO pin
(7)
Figure 47. Clock Set Up Sequence (1)
<
>
PDN pin “L” Æ “H”
AK4647
150ns
“L”
(2)
DIF1-0, PLL3-0, FS3-0, BCKO, M/S bits
(3) VCOM
: PMVCM bit = “0” Æ “1”
VCOM
(4) MCKO
: MCKO bit = “1”
MCKO
: MCKO bit = “0”
(5) PMPLL bit “0” Æ “1”
MCKI pin
PLL
40ms(max)
(6) PLL
BICK, LRCK
(7) MCKO bit = “1”
MCKO pin
(8) MCKO bit = “1”
PLL
MCKO pin
(1)
MS0566-J-00
PLL
2006/11
- 62 -
ASAHI KASEI
[AK4647]
2. PLL
(LRCK or BICK pin)
Example:
Power Supply
Audio I/F Format : MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
(1)
PDN pin
(2)
4fs
(1)ofPower Supply & PDN pin = “L” Æ “H”
(3)
PMVCM bit
(Addr:00H, D6)
PMPLL bit
(2) Addr:04H, Data:32H
Addr:05H, Data:27H
(Addr:01H, D0)
LRCK pin
BICK pin
Input
(3) Addr:00H, Data:40H
(4)
Internal Clock
(5)
(4) Addr:01H, Data:01H
Figure 48. Clock Set Up Sequence (2)
<
>
PDN pin “L” Æ “H”
AK4647
150ns
“L”
(2)
DIF1-0, FS3-0, PLL3-0 bits
(3) VCOM
: PMVCM bit = “0” Æ “1”
VCOM
(4) PMPLL bit “0” Æ “1”
PLL
(LRCK or BICK pin)
PLL
LRCK PLL
2ms(max)
(5) PLL
(1)
MS0566-J-00
PLL
160ms(max), BICK
PLL
2006/11
- 63 -
ASAHI KASEI
[AK4647]
3. PLL
(MCKI pin)
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
Power Supply
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(2)
(3)
(2)Addr:04H, Data:4AH
Addr:05H, Data:27H
PMVCM bit
(Addr:00H, D6)
(4)
MCKO bit
(Addr:01H, D1)
(3)Addr:00H, Data:40H
PMPLL bit
(Addr:01H, D0)
(5)
MCKI pin
(4)Addr:01H, Data:03H
Input
40msec(max)
(6)
MCKO pin
MCKO output start
Output
(7)
(8)
BICK pin
LRCK pin
Input
BICK and LRCK input start
Figure 49. Clock Set Up Sequence (3)
<
>
PDN pin “L” Æ “H”
AK4647
150ns
“L”
(2)
DIF1-0, PLL3-0, FS3-0, BCKO, M/S bits
(3) VCOM
PMVCM bit = “0” Æ “1”
VCOM
(4) MCKO
: MCKO bit = “1”
(5) PMPLL bit “0” Æ “1”
MCKI pin
PLL
40ms(max)
(6) PLL
MCKO pin
(7)
MCKO pin
(8) MCKO
BICK, LRCK
(1)
MS0566-J-00
PLL
2006/11
- 64 -
ASAHI KASEI
[AK4647]
4.
(
)
Example:
Audio I/F Format: MSB justified (ADC and DAC)
Input MCKI frequency: 256fs
Sampling Frequency: 44.1kHz
MCKO: Disable
Power Supply
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(2)
(2) Addr:04H, Data:02H
Addr:05H, Data:00H
(3)
PMVCM bit
(Addr:00H, D6)
(4)
MCKI pin
Input
(3) Addr:00H, Data:40H
(4)
LRCK pin
BICK pin
Input
MCKI, BICK and LRCK input
Figure 50. Clock Set Up Sequence (4)
<
>
PDN pin “L” Æ “H”
AK4647
150ns
(2)
DIF1-0, FS1-0 bits
(3) VCOM
PMVCM bit = “0” Æ “1”
VCOM
(4) MCKI, LRCK, BICK
(1)
MS0566-J-00
“L”
2006/11
- 65 -
ASAHI KASEI
[AK4647]
„
Example:
FS3-0 bits
(Addr:05H, D5&D2-0)
0,000
PLL Master Mode
Audio I/F Format:MSB justified (ADC & DAC)
Sampling Frequency:44.1kHz
Pre MIC AMP:+20dB
MIC Power On
ALC setting:Refer to Table 29
ALC bit=“1”
1,111
(1)
MIC Control
(1) Addr:05H, Data:27H
001
(Addr:02H, D2-0)
101
(2) Addr:02H, Data:05H
(2)
ALC Control 1
00H
(Addr:06H)
3CH
(3) Addr:06H, Data:3CH
E1H
(4) Addr:08H, Data:E1H
(3)
ALC Control 2
E1H
(Addr:08H)
(4)
(5) Addr:0BH, Data:00H
ALC Control 3
00H
(Addr:0BH)
00H
(6) Addr:07H, Data:21H
(5)
ALC Control 4
07H
(Addr:07H)
21H
01H
(9)
(6)
ALC State
ALC Disable
ALC Enable
(7) Addr:00H, Data:41H
Addr:10H, Data:01H
ALC Disable
Recording
PMADL/R bits
(Addr:00H&10H, D0)
ADC Internal
State
(8) Addr:00H, Data:40H
Addr:10H, Data:00H
1059 / fs
(8)
(7)
Power Down
Initialize Normal State Power Down
(9) Addr:07H, Data:01H
Figure 51. MIC Input Recording Sequence
<
>
fs=44.1kHz
”
ALC
ALC
“Figure 25. ALC
(1)
(FS3-0 bits)
PLL
PLL
(7)
ADC
(2)
(
02H)
(3) ALC Timer (
06H)
(4) ALC REF (
08H)
(5) LMTH1, RGAIN1 bits
(
0BH)
(6) LMTH0, RGAIN0, LMAT1-0, ALC bits
(
07H)
(7)
ADC
: PMADL = PMADR bits = “0” → “1”
ADC
1059/fs=24ms@fs=44.1kHz
ALC
(IVL/R7-0 bits)
(+30dB)
HPF
“1”
(8)
PMMP bit = “1”
4
ADC
ADC
ADC
AC
PMVCM bit =
60k(typ)
Power-up
: PMADL = PMADR bits = “1” → “0”
ALC Disable
ALC
(ALC bit = “0”)
ADC
(PMADL = PMADR bits = “0”)
PMADL = PMADR bits = “0”
(IVL/R7-0 bits)
(9) ALC Disable: ALC bit = “1” → “0”
MS0566-J-00
2006/11
- 66 -
ASAHI KASEI
[AK4647]
„
Example:
FS3-0 bits
(Addr:05H, D5&D2-0)
0,000
(1)
DACH bit
(2)
(Addr:0FH, D0)
BST1-0 bits
(Addr:0EH, D3-2)
IVL/R7-0 bits
(Addr:09H&0CH, D7-0)
PLL, Master Mode
Audio I/F Format :MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Digital Volume: −8dB
Bass Boost level : Middle
1,111
(13)
00
10
00
(3)
(12)
E1H
91H
(1) Addr:05H, Data:27H
(2) Addr:0FH, Data:09H
(3) Addr:0EH, Data:19H
(4) Addr:09H&0CH, Data:91H
(4)
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
(5) Addr:0AH&0DH, Data:28H
18H
28H
(6) Addr:00H, Data:64H
(5)
PMDAC bit
(7) Addr:01H, Data:39H
(Addr:00H, D2)
(6)
(11)
(8) Addr:01H, Data:79H
PMBP bit
(Addr:00H, D5)
PMHPL/R bits
Playback
(7)
(10)
(9) Addr:01H, Data:39H
(Addr:01H, D5-4)
(10) Addr:01H, Data:09H
HPMTN bit
(8)
(9)
(11) Addr:00H, Data:40H
(Addr:01H, D6)
HPL/R pins
Normal Output
(12) Addr:0EH, Data:11H
(13) Addr:0FH, Data:08H
Figure 52. Headphone-Amp Output Sequence
<
>
(1)
(FS3-0 bits)
(2) DAC Æ HP-Amp
: DACH bit = “0” → “1”
(3)
(BST1-0 bits)
(4)
(
09H&0CH)
PMADL = PMADR bits = “0”
IVL7-0 = IVR7-0 bits = “91H”(0dB)
(5)
(
0AH&0DH)
DVOLC bit = “1”(default)
DVL7-0bits(0AH) Lch
Rch
DAC
Default (0dB)
(6) DAC
MIN-Amp
: PMDAC = PMBP bits = “0” → “1”
(1059/fs=24ms@fs=44.1kHz) DAC
2’s
“0”
DAC
(22/fs=0.5ms@fs=44.1kHz)
DAC
PMADL bit
PMADR bit “1”
DAC
ALC bit = “1”
(1059/fs = 24ms
@fs=44.1kHz) ALC
(ALC
IVL/R7-0 bits
)
ALC IVL/R7-0 bits
(7)
: PMHPL = PMHPR bits = “0” → “1”
HVSS
(8)
: HPMTN bit = “0” → “1”
MUTET pin
HVDD
MUTET pin
C
= 1μF, HVDD=3.3V
τr =100ms(typ), 250ms(max)
(9)
: HPMTN bit = “1” → “0”
MUTET pin
HVDD
MUTET pin
C
= 1μF, HVDD=3.3V
τf =100ms(typ), 250ms(max)
HVSS
HVSS
2
(10)
: PMHPL = PMHPR bits = “1” → “0”
(11) DAC
MIN-Amp
: PMDAC = PMBP bits = “1” → “0”
(12)
OFF: BST1-0 bits = “00”
(13) DAC Æ HP-Amp
Disable: DACH bit = “1” → “0”
MS0566-J-00
2006/11
- 67 -
ASAHI KASEI
[AK4647]
„
Example:
FS3-0 bits
(Addr:05H, D5&D2-0)
0,000
PLL, Master Mode
Audio I/F Format :MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Digital Volume: −8dB
LOVL=MINL bits = “0”
1,111
(1)
(1) Addr:05H, Data:27H
(10)
DACL bit
(2)
(2) Addr:02H, Data:10H
(Addr:02H, D4)
IVL/R7-0 bits
(Addr:09H&0CH, D7-0)
E1H
(3) Addr:09H&0CH, Data:91H
91H
(3)
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
(4) Addr:0AH&0DH, Data:28H
18H
28H
(5) Addr:03H, Data:40H
(4)
LOPS bit
(6) Addr:00H, Data:6CH
(Addr:03H, D6)
(5)
(7)
(8)
(11)
PMDAC bit
(Addr:00H, D2)
Playback
PMBP bit
(8) Addr:03H, Data:40H
(Addr:00H, D5)
(6)
(9)
(9) Addr:00H, Data:40H
PMLO bit
(Addr:00H, D3)
(7) Addr:03H, Data:00H
>300 ms
(10) Addr:02H, Data:00H
LOUT pin
ROUT pin
>300 ms
Normal Output
(11) Addr:03H, Data:00H
Figure 53. Stereo Lineout Sequence
<
>
(1)
(FS3-0 bits)
(5) DAC
PLL
(2) DAC Æ
: DACL bit = “0” Æ “1”
(3)
(
09H&0CH)
PMADL = PMADR bits = “0”
IVL7-0 = IVR7-0 bits = “91H”(0dB)
(4)
(
0AH&0DH)
DVOLC bit = “1”(default)
DVL7-0bits(0AH) Lch
Rch
DAC
Default (0dB)
(5)
: LOPS bit = “0” Æ “1”
(6) DAC, MIN-Amp
: PMDAC = PMBP = PMLO bits = “0” → “1”
(1059/fs=24ms@fs=44.1kHz) DAC
2’s
“0”
DAC
(22/fs=0.5ms@fs=44.1kHz)
DAC
PMADL bit
PMADR bit “1”
DAC
ALC bit = “1”
(1059/fs = 24ms
@fs=44.1kHz) ALC
(ALC
IVL/R7-0 bits
)
ALC IVL/R7-0 bits
PMLO bit = “1” LOUT, ROUT pins
C = 1μF, AVDD=3.3V
max. 300ms
(7)
: LOPS bit = “1” Æ “0”
LOUT, ROUT pins
LOUT, ROUT pins
: LOPS bit: “0” Æ “1”
: PMDAC = PMBP = PMLO bits = “1” → “0”
C = 1μF, AVDD=3.3V
max. 300ms
(8)
(9) DAC, MIN-Amp
LOUT, ROUT pins
(10) DAC Æ
(11)
LOUT, ROUT pins
Disable: DACL bit = “1” Æ “0”
: LOPS bit = “1” Æ “0”
MS0566-J-00
2006/11
- 68 -
ASAHI KASEI
[AK4647]
„
ADC
DAC
1. PLL
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
(1)
PMPLL bit
(Addr:01H, D0)
(2)
MCKO bit
"1" or "0"
(1) (2) Addr:01H, Data:08H
(Addr:01H, D1)
(3)
External MCKI
Input
(3) Stop an external MCKI
Figure 54. Clock Stopping Sequence (1)
<
>
(1) PLL
(2) MCKO
(3)
: PMPLL bit = “1” → “0”
: MCKO bit = “1” → “0”
2. PLL
(LRCK, BICK pin)
Example
Audio I/F Format : MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
(1)
PMPLL bit
(Addr:01H, D0)
(2)
External BICK
Input
(1) Addr:01H, Data:00H
(2)
External LRCK
Input
(2) Stop the external clocks
Figure 55. Clock Stopping Sequence (2)
<
>
(1) PLL
(2)
: PMPLL bit = “1” → “0”
MS0566-J-00
2006/11
- 69 -
ASAHI KASEI
[AK4647]
3. PLL
(MCKI pin)
Example
(1)
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: MCKI
BICK frequency: 64fs
PMPLL bit
(Addr:01H, D0)
(1)
MCKO bit
(1) Addr:01H, Data:00H
(Addr:01H, D1)
(2)
External MCKI
Input
(2) Stop the external clocks
Figure 56. Clock Stopping Sequence (3)
<
>
(1) PLL
MCKO
(2)
: PMPLL bit = “1” → “0”
: MCKO bit = “1” → “0”
4.
(1)
External MCKI
Input
Example
(1)
External BICK
Input
External LRCK
Input
Audio I/F Format :MSB justified(ADC & DAC)
Input MCKI frequency:1024fs
(1)
(1) Stop the external clocks
Figure 57. Clock Stopping Sequence (4)
<
>
(1)
„
10μA)
PMVCM bit = “0”
PDN pin = “L”
MS0566-J-00
(typ.
(typ. 10μA)
2006/11
- 70 -
ASAHI KASEI
[AK4647]
48pin LQFP(Unit:mm)
1.70Max
9.0 ± 0.2
0.13 ± 0.13
7.0
36
25
24
48
13
7.0
37
1
9.0 ± 0.2
1.40 ± 0.05
12
0.16 ± 0.07
0.22 ± 0.08
0.5
0.10 M
0° ∼ 10°
0.10
0.5 ± 0.2
„
:
:
:
MS0566-J-00
2006/11
- 71 -
ASAHI KASEI
[AK4647]
AK4647VQ
XXXXXXX
1
XXXXXXX: Date code identifier
Date (YY/MM/DD)
06/11/10
Revision
00
Reason
Page
Contents
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MS0566-J-00
2006/11
- 72 -