データシート

[AK4128A]
AK4128A
8ch 216kHz / 24-Bit Asynchronous SRC
AK4128A
8ch
8kHz ∼ 216kHz
(SRC)
8kHz ∼ 216kHz
TDM
/DVD
• 8 channels input/output
• Asynchronous Sample Rate Converter
• Input Sample Rate Range (FSI): 8kHz ∼ 216kHz
• Output Sample Rate Range (FSO): 8kHz ∼ 216kHz
• Input to Output Sample Rate Ratio: 1/6 to 6
• THD+N: −130dB
• Dynamic Range: 140dB (A-weighted)
• I/F format: MSB justified, LSB justified, I2S compatible and TDM
• Oscillator for Internal Operation Clock
• Clock for Master mode: 128/256/384/512/768fso
• On-chip X’tal oscillator
• Digital De-emphasis Filter (32kHz, 44.1kHz and 48kHz)
• Soft Mute Function
• SRC Bypass mode (Master/Slave)
• μP Interface: I²C bus
• Power Supply: AVDD, DVDD1-4: 3.0 ∼ 3.6V (typ. 3.3V)
• Ta = −20 ∼ 85°C (AK4128AEQ), −40 ∼ 85°C (AK4128AVQ)
• Package: 64LQFP
MS1242-J-01
2011/06
-1-
DITHER
SMT1
SMT0
SMSEMI
SMUTE
VSS2-5
DVDD1-4
INAS
DEM1
DEM0
IDIF2
IDIF1
IDIF0
[AK4128A]
OLRCK
OBICK
SRC1
Bypass
Input
Serial
Audio
I/F
IBICK1
ILRCK1
SDTI1
DEM
FIR
SRC
SMUTE
+
Dither
0.5 LSB
SRC
DEM
FIR
+
SMUTE
SRC
SRC
Dither
DEM
FIR
SRC
Dither
DEM
FIR
SRC4
+
SMUTE
SRC
SRC
Dither
IMCLK
PDN
PM1
PM2
Internal
OSC
uP
I/F
CAD0
SDTO3
0.5 LSB
Bypass
Input
Serial
Audio
I/F
IBICK4
ILRCK4
SDTI4
SDTO4
0.5 LSB
UNLOCK
Bypass
X’tal
Osc
MCKO
Clock
Div
SDA SCL XTO OMCLK/XTI
SPB
SDTO2
SRC3
+
SMUTE
SRC
ODIF1
ODIF0
Output
Serial
Audio
I/F
0.5 LSB
Bypass
Input
Serial
Audio
I/F
IBICK3
ILRCK3
SDTI3
OBIT1
OBIT2
SRC2
Bypass
Input
Serial
Audio
I/F
IBICK2
ILRCK2
SDTI2
SDTO1
Internal
Regulator
SRC
CM2 CM1 CM0
REF
AVDD
VSS1
VD18
DITHER
SMT1
SMT0
SMSEMI
SMUTE
VSS2-5
DVDD1-4
INAS
DEM1
DEM0
IDIF2
IDIF1
IDIF0
Figure 1. AK4128A Block Diagram (Synchronous mode INAS pin = “L”)
OLRCK
OBICK
SRC1
Bypass
Input
Serial
Audio
I/F
IBICK1
ILRCK1
SDTI1
DEM
FIR
SRC
SMUTE
SRC
Dither
+
IBICK2
ILRCK2
SDTI2
DEM
FIR
SRC
SMUTE
SRC
DEM
FIR
SRC
0.5LSB
SMUTE
SRC
+
DEM
FIR
SRC
SRC4
SMUTE
SRC
Dither
IMCLK
PDN
PM1
PM2
Internal
OSC
uP
I/F
CAD0
X’tal
Osc
SDA SCL XTO OMCLK/XTI
SPB
SDTO3
0.5LSB
Bypass
Input
Serial
Audio
I/F
+
SDTO4
0.5LSB
UNLOCK
Bypass
Clock
Div
CM2 CM1 CM0
SDTO2
SRC3
Dither
IBICK4
ILRCK4
SDTI4
Output
Serial
Audio
I/F
+
Bypass
Input
Serial
Audio
I/F
ODIF1
ODIF0
SRC2
Dither
IBICK3
ILRCK3
SDTI3
OBIT1
OBIT0
0.5LSB
Bypass
Input
Serial
Audio
I/F
SDTO1
MCKO
SRC
Internal
Regulator
REF
AVDD
VSS1
VD18
Figure 2. AK4128A Block Diagram (Asynchronous mode INAS pin = “H”)
MS1242-J-01
2011/06
-2-
[AK4128A]
■ AK4126
(1)
AK4126
AK4128A
INAS pin
PLL
PLL2-0 pin PLL
61
PLL
61
PLL
CM2-0 pin
FSI,
FSO
IBICK, OBICK
BYPS bit
CM2-0 pin
216kHz
256fs
192kHz
64fs
TDM Mode
IDIF2-0
TDM pin
IDIF2-0 bit
SMUTE4-1
bit
DEM41-40,
31-30, 21-20, 11-10 bit
IDIF42-40,
32-30, 22-20, 12-10 bit
I2C
SPB pin
PLL
FSI FSO
1.8V
MS1242-J-01
2011/06
-3-
[AK4128A]
(2)
Pin#
AK4126
AK4128A
Pin Name
Pin Name
1
2
7
14
15
16
17
18
32
33
42
47
48
49
51
54
55
56
57
58
59
61
NC
TEST0
TST0
TST1
TST2
NC
TST3
TST4
TST5
NC
TST6
TEST4
NC
NC
TST8
PLL2
PLL1
PLL0
TST9
TST10
NC
FILT
IBICK2
IMCLK
SDTI4
ILRCK3
IBICK3
ILRCK4
IBICK4
INAS
PM2
TDM
SDTO4
OMCLK/XTI
XTO
MCKO
CAD0
TST1
SMSEMI
TST2
SCL
SDA
SPB
VD18
63
TST11
TST3
NC
ILRCK2
64
*: 61
AK4126
AK4126
(PM2/1 pin = “LL”)
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L or H
L or H
L or H
L
L
L
*
AK4126: “Open”
AK4128A: “L”
L
AK4128A
FILT
VD18
R
C2
1uF
C1
Figure 3. AK4126
(Figure 3
Figure 4. AK4128A
)
AK4126
MS1242-J-01
2011/06
-4-
[AK4128A]
■
−20 ∼ +85°C
−40 ∼ +85°C
AK4128A
AK4128AEQ
AK4128AVQ
AKD4128A
64pin LQFP (0.5mm pitch)
64pin LQFP (0.5mm pitch)
DVDD3
SDTO4
SDTO1
SDTO2
SD TO3
ODIF0
ODIF1
CM0
CM1
CM2
TDM
42
41
40
39
38
37
36
35
34
33
OBICK
45
VSS4
OLRCK
46
43
OMCLK/XTI
47
44
XTO
48
■
MCKO
49
32
PM 2
TST0
50
31
OBIT1
CAD0
51
30
OBIT0
D VDD4
52
29
PM 1
VSS5
53
28
DEM 1
TST1
54
27
DEM 0
SMSEM I
55
26
SM T1
TST2
56
25
SM T0
Top View
14
15
16
IBICK3
ILRCK4
IBICK4
ILRCK3
17
13
64
IDIF2
IL RCK2
12
INAS
IDIF1
18
11
63
IDIF0
TST3
10
UNLOCK
SDTI3
62
9
VSS1
SDTI2
DVDD 2
19
8
20
SDTI1
61
7
VD 18
SDTI4
VSS3
6
21
5
60
VSS2
AVDD
4
SM UTE
IBICK1
22
DVDD1
59
3
SPB
ILRCK1
DITHER
2
PDN
23
IMCLK
24
1
57
58
IBICK2
SCL
SDA
MS1242-J-01
2011/06
-5-
[AK4128A]
No.
Pin Name
I/O
1
IBICK2
I
2
3
4
5
6
7
8
9
10
11
12
13
IMCLK
ILRCK1
IBICK1
DVDD1
VSS2
SDTI4
SDTI1
SDTI2
SDTI3
IDIF0
IDIF1
IDIF2
I
I
I
I
I
I
I
I
I
I
14
ILRCK3
I
15
IBICK3
I
16
ILRCK4
I
17
IBICK4
I
18
INAS
I
19
UNLOCK
O
20
21
22
23
DVDD2
VSS3
SMUTE
DITHER
I
I
24
PDN
I
25
26
27
28
29
30
31
32
SMT0
SMT1
DEM0
DEM1
PM1
OBIT0
OBIT1
PM2
I
I
I
I
I
I
I
I
33
TDM
I
Function
2
INAS pin = “L”
VSS2-5
1
1
3.0 ∼ 3.6V
4
1
2
3
0
1
2
INAS pin = “L”
(Note 2)
(Note 2)
(Note 2)
3
VSS2-5
3
INAS pin = “L”
INAS pin = “L”
VSS2-5
4
VSS2-5
4
INAS pin = “L”
VSS2-5
“L” (
“H” (DVDD1-4
):
):
PDN pin= “L”
UNLOCK
3.0 ∼ 3.6V
(Note 3)
“H”:
“H”
“H” : Soft Mute, “L” : Normal Operation
“H”: Dither ON, “L”: Dither OFF
, “L”:
“L”
AK4128A
0
1
0 (Note 4)
1 (Note 4)
1
0
1
2
TDM
“L”(
“H”(DVDD1-4
): Stereo mode.
): TDM mode.
MS1242-J-01
2011/06
-6-
[AK4128A]
No.
34
35
36
37
38
Pin Name
CM2
CM1
CM0
ODIF1
ODIF0
39
SDTO3
O
40
SDTO2
O
41
SDTO1
O
42
SDTO4
O
43
44
VSS4
DVDD3
-
45
OBICK
I/ O
46
OLRCK
I/ O
47
OMCLK/XTI
I
48
XTO
O
49
MCKO
O
50
TST0
I
51
CAD0
I
52
53
DVDD4
VSS5
-
54
TST1
I
55
SMSEMI
I
56
TST2
I
57
SCL
I/O
I
I
I
I
I
I
58
SDA
I/ O
59
SPB
I
Function
2
1
0
/
/
/
1
0
3
SDTO3
“L”
2
PDN pin = “L”
SDTO2
“L”
1
PDN pin= “L”
SDTO1
“L”
4
SDTO4
“L”
3.0 ∼ 3.6V
PDN pin= “L”
OBICK
“L”
PDN pin= “L”
/
OLRCK
“L”
PDN pin= “L”
XTO
Hi-Z
PM2 pin= “H” PDN pin = “L”
PM2 pin= “L” PDN pin= “L”
MCKO
MCKO
L
Hi-Z
VSS2-5
0
(SPB pin = “L”)
3.0 ∼ 3.6V
VSS2-5
VSS2-5
“H”:
, “L”:
VSS2-5
I2C
DVDD1-4
DVDD1-4 + 0.3V
VSS2-5
2
IC
DVDD1-4
DVDD1-4 + 0.3V
“L”)
VSS2-5
(SPB pin= “H”)
(SPB pin= “L”)
(SPB pin= “H”)
(SPB pin=
“H”:
, “L”:
MS1242-J-01
2011/06
-7-
[AK4128A]
No.
60
Pin Name
AVDD
I/O
-
61
VD18
O
62
VSS1
-
63
TST3
I
Function
3.0 ∼ 3.6V
1.8V
PDN pin= “L”
DV18
L
VD18 pin
VD18 pin DVSS
1 [ F] 30%
30%
VD18 pin
VSS2-5
2
VSS2-5
Note:
DVDD1-4
Note 1. SPB, CM2-0, INAS, PM2-1, OBIT1-0, TDM, ODIF1-0, IDIF2-0, CAD0 pin
64
ILRCK2
I
Note 2.
INAS pin = “L”
(SPB pin= “L”)
SRC1
PDN pin= “L”
4
IDIF2-0 pin
bit
SRC3
Note 3.
SRC1
(SPB pin= “H”)
IDIF2-0 pin
IDIF12, IDIF11, IDIF10
SRC1
IDIF22, IDIF21, IDIF20 bit
SRC2
IDIF32, IDIF31, IDIF30 bit
IDIF42, IDIF41, IDIF40 bit
SRC4
(SPB pin= “L”)
SRC1~4
SMUTE pin
(SPB pin= “H”)
SMUTE pin
SMUTE1 bit
SMUTE2 bit
SRC2
SMUTE3 bit
SRC3
SMUTE4 bit
SRC4
Note 4.
(SPB pin= “L”)
SRC1
SRC4
DEM[21:20] bit
(SPB pin= “H”)
SRC2
SRC1~4
DEM1-0 pin
DEM[31:30] bit
DEM1-0 pin
SRC3
DEM[11:10] bit
DEM[41:40] bit
■
Digital
IBICK2, IMCLK, SDTI3 4, ILRCK3,
IBICK3, ILRCK4, IBICK4, SMUTE,
DITHER, OMCLK/XTI, ILRCK2,
SDA, SCL, CAD0, TST0 3
UNLOCK, SDTO1 4, MCKO, XTO
MS1242-J-01
VSS2~5
2011/06
-8-
[AK4128A]
(VSS1-5=0V; Note 5)
Parameter
Symbol
min
max
Units
Analog
AVDD
−0.3
4.2
V
Digital
DVDD1-4
−0.3
4.2
V
Input Current, Any Pin Except Supplies
IIN
±10
mA
Digital Input Voltage
(Note 6)
VIND
−0.3
DVDD1-4 + 0.3
V
Ambient Temperature
AK4128AEQ
Ta
−20
85
°C
(Power applied) (Note 7)
AK4128AVQ
Ta
−40
85
°C
Storage Temperature
Tstg
−65
150
°C
Note 5.
VSS1-5
Note 6. IMCLK, IBICK4-1, ILRCK4-1, IDIF2-0, INAS, SUMTE, DITHER, PDN, SMT1-0, DEM1-0, PM2-1, OBIT1-0,
TDM, CM2-0, ODIF1-0, SDTO4-1, OBICK, OLRCK, OMCLK/XTI, CAD0, SMSEMI, SCL, SDA, SPB pin.
Note 7.
100%
Note 8. DVDD1-4
Power Supplies:
:
(VSS1-5=0V; Note 5)
Parameter
Power Supplies:
(Note 9)
Analog
Digital
Difference
Note 5.
Note 8. DVDD1-4
Note 9. AVDD DVDD1-4
Symbol
AVDD
DVDD1-4
AVDD - DVDD1-4
VSS1-5
min
3.0
3.0
-0.3
typ
3.3
3.3
0
max
3.6
3.6
+0.3
Units
V
V
V
PDN pin= “L”
PDN pin= “H”
:
MS1242-J-01
2011/06
-9-
[AK4128A]
SRC
(Ta=25°C; AVDD=DVDD1-4=3.3V; VSS1-5=0V; Signal Frequency=1kHz; data=24bit; measurement bandwidth =
20Hz ~ FSO/2; unless otherwise specified.)
Parameter
Symbol
min
typ
max
Units
SRC Characteristics:
Resolution
24
Bits
Input Sample Rate
FSI
8
216
kHz
Output Sample Rate
FSO
8
216
kHz
THD+N
(Input = 1kHz, 0dBFS, Note 10)
FSO/FSI = 44.1kHz/48kHz
−130
dB
FSO/FSI = 48kHz/44.1kHz
−124
dB
FSO/FSI = 48kHz/192kHz
−133
dB
FSO/FSI = 192kHz/48kHz
−124
dB
Worst Case (FSO/FSI = 32kHz/176.4kHz)
-91
dB
Dynamic Range (Input = 1kHz, −60dBFS, Note 10)
FSO/FSI = 44.1kHz/48kHz
136
dB
FSO/FSI = 48kHz/44.1kHz
136
dB
FSO/FSI = 48kHz/192kHz
136
dB
FSO/FSI = 192kHz/48kHz
132
dB
Worst Case (FSO/FSI = 48kHz/32kHz)
132
dB
Dynamic Range (Input = 1kHz, −60dBFS, A-weighted, Note 10)
FSO/FSI = 44.1kHz/48kHz
140
dB
Ratio between Input and Output Sample Rate
FSO/FSI
1/6
6
Note 10. Audio Precision System Two Cascade
(Ta=25°C; AVDD=DVDD1-4=3.0~3.6V; VSS1-5=0V; Signal Frequency=1kHz; data=24bit;
4
(INAS pin = “H”), Output PORT: Master mode, OMCLK/XTI
X’tal
, PM2/1 pin = “H/L” 8ch mode, unless
otherwise specified.)
Parameter
min
typ
max
Units
Power Supplies
Power Supply Current
Normal operation (PDN pin = “H”)
AVDD+DVDD1-4
mA
42
FSI=FSO=48kHz: AVDD=DVDD1-4=3.3V (Note 12)
mA
108
FSI=FSO=192kHz: AVDD=DVDD1-4=3.3V (Note 13)
mA
164
109
: AVDD=DVDD1-4=3.6V (Note 14)
Power down (PDN pin = “L”) (Note 11)
μA
100
10
AVDD+DVDD1-4
Note 11.
VSS2-5
Note 12.
OMCLK/XTI
24.576MHz
41 [mA] (typ)
Note 13.
OMCLK/XTI
24.576MHz
105 [mA] (typ)
Note 14.
OMCLK/XTI
24.576MHz
106 [mA] (typ)
MS1242-J-01
2011/06
- 10 -
[AK4128A]
(Ta= 25°C; AVDD=DVDD1-4=3.0 ∼ 3.6V)
Parameter
Symbol
Digital Filter
Passband −0.01dB 0.985 ≤ FSO/FSI ≤ 6.000
PB
0.905 ≤ FSO/FSI < 0.985
PB
0.714 ≤ FSO/FSI < 0.905
PB
0.656 ≤ FSO/FSI < 0.714
PB
0.536 ≤ FSO/FSI < 0.656
PB
0.492 ≤ FSO/FSI < 0.536
PB
0.452 ≤ FSO/FSI < 0.492
PB
0.357 ≤ FSO/FSI < 0.452
PB
0.324 ≤ FSO/FSI < 0.357
PB
0.246 ≤ FSO/FSI < 0.324
PB
0.226 ≤ FSO/FSI < 0.246
PB
0.1667 ≤ FSO/FSI < 0.226
PB
Stopband
0.985 ≤ FSO/FSI ≤ 6.000
SB
0.905 ≤ FSO/FSI < 0.985
SB
0.714 ≤ FSO/FSI < 0.905
SB
0.656 ≤ FSO/FSI < 0.714
SB
0.536 ≤ FSO/FSI < 0.656
SB
0.492 ≤ FSO/FSI < 0.536
SB
0.452 ≤ FSO/FSI < 0.492
SB
0.357 ≤ FSO/FSI < 0.452
SB
0.324 ≤ FSO/FSI < 0.357
SB
0.246 ≤ FSO/FSI < 0.324
SB
0.226 ≤ FSO/FSI < 0.246
SB
0.1667 ≤ FSO/FSI < 0.226
SB
Passband Ripple
PR
Stopband Attenuation 0.985 ≤ FSO/FSI ≤ 6.000
SA
0.905 ≤ FSO/FSI < 0.985
SA
0.714 ≤ FSO/FSI < 0.905
SA
0.656 ≤ FSO/FSI < 0.714
SA
0.536 ≤ FSO/FSI < 0.656
SA
0.492 ≤ FSO/FSI < 0.536
SA
0.452 ≤ FSO/FSI < 0.492
SA
0.357 ≤ FSO/FSI < 0.452
SA
0.324 ≤ FSO/FSI < 0.357
SA
0.246 ≤ FSO/FSI < 0.324
SA
0.226 ≤ FSO/FSI < 0.246
SA
0.1667 ≤ FSO/FSI < 0.226
SA
Group Delay
(Note 15)
GD
Note 15. ILRCK OLRCK
SDTI
OLRCK
MS1242-J-01
min
typ
0
0
0
0
0
0
0
0
0
0
0
0
0.5417FSI
0.5021FSI
0.3965FSI
0.3643FSI
0.2974FSI
0.2813FSI
0.2604FSI
0.2116FSI
0.1969FSI
0.1573FSI
0.1471FSI
0.1020FSI
max
Units
0.4583FSI
0.4167FSI
0.3195FSI
0.2852FSI
0.2182FSI
0.2177FSI
0.1948FSI
0.1458FSI
0.1302FSI
0.0917FSI
0.0826FSI
0.0583FSI
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
1/fs
SDTO
±0.01
121.2
121.4
115.3
116.9
114.6
100.2
103.3
102.0
103.6
103.3
101.5
73.2
-
64
ILRCK
-
2011/06
- 11 -
[AK4128A]
DC
(Ta= 25°C; AVDD=DVDD1-4=3.0 ∼ 3.6V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage
SDA pin
(Iout=−400μA)
Low-Level Output Voltage
SDA pin
(Iout=400μA)
SDA pin
(Iout=3mA)
Input Leakage Current
Symbol
VIH
VIL
min
70%DVDD1-4
-
typ
-
max
30%DVDD1-4
Units
V
V
VOH
DVDD1-4 − 0.4
-
-
V
VOL
VOL
Iin
-
-
-
-
0.4
0.4
±10
V
V
μA
(Ta= 25°C; AVDD=DVDD1-4=3.0 ∼ 3.6V; CL=20pF)
Parameter
Master Clock Timing
Crystal Oscillator Frequency
IMCLK Input
Frequency
Duty
OMCLK Input
128 FSO :
Pulse Width Low
Pulse Width High
256 FSO :
Pulse Width Low
Pulse Width High
384 FSO :
Pulse Width Low
Pulse Width High
512 FSO :
Pulse Width Low
Pulse Width High
768 FSO :
Pulse Width Low
Pulse Width High
MCKO Output
Frequency
Duty (Note 16)
Note 16.
Symbol
min
fXTAL
11.2896
fECLK
dECLK
1.024
40
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
1.024
13
13
2.048
13
13
3.072
10
10
4.096
13
13
6.144
10
10
fMCK
dMCLK
MS1242-J-01
1.024
40
MCKO
typ
50
max
Units
24.576
MHz
36.864
60
MHz
%
27.648
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
27.648
36.864
27.648
36.864
50
36.864
60
MHz
%
Duty
2011/06
- 12 -
[AK4128A]
Input PORT LRCK for Stereo Mode (ILRCK1-4)
Frequency
Duty Cycle
Slave Mode
Output PORT LRCK for StereoMode (OLRCK)
Frequency
Slave mode
Master mode OMCLK
128FSO mode
Master mode OMCLK
256FSO mode
Master mode OMCLK
384FSO mode
Master mode OMCLK
512FSO mode
Master mode OMCLK
768FSO mode
Duty Cycle
Slave Mode
Master Mode
Input PORT LRCK for TDM256 Mode (ILRCK1)
(INAS pin = “L”)
Frequency
“H” time (slave mode)
“L” time (slave mode)
Output PORT LRCK for TDM256 Mode (OLRCK)
Frequency
“H” time (slave mode)
“L” time (slave mode)
“H” time
(Master mode, TDM256 24bit MSB justified)
“L” time
(Master mode, TDM256 24bit I2S)
Audio Interface Timing
Input PORT ( Stereo Slave mode)
IBICK1-4 Period (FSI= 8kHz ∼ 54kHz)
(FSI=54kHz ∼ 108kHz)
(FSI=108kHz ∼ 216kHz)
IBICK1-4 Pulse Width Low
Pulse Width High
ILRCK1-4 Edge to IBICK1-4 “↑”(Note 17)
IBICK1-4 “↑” to ILRCK1-4 Edge (Note 17)
SDTI1-4 Hold Time from IBICK1-4 “↑”
SDTI1-4 Setup Time to IBICK1-4 “↑”
Input PORT (TDM256 slave mode)
IBICK1 Period
IBICK1 Pulse Width Low
Pulse Width High
ILRCK1 Edge to IBICK1 “↑”
(Note 17)
IBICK1 “↑” to ILRCK1 Edge
(Note 17)
SDTI1 Hold Time from IBICK1 “↑”
SDTI1 Setup Time to IBICK1 “↑”
Output PORT ( Stereo Slave mode)
OBICK Period (FSO= 8kHz ∼ 54kHz)
(FSO= 54kHz ∼ 108kHz)
(FSO=108kHz ∼ 216kHz)
OBICK Pulse Width Low
Pulse Width High
OLRCK Edge to OBICK “↑” (Note 17)
OBICK “↑” to OLRCK Edge (Note 17)
OLRCK to SDTO1-4 (MSB) (Except I2S mode)
OBICK “↓” to SDTO1-4
FSI
Duty
8
48
FSO
FSO
FSO
FSO
FSO
FSO
Duty
Duty
8
8
8
8
8
8
48
FSI
tLRH
tLRL
216
52
kHz
%
216
216
108
96
54
48
52
kHz
kHz
kHz
kHz
kHz
kHz
%
%
8
1/256FSI
1/256 FSI
48
kHz
ns
ns
FSO
tLRH
tLRL
8
1/256 FSO
1/256 FSO
48
kHz
ns
ns
tLRH
-
1/8 FSO
-
ns
tLRL
-
1/8 FSO
-
ns
tBCK
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
1/256 FSI
1/128 FSI
1/64 FSI
27
27
15
15
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
81
32
32
20
20
20
10
ns
ns
ns
ns
ns
ns
ns
tBCK
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
1/256 FSO
1/128 FSO
1/64 FSO
27
27
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
MS1242-J-01
50
50
50
20
20
2011/06
- 13 -
[AK4128A]
Output PORT (TDM256 slave mode)
OBICK Period
tBCK
81
OBICK Pulse Width Low
tBCKL
32
Pulse Width High
tBCKH
32
OLRCK Edge to OBICK “↑”
(Note 17)
tLRB
20
OBICK “↑” to OLRCK Edge
(Note 17)
tBLR
20
OBICK “↓” to SDTO1
tBSD
20
Output PORT (Stereo Master mode)
OBICK Frequency
fBCK
64 FSO
OBICK Duty
dBCK
50
OBICK “↓” to OLRCK Edge
tMBLR
−20
20
OBICK “↓” to SDTO1-4
tBSD
−20
20
Output PORT (TDM256 master mode)
OBICK Frequency
fBCK
256 FSO
OBICK Duty
dBCK
50 (Note 19)
OBICK “↓” to OLRCK Edge
10
tMBLR
−10
OBICK “↓” to SDTO1
20
tBSD
−20
Reset Timing
tPD
150
PDN Pulse Width
(Note 18)
Note 17.
LRCK
BICK “↑”
Note 18. AK4128A PDN pin = “L”
Note 19. OMCLK=512FSO
OMCLK=256FSO
OMCLK
OBICK pin
OMCLK=384FSO
dBCK= (tCLKH)/(tCLKH+1/fCLK) x100 [%]
(tCLKL)/(tCLKL+1/fCLK) x100 [%]
OMCLK=768FSO
dBCK= (1/fCLK)/(3/fCLK) x100 [%]
ns
ns
ns
ns
ns
ns
Hz
%
ns
ns
Hz
%
ns
ns
ns
OMCLK=384FSO
1/fCLK
1/fCLK
tCLKH
tCLKL
tCLKL
tCLKH
tCLKL
1/fCLK
1/fCLK
OMCLK=768FSO
1/fCLK
1/fCLK
1/fCLK
1/fCLK
3/fCLK
3/fCLK
MS1242-J-01
2011/06
- 14 -
[AK4128A]
Parameter
Control Interface Timing (I2C Bus):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 20)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise
Suppressed by Input Filter
Capacitive load on bus
Note 20.
300ns (SCL
Symbol
min
fSCL
tBUF
tHD:STA
typ
max
Units
1.3
0.6
400
-
kHz
μs
μs
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
1.3
0.6
0.6
0
0.1
0.6
0
0.3
0.3
50
μs
μs
μs
μs
μs
μs
μs
μs
ns
Cb
-
400
pF
)
MS1242-J-01
2011/06
- 15 -
[AK4128A]
■
1/fECLK
VIH
IMCLK(I)
VIL
tECLKH
tECLKL
dECLK
= tECLKH (or tECLKL) x fECLK x 100
1/fCLK
VIH
OMCLK(I)
VIL
tCLKH
tCLKL
1/fMCK
MCKO(O)
50%DVDD
tMCKH
tMCKL
dMCLK
= tMCKH (or tMCKL) x fMCK x 100
Figure 5. IMCLK, OMCLK, MCKO Clock Timing
Stereo Mode and Slave Mode
1/FSI
VIH
LRCK1-4(I)
VIL
tLRCH
tLRCL
Duty
= tLRCH (or tLRCL) x FSI x 100
tBCK
VIH
IBICK1-4(I)
VIL
tBCKH
tBCKL
TDM256 Mode and Slave Mode
1/FSI
VIH
LRCK1(I)
VIL
tLRH
tLRL
tBCK
VIH
IBICK1(I)
VIL
tBCKH
tBCKL
Figure 6. ILRCK1-4, IBICK1-4 Clock Timing
MS1242-J-01
2011/06
- 16 -
[AK4128A]
Stereo Mode and Slave Mode
1/FSO
VIH
OLRCK(I)
VIL
tLRCH
tLRCL
Duty
= tLRCH (or tLRCL) x FSO x 100
tBCK
VIH
OBICK(I)
VIL
tBCKH
tBCKL
TDM256 Mode and Slave Mode
1/FSO
VIH
OLRCK(I)
VIL
tLRH
tLRL
tBCK
VIH
OBICK(I)
VIL
tBCKH
tBCKL
Figure 7. OLRCK, OBICK, Clock Timing (Slave Mode)
Stereo Mode and Master Mode
1/FSO
50%DVDD
OLRCK(O)
tLRCH
tLRCL
Duty
= tLRCH (or tLRCL) x FSO x 100
1/ fBCK
OBICK(O)
50%DVDD
tBICKH
tBICKL
dBCK
= tBICKH(or tBICKL) x fBCK x 100
TDM256 Mode and Master Mode
1/FSO
50%DVDD
OLRCK(O)
24bit MSB justified
tLRH
1/FSO
50%DVDD
OLRCK(O)
24bit I2 S
tLRL
1/ fBCK
OBICK(O)
50%DVDD
tBICKH
tBICKL
dBCK
= tBICKH(or tBICKL) x fBCK x 100
Figure 8. OLRCK, OBICK, Clock Timing (Master Mode)
MS1242-J-01
2011/06
- 17 -
[AK4128A]
VIH
ILRCK 1-4
VIL
tBLR
tLRB
VIH
IBICK1- 4
VIL
tSDS
tSDH
VIH
SDTI 1-4
VIL
Figure 9. Input PORT Audio Interface Timing (Stereo Slave mode and TDM256 Slave Mode)
VIH
OLRCK
VIL
tBLR
tLRB
VIH
OBICK
VIL
tBSD
tLRS
SDTO 1-4
50% D VDD
Figure 10. Output PORT Audio Interface Timing (TDM256 Slave mode & Stereo Slave mode)
MS1242-J-01
2011/06
- 18 -
[AK4128A]
OLRCK
50%DVDD
tMBLR
50%DVDD
OBICK
tBSD
50%DVDD
SDTO1-4
Figure 11. Output PORT Audio Interface Timing (TDM256 Master mode & Stereo Master mode)
tPD
PDN
VIL
Figure 12. Power Down Timing
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
tSU:STO
Start
Stop
Figure 13. I2C Bus
MS1242-J-01
2011/06
- 19 -
[AK4128A]
■
AK4128A
INAS pin
INAS pin “L”
INAS pin
FSI pin
Mode
L
H
Data
SDTI1
SDTI2
SDTI3
SDTI4
SDTI1
SDTI2
SDTI3
SDTI4
“H”
LRCK
BICK
ILRCK1
(Note 21)
IBICK1
(Note 22)
ILRCK1
ILRCK2
ILRCK3
ILRCK4
IBICK1
IBICK 2
IBICK 3
IBICK 4
Note 21. ILRCK2-4 VSS2-5
Note 22. IBICK2-4 VSS2-5
Table 1. Input Data Synchronous/Asynchronous Mode Setting
■
MSB
2’s complement
BICK1, IBICK2, IBICK3, IBICK4
SDTI1, SDTI2, SDTI3, SDTI4
(SPB pin= “L”)
SRC1~4
IDIF2-0 pin
PDN pin = “L”
(SPB pin= “H”)
IDIF2-0 pin
SRC2
IDIF[32:30] bit
SRC3
IDIF[42:40] bit
IDIF2-0 pin
IDIF[22:20] bit
IDIF[12:10] bit
SDTO2
SMUTE pin= “H”
SMUTE4 bit= “1”
IDIF[12:10] bit
SRC4
SRC1
SMUTE1 bit= “1”
IDIF[22:20] bit
SMUTE pin= “H”
SDTO1
SMUTE2 bit= “1”
SMUTE pin= “H”
IDIF[32:30] bit
SMUTE3 bit = “1”
SDTO3
IDIF[42:40] bit
SMUTE pin= “H”
SDTO4
Mode 5/6 TDM mode
TDM mode
(INAS pin = “L”)
SDTI2-4
(INAS pin = “H”)
AK4128A
IBICK1-4
8ch
VSS2-5
TDM mode
SDTI1
SDTI1-4
(INAS pin = “H”)
TDM mode
256FSI
MS1242-J-01
2011/06
- 20 -
[AK4128A]
Mode
0
1
2
3
4
5
6
IDIF2
Pin
(Note 23)
L
L
L
IDIF1
Pin
(Note 23)
L
L
H
IDIF0
Pin
(Note 23)
L
H
L
ILRCK
1-4
SDTI1-4 Format
IBICK
1-4
IBICK1-4
Freq
16bit, LSB justified
≥ 32FSI
20bit, LSB justified
≥ 40FSI
24bit, MSB justified
≥ 48FSI
24 or 16bit I2S Compatible
≥
48FSI
Input
Input
L
H
H
32FSI
16bit I2S Compatible
H
L
L
24bit, LSB justified
≥ 48FSI
H
L
H
TDM 24bit, MSB justified
256FSI
H
H
X
TDM 24bit, I2S Compatible
256FSI
Table 2. Input PORT Audio Interface Format (Parallel Control Mode, SPB pin= “L”) (X: Don’t care)
Note 23.
SRC1
(SPB pin= “H”)
IDIF2-0 pin
SRC2
IDIF[32:30] bit
IDIF[22:20] bit
SRC3
IDIF[12:10] bit
IDIF[42:40] bit
SRC4
ILRCK
0 1 2 3
9 10 11 12 13 14 15 0 1 2 3
9 10 11 12 13 14 15 0 1
IBICK(32fs)
SDTI(i)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
0 1 2 3
17 18 19 20
31 0 1 2 3
7 6 5 4 3 2 1 0 15
17 18 19 20
31 0 1
IBICK(64fs)
SDTI(i)
Don't Care
15 14 13 12
1 0
Don't Care
15 14 13 12
2 1 0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 14. Mode 0 Timing (16bit, LSB justified)
ILRCK
0 1 2
12 13
24
31 0 1 2
12 13
24
31 0 1
IBICK(64fs)
SDTI(i)
19
Don't Care
8
1 0
Don't Care
19
8
1 0
19:MSB, 0:LSB
Lch Data
Rch Data
Figure 15. Mode 1 Timing (20bit, LSB justified)
ILRCK
0 1 2
20 21 22 23 24
31 0 1 2
20 21 22 23 24
31 0 1
IBICK(64fs)
SDTI(i)
23 22
4 3 2 1 0
Don't Care 23 22
4 3 2 1 0
Don't Care 23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 16. Mode 2 Timing (24bit, MSB justified)
MS1242-J-01
2011/06
- 21 -
[AK4128A]
ILRCK
0 1 2 3
21 22 23 24 25
0 1 2
21 22 23 24 25
0 1
IBICK(64fs)
23 22
SDTI(i)
4 3 2 1 0 Don't Care 23 22
4 3 2 1 0
Don't Care
23:MSB, 0:LSB
Lch Data
Rch Data
2
Figure 17. Mode 3 Timing (24bit I S)
ILRCK
0 1 2
8 9
24
31 0 1 2
8 9
24
31 0 1
IBICK(64fs)
23
Don't Care
SDTI(i)
8
1 0
Don't Care
23
8
1 0
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 18. Mode 4 Timing (24bit, LSB justified)
Note : SDTI SDTI1, SDTI2, SDTI3, SDTI4
IBICK2, IBICK3, IBICK4
ILRCK ILRCK1, ILRCK2, ILRCK3, ILRCK4
IBICK IBICK1
256 IBICK
ILRCK1(I)
IBICK1 (I: 256FSI)
SDTI1(I)
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
L1
R1
L2
R2
L3
R3
L4
R4
32 IBICK
32 I BICK
32 I BICK
32 I BICK
32 IBICK
32 I BICK
32 I BICK
32 I BICK
Figure 19. Mode 5 Timing (TDM, 24bit, MSB justified, SDTI2-4: Don’t care)
256 IBICK
ILRCK1(I)
IBICK1(I: 256FSI)
SDTI1(I)
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
L1
R1
L2
R2
L3
R3
L4
R4
32 IBICK
32 I BICK
32 I BICK
32 I BICK
32 IBICK
32 I BICK
32 I BICK
32 I BICK
Figure 20. Mode 6 Timing (TDM, I2S, SDTI2-4: Don’t care)
MS1242-J-01
2011/06
- 22 -
[AK4128A]
■
/
SRC
CM2-0 pin
0
1
2
3
CM2
pin
L
L
L
L
CM1
pin
L
L
H
H
CM0
pin
L
H
L
H
4
H
L
5
6
7
H
H
H
L
H
H
Mode
Note 24.
Master
Master
Master
Master
256FSO
384FSO
512FSO
768FSO
L
Slave
Not used. (Note 24)
H
L
H
Master
Slave(Bypass)
Master(Bypass)
128FSO (Note 25)
Note 25.
Default
(SPB pin = “H”)
“0”(SRC mode)
0
1
2
3
CM2
pin
L
L
L
L
CM1
pin
L
L
H
H
CM0
pin
L
H
L
H
BYPS
bit
0
0
0
0
4
H
L
L
0
H
H
H
L
L
L
L
H
H
H
H
L
H
H
L
L
H
H
L
L
H
H
H
L
H
L
H
L
H
L
H
L
H
Mode
5
6
7
8
9
10
11
12
13
14
15
Note 26.
MCKO
FSO
MCKO
256FSO
384FSO
512FSO
768FSO
OMCLK
8k∼108kHz
8k∼96kHz
8k∼54kHz
8k∼48kHz
FSO
44.1~96kHz
29.4~64kHz
22.05~48kHz
14.7~32kHz
8k∼216kHz
-
128FSO
IMCLK
8k∼216kHz
88.2~192kHz
8k∼216kHz
-
Not used. (Note 24)
VSS2-5pin
Mode 4
OMCLK/XTI
VSS2-5
L
OMCLK/XTI pin
MCKO
Mode 6, 7
OMCLK/XTI
TDM Mode
Table 3. Output PORT Master/Slave/ Bypass Mode Control (SPB pin = “L”)
MCKO
BYPS bit
OMCLK/XTI
Master / Slave
BYPS bit
Master / Slave
SRC
OMCLK/XTI
Master
Master
Master
Master
256FSO
384FSO
512FSO
768FSO
Slave
Not used. (Note 26)
SRC mode
MCKO
256FSO
384FSO
512FSO
768FSO
FSO
8∼108kHz
8∼96kHz
8∼54kHz
8k~48kHz
FSO
44.1~96kHz
29.4~64kHz
22.05~48kHz
14.7~32kHz
8∼216kHz
-
0
Master
128FSO (Note 25) 128FSO
8∼216kHz 88.2~192kHz
0
Slave (Bypass)
0
Master (Bypass)
1
Master (Bypass)
1
Master (Bypass)
IMCLK
1
Master (Bypass)
Not used. (Note 26)
8∼216kHz
1
Master (Bypass)
1
Slave (Bypass)
1
Master (Bypass)
1
Slave (Bypass)
1
Master (Bypass)
VSS2-5 pin
Mode 4
OMCLK/XTI
VSS2-5
L
OMCLK/XTI pin
MCKO
Mode 6~15
OMCLK/XTI
Table 4. Output PORT Master/Slave/ Bypass Mode Control (SPB pin = “H”)
MS1242-J-01
2011/06
- 23 -
[AK4128A]
(1)
OLRCK pin
OMCLK/XTI pin
MCKO pin
a.
OBICK pin
OMCLK/XTI pin
IMCLK pin
X’tal
PDN pin= “L”
OMCLK/XTI pin
XTI
C
460kΩ (typ)
C
XTO
AK4128A
Table 5
Note:
Figure 21. X’tal Mode
11.2896
[MHz]
R1[Ω] max
C[pF] max
Table 5.
OMCLK
OMCLK
OMCLK
OMCLK
OMCLK
256FSO
384FSO
512FSO
768FSO
128FSO
X’tal
12.288
60
15
24.576
(R1)
X’tal
X’tal
X’tal
X’tal
X’tal
FSO
FSO
FSO
FSO
FSO
44.1kHz
29.4kHz
22.05kHz
14.7kHz
88.2kHz
(C)
96kHz
64kHz
48kHz
32kHz
192kHz
b.
- Note: DVDD1-4
XTI
External
Clock
460kΩ (typ)
XTO
AK4128A
Figure 22. External Clock (OMCLK) mode
(2)
OLRCK pin
OBICK pin
MS1242-J-01
2011/06
- 24 -
[AK4128A]
(3) SRC
SRC
“H”)
SRC
SDTO4
mode
(INAS pin = “L”)
SDTI1 SDTO1, SDTI2
SRC
ILRCK1 IBICK1
SDTI1-4
Table 2
SDTO1-4
OBICK pin
ILRCK1 OLRCK
DITHER
SMT1
SMT0
SMSEMI
SMUTE
VSS2-5
DVDD1-4
INAS
DEM1
DEM0
OLRCK pin
IDIF2
IDIF1
IDIF0
Table 6, Table 7
IBICK1 OBICK
(INAS pin =
SDTO2, SDTI3 SDTO3, SDTI4
(INAS pin = “H”)
SRC
OLRCK
OBICK
SRC1
Bypass
Input
Serial
Audio
I/F
IBICK1
ILRCK1
SDTI1
DEM
FIR
SRC
SMUTE
+
Dither
0.5 LSB
SRC
DEM
FIR
SRC
SMUTE
SRC
Dither
+
DEM
FIR
SRC
SMUTE
SRC
+
DEM
FIR
SRC
SRC4
SMUTE
SRC
Dither
IMCLK
PDN
PM1
PM2
Internal
OSC
uP
I/F
CAD0
Figure 23.
X’tal
Osc
SDA SCL XTO OMCLK/XTI
SPB
SDTO3
0.5 LSB
Bypass
Input
Serial
Audio
I/F
+
SDTO4
0.5 LSB
UNLOCK
Bypass
Clock
Div
CM2 CM1 CM0
SRC
SDTO2
SRC3
Dither
IBICK4
ILRCK4
SDTI4
ODIF1
ODIF0
Output
Serial
Audio
I/F
0.5 LSB
Bypass
Input
Serial
Audio
I/F
IBICK3
ILRCK3
SDTI3
OBIT1
OBIT2
SRC2
Bypass
Input
Serial
Audio
I/F
IBICK2
ILRCK2
SDTI2
SDTO1
MCKO
SRC
Internal
Regulator
REF
AVDD
VSS1
VD18
(Synchronous mode INAS pin = “L”)
MS1242-J-01
2011/06
- 25 -
[AK4128A]
SDTI1-4
Table 3
SDTO1-4
DITHER
SMT1
SMT0
SMSEMI
VSS2-5
DVDD1-4
INAS
DEM1
SMUTE
ILRCK1 IBICK1
OBICK pin
IBICK1
DEM0
IDIF2
IDIF1
IDIF0
SRC
ILRCK1 IBICK1
Table 6, Table 7
ILRCK1
OLRCK pin
OLRCK
OBICK
SRC1
Bypass
Input
Serial
Audio
I/F
IBICK1
ILRCK1
SDTI1
DEM
FIR
SRC
SMUTE
+
Dither
0.5 LSB
SRC
IBICK2
ILRCK2
SDTI2
DEM
FIR
SRC
SMUTE
SRC
Dither
+
DEM
FIR
SRC
SRC
+
DEM
FIR
SRC
SRC4
SMUTE
SRC
Dither
IMCLK
PDN
PM1
PM2
Internal
OSC
uP
I/F
CAD0
Figure 24.
X’tal
Osc
SDA SCL XTO OMCLK/XTI
SPB
SDTO3
0.5 LSB
Bypass
Input
Serial
Audio
I/F
+
SDTO4
0.5 LSB
UNLOCK
Bypass
Clock
Div
CM2 CM1 CM0
SRC
SDTO2
SRC3
SMUTE
Dither
IBICK4
ILRCK4
SDTI4
ODIF1
ODIF0
Output
Serial
Audio
I/F
0.5 LSB
Bypass
Input
Serial
Audio
I/F
IBICK3
ILRCK3
SDTI3
OBIT1
OBIT2
SRC2
Bypass
Input
Serial
Audio
I/F
SDTO1
MCKO
SRC
Internal
Regulator
REF
AVDD
VSS1
VD18
(Synchronous mode INAS pin = “L”)
MS1242-J-01
2011/06
- 26 -
[AK4128A]
■
ODIF1-0 pin OBIT1-0 pin
MSB
2’s
SDTO1-4 OBICK
PDN pin = “L”
IBICK1 OBICK
ILRCK1 OLRCK
SDTO1, SDTO2, SDTO3, SDTO4
OBIT1-0 pin TDM pin
TDM pin= “H”
TDM mode
SDTO1
8ch
SDTO2-4
Mode
0
1
2
3
4
5
6
7
Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TDM
pin
L
H
(* TDM mode
VSS2-5
TDM pin
L
L
L
L
H
H
H
H
ODIF1-0 pin
TDM mode
“L”
ODIF1 pin
ODIF0 pin
SDTO1-4 Format
L
L
LSB justified
L
H
Reserved
H
L
MSB justified
H
H
I2S Compatible
L
L
Reserved
L
H
Reserved
H
L
TDM256 mode 24bit MSB justified
H
H
TDM256 mode 24bit I2S Compatible
Table 6. Output PORT Audio Interface Format 1
Master / Slave
setting
OBIT1
pin
OBIT0
pin
SDTO
1-4
Slave
(CM2-0 =
“HLL” or
“HHL”)
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
16bit
18bit
20bit
24bit
16bit
18bit
20bit
24bit
*
*
*
*
Master
(CM2-0 =
“HLL”/“HHL”
)
Slave
(CM2-0 =
“HLL” or
“HHL”)
Master
(CM2-0 =
“HLL”/“HHL”
)
OBICK Frequency
LSB
MSB justified, I2S
justified
≥ 32FSO
≥ 36FSO
64FSO
≥ 40FSO
≥ 48FSO
OLRCK
OBICK
Input
Input
Output
Output
64FSO
TDM256
mode
24bit
Input
Input
256FSO
TDM256
mode
24bit
Output
Output
256FSO
Table 7. Output PORT Audio Interface Format 2
24bit
OBIT1/0 pin
1ch
)
MS1242-J-01
2011/06
- 27 -
[AK4128A]
OLRCK
0 1
8 9 10 11 12 13 14 15 16 17
20 21 22 23
29 30 31 0 1
8 9 10 11 12 13 14 15 16 17
20 21 22 23
29 30 31 0 1 2
OBICK(64fs)
15 14
11 10 9 8
2 1 0
15 14
11 10 9 8
2 1 0
17 16 15 14
11 10 9 8
2 1 0
17 16 15 14
11 10 9 8
2 1 0
19 18 17 16 15 14
11 10 9 8
2 1 0
19 18 17 16 15 14
11 10 9 8
2 1 0
11 10 9 8
2 1 0
23 22 21 20 19 18 17 16 15 14
11 10 9 8
2 1 0
SDTO(O)
15:MSB, 0:LSB
SDTO(O)
17:MSB, 0:LSB
SDTO(O)
19:MSB, 0:LSB
SDTO(O)
23 22 21 20 19 18 17 16 15 14
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 25. Stereo Mode LSB justified Timing
OLRCK
0 1 2 3 4
13 14 15 16 17 18 19 20 21 22 23 24
31 0 1 2 3 4
13 14 15 16 17 18 19 20 21 22 23 24
31 0 1 2
OBICK(64fs)
SDTO(O)
15 14 13 12
2 1 0
15 14 13 12
2 1 0
15 14
17 16 15 14
4 3 2 1 0
17 16
19 18 17 16
6 5 4 3 2 1 0
19 18
23 22 21 20
10 9 8 7 6 5 4 3 2 1 0
23 22
15:MSB, 0:LSB
SDTO(O)
17 16 15 14
4 3 2 1 0
17:MSB, 0:LSB
SDTO(O)
19 18 17 16
6 5 4 3 2 1 0
19:MSB, 0:LSB
SDTO(O)
23 22 21 20
10 9 8 7 6 5 4 3 2 1 0
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 26. Stereo Mode MSB justified Timing
OLRCK
0 1 2 3 4
14 15 16 17 18 19 20 21 22 23 24
0 1 2 3 4
14 15 16 17 18 19 20 21 22 23 24
31 0 1 2
OBICK(64fs)
SDTO(O)
15 14 13 12
2 1 0
15 14 13 12
2 1 0
15
17 16 15 14
4 3 2 1 0
17
19 18 17 16
6 5 4 3 2 1 0
19
23 22 21 20
10 9 8 7 6 5 4 3 2 1 0
23
15:MSB, 0:LSB
SDTO(O)
17 16 15 14
4 3 2 1 0
17:MSB, 0:LSB
SDTO(O)
19 18 17 16
6 5 4 3 2 1 0
19:MSB, 0:LSB
SDTO(O)
23 22 21 20
10 9 8 7 6 5 4 3 2 1 0
23:MSB, 0:LSB
Lch Data
Rch Data
2
Figure 27. Stereo Mode I S Compatible Timing
Note : SDTO SDTO1, SDTO2, SDTO3, SDTO4
MS1242-J-01
2011/06
- 28 -
[AK4128A]
256 OBICK
1/ 8FSO
OLRCK(O)
OBICK(O) (256FSO)
SDTO 1 (O)
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
L1
R1
L2
R2
L3
R3
L4
R4
32OBICK
32OBICK
32OBICK
32OBICK
32OBICK
32OBICK
32OBICK
32OBICK
Figure 28. TDM 256 mode 24bit MSB justified Timing at Master Mode. (SDTO2-4: “L” outputs)
256 OBICK
min. 1/ 256FSO
OLRCK(I)
OBICK(I) (256FSO)
SDTO 1 (O)
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
L1
R1
L2
R2
L3
R3
L4
R4
32 OBICK
32 OBICK
32 OBICK
32 OBICK
32 OBICK
32 OBICK
32 OBICK
32 OBICK
Figure 29. TDM 256 mode 24bit MSB justified Timing at Slave Mode. (SDTO2-4: “L” outputs)
256 OBICK
1/8FSO
OLRCK(O)
OBICK (O: 256FSO)
SDTO 1 (O)
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
L1
R1
L2
R2
L3
R3
L4
R4
32 OBICK
32 OBICK
32 OBICK
32 OBICK
32 OBICK
32 OBICK
32 OBICK
32 OBICK
23
Figure 30. TDM 256 mode 24bit I2S Compatible Timing at Master Mode (SDTO2-4: “L” outputs)
256 OBICK
min. 1/ 256FSO
OLRCK(I)
OBICK ( I: 256FSO)
SDTO 1 (O)
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
L1
R1
L2
R2
L3
R3
L4
R4
32 OBICK
32 OBICK
32 OBICK
32 OBICK
32 OBICK
32 OBICK
32 OBICK
32 OBICK
Figure 31. TDM 256 mode 24bit I2S Compatible Timing at Slave Mode (SDTO2-4: “L” outputs)
MS1242-J-01
2011/06
- 29 -
[AK4128A]
■ 6/4
AK4128A
8ch
6ch
4ch
6
4
PM2/1 pin “L/L”
8ch
6ch (SDTI1Æ SDTO1, SDTI2 Æ SDTO2 and SDTI3 Æ SDTO3)
2ch (SDTI4 Æ SDTO4)
(“L”
)
PM2/1 pin “L/H”
8ch
4ch (SDTI1Æ SDTO1 and SDTI2 Æ SDTO2)
4ch (SDTI3 Æ SDTO3 and SDTI4 Æ
SDTO4)
(“L”
)
6
4
MCKO
XTO pin MCKO pin
Hi-z
PM2
pin
L
L
L
L
H
H
H
H
PM1
pin
L
L
H
H
L
L
H
H
PDN
pin
L
H
L
H
L
H
L
H
Mode
6-channel
mode
4-channel
mode
8-channel
mode
Not
available
X’tal Oscillator
XTI pin
XTO pin
MCKO pin
Pull down to VSS2-5 (note)
Hi-z
Input
Hi-z
Pull down to VSS2-5 (note)
Power-down
Hi-z
Input
Power-down
Pull down to VSS2-5 (note)
Hi-z
L
Normal operation
Input
Output
Normal operation
Note: Pull down (460kΩ typ.) to VSS2-5.
Table 8. Channel Mode Setting
Power-down
■
1. Manual Mode
SRC
(SPB pin = “L”)
SRC1-4
SMUTE pin
(SPB pin= “H”)
SMUTE pin
SMUTE1 bit
SRC1
SMUTE2 bit
SRC2
SMUTE3 bit
SRC3
SMUTE4 bit
SRC4
SMUTE pin “H”
SMUTE1-4 bit ”1”
1024OLRCK
(@ SMT1 pin = “L” and SMT0
pin = “L”)
−∞ (“0”)
SMUTE pin “L”
SMUTE1-4 bit
”0”
−∞
−∞
1024OLRCK
(@ SMT1 pin = “L” and SMT0 pin = “L”) 0dB
0dB
SMT1-0 pin
SMT1pin
L
L
H
H
SMT1-0 pin
SMT0 pin
Period
FSO=48kHz FSO=96kHz
L
1024/FSO
21.3ms
10.7ms
H
2048/FSO
42.7ms
21.3ms
L
4096/FSO
85.3ms
42.7ms
H
8192/FSO
170.7ms
85.3ms
Table 9. Soft Mute Cycle Setting (Parallel Mode)
MS1242-J-01
FSO=192kHz
5.3ms
10.7ms
21.3ms
42.7ms
2011/06
- 30 -
[AK4128A]
SM U T E p in ,
SM U T E1 -4 b it
(1 )
0dB
(1 )
(2 )
Atte nu a tio n
-∞
All “0” code
SD T O
Note : SDTO
(1)
SDTO1, SDTO2, SDTO3, SDTO4
SMT1-0 pin
(Table 9)
−∞ (“0”)
(2)
0dB
Figure 32. Soft Mute Function (Manual Mode)
2. Semi-Auto
(PDN pin = “L” → “H”)
PDN pin = “L” → “H”
SMSEMI pin= “H”
4410/FSO=100ms@FSO=44.1kHz
SMUTE pin “H”
“L”
SMSEMI pin
PDN p in
PDN pin =
“L ”
Do n’t ca re
S MU TE pin
“L”
(1 )
0dB
Atte nu a tio n
(2 )
4 41 0 /fso
-∞
A ll “0” code
SDT O
Note : SDTO
(1)
(2) 4410/FSO
SDTO1, SDTO2, SDTO3, SDTO4
(Table 9)
0dB
0dB
Table 9
Figure 33. Soft Mute Function (Semi-Auto Mode)
MS1242-J-01
2011/06
- 31 -
[AK4128A]
■
AK4128A
pin “H”
SRC
SRC mode SRC
OBIT1-0 pin
DITHER
1bit
24-bit
DITHER pin= “H”
DITHER pin=“L”
■
IIR
DEM[11:10] bit
bit
SRC4
3
(32kHz, 44.1kHz, 48kHz)
(SPB pin= L”)
SRC1~4
(SPB pin = “H”)
DEM1/0 pin
SRC1
DEM[21:20] bit
SRC2 DEM[31:30] bit
(tc = 50/15μs)
DEM1/0 pin
SRC3
DEM[41:40]
DEM11pin
DEM10 pin Mode(SDTI1-4)
L
L
44.1kHz
L
H
OFF
H
L
48kHz
H
H
32kHz
Table 10. De-emphasis Filter Setting (Parallel Control Mode (SPB pin= “L”))
DEM11bit
DEM10 bit
Mode(SDTI1)
L
L
44.1kHz
L
H
OFF
H
L
48kHz
H
H
32kHz
Table 11. De-emphasis Filter Setting for SDTI1 (Serial Control Mode (SPB pin = “H”))
DEM21 bit
DEM20 bit
Mode(SDTI2)
L
L
44.1kHz
L
H
OFF
H
L
48kHz
H
H
32kHz
Table 12. De-emphasis Filter Setting for SDTI2 (Serial Control Mode (SPB pin= “H”))
DEM31 bit
DEM30 bit
Mode(SDTI3)
L
L
44.1kHz
L
H
OFF
H
L
48kHz
H
H
32kHz
Table 13. De-emphasis Filter Setting for SDTI3 (Serial Control Mode (SPB pin = “H”))
DEM41 bit
DEM40 bit
Mode(SDTI4)
L
L
44.1kHz
L
H
OFF
H
L
48kHz
H
H
32kHz
Table 14. De-emphasis Filter Setting for SDTI4 (Serial Control Mode (SPB pin = “H”))
MS1242-J-01
2011/06
- 32 -
[AK4128A]
■
AK4128A
DVDD1-4
1.8V
1.8V
PDN pin
PDN pin= “H”
PDN pin= “L”
SRC
“UNLOCK”
“L”
“H”
■
AK4128A PDN pin “L”
PDN pin = “L”
SDTO1-4
SRC
SDTO1-4
“L”
PDN pin
“L”
23ms (max)
ILRCK1-4
SDTI SDTI1, SDTI2, SDTI3, SDTI4
“L”
Case 1:
External clocks
(Input port)
Don’t care
Input Clocks 1
Input Clocks 2
Don’t care
SDTI
Don’t care
Input Data 1
Input Data 2
Don’t care
External clocks
(Output port)
Don’t care
Output Clocks 1
Output Clocks 2
Don’t care
PDN
23ms(max)
(Internal state) Power-down
SDTO4
“0” data
SDTO3
“0” data
SDTO2
“0” data
SDTO1
“0” data
(1)
23ms(max)
Normal
operation
PD
Normal data
(1)
Normal
operation
Power-down
“0” data
Normal data
“0” data
“0” data
Normal data
“0” data
Normal data
“0” data
Normal data
“0” data
Normal data
“0” data
Normal data
Normal data
“0” data
UNLOCK
Figure 34. System Reset 1
MS1242-J-01
2011/06
- 33 -
[AK4128A]
Case 2:
External clocks
(Input port)
(No Clock)
SDTI
External clocks
(Output port)
Input Clocks
Don’t care
(Don’t care)
Input Data
Don’t care
(Don’t care)
Output Clocks
Don’t care
PDN
21ms(max)
Normal
operation
Power-down
Normal data
“0” data
(2)
(Internal state) Power-down
SDTO4
“0” data
SDTO3
“0” data
Normal data
“0” data
SDTO2
“0” data
Normal data
“0” data
SDTO1
“0” data
Normal data
“0” data
UNLOCK
Figure 35. System Reset 2
Note 27. SPB, CM2-0, INAS, PM2-1, OBIT1-0, TDM, ODIF1-0, IDIF2-0, CAD0 pin
Note 28. PDN pin= “L”
“L”
Note 29. (1)
Note 30. (2)
UNLCOK pin “H”
PDN pin “↑”
FSO/FSI
SRC
SDTO1-4 pin
SRC1-4
FSO/FSI
SRC1-4
FSO/FSI
(
(FSO/FSI
+
+ FSO/FSI
+
MS1242-J-01
+
Group Delay)
+
PDN pin= “L”
SRC
UNLOCK pin
UNLOCK pin “H”
Group Delay)
2011/06
- 34 -
[AK4128A]
■
AK4128A
Figure 36, Figure 37
(Figure 36)
(Figure 36) SDTO SDTO1-4
PDN pin
PDN pin
RSTN bit
External clocks
(Input port
or Output port)
Clocks 1
Clocks 2
Don’t care
PDN pin
max 23ms
(Internal state) Normal operation Power-down
SDTO
Att.Level
Normal data
1024/FSO
1024/FSO
0dB
- ∞dB
Note 31.
SDTI “0”
Note 32. Note 31
Note 33. (3)
(
Normal operation
Note 31
Normal data
SMUTE (Note32,
recommended)
(3)
PDN pin “L”
“0”
GD
SMUTE
+ FSO/FSI
+
Group Delay)
Figure 36. Sequence of changing clocks (Parallel Control Mode SPB pin =“L”)
External clocks
(Input port or Output port)
Clocks 1
Don’t care
Clocks 2
RSTN bit
(Internal state)
Normal operation
SDTO
Normal data
(4)
Normal operation
Note 34
Normal data
1024/F SO
1024/FSO
Att.Level
0dB
-∞dB
Note 34.
RSTN bit “L”
GD
SDTI “0”
“0”
Note 35. Note 34
Note 36.
Note 37. (4)
SMUTE
0.5/FSI+8/FSI(O)+156/FSO
1.5/FSI+8/FSI(O)+156/FSO
(FSI(O) FSI FSO
)
Figure 37. Sequence of changing clocks (Serial Control Mode SPB pin= “H”)
MS1242-J-01
2011/06
- 35 -
[AK4128A]
1. PDN pin
RSTN bit
ILRCKx (x=1,2,3,4)
FSO/FSI
ILRCKx
(min. 59.4 MHz, typ. 73.5 MHz)
|
|
ILRCKx
ILRCKx
FSI
FSO/FSI
SDTOx
FSO
L
)
|
0.5/FSI+8/FSI(O)+156/FSO
SRC
|
|
1.5/FSI+8/FSI(O)+156/FSO (FSI(O)
|
SRC
ILRCKx
5148/FSO (Note 38) (max.
643.5ms @FSO=8kHz)
ILRCKx
+156/FSO
2. PDN pin
SRC
1.5/FSI+8/FSI(O)+156/FSO (FSI(O)
RSTN bit
FSI
FSO
)
OLRCK
FSO/FSI
OLRCK
|
|
OLRCK
OLRCK 8
FSO/FSI
SDTOx
0.5/FSI+8/FSI(O)+156/FSO
1.5/FSI+8/FSI(O)+156/FSO (FSI(O) FSI FSO
SRC
|
|
|
|
SRC
@FSO=8kHz)
OLRCK
+156/FSO
Note 38. FSO=8kHz
FSO=32kHz
0.5/FSI+8/FSI(O)
SRC
“L”
)
OLRCK
5148/FSO (Note 38) (max. 643.5ms
SRC
1.5/FSI+8/FSI(O)+156/FSO (FSI(O)
FSO/FSI 1/6
FSO/FSI 1/6
1/5.99
1/5.99
FSI
FSO
)
0.5/FSI+8/FSI(O)
SRC
160.9ms
MS1242-J-01
2011/06
- 36 -
[AK4128A]
■
19 pin “UNLOCK”
pin “↑”
SDTO1-4 pin
SRC
FSO/FSI
UNLOCK pin
6
SRC1-3
4
SRC1-2
1
PDN pin= “L”
UNLOCK pin “H”
FSO/FSI
SRC
UNLOCK pin SRC1-4
SRC1-4
FSO/FSI
“L”
PDN
“H”
UNLOCK pin SRC1-3
1
FSO/FSI
SRC1-2
FSO/FSI
FSO/FSI
“L”
“H”
FSO/FSI
“L”
“H”
UNLOCK pin
“H”
SRC
FSO/FSI
NAND
“OR”
UNLOCK pin
FSO/ FSI
Figure 38. Internal Flag and UNLOCK pin Output
PDN pin = “L”
PDN pin “↑”
RSTN bit= “0”
CM2-0 pin
SRC
1.4ms(max)
BYPS bit “1”
MS1242-J-01
UNLOCK pin “L”
UNLOCK pin
“L”
2011/06
- 37 -
[AK4128A]
■
AK4128A I2C
(max:400kHz)
SCL, SDA pin
DVDD1-4 + 0.3V
1.
IC
·
1
·
IC
IC
READ
IC
WRITE
·
1-1.
“H”
SDA
“H”
·
·
“L”
SCL
“L”
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 39. Data transfer
1-2.
SCL
“H”
SDA
“H”
·
“L”
·
SCL
·
“H”
SDA
“L”
“H”
·
SCL
SDA
START CONDITION
STOP CONDITION
Figure 40. START and STOP conditions
MS1242-J-01
2011/06
- 38 -
[AK4128A]
1-3.
IC
1
SDA
IC
SDA
(HIGH
AK4128A
WRITE
AK4128A
READ
SDA
)
“L”
·
·
SDA
AK4128A
·
AK4128A
Clock pulse
for acknowledge
SCL FROM
MASTER
1
8
9
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
START
CONDITION
acknowledge
Figure 41. Acknowledge on the I2C-bus
1-4. FIRST BYTE
1
IC
“001001”
1
R/W bit= “0”
·
IC
(CAD0)
7
8
WRITE
0
·
CAD0 pin = “H”
(
0
1
”1”
IC
)
R/W bit
0
0
7
CAD0 pin = “L”
R/W bit= “1”
1
CAD0
6
”0”
·
READ
R/W
Figure 42. The First Byte
MS1242-J-01
2011/06
- 39 -
[AK4128A]
2. WRITE
R/W bit
“0”
AK4128A WRITE
WRITE
2
2
MSB first
6
0
“0”
0
0
0
0
0
A1
A0
(*: Don’t care)
Figure 43. The Second Byte
2
3
MSB first
8
D7
D6
D5
3
D4
D3
D2
D1
D0
Figure 44. Byte structure after the second byte
AK4128A
3
·
03H
·
00H
S
T
A
R
T
SDA
Slave
Address
Register
Address(n)
S
T
Data(n+x) O
P
Data(n+1)
Data(n)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
Figure 45. WRITE Operation
MS1242-J-01
2011/06
- 40 -
[AK4128A]
3. READ
R/W bit
“1”
AK4128A
READ
·
03H
AK4128A
00H
·
·
·
READ
3-1.
AK4128A
·
AK4128A
·
·
READ
·
·
·
(READ
WRITE
n+1
(R/W bit = “1”)
·
)
n
·
·
·
1
1
READ
·
S
T
A
R
T
SDA
Slave
Address
Data(n)
Data(n+1)
S
Data(n+x) T
O
P
Data(n+2)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
Figure 46. CURRENT ADDRESS READ
3-2.
·
·
·
(R/W bit = “1”)
·
WRITE
WRITE
READ
·
·
(R/W bit = “0”)
AK4128A
·
READ
·
(R/W bit = “1”)
AK4128A
·
1
·
READ
S
T
A
R
T
SDA
S
T
A
R
T
Word
Address(n)
Slave
Address
S
Slave
Address
Data(n)
S
Data(n+x) T
O
P
Data(n+1)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 47. RANDOM READ
MS1242-J-01
2011/06
- 41 -
[AK4128A]
■
Addr
Register Name
D7
D6
D5
D4
D3
D2
00H
Reset & Mute
SMUTE4 SMUTE3 SMUTE2 SMUTE1
0
BYPS
01H
De-emphasis
DEM41 DEM40 DEM31 DEM30 DEM21 DEM20
02H Input Audio Data Format 1
0
IDIF22 IDIF21 IDIF20
0
IDIF12
03H Input Audio Data Format 2
0
IDIF42 IDIF41 IDIF40
0
IDIF32
Note 39. PDN pin “L”
Note 40.
00H~03H
“0”
BYPS, IDIF12-10, 22-20, 32-30, 42-40 bit
RSTN bit = “0”
Note 41. PDN pin“↑”
1.4ms (max)
D1
0
DEM11
IDIF11
IDIF31
D0
RSTN
DEM10
IDIF10
IDIF30
”1”
I2C
■
Addr
00H
Register Name
Reset & Mute
R/W
Default
D7
SMUTE4
R/W
0
D6
SMUTE3
R/W
0
D5
SMUTE2
R/W
0
D4
SMUTE1
R/W
0
RSTN: Digital Reset control
0:
1:
(default)
“0”
D3
0
RD
0
SRC1-4
D2
BYPS
R/W
0
D1
0
RD
0
D0
RSTN
R/W
1
I2C
BYPS: Bypass Mode Control
0 : SRC Mode(default)
1 : SRC
Table 3
SMUTE1: SRC1 Soft Mute Control
0:
(default)
1:
(SPB pin= “H”)
SMUTE pin
SMUTE1 bit
SRC1
SMUTE2: SRC2 Soft Mute Control
0:
(default)
1:
(SPB pin= “H”)
SMUTE pin
SMUTE2
(SPB pin= “H”)
SMUTE pin
SMUTE3
bit
SRC2
SMUTE3: SRC3 Soft Mute Control
0:
(default)
1:
bit
SRC3
MS1242-J-01
2011/06
- 42 -
[AK4128A]
SMUTE4: SRC4 Soft Mute Control
0:
(default)
1:
(SPB pin= “H”)
bit
Addr
01H
SMUTE pin
SMUTE4
SRC4
Register Name
De-emphasis
R/W
Default
D7
DEM41
R/W
0
D6
DEM40
R/W
1
D5
DEM31
R/W
0
D4
DEM30
R/W
1
D3
DEM21
R/W
0
D2
DEM20
R/W
1
D1
DEM11
R/W
0
D0
DEM10
R/W
1
DEM11/10: SRC1 De-emphasis Control
Default: “01” De-emphasis=OFF
DEM21/20: SRC2 De-emphasis Control
Default: “01” De-emphasis=OFF
DEM31/30: SRC3 De-emphasis Control
Default: “01” De-emphasis=OFF
DEM41/40: SRC4 De-emphasis Control
Default: “01” De-emphasis=OFF
bit
SRC1
DEM41, DEM40 bit
Addr
Register Name
02H
Input Audio Data Format 1
R/W
Default
Addr
Register Name
03H
Input Audio Data Format 2
R/W
Default
IDIF12/11/10: SRC1
Default : “000”
IDIF22/21/20: SRC2
Default : “000”
IDIF32/31/30: SRC3
Default : “000”
IDIF42/41/40: SRC4
Default : “000”
IDIF10 bit
SRC3
(SPB pin=”H”)
DEM21, DEM20 bit
SRC4
DEM1-0 pin
SRC2
DEM31, DEM30 bit
D7
D6
D5
D4
DEM11, DEM10
SRC3
D3
D2
D1
D0
0
IDIF22
IDIF21
IDIF20
0
IDIF12
IDIF11
IDIF10
RD
0
R/W
0
R/W
0
R/W
0
RD
0
R/W
0
R/W
0
R/W
0
D7
D6
D5
D4
D3
D2
D1
D0
0
IDIF42
IDIF41
IDIF40
0
IDIF32
IDIF31
IDIF30
RD
0
R/W
0
R/W
0
R/W
0
RD
0
R/W
0
R/W
0
R/W
0
Mode 0 (Table 2
)
Mode 0 (Table 2
)
Mode 0 (Table 2
)
Mode 0 (Table 2
)
(SPB pin = “H”)
IDIF2-0 pin
SRC1
IDIF22, IDIF21, IDIF20 bit
IDIF42, IDIF41, IDIF40 bit
SRC4
MS1242-J-01
SRC2
IDIF12, IDIF11,
IDIF32, IDIF31, IDIF30 bit
2011/06
- 43 -
[AK4128A]
Figure 48, Figure 49
(AKD4128)
•
(SPB pin = “L”).
•
(INAS pin = “L”).
• OMCLK/XTI
X’tal
• Input PORT: Slave mode, IBICK1 lock mode (64FSI), 24 bit MSB justified
• Output PORT: Slave mode, 24 bit MSB justified
• Dither = OFF, DEM=OFF, PM2/1 pin= “H/L” (8ch mode)
C1= 0.1μF
C2=10μF
C3=1μF± 30%
3.3V
+
C2
C1
C
C
+
C2
C3
FSI
64FSI
53
52
51
50
49
MCKO
54
TST0
55
CAD0
56
DVDD4
VD18
AVDD
57
TST1
VSS1
58
VSS5
TST3
59
TST2
60
SMSEMI
+
61
SCL
62
SPB
63
SDA
64
ILRCK2
C1
1 IBICK2
XTO 48
2 IMCLK
XTI/OMCLK 47
FSO
3 ILRCK1
OLRCK 46
4 IBICK1
OBICK 45
5 DVDD1
DVDD3 44
64FSO
C1
DSP1
C1
6 VSS2
VSS4 43
7 SDTI4
SDTO4 42
8 SDTI1
SDTO1 41
Top View
9 SDTI2
DSP2
SDTO2 40
SMT1
DEM0
DEM1
PM1
OBIT0
OBIT1
PM2
TDM 33
SMT0
16 ILRCK4
PDN
CM2 34
DITHER
CM1 35
15 IBICK3
SMUTE
CM0 36
14 ILRCK3
VSS3
13 IDIF2
DVDD2
ODIF1 37
UNLOCK
ODIF0 38
12 IDIF1
INAS
SDTO3 39
11 IDIF0
IBICK4
10 SDTI3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C1
+
C2
uP
Notes:
- VSS1 -5
- DVDD1-4
- VD18 pin
- X’tal
DVSS
1μF± 30%(
)
VD18 pin
R1
C
Table 5
Figure 48. Typical Connection Diagram (Parallel Control Mode)
MS1242-J-01
2011/06
- 44 -
[AK4128A]
•
(SPB pin = “H”).
•
(INAS pin = “H”).
256FSO, X’tal
• OMCLK/XTI
• Input PORT: Slave mode, IBICK1~4 lock mode (64FSI)
• Output PORT: Master mode, 24 bit MSB justified.
• Dither = OFF,
PM2/1 pin= “H/L” (8ch mode)
C1= 0.1μF
C2=10μF
C3=1μF± 30%
3.3V
+
C2
C1
C
+
C
C2
C3
56
55
TST3
VD18
AVDD
SPB
SDA
SCL
TST2
SMSEMI
54
53
52
51
50
49
TST0
57
MCKO
58
CAD0
59
DVDD4
60
TST1
61
1 IBICK2
XTO 48
2 IMCLK
XTI/OMCLK 47
FSO
FSI
DSP1
62
VSS1
ILRCK2
DSP2
63
VSS5
C1
+
64
3 ILRCK1
64FSI
OLRCK 46
4 IBICK1
OBICK 45
5 DVDD1
DVDD3 44
64FSO
C1
C1
6 VSS2
VSS4 43
DSP5
7 SDTI4
SDTO4 42
8 SDTI1
SDTO1 41
Top View
9 SDTI2
SDTO2 40
10 SDTI3
SDTO3 39
11 IDIF0
ODIF0 38
12 IDIF1
ODIF1 37
13 IDIF2
CM0 36
14 ILRCK3
CM1 35
DSP3
15 IBICK3
CM2 34
16 ILRCK4
TDM 33
IBICK4
INAS
UNLOCK
DVDD2
VSS3
SMUTE
DITHER
PDN
SMT0
SMT1
DEM0
DEM1
PM1
OBIT0
OBIT1
PM2
DSP4
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C1
+
C2
uP
Notes:
- VSS1-5
- DVDD1-4
- VD18 pin
- X’tal
DVSS
R1
1μF± 30%(
VD18 pin
C
)
Table 5
Figure 49. Typical Connection Diagram (Serial Control Mode)
MS1242-J-01
2011/06
- 45 -
[AK4128A]
1.
AVDD, DVDD1-4
VSS1-5
2
AK4128A ILRCK1-4
IBICK
Figure 50
Figure 50
0.02[UIpp]
(2)
(1)
Figure 50. Jitter Tolerance
(1)
(2)
Note
Y
THD+N
1[UIpp]
ILRCK
ILRCK
FSI=48kHz
MS1242-J-01
1[UIpp]=1/48kHz=20.8 s
2011/06
- 46 -
[AK4128A]
3.
Table 15
AK4128A
Ratio
FSO/FSI [kHz]
4.000
1.000
0.919
0.725
0.667
0.544
0.500
0.500
0.459
0.363
0.333
0.250
0.250
0.230
0.167
0.181
0.167
0.181
192/48.0
48.0/48.0
44.1/48.0
32.0/44.1
32.0/48.0
48.0/88.2
48.0/96.0
44.1/88.2
44.1/96.0
32.0/88.2
32.0/96.0
48.0/192.0
44.1/176.4
44.1/192.0
32.0/192.0
32.0/176.4
8/48.0
8/44.1
Stopband
Attenuation [dB]
22.000
26.000
−121.2
22.000
26.000
−121.2
20.000
24.100
−121.4
14.088
17.487
−115.3
13.688
17.488
−116.9
19.250
26.232
−114.6
20.900
27.000
−100.2
19.202
24.806
−100.2
18.700
25.000
−103.3
12.863
18.665
−102.0
12.500
18.900
−103.6
17.600
30.200
−104.0
16.170
27.746
−104.0
15.860
28.240
−103.3
11.200
19.600
−73.2
10.278
17.987
−73.2
2.800
4.900
−73.2
2.5695
4.4968
−73.2
Table 15. Digital Filter Example
Passband [kHz]
Stopband [kHz]
Gain [dB]
−0.01@ 20k
−0.01@ 20k
−0.01@ 20k
−0.01@ 14.5k
−0.19@ 14.5k
−0.03@ 20k
−0.01@ 20k
−0.08@ 20k
−0.23@ 20k
−0.75@ 14.5k
−1.07@ 14.5k
−0.18@ 20k
−1.34@ 20k
−1.40@ 20k
−2.97@ 14.5k
−7.88@ 14.5k
−2.97@ 3.625k
−7.88@ 3.625k
4. I2C
SCL pin, SDA pin
DVDD1-4
I2C
DVDD1-4
DVDD1-4
+3.3V
DVDD1-4
AK4128A
SDA pin
VSS2-5
Figure 51. SDA pin output
MS1242-J-01
2011/06
- 47 -
[AK4128A]
64pin LQFP(Unit: mm)
12.0
Max 1.85
10.0
1.40
0.00~0.25
33
32
48
12.0
49
64
17
16
1
0.5
0.2±0.1
0.09~0.25
0.10 M
0°~10°
0.50±0.25
0.10
■
MS1242-J-01
2011/06
- 48 -
[AK4128A]
(AK4128AEQ)
AKM
AK4128AEQ
XXXXXXX
1
XXXXXXX: Date code identifier
(AK4128AVQ)
AKM
AK4128AVQ
XXXXXXX
1
XXXXXXX: Date code identifier
MS1242-J-01
2011/06
- 49 -
[AK4128A]
Date (YY/MM/DD)
10/09/13
11/06/02
Revision
00
01
Reason
Page
Contents
4
■ AK4126
(2)
: No. 63-pin
z
z
z
z
z
z
MS1242-J-01
2011/06
- 50 -