AKM AKD4128A-A

[AKD4128A-A]
AKD4128A-A
AK4128A-A Evaluation Board Rev.0
GENERAL DESCRIPTION
The AKD4128A-A is an evaluation board for AK4128A, the digital sample rate converter. The
AKD4128A-A has the digital audio interface and can achieve the interface with digital audio system via
optical or coaxial connector.
„ Ordering guide
AKD4128A-A
---
AK4128A Evaluation Board
FUNCTION
• DIR/DIT with optical or coaxial input/output
• 10pin Header for AKM AD/DA evaluation board
D3.3V-1
O pt In
AVDD
DVDD
＋5V
GND
D3.3V-2
AK4114
(DIR)
Regu lator
COAX
Regu lator
10pi n
Header
O pt In
Regu lator
AK4114
(DIR)
AK4114
(DIT)
AK4128A
COAX
10pi n
Header
O pt In
O pt Out
10pi n
Header
CO AX
AK4114
(DIR)
COAX
10pi n
Header
O pt In
COAX
10pi n
Header
AK4114
(DIR)
10pi n
Header
(I 2C)
Figure 1. AKD4128A-A Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
[KM104301]
2010/09
-1-
[AKD4128A-A]
„ Operation sequence
1) Set up the power supply lines.
Name of
jack
+5V
Color
of jack
Orange
Typ
Voltage
+5V
Used for
Open / Connect
Regulator T1,T2,T3:
AVDD and DVDD of
AK4128A, AK4114, Digital
Logic
AVDD
Red
+3.3V
AVDD of AK4128A
DVDD
Red
+3.3V
DVDD of AK4128A
D3.3V-1
Red
+3.3V
AK4114, Digital Logic
D3.3V-2
Red
+3.3V
AK4114, Digital Logic
GND
Black
0V
Ground
Should be always connected
When default setting.
Should be always connected
when AVDD of AK4128A is not
supplied from regulator T1.
In this case “JP1” is set to “AVDD”
side.
Should be always connected
when DVDD of AK4128A is not
supplied from regulator T1.
In this case “JP2” is set to
“DVDD” side.
Should be always connected
when AK4114 and Digital Logic is
not supplied from regulator T2.
In this case “JP3” is set to
“D3.3V-1” side.
Should be always connected
when AK4114 and Digital Logic is
not supplied from regulator T3.
In this case “JP4” is set to
“D3.3V-2” side.
Should be always connected
Default
Setting
+5V
Open
Open
Open
Open
GND
Table 1. Set up the power supply lines
Each supply line should be distributed from the power supply unit.
[KM104301]
2010/09
-2-
[AKD4128A-A]
2)
Set up the jumper pin of power supply unit.
(1).Setup the AVDD of AK4128A.
a).When using AVDD jack.
J P1
3
AVDD
b).When using Regulator.
JP1
3
REG
AVDD
AVDD-SEL
R EG
AVDD -SEL
(2).Setup the DVDD of AK4128A.
a).When using DVDD jack.
J P2
b).When using Regulator.
JP2
3
REG
3
DVDD
REG
DVDD-SEL
DVD D
DVDD -SEL
(3).Setup the D3.3V-1(AK4114 and Digital Logic).
a).When using D3.3V-1 jack. b).When using Regulator.
J P3
JP3
3
D3.3V-1
3
REG
D3.3V-1
D3.3V-1 SEL
REG
D3.3V-1 SEL
(4). Setup the D3.3V-2(AK4114 and Digital Logic).
a).When using D3.3V-2 jack. b).When using Regulator.
J P4
JP4
3
REG
3
D3.3V-2
REG
D 3.3V-2 SEL
D3.3V-2
D3.3V-2 SEL
[KM104301]
2010/09
-3-
[AKD4128A-A]
3) Set up the evaluation mode, jumper pins. (See the followings.)
(1). Setting for Input port
(1)-1. When using DIR function of AK4114 (U2,U3,U4 and U5)
(1)-2. When using all clocks are fed through the 10pin port
(2). Setting for Output port
(2)-1. When using DIT function of AK4114 (U6)
(2)-2. When using all clocks are fed through the 10pin port(PORT5).
(3). Other jumper pins setup.
4) Power on.
The AK4128A should be reset once bringing SW2 (PDN) “L” upon power-up.
[KM104301]
2010/09
-4-
[AKD4128A-A]
„ Set up the evaluation mode, jumper pins.
(1). Setting for Input port
(1)-1. When using DIR function of AK4114 (U2,U3,U4 and U5)
When using J1-4(COAX) and PORT6-9(OPT), nothing should be connected to PORT1-4.
(1)-1-1. Setup the RX.
(a) Select to Optical jack (Default)
(b) Select to BNC jack
IN P U T x S E L
IN P U T x S E L
3
3
BN C
O PT
BNC
OPT
* "x" contains a number (1 - 4).
(1)-1-2. Setup the IBICK1-4, ILRCK1-4 and SDTI1-4.
When using J1-4(COAX) and PORT6-9(OPT), nothing should be connected to PORT1-4.
６
５
JP27
IMCLK-SEL
IBICKx
ILRCKx
SDTIx
2
EXT
DSP1
DIR
* "x" contains a number (1 - 4).
[KM104301]
2010/09
-5-
[AKD4128A-A]
(1)-1-3. Setup the SDTI1, SDTI2, SDTI3 and SDTI4.
Select to input signal for SDTI1, SDTI2, SDTI3 and SDTI4 of AK4128A(U1).
(a). When using “Synchronous Mode” (INAS pin = “L”). (Default)
Asynchronous
Synchronous
GND
5
6
Asynchronous
Synchronous
GND
5
6
Asynchronous
Synchronous
GN D
5
6
5
6
Asynchronous
Synchronous
GND
JP8
SDTI4-SEL
2
JP7
SDTI3-SEL
2
JP6
SDTI2-SEL
2
2
JP5
SDTI1-SEL
JP7
SDTI3-SEL
JP8
SDTI4-SEL
Asynchronous
Synchronous
GND
5
6
Asynchronous
Synchronous
GND
5
6
Asynchronous
Synchronous
GN D
5
6
5
6
Asynchronous
Synchronous
GND
2
JP6
SDTI2-SEL
2
2
JP5
SDTI1-SEL
2
(b).When using “Asynchronous Mode” (INAS pin = “H”).
JP6
SDTI2-SEL
JP7
SDTI3-SEL
JP8
SDTI4-SEL
[KM104301]
2
Asynchronous
Synchronous
GND
5
6
Asynchronous
Synchronous
GN D
5
6
5
6
Asynchronous
Synchronous
GND
Asynchronous
Synchronous
GND
5
6
2
2
JP5
SDTI1-SEL
2
(c). Connect to GND.
2010/09
-6-
[AKD4128A-A]
(1)-2. When using all clocks are fed through the 10pin port
(1)-2-1. Setup the RX.
When using PORT1-4, nothing should be connected to J1-4 (COAX) and PORT6-9 (OPT).
(1)-2-2. Setup the IBICK1-4, ILRCK1-4 and SDTI1-4.
When using PORT1-4, nothing should be connected to J1-4 (COAX) and PORT6-9 (OPT).
６
５
JP27
IMCLK-SEL
IBICKx
ILRCKx
SDTIx
2
EXT
DSP1
DIR
* "x" contains a number (1 - 4).
(1)-2-3. Setup the SDTI1, SDTI2, SDTI3 and SDTI4.
Select to input signal for SDTI1, SDTI2, SDTI3 and SDTI4 of AK4128A(U1).
(a). When using “Synchronous Mode” (INAS pin = “L”). (Default)
Asynchronous
Synchronous
GND
5
6
Asynchronous
Synchronous
GND
5
6
Asynchronous
Synchronous
GN D
5
6
5
6
Asynchronous
Synchronous
GND
JP8
SDTI4-SEL
2
JP7
SDTI3-SEL
2
JP6
SDTI2-SEL
2
2
JP5
SDTI1-SEL
JP7
SDTI3-SEL
JP8
SDTI4-SEL
Asynchronous
Synchronous
GND
5
6
Asynchronous
Synchronous
GND
5
6
Asynchronous
Synchronous
GN D
5
6
5
6
Asynchronous
Synchronous
GND
2
JP6
SDTI2-SEL
2
2
JP5
SDTI1-SEL
2
(b).When using “Asynchronous Mode” (INAS pin = “H”).
JP6
SDTI2-SEL
JP7
SDTI3-SEL
JP8
SDTI4-SEL
[KM104301]
2
Asynchronous
Synchronous
GND
5
6
Asynchronous
Synchronous
GN D
5
6
5
6
Asynchronous
Synchronous
GND
Asynchronous
Synchronous
GND
5
6
2
2
JP5
SDTI1-SEL
2
(c). Connect to GND.
2010/09
-7-
[AKD4128A-A]
(2). Setting for Output port
(2)-1. When using DIT function of AK4114 (U6)
(2)-1-1. Setup the TX.
(a) Select to Optical jack (Default)
(b) Select to BNC jack
BNC
3
BNC
3
OPT
J P44
O U TP U T S EL
OPT
JP44
O UT PUT S EL
(2)-1-2. Setup the TXI.
Select to input signal for XTI/OMCLK pin of AK4128A(U1) and XTI pin of AK4114(U6).
(a) When using X’Tal(X1). In this case, X’Tal(X2) is “open”.
JP20
MCKO
JP45
DIT-OMCLK SEL
2
JP53
SEL3
3
JP52
EXT-CLK
EXT
GND
DIT
DSP5
EXT
OMCLK
5
3
6
AK4128
JP51
DIT-OMCKO SEL
2 4
(b) When using X’Tal(X2). In this case, X’Tal(X1) is “open”.
JP20
MCKO
JP45
DIT-OMCLK SEL
2
JP53
SEL3
3
JP52
EXT-CLK
EXT
GND
DIT
DSP5
EXT
OMCLK
5
3
6
AK4128
JP51
DIT-OMCKO SEL
2 4
(c) When using J8(EXT-CLK). In this case, X’Tal(X1 and X2) is “open”.
JP45
DIT-OMCLK SEL
2
JP20
MCKO
3
JP53
SEL3
GND
DIT
DSP5
EXT
OMCLK
[KM104301]
6
3
JP52
EXT-CLK
5
EXT
AK4128
JP51
DIT-OMCKO SEL
2 4
2010/09
-8-
[AKD4128A-A]
(2)-1-3. Setup the OBICK, OLRCK and SDTO.
(2)-1-3-1.When using OBICK, OLRCK of AK4114(U6), and SDTO of AK4128A(U1).
JP48
O B IC K
JP49
O LRCK
DIT-Master
JP19
AK4128-OLRCK SEL
2
2
JP18
AK4128-OBICK SEL
4
DIT-Slave
DIT-Master
3
DIT-Slave
4
3
2
JP47
DIT-OLRCK SEL
2
JP46
DIT-OBICK SEL
JP50
SDTO
AK4128-Master
3
4
AK4128-Slave
AK4128-Master
3
4
AK4128-Slave
(2)-1-3-2.When using OBICK, OLRCK and SDTO of AK4128A(U1).
JP48
O B IC K
JP49
O LRCK
DIT-Master
JP19
A K4128-OLRCK SE L
2
2
JP 18
A K4128-OB ICK S EL
4
DIT-Slave
DIT-Master
3
DIT-Slave
4
3
2
JP47
DIT-OLRCK SEL
2
JP46
DIT-OBICK SEL
JP50
SDTO
3
4
AK 4128-Slave
AK 4128-Master
3
4
A K4128-Slav e
A K4128-M aster
[KM104301]
2010/09
-9-
[AKD4128A-A]
(2)-1-4. Selection of SDTO1, SDTO2, SDTO3 and SDTO4.
(a) Select to SDTO1 (b)Select to SDTO2 (c)Select to SDTO3 (d)Select to SDTO4
1
2
3
4
８
SDTO
1
2
3
4
７
SDTO
2
2
JP1 7
S D TO -S E L
８
７
SDTO
1
2
3
4
８
７
SDTO
1
2
3
4
８
７
J P17
SD TO -SE L
2
JP 1 7
S D TO -S E L
2
JP17
SD T O -SEL
(2)-2. When using all clocks are fed through the 10pin port(PORT5).
(2)-2-1.Setup TX.
As Optical connector:PORT10(OPT) and BNC connector:J5(COAX) are not used, please don’t
connect anything.
(2)-2-2. Setup the OBICK, OLRCK and SDTO.
(2)-2-2-1. When using OBICK and OLRCK of 10pin port, and SDTO of AK4128A(U1).
JP48
O B IC K
JP49
O LRCK
DIT-Master
JP19
A K4 12 8-O LR C K SE L
2
2
JP 18
A K41 2 8-O B ICK S EL
4
DIT-Slave
DIT-Master
3
DIT-Slave
4
3
2
JP47
DIT-OLRCK SEL
2
JP46
DIT-OBICK SEL
JP50
SDTO
AK 412 8 -Maste r
3
4
AK 412 8 -Sla ve
A K4 12 8-M a ster
3
4
A K4 12 8-Sl av e
[KM104301]
2010/09
- 10 -
[AKD4128A-A]
(2)-2-2-2. When using OBICK, OLRCK and SDTO of AK4128A(U1).
JP48
O B IC K
JP49
O LRCK
DIT-Master
JP19
A K4 12 8-O LR C K SE L
2
2
JP 18
A K41 2 8-O B ICK S EL
4
DIT-Slave
DIT-Master
3
DIT-Slave
4
3
2
JP47
DIT-OLRCK SEL
2
JP46
DIT-OBICK SEL
JP50
SDTO
AK 412 8 -Maste r
3
4
AK 412 8 -Sla ve
A K4 12 8-M a ster
3
4
A K4 12 8-Sl av e
(2)-2-2-3. Selection of SDTO1, SDTO2, SDTO3 and SDTO4.
(b)Select to SDTO2 (c)Select to SDTO3 (d)Select to SDTO4
[KM104301]
1
2
3
4
８
SDTO
1
2
3
4
７
７
SDTO
2
JP1 7
S D TO -S E L
2
1
2
3
4
８
SDTO
1
2
3
4
７
SDTO
８
７
J P17
SD TO -SE L
2
JP 1 7
S D TO -S E L
2
JP17
SD T O -SEL
８
(a) Select to SDTO1
2010/09
- 11 -
[AKD4128A-A]
(3). Other jumper pins setup.
[ JP9 (SEL1) ]：The selection of input signal to IMCLK pin.
IMCLK ：Connect to MCLK signal of DIR or 10 pin PORT. (Default)
GND ：Connect to GND
[ JP10 (ILRCK2-SEL) ]：The selection of input signal to ILRCK2 pin.
ILRCK2：Connect to LRCK2 signal of DIR or 10 pin PORT. (Default)
GND ：Connect to GND
[ JP11 (ILRCK3-SEL) ]：The selection of input signal to ILRCK3 pin.
ILRCK3：Connect to LRCK3 signal of DIR or 10 pin PORT. (Default)
GND ：Connect to GND
[ JP12 (IBICK3-SEL) ]：The selection of input signal to IBICK3 pin.
IBICK3：Connect to BICK3 signal of DIR or 10 pin PORT. (Default)
GND ：Connect to GND
[ JP13 (ILRCK4-SEL) ]：The selection of input signal to ILRCK4 pin.
ILRCK4：Connect to LRCK4 signal of DIR or 10 pin PORT. (Default)
GND ：Connect to GND
[ JP14 (IBICK4-SEL) ]：The selection of input signal to IBICK4 pin.
IBICK4 ：Connect to BICK4 signal of DIR or 10 pin PORT. (Default)
GND ：Connect to GND
[ JP15 (SEL2) ]：The selection of input signal to INAS pin.
INAS ：Connect to INAS signal (Default)
GND ：Connect to GND
[ JP16 (UNLOCK) ]：The selection of connection to UNLOCK pin and LE1.
OPEN ：Unconnection.
SHORT ：Connection. (Default)
[ JP21 (TST0) ]：The selection of connection to TST0 pin and SW17(TST0).
OPEN ：Unconnection.
SHORT ：Connection. (Default)
[ JP22 (TST1) ]：The selection of connection to TST1 pin and SW3(TST1).
OPEN ：Unconnection.
SHORT ：Connection. (Default)
[ JP23 (TST2) ]：The selection of connection to TST2 pin and SW3(TST2).
OPEN ：Unconnection.
SHORT ：Connection. (Default)
[ JP24 (SEL4) ]：The selection of input signal to SDA pin.
SDA ：Connect to SDA signal of 10 pin PORT(PORT11). (Default)
GND ：Connect to GND
[ JP25 (TST3) ]：The selection of connection to TST3 pin and SW17(TST3).
OPEN ：Unconnection.
SHORT ：Connection. (Default)
[KM104301]
2010/09
- 12 -
[AKD4128A-A]
[ JP31 (EXT-CLK) ]：The selection of J7(EXT-CLK) connector.
OPEN ：J7(EXT-CLK) connector is use.
SHORT ：J7(EXT-CLK) connector is not use. (Default)
* If “JP31(EXT-CLK)” is set to “OPEN”, JP27 is set to “EXT”.
[KM104301]
2010/09
- 13 -
[AKD4128A-A]
„ Setup the DIP SW.
(1). Setup the AK4128A(U1).
(1)-1. SW3 setting
Upper-side is “H” and lower-side is “L”.
SW3
No.
1
2
3
4
5
6
7
8
Mode
0
1
2
Name
ON (“H”)
IDIF2
IDIF1
IDIF0
SPB
TST1
TST2
SMSEMI
CAD0
IDIF2
pin
L
L
L
OFF (“L”)
Audio Interface Format Setting for Input PORT
Refer to Table 3
Serial Control Mode
Parallel Control Mode
TEST Pin
Fixed to ”L”
Semi-auto Mode
Manual Mode
Chip Address 0 bit=”1”
Chip Address 0 bit=”0”
Table 2. SW3 Setting
IDIF1 IDIF0
pin
pin
L
L
L
H
H
L
H
SDTI1-4 Format
16bit, LSB justified
20bit, LSB justified
24bit, MSB justified
2
24/16bit, I S Compatible
IBICK
Freq
≥ 32FSI
≥ 40FSI
≥ 48FSI
≥ 48FSI or
32FSI
≥ 48FSI
Default
L
H
L
L
L
L
L
L
(Default)
3
L
H
4
5
6
H
H
H
L
L
24bit, LSB justified
L
H
Reserved
H
H
Table 3. AK4128A Audio Interface Format Setting for Input PORT
[KM104301]
2010/09
- 14 -
[AKD4128A-A]
(1)-2. SW3 setting
Upper-side is “H” and lower-side is “L”.
SW4
No.
1
2
3
4
5
6
7
8
Mode
Name
OBIT1
OBIT0
TDM
CM2
CM1
CM0
ODIF1
ODIF0
TDM
pin
0
1
2
3
4
5
6
L
H
7
TDM
Mode
pin
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ON (“H”)
L
Default
H
H
L
H
L
L
H
L
Output PORT Audio Interface Format Setting 2
Refer to Table 6
TDM mode
Stereo mode
Clock Select or Mode Select pin for Output PORT
Refer to Table 7
Output PORT Audio Interface Format Setting 1
Refer to Table 5
Table4. SW4 Setting
ODIF1 ODIF0
pin
pin
L
L
L
H
H
L
H
H
L
L
L
H
SDTO1-4 Format
LSB justified
(Reserved)
MSB justified
I2S Compatible
(Default)
(Reserved)
TDM256 mode
24bit MSB justified
TDM256 mode
H
H
24bit I2S Compatible
Table 5. Output PORT Audio Interface Format Setting 1
H
L
Master / Slave
setting
OBIT1 OBIT0
pin
pin
SDTO
1-4
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
16bit
18bit
20bit
24bit
16bit
18bit
20bit
24bit
Slave
(CM2-0 =
“HLL” or
“HHL”)
*
*
Master
(Not CM2-0 =
“HLL”/“HHL”)
*
*
Slave
(CM2-0 =
“HLL” or
“HHL”)
Master
(Not CM2-0 =
“HLL”/“HHL”)
H
OFF (“L”)
OLRCK OBICK
Input
Input
OBICK Frequency
MSB
LSB
justified,
justified
2
IS
≥ 32FSO
≥ 36FSO
64FSO
≥ 40FSO
≥ 48FSO
Output
Output
64FSO
TDM256
mode
24bit
Input
Input
256FSO
TDM256
mode
24bit
Output
Output
256FSO
(Default)
Table 6. Output PORT Audio Interface Format Setting 2
[KM104301]
2010/09
- 15 -
[AKD4128A-A]
Mode
0
1
2
3
CM2 CM1 CM0
pin
pin
pin
L
L
L
L
L
H
L
H
L
L
H
H
4
H
L
5
6
7
H
H
H
L
H
H
L
Master /
Slave
Master
Master
Master
Master
Slave
OMCLK/XTI
Input
256FSO
384FSO
512FSO
768FSO
In External Clock
Mode,
1.024MHz~36.864MHz.
In X’tal Mode, X’tal
oscillation frequency.
128FSO
MCKO
Output
256FSO
384FSO
512FSO
768FSO
FSO
8k ∼ 108kHz
8k ∼ 96kHz
8k ∼ 54kHz
8k ∼ 48kHz
OMCLK
Input Clock
8k ∼ 216kHz
(Default)
H
Master
128FSO
8k ∼ 216kHz
Slave
L
IMCLK
Not used. (note)
8k ∼ 216kHz
(Bypass)
Input Clock
H
Table 7. Output PORT Master/Slave/Bypass Mode Control Setting
(1)-3. SW5 setting
Upper-side is “H” and lower-side is “L”.
SW4
No.
1
2
3
4
5
6
7
8
Name
ON (“H”)
INAS
DITHER
SMT1
SMT0
DEM0
DEM1
PM2
PM1
SMT1pin
L
L
H
H
OFF (“L”)
Asynchronous mode
Synchronous mode
Dither ON
Dither OFF
Soft Mute Timer Setting
Refer to Table 9
De-emphasis Filter Setting
Refer to Table 10
Channel Mode Setting
Refer to Table 11
Table 8. SW5 Setting
SMT0 pin
L
H
L
H
DEM1pin
L
L
H
H
Period
FSO=48kHz FSO=96kHz
1024/fso
21.3ms
10.7ms
2048/fso
42.7ms
21.3ms
4096/fso
85.3ms
42.7ms
8192/fso
170.7ms
85.3ms
Table 9. Soft Mute Cycle Setting
Default
L
L
L
L
H
L
H
L
FSO=192kHz
5.3ms
10.7ms
21.3ms
42.7ms
(Default)
DEM0 pin
Mode(SDTI1-4)
L
44.1kHz
H
OFF
(Default)
L
48kHz
H
32kHz
Table 10. De-emphasis Filter Setting
[KM104301]
2010/09
- 16 -
[AKD4128A-A]
PM2
pin
PM1
pin
PDN
pin
L
L
L
L
L
H
L
H
L
L
H
H
H
L
L
H
L
H
H
H
H
H
L
H
Mode
X’tal
Oscillator
6-channel
mode
Power-down
4-channel
mode
8-channel
mode
Not
available
Power-down
XTI pin
XTO pin
Pull down to
VSS2-5
Input
Pull down to
VSS2-5
MCKO pin
Hi-z
Hi-z
Hi-z
Input
Power-down
Pull down to
VSS2-5
Hi-z
Input
Output
-
-
Normal
operation
-
L
Normal
operation
-
(Default)
Table 11. Channel Mode Setting
(1)-4. SW17 setting
Upper-side is “H” and lower-side is “L”.
SW17
No.
1
2
Name
TST3
TST0
ON (“H”)
OFF (“L”)
TEST Pin
Fixed to ”L”
Table 12. SW17 Setting
[KM104301]
Default
L
L
2010/09
- 17 -
[AKD4128A-A]
(2). Setup the AK4114 (U2,U3,U4,U5,U6)
(2)-1. SW6(U2), SW7(U3), SW8(U4), SW9(U5) setting.
Upper-side is “H” and lower-side is “L”.
SW6
No.
1
2
3
SW7
No.
1
2
3
SW8
No.
1
2
3
Name
DIR1-OCKS1
DIR1-OCKS0
DIR1-DIF0
Name
DIR2-OCKS1
DIR2-OCKS0
DIR2-DIF0
Name
DIR3-OCKS1
DIR3-OCKS0
DIR3-DIF0
SW9
No.
1
2
3
DIR4-OCKS1
DIR4-OCKS0
DIR4-DIF0
Mode
0
1
2
3
OCKS1 pin
L
L
H
H
Name
ON (“H”)
OFF (“L”)
Default
H
L
L
Master Clock Frequency Setting
Refer to Table 17
2
24bit, I S Compatible 24bit, Left justified
Table 13. SW6 Setting
ON (“H”)
OFF (“L”)
Default
H
L
L
Master Clock Frequency Setting
Refer to Table 17
24bit, I2S Compatible 24bit, Left justified
Table 14. SW7 Setting
ON (“H”)
OFF (“L”)
Default
H
L
L
Master Clock Frequency Setting
Refer to Table 17
24bit, I2S Compatible 24bit, Left justified
Table 15. SW8 Setting
ON (“H”)
OFF (“L”)
Default
Master Clock Frequency Setting
Refer to Table 17
2
24bit, I S Compatible 24bit, Left justified
Table 16. SW9 Setting
OCKS0 pin
MCKO1
fs (max)
L
256fs
96 kHz
H
256fs
96 kHz
L
512fs
48 kHz
H
128fs
192 kHz
Table 17. Master Clock Frequency Setting
[KM104301]
H
L
L
(Default)
2010/09
- 18 -
[AKD4128A-A]
(2)-2. SW16(U6) setting.
Upper-side is “H” and lower-side is “L”.
SW16
No.
1
2
3
4
5
Name
ON (“H”)
OFF (“L”)
Master Clock Frequency Setting
Refer to Table 19
DIT-OCKS1
DIT-OCKS0
DIT-DIF2
DIT-DIF1
DIT-DIF0
Audio Interface Format Setting
Refer to Table 20
Default
H
L
H
L
L
Table 18. Master Clock Frequency Setting
Mode
0
1
2
3
Mode
0
1
2
3
4
5
6
7
OCKS1 pin
L
L
H
H
MCKO1
fs (max)
OCKS0 pin
L
256fs
96 kHz
H
256fs
96 kHz
L
512fs
48 kHz
(Default)
H
128fs
192 kHz
Table 19. Master Clock Frequency Setting
DIF2
pin
L
L
L
L
H
H
H
H
DIF0
pin
L
H
L
H
L
H
L
H
DIF1
pin
L
L
H
H
L
L
H
H
LRCK
BICK
I/O
24bit, Left justified
H/L
O
64fs
24bit, Left justified
H/L
O
64fs
24bit, Left justified
H/L
O
64fs
24bit, Left justified
H/L
O
64fs
24bit, Left justified
H/L
O
64fs
24bit, I2S Compatible L/H
O
64fs
24bit, Left justified
H/L
I
64-128fs
24bit, I2S Compatible L/H
I
64-128fs
Table 20. Audio Interface format Setting
DAUX Format
[KM104301]
I/O
O
O
O
O
O
O
I
I
(Default)
2010/09
- 19 -
[AKD4128A-A]
„ The function of the toggle SW
Upper-side is “H” and lower-side is “L”.
[SW1] (AK4128-SMUTE) ：Soft mute of AK4128A.
When using Soft mute function, SW1 is “H”.
[SW2] (AK4128-PDN)
：Resets the AK4128A. Keep “H” during normal operation.
The AK4128A should be resets once bringing “L” upon power-up.
[SW10] (DIR1-PDN)
：Resets the AK4114 (U2). Keep “H” during normal operation.
The AK4114 (U2) should be resets once bringing “L” upon power-up.
Keep “L” when AK4114 (U2) is not used.
[SW11] (DIR2-PDN)
：Resets the AK4114 (U3). Keep “H” during normal operation.
The AK4114 (U3) should be resets once bringing “L” upon power-up.
Keep “L” when AK4114 (U3) is not used.
[SW12] (DIR3-PDN)
：Resets the AK4114 (U4). Keep “H” during normal operation.
The AK4114 (U4) should be resets once bringing “L” upon power-up.
Keep “L” when AK4114 (U4) is not used.
[SW13] (DIR4-PDN)
： Resets the AK4114 (U5). Keep “H” during normal operation.
The AK4114 (U5) should be resets once bringing “L” upon power-up.
Keep “L” when AK4114 (U5) is not used.
[SW14] (DIT-PDN)
： Resets the AK4114 (U6). Keep “H” during normal operation.
The AK4114 (U6) should be resets once bringing “L” upon power-up.
Keep “L” when AK4114 (U6) is not used.
„ Indication for LED
[LE1] (UNLOCK)
：Monitor UNLOCK pin of the AK4128A (U1).
LED turns on when PDN pin = “L”.
[KM104301]
2010/09
- 20 -
[AKD4128A-A]
„ Serial Control
The AK4128A can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT1
(CTRL) with PC by 10 wire flat cable packed with the AKD4128A-A.
SCL
SDA
SDA(ACK)
AKD4128A-A
PORT 11 9
uP-I/F 10
2
10pin Header
Connect
10 wire flat Cable
Red
PC
Figure 1. Connection of 10 wire flat cable
[KM104301]
2010/09
- 21 -
[AKD4128A-A]
Control Soft Manual
„ Evaluation Board and Control Soft Settings
1. Set an evaluation board properly.
2. Connect the evaluation board to an IBM PC/AT compatible PC by a 10wire flat cable. Be aware of the direction of
the 10pin header. When running this control soft on the Windows 2000/XP, the driver which is included in the CD
must be installed. Refer to the “Driver Control Install Manual for AKM Device Control Software” for installing
the driver. When running this control soft on the windows 95/98/ME, driver installing is not necessary. This
control soft does not support the Windows NT.
3. Proceed evaluation by following the process below.
[KM104301]
2010/09
- 22 -
[AKD4128A-A]
■Operation Overview
Function, register map and testing tool can be controlled by this control soft. These controls are selected by upper tabs.
Buttons which are frequently used such as register initializing button “Write Default”, are located outside of the
switching tab window. Refer to the “■ Dialog Boxes” for details of each dialog box setting.
1.
[Port Reset]
2.
[Write Default]
3.
4.
5.
6.
7.
8.
9.
10.
11.
[All Write]
[All Read]
[Save]
[Load]
[All Req Write]
[Data R/W]
[Sequence]
[Sequence(File)]
[Read]
: For when connecting to USB I/F board (AKDUSBIF-A)
Click this button after the control soft starts up when connecting USB I/F board
(AKDUSBIF-A).
: Register Initializing
When the device is reset by a hardware reset, use this button to initialize the registers.
: Executing write commands for all registers displayed.
: Executing read commands for all registers displayed.
: Saving current register settings to a file.
: Executing data write from a saved file.
: “All Req Write” dialog box is popped up.
: “Data R/W” dialog box is popped up.
: “Sequence” dialog box is popped up.
: “Sequence(File)” dialog box is popped up.
: Reading current register settings and display on to the Register area
(on the right of the main window).
This is different from [All Read] button, it does not reflect to a register map, only
displaying hexadecimal.
Figure 3. Window of [ FUNCTION]
[KM104301]
2010/09
- 23 -
[AKD4128A-A]
■Dialog Boxes
[All Req Write]
Click [All Reg Write] button in the main window to open register setting files.
Register setting files saved by [SAVE] button can be applied.
Figure 4. Window of [ All Reg Write]
[Open (left)]
[Write]
[Write All]
[Help]
[Save]
[Open (right)]
[Close]
: Selecting a register setting file (*.akr).
: Executing register writing.
: Executing all register writings.
Writings are executed in descending order.
: Help window is popped up.
: Saving the register setting file assignment. The file name is “*.mar”.
: Opening a saved register setting file assignment “*. mar”.
: Closing the dialog box and finish the process.
*Operating Suggestions
(1) Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mar” should be
stored in the same folder.
(2) When register settings are changed by [Save] button in the main window, re-read the file to reflect new register
settings.
[KM104301]
2010/09
- 24 -
[AKD4128A-A]
[Data R/W]
Click the [Data R/W] button in the main window for data read/write dialog box.
Data write is available to specified address.
Figure 5. Window of [ Data R/W ]
Address Box : Input data address in hexadecimal numbers for data writing.
Data Box
: Input data in hexadecimal numbers.
Mask Box
: Input mask data in hexadecimal numbers.
This is “AND” processed input data.
[Write]
[Close]
: Writing to the address specified by “Address” box.
: Closing the dialog box and finish the process.
Data writing can be cancelled by this button instead of [Write] button.
*The register map will be updated after executing [Write] or [Read] commands.
[KM104301]
2010/09
- 25 -
[AKD4128A-A]
[Sequence]
Click [Sequence] button to open register sequence setting dialog box.
Register sequence can be set in this dialog box.
Figure 6. Window of [ Sequence ]
Sequence Setting
Set register sequence by following process bellow.
(1)Select a command
Use [Select] pull-down box to choose commands.
Corresponding boxes will be valid.
< Select Pull-down menu >
· No_use
: Not using this address
· Register
: Register writing
· Reg(Mask) : Register writing (Masked)
· Interval
: Taking an interval
· Stop
: Pausing the sequence
· End
: Finishing the sequence
(2)Input sequence
[Address]
[Data]
[Mask]
[ Interval ]
: Data address
: Writing data
: Mask
[Data] box data is ANDed with [Mask] box data. This is the actual writing data.
When Mask = 0x00, current setting is hold.
When Mask = 0xFF, the 8bit data which is set in the [Data] box is written.
When Mask =0x0F, lower 4bit data which is set in the [Data] box is written.
Upper 4bit is hold to current setting.
: Interval time
[KM104301]
2010/09
- 26 -
[AKD4128A-A]
Valid boxes for each process command are shown bellow.
· No_use
· Register
· Reg(Mask)
· Interval
· Stop
· End
: None
: [Address], [Data], [Interval]
: [Address], [Data], [Mask], [Interval]
: [Interval]
: None
: None
Control Buttons
The function of Control Button is shown bellow.
[Start]
[Help]
[Save]
[Open]
[Close]
: Executing the sequence
: Opening a help window
: Saving sequence settings as a file. The file name is “*.aks”.
: Opening a sequence setting file “*.aks”.
: Closing the dialog box and finish the process.
Stop of the sequence
When “Stop” is selected in the sequence, processing is paused and it starts again when [Start] button is clicked.
Restarting step number is shown in the “Start Step” box. When finishing the process until the end of sequence,
“Start Step” will return to “1”.
The sequence can be started from any step by writing the step number to the “Start Step” box.
Write “1” to the “Start Step” box and click [Start] button, when restarting the process from the beginning.
[KM104301]
2010/09
- 27 -
[AKD4128A-A]
[Sequence(File)]
Click [Sequence(File)] button to open sequence setting file dialog box.
Those files saved in the “Sequence setting dialog” can be applied in this dialog.
Figure 7. Window of [ Sequence(File) ]
[Open (left)] : Opening a sequence setting file (*.aks).
[Start]
: Executing the sequence setting.
[Start All]
: Executing all sequence settings.
Sequences are executed in descending order.
[Help]
: Pop up the help window.
[Save]
: Saving sequence setting file assignment. The file name is “*.mas”.
[Open(right)] : Opening a saved sequence setting file assignment “*. mas”.
[Close]
: Closing the dialog box and finish the process.
*Operating Suggestions
(1) Those files saved by [Save] button and opened by [Open] button on the right of the dialog
“*.mas” should be stored in the same folder.
(2) When “Stop” is selected in the sequence the process will be paused and a pop-up message will appear. Click
“OK” to continue the process.
Figure 8. Window of [ Sequence Pause ]
[KM104301]
2010/09
- 28 -
[AKD4128A-A]
1. [REG]: Register Map
This tab is for a register writing and reading.
Each bit on the register map is a push-button switch.
Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red).
Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray)
Grayout registers are Read Only registers. They can not be controlled.
The registers which is not defined in the datasheet are indicated as “---”.
Figure 9. Window of [ REG]
[KM104301]
2010/09
- 29 -
[AKD4128A-A]
[Write]: Data Writing Dialog
It is for when changing two or more bits on the same address at the same time.
Click [Write] button located on the right of the each corresponded address for a pop-up dialog box.
When checking the checkbox, the register will be “H” or “1”, when not checking the register will be “L” or ”0”.
Click [OK] to write setting value to the registers, or click [Cancel] to cancel this setting.
Figure 10. Window of [ Register Set ]
[Read]: Data Read
Click [Read] button located on the right of the each corresponded address to execute register reading.
After register reading, the display will be updated regarding to the register status.
Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red).
Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray)
Please be aware that button statuses will be changed by Read command.
[KM104301]
2010/09
- 30 -
[AKD4128A-A]
2.[Tool]: Testing Tools
This tab screen is for evaluation testing tool.
Click buttons for each testing tool.
Figure 11. Window of [ Tool]
[KM104301]
2010/09
- 31 -
[AKD4128A-A]
[Repeat Test]: Repeat Test Dialog
Click [Repeat Test] button to open repeat test setting dialog box.
Figure 12. Window of [ Repeat Test]
[Loop Setting]: Loop Setting Dialog
Click [Loop Setting] button to open loop setting dialog box.
Figure 13. Window of [ Loop]
[KM104301]
2010/09
- 32 -
[AKD4128A-A]
Measurement Results
[Measurement condition]
• Measurement unit
• Power Supply
• Band width
• INAS pin
• OMCLK/XTI Input
• Output PORT
• Temperature
: Audio Precision, System Two Cascade
: AVDD=DVDD=3.3V
: 20Hz ∼ FSO/2
: “L” (Synchronous Mode)
: Use X’Tal (X1)
: Slave Mode
: Room
[Measurement Result]
SRC Characteristics
THD+N
(Input = 1kHz, 0dBFS)
FSO/FSI = 44.1kHz/48kHz
FSO/FSI = 48kHz/44.1kHz
FSO/FSI = 48kHz/192kHz
FSO/FSI = 192kHz/48kHz
Worst Case (FSO/FSI = 32kHz/176.4kHz)
Dynamic Range
(Input = 1kHz, −60dBFS)
FSO/FSI = 44.1kHz/48kHz
FSO/FSI = 48kHz/44.1kHz
FSO/FSI = 48kHz/192kHz
FSO/FSI = 192kHz/48kHz
Worst Case(FSO/FSI = 48kHz/32kHz)
Dynamic Range
(Input = 1kHz, −60dBFS, A-weighted)
FSO/FSI = 44.1kHz/48kHz
SDTO1
Lch
Rch
SDTO2
Lch
Rch
SDTO3
Lch
Rch
SDTO4
Lch
Rch
Unit
130.4
125.0
133.3
124.9
130.4
130.4
125.0
133.4
124.9
130.4
130.3
125.0
133.5
124.7
130.3
130.3
125.0
133.3
124.9
130.3
130.4
125.1
133.3
124.9
130.4
130.4
125.1
133.4
124.9
130.4
130.4
125.1
133.4
124.9
130.4
130.4
125.1
133.5
124.9
130.4
dB
dB
dB
dB
dB
136.5
136.7
136.3
132.6
136.2
136.5
136.8
136.5
132.6
136.5
136.7
136.6
136.4
132.7
136.3
136.7
136.7
136.3
132.7
136.3
136.7
136.6
136.3
132.6
136.5
136.9
136.8
136.3
132.7
136.5
136.8
136.8
136.4
132.7
136.2
136.8
136.9
136.4
132.7
136.3
dB
dB
dB
dB
dB
140.2 140.4 140.2 140.1 140.1 140.1 140.2 140.2
dB
[KM104301]
2010/09
- 33 -
[AKD4128A-A]
[Plots]
AKM
AK4128A FFT
AVDD=DVDD=3.3V, FSO/FSI=44.1kHz/48kHz, 1kHz/0dBFS Input
+0
-10
-20
-30
-40
-50
-60
-70
-80
d
B
F
S
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure 14. FFT Plot (Input = 0dBFS)
AKM
AK4128A FFT
AVDD=DVDD=3.3V, FSO/FSI=44.1kHz/48kHz, 1kHz/-60dBFS Input
+0
-10
-20
-30
-40
-50
-60
-70
-80
d
B
F
S
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
20
50
100
200
500
1k
2k
Hz
Figure 15. FFT Plot (Input = -60dBFS)
[KM104301]
2010/09
- 34 -
[AKD4128A-A]
AKM
AK4128A THD+N vs. Input Level
AVDD=DVDD=3.3V, FSO/FSI=44.1kHz/48kHz, fin=1kHz
-120
-122
-124
-126
-128
-130
-132
d
B
F
S
-134
-136
-138
-140
-142
-144
-146
-148
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 16. THD+N vs. Input Level
AKM
AK4128A THD+N vs. Input Frequency
AVDD=DVDD=3.3V, FSO/FSI=44.1kHz/48kHz, 0dBFS Input
-90
-95
-100
-105
-110
-115
d
B
F
S
-120
-125
-130
-135
-140
-145
-150
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 17. THD+N vs. Input Frequency (Input = 0dBFS)
[KM104301]
2010/09
- 35 -
[AKD4128A-A]
AKM
AK4128A THD+N vs. Input Frequency
AVDD=DVDD=3.3V, FSO/FSI=44.1kHz/48kHz, -60dBFS Input
-90
-95
-100
-105
-110
-115
d
B
F
S
-120
-125
-130
-135
-140
-145
-150
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 18. THD+N vs. Input Frequency (Input = -60dBFS)
AKM
AK4128A Linearity
AVDD=DVDD=3.3V, FSO/FSI=44.1kHz/48kHz, fin=1kHz
+0
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 19. Linearity
[KM104301]
2010/09
- 36 -
[AKD4128A-A]
AKM
AK4128A Frequency Response (Yellow:FSI=44.1kHz, Blue:FSI=48kHz, Red:FSI=96kHz, Green:FSI=192kHz)
AVDD=DVDD=3.3V, FSO=44.1kHz, 0dBFS Input
+1
+0.5
-0
FSI=44.1kHz
-0.5
-1
-1.5
-2
-2.5
d
B
F
S
FSI=192kHz
-3
-3.5
FSI=96kHz
-4
-4.5
FSI=48kHz
-5
-5.5
-6
-6.5
-7
-7.5
-8
1k
2k
3k
4k
5k
6k
7k
8k
9k
10k
11k
12k
13k
14k
15k
16k
17k
18k
19k
20k
21k
22k
Hz
Figure 20. Frequency Response (FSO=44.1kHz)
AKM
AK4128A Frequency Response (Blue:FSI=48kHz, Red:FSI=96kHz, Green:FSI=192kHz)
AVDD=DVDD=3.3V, FSO=48kHz, 0dBFS Input
+1
+0.5
-0
-0.5
-1
-1.5
FSI=192kHz
-2
-2.5
d
B
F
S
FSI=96kHz
-3
-3.5
FSI=48kHz
-4
-4.5
-5
-5.5
-6
-6.5
-7
-7.5
-8
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
22k
24k
Hz
Figure 21. Frequency Response (FSO=48kHz
[KM104301]
2010/09
- 37 -
[AKD4128A-A]
Revision History
Date
(YY/MM/DD)
10/08/24
Manual
Revision
KM104300
Board
Revision
0
Reason
Page
First edition
-
10/09/30
KM104301
0
Addition
Contents
33-37 Measurement Results and Plots were added.
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices
Corporation (AKM) or authorized distributors as to current status of the products.
z AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any
information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official approval
under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic
materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard
related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with the express
written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether
directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must
therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for
applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may
reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product
with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to
assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said
product in the absence of such notification.
[KM104301]
2010/09
- 38 -
E
TST0
CAD0
DVDD
TST1
TST2
SPB
SDA
AVDD
TST3
D
SMSEMI
C
SCL
B
ILRCK2
A
JP20
MCKO
TP29
DV18
+
TP22
TST3
C5
1u
JP21
TST0
49
TP21
TST0
51
52
TP23
DVDD
C4
C100 10u
10u
C6
+
C2
A
+
TP5
ILRCK2
R14
open
AK4128-DVDD
53
TP24
VSS5
C3
open
R19
short
50
JP22
TST1
54
56
55
JP23
TST2
GND
57
58
59
60
61
62
JP24
SEL4
TP25
AVDD
R5
51
SDA
JP25
TST3
64
CN4
64pin_4
R15
short
63
JP10
ILRCK2-SEL
TP26
VSS1
A
GND
ILRCK2
AK4128-MCKO
0.1u
GND
SDTI2
SDTI3
49
48
2
R1
51
TP1
IMCLK
2
IMCLK
XTI/OMCLK
47
51
TP2
ILRCK1
3
ILRCK1
OLRCK
51
TP3
IBICK1
4
IBICK1
R2
R3
AK4128-DVDD
C20 10p
2
X1
22.5792MHz
C21 10p
TP18
OMCLK
JP53
47
46
46
OBICK
45
TP19
OBICK
45
DVDD
DVDD
44
6
VSS2
VSS4
43
SDTO4
42
TP17
SDTO4
42
SDTO1
41
TP14
SDTO1
41
SDTI2
SDTO2
40
TP15
SDTO2
40
TP16
SDTO3
39
AK4128-DVDD
C10
0.1u
7
51
TP13
SDTI4
7
SDTI4
8
R4
51
TP4
SDTI1
8
SDTI1
9
R7
51
TP7
SDTI2
9
R10
51
TP10
SDTI3
10
SDTI3
SDTO3
39
U1
AK4128A
OMCLK
AK4128-OMCLK
GND
SEL3
5
C1
0.1u
B
48
TP20
OLRCK
R13
10
1
50
TST0
MCKO
51
CAD0
52
DVDD
53
VSS5
55
54
TST1
TST2
SMSEMI
56
57
SCL
SDA
58
59
SPB
AVDD
XTO
C7 +
10u
C
60
IBICK2
6
SDTI1
61
1
4
JP8
Asynchronous
Synchronous
GND
JP5
Asynchronous
SDTI4-SEL
Synchronous
GND
JP6
SDTI1-SEL
Asynchronous
Synchronous
GND
JP7
Asynchronous
SDTI2-SEL
Synchronous
GND
DV18
TP6
IBICK2
5
SDTI4
VSS1
51
3
IBICK1
62
R6
SEL1
ILRCK1
64pin_3
1
JP9
IMCLK
IMCLK
TST3
ILRCK2
B
IBICK2
63
64
0.1u
CN1
JP19 AK4128-OLRCK SEL
AK4128-Slave
AK4128-Master
AK4128-OLRCK-S
AK4128-OLRCK-M
JP18 AK4128-OBICK SEL
AK4128-Slave
AK4128-Master
AK4128-OBICK-S
AK4128-OBICK-M
44
+C8
10u
43
JP17
SDTO1
SDTO2
SDTO3
SDTO4
AK4128-SDTO
C
SDTO-SEL
SDTI3-SEL
IDIF0
11
11
IDIF0
ODIF0
38
38
ODIF0
IDIF1
12
12
IDIF1
ODIF1
37
37
ODIF1
IDIF2
CM0
36
36
CM0
TP8
ILRCK3
14
ILRCK3
CM1
35
35
CM1
15
IBICK3
CM2
34
34
CM2
16
TDM
33
33
TDM
PM2
OBIT1
D
CN3
32
31
OBIT0
30
PM1
29
DEM1
28
DEM0
27
SMT0
SMT1
26
25
DITHER
VSS3
PDN
24
23
17
SMUTE
ILRCK4
64pin_1
22
TP11
ILRCK4
21
16
51
DVDD
51
R11
UNLOCK
R9
20
ILRCK4-SEL
15
TP9
IBICK3
INAS
GND
D
R8
19
GND
JP13
IBICK3-SEL
ILRCK4
14
IBICK4
GND
JP12
ILRCK3-SEL
IBICK3
IBICK3
ILRCK4
13
51
13
JP11
ILRCK3
18
IDIF2
ILRCK3
JP15
SEL2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
GND
INAS
JP16
UNLOCK
18
17
JP14
IBICK4-SEL
IBICK4
10u
E
PM2
OBIT1
OBIT0
PM1
DEM1
DEM0
SMT1
SMT0
AK4128-PDN
DITHER
SMUTE
UNLOCK
B
INAS
IBICK4
A
GND
E
TP27
PDN
C13
AK4128-DVDD
R12
51
CN2
64pin_2
TP28
SMUTE
0.1u
+
TP12
IBICK4
TP30
UNLOCK
C12
Title
Size
A2
Date:
C
D
AKD4128A-A
Document Number
Rev
AK4128A
Tuesday, August 24, 2010
E
Sheet
0
1
of
10
A
B
C
D
E
E
E
L2 47u
1
2
D3.3V-1
PORT6
2
1
D3.3V-1
C25
0.1u
+ C26
10u
+
GND
OUT
TORX141
C117 10u
C116 0.1u
R20 51
C30
0.1u
JP26
OPT
C115
0.47u
R41
18k
1
IPS0
2
3
37
INT1
38
39
R
AVDD
40
41
42
AVSS
NC
RX0
43
44
RX1
45
TEST1
NC
47
48
BNC
INPUT1 SEL
RX2
R25
75
46
1
RX3
2
3
4
5
+
J1
BNC-R-PC
COAX
VCOM
RX
VCC
3
INT0
36
NC
OCKS0
35
DIR1-OCKS0
DIF0
OCKS1
34
DIR1-OCKS1
CM1
33
CM0
32
PDN
31
XTI
30
D
D
TEST2
5
DIF1
6
NC
7
DIF2
8
IPS1
XTO
29
9
P/SN
DAUX
28
10
XTL0
MCKO2
27
11
XTL1
BICK
26
AK4114
R42
R49
R46
R47
JP28
IBICK1
PORT1
A1-10PA-2.54DSA
2
IMCLK 1
4
IBICK1 3
ILRCK1 5
6
SDTI1 7
8
51
51
51
51
9
C
10
DSP1
JP30
SDTI1
R48
220k
LRCK
25
DIR1-PDN
R44
220k
R43
220k
R45
220k
24
MCKO1
DVSS
22
23
DVDD
C112
10u
+
21
VOUT
20
COUT
BOUT
UOUT
19
18
17
16
14
13
C114
0.1u
C113
10u
+
C111
0.1u
TX1
SDTO
TX0
VIN
TVDD
12
U2
DVSS
C
4
15
DIR1-DIF0
JP29
ILRCK1
D3.3V-1
B
B
JP27
DIR1-MCKO
DIR
DSP1
EXT
J7
BNC-R-PC
EXT-CLK
IMCLK-SEL
R52
51
DIR1-BICK
JP31
EXT-CLK
DIR1-LRCK
DIR1-SDTI1
A
A
Title
Size
A2
Date:
A
B
C
D
AKD4128A-A
Document Number
Rev
DIR1
Tuesday, August 24, 2010
E
0
Sheet
2
of
10
A
B
C
D
E
E
E
L3 47u
1
2
D3.3V-1
PORT7
2
1
D3.3V-1
C27
0.1u
TORX141
+ C28
10u
+
GND
OUT
C125 10u
C124 0.1u
R21 51
C31
0.1u
JP32
OPT
C123
0.47u
R50
18k
IPS0
2
3
38
37
INT1
R
AVDD
39
40
41
AVSS
42
RX0
43
NC
RX1
44
45
TEST1
NC
47
48
1
RX2
R26
75
BNC
INPUT2 SEL
46
1
RX3
2
3
4
5
+
J2
BNC-R-PC
COAX
VCOM
RX
VCC
3
INT0
36
NC
OCKS0
35
DIR2-OCKS0
DIF0
OCKS1
34
DIR2-OCKS1
CM1
33
CM0
32
PDN
31
D
D
DIR2-DIF0
4
TEST2
5
DIF1
6
NC
7
DIF2
XTI
30
8
IPS1
XTO
29
9
P/SN
DAUX
28
XTL0
MCKO2
27
11
XTL1
BICK
26
JP33
IBICK2
12
VIN
SDTO
25
JP35
SDTI2
U3
AK4114
DIR2-PDN
PORT2
A1-10PA-2.54DSA
1
R59
R56
R58
C
2
4
6
8
10
IBICK2 3
ILRCK2 5
SDTI2 7
51
51
51
9
DSP2
LRCK
R54
220k
R53
220k
R55
220k
24
MCKO1
DVSS
C119
10u
23
22
VOUT
DVDD
C122
0.1u
C120
10u
+
21
20
UOUT
19
BOUT
TX1
COUT
18
17
16
TX0
15
14
C118
0.1u
+
13
TVDD
10
DVSS
C
JP34
ILRCK2
D3.3V-1
B
B
DIR2-BICK
DIR2-LRCK
DIR2-SDTI2
A
A
Title
Size
A2
Date:
A
B
C
D
AKD4128A-A
Document Number
Rev
DIR2
Tuesday, August 24, 2010
E
0
Sheet
3
of
10
A
B
C
D
E
E
E
L4 47u
1
2
D3.3V-2
PORT8
GND
OUT
2
1
D3.3V-2
C29
0.1u
TORX141
+ C32
10u
+
3
C132 10u
C131 0.1u
R32 51
C33
0.1u
C130
0.47u
R51
18k
DIR3-DIF0
1
IPS0
2
NC
3
DIF0
4
TEST2
5
DIF1
6
NC
7
8
9
38
37
INT1
R
AVDD
40
39
42
41
AVSS
NC
RX0
43
44
RX1
45
TEST1
47
48
BNC
INPUT3 SEL
RX2
R33
75
D
46
1
NC
2
3
4
5
RX3
COAX
JP36
OPT
+
J3
BNC-R-PC
VCOM
RX
VCC
U4
D
INT0
36
OCKS0
35
DIR3-OCKS0
OCKS1
34
DIR3-OCKS1
CM1
33
CM0
32
PDN
31
DIF2
XTI
30
IPS1
XTO
29
P/SN
DAUX
28
AK4114
DIR3-PDN
C
C
PORT3
A1-10PA-2.54DSA
27
1
26
JP37
IBICK3
25
JP39
SDTI3
51
51
51
2
4
6
8
10
IBICK3 3
ILRCK3 5
SDTI3 7
9
DSP3
R70
220k
LRCK
BICK
SDTO
R73
R71
R72
R57
220k
R60
220k
24
MCKO1
DVSS
C127
10u
23
DVDD
22
C128
10u
+
21
VOUT
20
COUT
BOUT
TX1
UOUT
19
18
17
14
13
C129
0.1u
+
C126
0.1u
16
VIN
15
XTL1
12
TVDD
11
MCKO2
TX0
XTL0
DVSS
10
JP38
ILRCK3
D3.3V-2
B
B
DIR3-BICK
DIR3-LRCK
A
A
DIR3-SDTI3
Title
Size
A2
Date:
A
B
C
D
AKD4128A-A
Document Number
Rev
DIR3
Tuesday, August 24, 2010
E
0
Sheet
4
of
10
A
B
C
D
E
E
E
L5 47u
1
2
D3.3V-2
PORT9
GND
OUT
2
1
D3.3V-2
C34
0.1u
TORX141
+ C35
10u
+
3
C139 10u
C138 0.1u
R34 51
C51
0.1u
JP40
OPT
C137
0.47u
R74
18k
DIR4-DIF0
C
1
IPS0
2
37
INT1
38
39
R
AVDD
40
41
42
AVSS
NC
RX0
43
44
RX1
45
TEST1
NC
47
48
D
RX2
R35
75
BNC
INPUT4 SEL
46
1
RX3
2
3
4
5
+
J4
BNC-R-PC
COAX
VCOM
RX
VCC
D
INT0
36
NC
OCKS0
35
DIR4-OCKS0
3
DIF0
OCKS1
34
DIR4-OCKS1
4
TEST2
CM1
33
5
DIF1
CM0
32
6
NC
PDN
31
7
DIF2
XTI
30
8
IPS1
XTO
29
9
P/SN
DAUX
28
U5
AK4114
DIR4-PDN
C
PORT4
A1-10PA-2.54DSA
SDTO
25
JP43
SDTI4
IBICK4
ILRCK4
SDTI4
51
51
51
1
3
5
7
9
2
4
6
8
10
DSP4
R77
220k
R75
220k
R76
220k
24
DVSS
C134
10u
23
22
C135
10u
+
21
VOUT
20
19
18
17
16
15
TVDD
14
13
C136
0.1u
+
C133
0.1u
R80
R78
R79
LRCK
VIN
MCKO1
12
DVDD
JP41
IBICK4
UOUT
26
COUT
BICK
BOUT
XTL1
TX1
MCKO2
11
TX0
XTL0
27
DVSS
10
JP42
ILRCK4
D3.3V-2
B
B
DIR4-BICK
DIR4-LRCK
DIR4-SDTI4
A
A
Title
Size
A2
Date:
A
B
C
D
AKD4128A-A
Document Number
Rev
DIR4
Tuesday, August 24, 2010
E
0
Sheet
5
of
10
A
B
C
D
E
E
E
+
C60 10u
D3.3V-2
C61 0.1u
3
4
37
INT1
R
AVDD
39
40
VCOM
41
AVSS
42
43
NC
RX0
45
44
RX1
46
INT0
36
NC
OCKS0
35
DIT-OCKS0
DIF0
OCKS1
34
DIT-OCKS1
TEST2
CM1
33
5
DIF1
CM0
32
6
NC
PDN
31
U6
AK4114
7
DIF2
XTI
30
8
IPS1
XTO
29
9
P/SN
DAUX
28
10
XTL0
MCKO2
27
11
XTL1
BICK
26
12
VIN
SDTO
25
D
D3.3V-2
DIT-PDN
1
DIT-DIF2
2
TEST1
NC
RX3
DIT-DIF1
IPS0
RX2
47
48
+
DIT-DIF0
D
1
38
C62
0.47u
C55 10p
JP51
AK4128
EXT
DIT-MCKO
2
X2
22.5792MHz
C54 10p
DIT-OMCKO SEL
JP50
SDTO
JP48
DVSS
LRCK
24
23
22
VOUT
DVDD
C57
0.1u
C
JP49
OLRCK
C56
10u
R84
R93
R90
R92
+
+
C58
10u
21
20
COUT
UOUT
19
18
TX1
BOUT
17
16
DVSS
TVDD
TX0
15
14
13
C59
0.1u
MCKO1
OBICK
C
51
51
51
51
OMCLK
OBICK
OLRCK
SDTO
PORT5
A1-10PA-2.54DSA
1
3
5
7
9
D3.3V-2
2
4
6
8
10
DSP5
R91
220k
R88
220k
R87
220k
R89
220k
PORT10
TOTX141
TX(OPT)
IN
VCC
3
2
GND
1
D3.3V-2
C53
0.1u
OPT
B
B
BNC
J5
T4
BNC-R-PC DA-02F
TX(COAX)
R86
240
C52
JP44
OUTPUT SEL
JP45
DIT-OMCLK
0.1u
J8
BNC-R-PC
EXT-CLK
DIT
DSP5
EXT
DIT-OMCLK SEL
R85
150
JP46
1:1
DIT-OBICK-S
DIT-OBICK-M
R94
51
JP52
DIT-Slave
DIT-Master
EXT-CLK
DIT-OBICK SEL
JP47
DIT-OLRCK-S
DIT-OLRCK-M
DIT-Slave
DIT-Master
DIT-OLRCK SEL
DIT-SDTO
A
A
Title
Size
A2
Date:
A
B
C
D
AKD4128A-A
Document Number
Rev
DIT
Tuesday, August 24, 2010
E
0
Sheet
6
of
10
A
B
C
9
A8
Y8
11
8
A7
Y7
12
DIR1-BICK
7
A6
Y6
13
DIR1-LRCK
6
A5
Y5
14
DIR1-SDTI1
5
A4
Y4
15
DIR2-SDTI2
4
A3
Y3
16
DIR2-LRCK
3
A2
Y2
17
DIR2-BICK
2
A1
Y1
18
19
G2
GND
10
DIR1-MCKO
E
U11
74LVC541A
D
E
9
A8
Y8
11
8
A7
Y7
12
7
A6
Y6
13
AK4128-OBICK-M
6
A5
Y5
14
DIT-OBICK-M
5
A4
Y4
15
AK4128-OLRCK-M
4
A3
Y3
16
ILRCK2
DIT-OLRCK-M
3
A2
Y2
17
IBICK2
AK4128-SDTO
2
A1
Y1
18
19
G2
GND
10
1
G1
VCC
20
AK4128-MCKO
IMCLK
DIT-OMCLK
IBICK1
ILRCK1
SDTI1
SDTI2
U13
74LVC541A
DIT-MCKO
AK4128-OMCLK
DIT-OBICK-S
AK4128-OBICK-S
DIT-OLRCK-S
AK4128-OLRCK-S
D
D
DIT-SDTO
C121
0.1u
1
G1
VCC
20
9
A8
Y8
11
8
A7
Y7
12
DIR3-LRCK
7
A6
Y6
13
DIR3-SDTI3
6
A5
Y5
14
DIR4-SDTI4
5
A4
Y4
15
DIR4-LRCK
4
A3
Y3
16
3
A2
Y2
17
2
A1
Y1
18
19
G2
GND
10
1
G1
VCC
20
C141
0.1u
D3.3V-1
D3.3V-2
C
C
DIR3-BICK
B
E
DIR4-BICK
U12
74LVC541A
IBICK3
ILRCK3
SDTI3
SDTI4
ILRCK4
B
IBICK4
C140
0.1u
D3.3V-2
A
A
Title
Size
A3
Date:
A
B
C
D
AKD4128A-A
Document Number
Buffer
Tuesday, August 24, 2010
Rev
0
Sheet
E
7
of
10
A
B
C
D
D3.3V-1
K
D3.3V-1
A
D1
HSU119
R24
10k
D3.3V-1
1
L
SW1
ATE1D-2M3
AK4128-SMUTE
H
1
2
3
4
5
6
7
1A
1Y
2A
2Y
3A
3Y
GND
VCC
6A
6Y
5A
5Y
4A
4Y
14
13
12
11
10
9
8
D3.3V-1
K
A
1
3
9
7
5
3
1
R63
10k
SCL
SDA
SDA(ACK) R67
R66
0
R64
10k
R65
470
R23
10k
470
AK4128-PDN
D3.3V-1
10k
R69
10k
U10
uP-I/F
74HC14
R68
1
3
5
9
11
13
1A
2A
3A
4A
5A
6A
14
VCC
7
GND
C65
0.1u
1Y
2Y
3Y
4Y
5Y
6Y
R61
2
4
6
8
10
12
100
R62
SCL
SDA
100
E
74LS07
H
UNLOCK
C24
0.1u
2
D
L
SW2
ATE1D-2M3
AK4128-PDN
10
8
6
4
2
C22
0.1u
D3.3V-1
D2
HSU119
PORT11
A1-10PA-2.54DSA
U7
C23
0.1u
2
3
SMUTE
E
E
D
LE1
SML-210LT
D3.3V-1
1
2
R22
1k
UNLOCK
A
D4
HSU119
R28
10k
D6
HSU119
A
K
D3.3V-2
K
D3.3V-2
C
C
R30
10k
C37
0.1u
1A
1Y
2A
2Y
3A
3Y
GND
VCC
6A
6Y
5A
5Y
4A
4Y
14
13
12
11
10
9
8
D3.3V-2
C44
0.1u
DIR2-PDN
A
U9
1
2
3
4
5
6
7
C48
0.1u
K
R27
10k
H
1A
1Y
2A
2Y
3A
3Y
GND
VCC
6A
6Y
5A
5Y
4A
4Y
14
13
12
11
10
9
8
D3.3V-2
C49
0.1u
DIT-PDN
DIR4-PDN
D3.3V-2
74HC14
D5
HSU119
A
K
D3.3V-2
D3
HSU119
L
SW12
ATE1D-2M3
DIR3-PDN
U8
1
2
3
4
5
6
7
1
3
H
DIR3-PDN
2
1
L
SW10
ATE1D-2M3
DIR1-PDN
2
3
DIR1-PDN
74HC14
R29
10k
L
SW13
ATE1D-2M3
DIR4-PDN
C36
0.1u
1
3
H
H
C45
0.1u
2
2
L
SW11
ATE1D-2M3
DIR2-PDN
1
B
3
B
K
D3.3V-2
A
3
A
2
L
SW14
ATE1D-2M3
DIT-PDN
1
D7
HSU119
R31
10k
A
H
C50
0.1u
Title
Size
A3
Date:
A
B
C
D
AKD4128A-A
Document Number
LOGIC
Tuesday, August 24, 2010
Rev
0
Sheet
E
8
of
10
A
B
SW3
A6E-8104
D3.3V-1
E
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
C
D
SW4
A6E-8104
CAD0
SMSEMI
TST2
TST1
SPB
IDIF0
IDIF1
IDIF2
D3.3V-1
CAD0
SMSEMI
TST2
TST1
SPB
IDIF0
IDIF1
IDIF2
8
7
6
5
4
3
2
1
E
ODIF0
ODIF1
CM0
CM1
CM2
TDM
OBIT0
OBIT1
9
10
11
12
13
14
15
16
RP2
ODIF0
ODIF1
CM0
CM1
CM2
TDM
OBIT0
OBIT1
RP3
9
8
7
6
5
4
3
2
1
9
8
7
6
5
4
3
2
1
47K
SW5
A6E-8104
D3.3V-1
D
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
E
47k
PM1
PM2
DEM1
DEM0
SMT0
SMT1
DITHER
INAS
SW17
A6E-2104
PM1
PM2
DEM1
DEM0
SMT0
SMT1
DITHER
INAS
D3.3V-1
2
1
TST0
TST3
3
4
D
TST0
TST3
RP1
3
2
1
RP4
47k
9
8
7
6
5
4
3
2
1
47K
C
C
SW6
A6E-3104
D3.3V-1
3
2
1
4
5
6
SW7
A6E-3104
DIR1-DIF0
DIR1-OCKS0
DIR1-OCKS1
D3.3V-1
DIR1-DIF0
DIR1-OCKS0
DIR1-OCKS1
3
2
1
DIR2-DIF0
DIR2-OCKS0
DIR2-OCKS1
4
5
6
RP5
DIR2-DIF0
DIR2-OCKS0
DIR2-OCKS1
RP6
3
2
1
3
2
1
47k
47k
B
B
SW8
A6E-3104
D3.3V-2
3
2
1
4
5
6
SW9
A6E-3104
DIR3-DIF0
DIR3-OCKS0
DIR3-OCKS1
D3.3V-2
DIR3-DIF0
DIR3-OCKS0
DIR3-OCKS1
3
2
1
DIR4-DIF0
DIR4-OCKS0
DIR4-OCKS1
4
5
6
RP7
RP8
3
2
1
3
2
1
47k
SW16
A6E-5104
D3.3V-2
A
5
4
3
2
1
6
7
8
9
10
DIR4-DIF0
DIR4-OCKS0
DIR4-OCKS1
47k
DIT-DIF0
DIT-DIF1
DIT-DIF2
DIT-OCKS0
DIT-OCKS1
DIT-DIF0
DIT-DIF1
DIT-DIF2
DIT-OCKS0
DIT-OCKS1
A
RP9
5
4
3
2
1
Title
Size
A3
47k
A
Date:
B
C
D
AKD4128A-A
Document Number
SW
Tuesday, August 24, 2010
Rev
0
Sheet
E
9
of
10
A
B
C
D
E
E
E
AVDD
+5V
AVDD
C38
47u
+
IN
OUT
C39
0.1u
JP1
AVDD-SEL
AVDD
REG
2
0.1u
C40
1
3
GND
T1
LT1117-3.3
+ C46
47u
DVDD
D
D
DVDD
GND
JP2
DVDD-SEL
DVDD
TP31
GND1
REG
TP32
GND2
TP33
GND3
TP34
GND4
D3.3V-1
C
D3.3V-1
C43
47u
+
IN
OUT
C41
0.1u
JP3
D3.3V-1 SEL
D3.3V-1
REG
2
1
3
GND
T2
LT1117-3.3
C
C42
0.1u
+ C47
47u
D3.3V-2
B
B
D3.3V-2
C67
47u
+
C66
0.1u
IN
OUT
JP4
D3.3V-2 SEL
D3.3V-2
REG
2
1
3
GND
T3
LT1117-3.3
C63
0.1u
+ C64
47u
A
A
Title
Size
A3
Date:
A
B
C
D
AKD4128A-A
Document Number
Rev
0
Power Supply
Tuesday, August 24, 2010
Sheet
E
10
of
10
AK4128A-A Rev.0
部品面シルク図
AKD4128A-A Rev.0 Evaluation Board
AK4128A-A Rev.0
半田面シルク図
AK4128A-A Rev.0
部品面パターン図
AK4128A-A Rev.0
半田面パターン図