Data Sheet

[AP1151ADS]
AP1151ADS
14V Input Adjustable Voltage LDO Regulator
1. General Description
The AP1151ADS is a low dropout linear regulator with ON/OFF control, which can supply 200mA load current.
The IC is an integrated circuit with a silicon monolithic bipolar structure. The output voltage can be set from
1.3V to 14.5V by external resistors. The output capacitor is available to use a small 0.22μF ceramic capacitor.
The over current, thermal and reverse bias protections are integrated, and also the package is small and thin type.
The IC is designed for space saving requirements.
2. Features
 Available to use a small 0.22μF ceramic capacitor
 Dropout Voltage
 Output Current
VDROP=120mV at 100mA
200mA, Peak 320mA
1.27V  20mV
 High Precision reference voltage
 Programmable output voltage
 High ripple rejection ratio
1.3V to 13.5V
80dB at 1kHz
 Wide operating voltage range
 Very low quiescent current
2.1V to 14.0V
IQUT=78A at IOUT=0mA
 On/Off control (High active)
 Built-in Short circuit protection, thermal shutdown
 Built-in reverse bias over current protection
 Available very low noise application
 Very small surface mount package
SOT23-6
3. Applications
 Automotive accessory equipment
 Any Electronic Equipment
 Battery Powered Systems
 Mobile Communication
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4. Table of Contents
1.
2.
3.
4.
5.
6.
7.
General Description ........................................................................................................................................... 1
Features .............................................................................................................................................................. 1
Applications ....................................................................................................................................................... 1
Table of Contents ............................................................................................................................................... 2
Block Diagram ................................................................................................................................................... 3
Ordering Information ......................................................................................................................................... 3
Pin Configurations and Functions ...................................................................................................................... 3
■ Pin Configurations ............................................................................................................................................ 3
■ Function ............................................................................................................................................................ 4
8. Absolute Maximum Ratings .............................................................................................................................. 5
9. Recommended Operating Conditions ................................................................................................................ 5
10.
Electrical Characteristics ................................................................................................................................ 6
■ Electrical Characteristics of Ta=Tj=25C ........................................................................................................ 6
■ Electrical Characteristics of Ta=-40C~85C .................................................................................................. 7
11.
Description ..................................................................................................................................................... 8
11.1 DC Characteristics ...................................................................................................................................... 8
11.2 Temperature Characteristics ..................................................................................................................... 12
11.3 AC Characteristics .................................................................................................................................... 14
11.4 ON / OFF Transient .................................................................................................................................. 16
11.5 LOAD Transient ....................................................................................................................................... 17
11.6 Line Transient........................................................................................................................................... 18
11.7 Output Noise Characteristics .................................................................................................................... 19
11.8 ESR Stability ............................................................................................................................................ 20
11.9 Operating Region and Power Dissipation ................................................................................................ 21
11.10 ON/OFF Control ................................................................................................................................... 22
11.11 Noise Bypass ........................................................................................................................................ 22
11.12 The notes of the evaluation when output terminal is short-circuit to GND .......................................... 23
12.
Definition of term ......................................................................................................................................... 24
13.
Recommended External Circuits .................................................................................................................. 25
■External Circuit ............................................................................................................................................... 25
■Test Circuit ...................................................................................................................................................... 25
14.
Package ........................................................................................................................................................ 26
■ Outline Dimensions ........................................................................................................................................ 26
15.
Revise History .............................................................................................................................................. 27
IMPORTANT NOTICE .......................................................................................................................................... 28
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5. Block Diagram
3(Vin)
2(FB)
1(Vout)
Over Heat &
Over Current
Protection
320kΩ
Control
Circuit
500kΩ
Bandgap
Reference
4(Vcont)
5(GND)
6(Np)
Figure 1. Block Diagram
6. Ordering Information
AP1151ADS
Ta = -40 to 85°C
SOT23-6
7. Pin Configurations and Functions
NP
GND
VCONT
■ Pin Configurations
6
5
4
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2
3
VIN
VOUT
1
FB
(Top View)
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■ Function
Pin
No.
Pin
Description
Internal Equivalent Circuit
Description
Output Terminal
Vout
Vin
1
1
VOUT
FB
R2
VOUT  VFB 
2
R1
2
FB
3
VIN
Vref
The output voltage is decided by the
following formulas.
R1  R2
R1
Feedback Terminal
Connect a resistance R1 between GND, and
a resistance R2 between Vout.
Input Terminal
Vcont
4
On/Off Control Terminal
4
VCONT > 1.8V: ON
VCONT < 0.35V: OFF
320k
VCONT
500k
The pull-down resister (500k) is built-in.
5
GND
GND Terminal
Np
6
Noise Bypass Terminal
6
NP
Connect a bypass capacitor between GND.
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8. Absolute Maximum Ratings
Supply Voltage
Parameter
Symbol
VccMAX
Reverse Bias
VrevMAX
FB Pin Voltage
Np Pin Voltage
Control Pin Voltage
Junction temperature
Storage Temperature Range
VfbMAX
VNPMAX
VCONTMAX
Tj
TSTG
min
-0.4
-0.4
max
16
6
Unit
V
V
Condition
VoutTYP  2.0V
-0.4
14.5
V
2.0V < VoutTYP
-0.4
-0.4
-0.4
-55
5
5
16
150
150
V
V
V
C
C
Mounted on PCB
(Note 1)
Note 1. PD must be decreased at rate of 4.0mW/C for operation above 25C. θJA= 250C /W.
Power Dissipation
PD
-
500
mW
WARNING: The maximum ratings are the absolute limitation values with the possibility of the IC breakage.
When the operation exceeds this standard quality cannot be guaranteed.
9. Recommended Operating Conditions
Parameter
Operating Temperature Range
Operating Voltage Range
Output Voltage Range
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Symbol
min
typ
max
Unit
Ta
VOP
Vout
-40
2.1
1.3
-
85
14
13.5
C
V
V
-5-
Condition
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[AP1151ADS]
10. Electrical Characteristics
■ Electrical Characteristics of Ta=Tj=25C
The parameters with min or max values will be guaranteed at Ta=Tj=25C.
(Vin=4.0V, R1=51k, R2=68k, Vcont=1.8V, Ta=Tj=25C, unless otherwise specified.)
Parameter
Symbol
Condition
min
typ
max
Unit
Vfb
Iout = 5mA
1.250
1.270
1.290
V
FB pin Voltage
Line Regulation
Load Regulation (Note 2)
Dropout Voltage
Maximum Output Current
(Note 3)
Quiescent Current
LinReg
Vin = 5V
-
0.0
5.0
mV
LoaReg
Iout = 5mA ~ 100mA
-
11
27
mV
Iout = 5mA ~ 200mA
-
26
61
mV
Iout = 50mA
-
80
140
mV
Iout = 100mA
-
120
210
mV
Iout = 200mA
-
200
350
mV
240
320
-
mA
Vdrop
IoutMAX
When Vout drops 0.3V
Iq
Iout = 0mA
-
78
125
A
Standby Current
Istandby
Vcont = 0V
-
0.0
0.1
A
GND Pin Current
Control Terminal
Control Current
Ignd
Iout = 50mA
-
1.0
1.8
mA
Icont
Vcont = 1.8V
-
5.0
15.0
μA
Control Voltage
Vcont
Vout ON state
1.8
-
-
V
Vout OFF state
-
-
0.35
V
Vnp
-
1.27
-
V
Vo/Ta
-
35
-
Reference Value
Np Terminal Voltage
Output Voltage / Temp.
Output Noise Voltage
Ripple Rejection
ppm
/C
Vno
Cout=1.0F, Cnp=0.01F
Cfb=100pF, Iout=30mA
-
34
-
μVrms
R.R
Cout=1.0F, Cnp=0.01F
Cfb=100pF, Iout=10mA,
f=1kHz
-
80
-
dB
Cout=1.0F,
Cnp=0.001F
Cfb=100pF
tr
40
μs
Rise Time
Vcont : Pulse Wave
(100Hz)
Vcont ON  Vout95%
point
Note 2. Load Regulation changes with output voltage. The value mentioned above is guaranteed with the
condition at R1=51k, R2=68k (set at VoutTYP=3.0V).
Note 3. The maximum output current is limited by power dissipation.
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■ Electrical Characteristics of Ta=-40C~85C
The parameters with min or max values will be guaranteed at Ta=-40 ~ 85C.
(Vin=4.0V, R1=51k, R2=68k, Vcont=1.8V, Ta= -40 ~ 85C, unless otherwise specified.)
Parameter
Symbol
Condition
min
typ
max
Unit
Vfb
Iout
=
5mA
1.240
1.270
1.300
V
FB pin Voltage
Line Regulation
Load Regulation (Note 4)
Dropout Voltage
Maximum Output Current
(Note 5)
Quiescent Current
LinReg
Vin = 5V
-
0.0
8.0
mV
LoaReg
Iout = 5mA ~ 100mA
-
11
50
mV
Iout = 5mA ~ 200mA
-
26
80
mV
Iout = 50mA
-
80
180
mV
Iout = 100mA
-
120
270
mV
Iout = 200mA
-
200
390
mV
220
320
-
mA
Vdrop
IoutMAX
When Vout drops 0.3V
Iq
Iout = 0mA
-
78
150
A
Standby Current
Istandby
Vcont = 0V
-
0.0
0.5
A
GND Pin Current
Control Terminal
Control Current
Ignd
Iout = 50mA
-
1.0
2.2
mA
Vcont = 1.8V
-
5.0
15.0
μA
Vout ON state
1.8
-
-
V
Vout OFF state
-
-
0.35
V
Vnp
-
1.27
-
V
Vo/Ta
-
35
-
Control Voltage
Reference Value
Np Terminal Voltage
Output Voltage / Temp.
Output Noise Voltage
Ripple Rejection
Icont
Vcont
ppm
/C
Vno
Cout=1.0F, Cnp=0.01F
Cfb=100pF, Iout=30mA
-
34
-
μVrms
R.R
Cout=1.0F, Cnp=0.01F
Cfb=100pF, Iout=10mA,
f=1kHz
-
80
-
dB
Cout=1.0F,
Cnp=0.001F
Cfb=100pF
tr
40
μs
Rise Time
Vcont : Pulse Wave
(100Hz)
Vcont ON  Vout95%
point
Note 4. Load Regulation changes with output voltage. The value mentioned above is guaranteed with the
condition at R1=51k, R2=68k (set at VoutTYP=3.0V).
Note 5. The maximum output current is limited by power dissipation.
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11. Description
11.1 DC Characteristics
 Line Regulation
Test conditions
Vin=
VoutTYP+1.0V
3
1
Iout=5mA
11100C
Cin
1.0F
R2
Cfb
100pF
2
4
Vcont
1.8V
6
Cnp
0.001F
Cout
1.0F
R1
120k
VoutTYP= 1.3V : R1=120k, R2=2.8k
3.0V : R1=120k, R2=163.5k
5.0V : R1=120k, R2=352k
8.0V : R1=75k, R2=397k
13.0V : R1=51k, R2=470k
 Supply Current
Iout=0mA
Iout=0mA, VoutTYP=3.0V
Iin (mA)
 Iin vs Vin
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Vout=
1.3V,3.0V,5.0V,8.0V,13.0V
0
2
4
6
8
10
12 14
16
Vin (V)
 Dropout Voltage
 Short Circuit Current
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
-220
-240
14.0
12.0
Vout=3.0V
5.0V
8.0V
13.0V
10.0
Vout (V)
Vdrop (mV)
2.1V  VoutTYP
8.0
6.0
4.0
2.0
0.0
0
100
0
200
Iout (mA)
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100
200
300
400
500
Iout (mA)
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 Load Regulation
Test conditions
VoutTYP=1.3V
Vin=
VoutTYP+1.0V
3
1
11100C
Cin
1.0F
Iout=5mA
R2
2
4
Vcont
1.8V
6
Cnp
0.001F
Cfb
100pF
Cout
1.0F
R1
120k
VoutTYP= 1.3V : R1=120k, R2=2.8k
3.0V : R1=120k, R2=163.5k
5.0V : R1=120k, R2=352k
8.0V : R1=75k, R2=397k
13.0V : R1=51k, R2=470k
 Load Regulation
 Load Regulation
VoutTYP=3.0V
VoutTYP=5.0V
 Load Regulation
 Load Regulation
VoutTYP=8.0V
VoutTYP=13.0V
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Ignd (mA)
 Quiescent Current
Test conditions
Vin=
VoutTYP+1.0V
10
9
8
7
6
5
4
3
2
1
0
3
1
11100C
Cin
1.0F
Vcont
1.8V
100
R2
2
4
0
Iout=5mA
6
Cnp
0.001F
Cfb
100pF
Cout
1.0F
R1
120k
VoutTYP= 1.3V : R1=120k, R2=2.8k
3.0V : R1=120k, R2=163.5k
5.0V : R1=120k, R2=352k
8.0V : R1=75k, R2=397k
13.0V : R1=51k, R2=470k
200
Iout (mA)
 Standby Current (Off state)
Vcont=0V
1.E-06
Istanby (A)
1.E-07
1.E-08
1.E-09
1.E-10
1.E-11
0
2
4
6
8
10
12 14
16
Vin (V)
 Control Current
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 Control Current,ON/OFF Point
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 Vin vs Vout Regulation Point
Test conditions
2.1V  VoutTYP
Vin=
VoutTYP+1.0V
3
1
11100C
Cin
1.0F
Iout=5mA
R2
2
4
Vcont
1.8V
6
Cnp
0.001F
Cfb
100pF
Cout
1.0F
R1
120k
VoutTYP= 1.3V : R1=120k, R2=2.8k
3.0V : R1=120k, R2=163.5k
5.0V : R1=120k, R2=352k
8.0V : R1=75k, R2=397k
13.0V : R1=51k, R2=470k
 Reverse Bias Current
VoutTYP=1.3V
VoutTYP=1.3V
Vout (V)
 Vin vs Vout Regulation Point
1.34
1.32
1.30
1.28
1.26
1.24
1.22
1.20
1.18
1.16
1.14
Iout=0,50,100,150,200mA
1.5
1.6
1.7
1.8
1.9
2.0
Vin (V)
 Reverse Bias Current
Test conditions (Reverse Bias Current)
VoutTYP=3.0V, 5.0V, 8.0V, 13.0V
Vin=0V
Irev
3
1
11100C
Cin
1.0F
R2
2
4
Vcont
0V
6
Cnp
0.001F
Cfb
100pF
Cout
1.0F
Vrev
R1
120k
VoutTYP= 1.3V : R1=120k, R2=2.8k
3.0V : R1=120k, R2=163.5k
5.0V : R1=120k, R2=352k
8.0V : R1=75k, R2=397k
13.0V : R1=51k, R2=470k
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11.2 Temperature Characteristics
 Vref
Test conditions
VrefTYP=1.27V
Vin=
VoutTYP+1.0V
3
1
Iout=5mA
11100C
Cin
1.0F
R2
Cfb
100pF
2
4
6
Vcont
1.8V
Cnp
0.001F
Cout
1.0F
R1
120k
VoutTYP=3.0V : R2=163.5k
 Vout
 Quiescent Current
VoutTYP=3.0V
16
Iout=200mA
Iout=100mA
Iout=50mA
14
Iq(mA)
12
10
8
6
4
2
0
-40 -20
0
20
40
60
80
100
T a(°C)
 Dropout Voltage
 Supply Current
2.1V  VoutTYP
Iout=0mA
350
Iout=200mA
Iout=100mA
Iout=50mA
Vdrop(mV)
300
250
200
150
100
50
0
-40 -20
0
20
40
60
80
100
T a(°C)
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 Short Circuit Current
Vout=VoutTYP×90%, Ta=Tj
Vout=0V, Ta=Tj
360
400
340
380
320
360
Ishort(mA)
Iout MAX(mA)
 Maximum Output Current
300
280
340
320
260
300
240
280
220
260
-40 -20
0
20
40
60
80 100
-40 -20
0
Ta(℃)
20
40
60
80 100
60
80
100
60
80
100
Ta(℃)
 Load Regulation
 Line Regulation
VoutTYP=3.0V, Ta=Tj
10
LinReg(mV)
LoaReg(mV)
0
-10
-20
Iout=50mA
-30
Iout=100mA
-40
Iout=200mA
-50
-40 -20
0
20
40
60
80
10
8
6
4
2
0
-2
-4
-6
-8
-10
-40 -20
100
0
20
40
T a(℃)
T a(℃)
 ON/OFF Point
Vcont(V)
 Control Current
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Vout_ON
Vout_OFF
-40 -20
0
20
40
T a（℃）
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11.3 AC Characteristics
・Ripple Rejection
The ripple rejection (R.R) characteristic depends on the characteristic and the capacitance of the capacitor connected
at the output side. Also it depends on the output voltage. The R.R characteristic at 50kHz or more varies greatly with
the capacitor on the output side and PCB pattern. If necessary, please check stability during operation.
 Test conditions
 Cout=1.0F: Ceramic (C), Tantalum (T)
Vripple
Vin(DC)=VoutTYP+1.5V
200mVp-p
3
Cout=1F (T)
1
Iout=5mA
11100C
f=100Hz 1MHz
R2
2
4
6
Vcont
1.8V
Cnp
0.01F
Cfb
100pF
Cout
1.0F
R1
120k
Cout=1F (C)
VoutTYP=3.0V: R2=163.5k
 Cout=0.22F, 1.0F, 2.2F, 10F: Ceramic
 Cnp=0.001F, 0.01F, 0.1F
Cout=0.22F
Cout=1.0F
Cout=2.2F
Cnp=0.001F
Cnp=0.01F
Cnp=0.1F
Cout=10F
 R.R vs. Iout: Frequency=1kHz
 R.R vs. Low Vin: Frequency=1kHz
0
Ripple Rejection (dB)
Ripple Rejection (dB)
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
50
100
150
200
Iout=50mA
Iout=1mA
0.0
Iout (mA)
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Iout=200mA
Iout=150mA
Iout=100mA
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0.2
0.4
0.6
0.8
1.0
Vin-Vout(T yp) (V)
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 Cfb = 100pF, 1000pF, 0.01F, 0.1F
 Test conditions
VoutTYP=1.3V
Vripple
Vin(DC)=VoutTYP+1.5V
200mVp-p
3
1
11100C
f=100Hz 1MHz
2
4
Cfb=1000pF
Cfb=100pF
Vcont
1.8V
6
Cfb
100pF
Cout
1.0F
R1
Cnp
0.01F
VoutTYP= 1.3V :
R1=120k,
R2=2.8k
3.0V :
R1=120k,
R2=163.5k
5.0V :
R1=120k,
R2=352k
8.0V :
R1=75k,
R2=397k
13.0V : R1=51k, R2=470k
Cfb=0.01F
Cfb=0.1F
 VoutTYP=1.3V
 VoutTYP=5.0V
 VoutTYP=8.0V
 VoutTYP=13V
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Iout=5mA
R2
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[AP1151ADS]
11.4 ON / OFF Transient
The rise time of the regulator depends on Cout and Cnp. The fall time depends on Cout.
 Test conditions
Vcont
Vin=
VoutTYP+1.0V
Voltage
3
Cin
1.0F
Rise Time
1
11100C
2
4
Vout×95%
Vout
Vcont=0V2V
(f=100Hz)
Iout=30mA
R2
6
Cnp
0.001F
Cout
1.0F
R1
120k
VoutTYP=3.0V: R2=163.5k
Time
 Cout=1.0F, 2.2F, 4.7F
 Cout=1.0F, 2.2F, 4.7F
 Cnp=0.001F, 0.01F, 0.1F
 Cnp=0.001F, 0.01F, 0.1F
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Cfb
100pF
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[AP1151ADS]
11.5 LOAD Transient
No load voltage change can be greatly improved by delivering small load current to ground. Increase the load side
capacitor when the load change is fast or when there is a large current change. In addition, at no load, supplying small
load current to ground can reduce the voltage change.
 Test conditions
Vin=
VoutTYP+1.0V
3
1
11100C
Cin
1.0F
R2
2
4
Vcont
1.8V
6
Cnp
0.001F
Cfb
100pF
Iout
ONOFF
Cout
1.0F
R1
120k
VoutTYP=3.0V: R2=163.5k
 Iout=0→30mA, 0→100mA, 0→200mA
 Iout=30→0mA, 100→0mA, 200→0mA
 Iout=5→30mA, 5→100mA, 5→200mA
 Iout=30→5mA, 100→5mA, 200→5mA
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[AP1151ADS]
 Cout=1.0F, 2.2F, 4.7F: Iout=0→30mA
11.6
 Cout=1.0F, 2.2F, 4.7F: Iout=30→0mA
Line Transient
Test conditions
Vin=
VoutTYP+1.0V or +2.0V
3
1
11100C
Iout=30mA
R2
2
4
Vcont
1.8V
6
Cnp
0.001F
Cfb
100pF
Cout
1.0F
R1
120k
VoutTYP=3.0V: R2=163.5k
 Cout=1.0F, 2.2F, 4.7F
015000867-E-00
 Cnp=0.001F, 0.01F, 0.1F
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[AP1151ADS]
11.7 Output Noise Characteristics
Increase Cnp to decrease the noise. The recommended Cnp capacitance is 0.01F  0.1F. The amount of noise
increases with the higher output voltages.
 Test conditions
 Vout vs. Noise
Noise (uVrms)
R1=51k, R2=1.2k  470k
Vin=
VoutTYP+1.0V
100
90
80
70
60
50
40
30
20
10
0
3
1
Iout=30mA
11100C
Cin
1.0F
R2
Cfb
100pF
2
4
6
Vcont
1.8V
Cnp
0.01F
Cout
1.0F
R1
120k
BPF=400Hz 80kHz
VoutTYP=3.0V: R2=163.5k
1 2 3 4 5 6 7 8 9 10 11 12 13
Vout(T yp) (V)
 Cnp vs. Noise
 Iout vs. Noise
300
Ceramic
Cout=0.22uF
60
Cout=1.0uF
55
Cout=2.2uF
50
200
150
T antalum
100
Noise (uVrms)
Noise (uVrms)
250
Cout=0.22uF
Cout=1.0uF
Cout=2.2uF
45
Ceramic
40
35
30
50
T antalum
25
0
1p
10p
100p 1000p 0.01u
0
0.1u
50
100
150
Cnp (F)
 Iout vs. Noise (Cout: Ceramic)
Cfb=100pF, 1000pF, 0.01F, 0.1F
Cfb=100pF, 1000pF, 0.01F, 0.1F
100
Cfb=100pF
Cfb=1000pF
80
Cfb=0.01uF
Cfb=0.1uF
Noise (uVrms)
Noise (uVrms)
 Cnp vs. Noise (Cout: Ceramic)
60
40
20
0
1000p
0.01u
Cfb=100pF
60
55
50
45
40
35
30
25
20
15
10
Cfb=1000pF
Cfb=0.01uF
Cfb=0.1uF
0
0.1u
50
100
150
200
Iout (mA)
Cnp (F)
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200
Iout (mA)
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[AP1151ADS]
11.8 ESR Stability
Linear regulators require input and output capacitors in order to maintain the regulator's loop stability. If a 0.22F or
larger capacitor is connected to the output side, the IC provides stable operation at any voltage (1.3V  VoutTYP 
14.5V). But due to the parts are uneven, please enlarge the capacitance as much as possible. With larger capacity,
the output noise decreases more. In addition, the response to the load change, etc. can be improved. Enlarging the
capacity won’t damage the IC.
Moreover, increase the Cout capacitance when using the IC in the low current region and low voltage. Otherwise,
the IC oscillates.
The equivalent series resistance (ESR) of the output capacitor must be in the stable operation area. However, it is
recommended to use as large a value of capacitance as is practical. ESR values vary widely between ceramic and
tantalum capacitors. However, tantalum capacitors are assumed to provide more ESR damping resistance, which
provides greater circuit stability. This implies that a higher level of circuit stability can be obtained by using tantalum
capacitors when compared to ceramic capacitors with similar values.
A recommended value of the application is as follows.
Cin=Cout0.22F
Vin
Vout
AP1151ADS
R2
 510k 
Cin
 0.22 F
Cnp
 0.001 F
Cfb
 100p F
Cout
 0.22  F
R1
 120k 
GND
Figure 2. Recommended circuit
However, above recommended value does not satisfy some condition. Please refer to Figure 3. Select the Cout
capacitance according to the condition. If the fast load transient response is necessary, increase the Cout capacitance
as much as possible.
Vout=3.0V
Vout=5.0V
100
100
100
10
10
10
Vout=8.0V
100
100
Stable area
Cout=0.1F
1
0.1
Stable area
Cout=0.1F
1
0.1
ESR( )
Stable area
Cout=0.1F
10
Stable area
Cout=0.1F
1
0.1
Unstable area
Unstable area
10
ESR( )
ESR( )
ESR( )
Unstable area
1
Vout=13.0V
ESR( )
Vout=1.3V  2.0V
Stable area
Cout=0.1F
1
0.1
0.1
Unstable area
0.01
0.01
03
100
Iout (mA)
200
0.01
0
100
Iout (mA)
200
0.01
0
100
Iout (mA)
200
0.01
0
100
Iout (mA)
200
0
100
Iout (mA)
All stable: Cout0.22F
Figure 3. Output Voltage, Output Current vs. Stable Operation Area
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200
[AP1151ADS]
Figure 3 shows stable operation area with a ceramic capacitor of 0.1F (excluding the low voltage and the low
current region).If the capacitance is not increased in the low voltage, low current region, stable operation may not be
achieved. Please select the best output capacitor according to the voltage and current used. The stability of the
regulator improves if a large output side capacitor is used (the stable operation area extends.) Please use as large a
capacitance as is practical.
For evaluation
Kyocera: CM05B104K10AB, CM05B224K10AB, CM105B104K16A, CM105B224K16A, CM21B225K10A
Murata: GRM36B104K10, GRM42B104K10, GRM39B104K25, GRM39B224K10, GRM39B105K6.3
Generally, a ceramic capacitor has both a temperature characteristic and a voltage characteristic. Please consider
both characteristics when selecting the part. The B curves are the recommend characteristics.
Figure 4. Ceramic Capacitance vs. Voltage, Temperature
11.9 Operating Region and Power Dissipation
The power dissipation of the device is dependent on the junction temperature. Therefore, the package dissipation is
assumed to be an internal limitation. The package itself does not have enough heat radiation characteristic due to the
small size. Heat runs away by mounting IC on PCB. This value changes by the material, copper pattern etc. of PCB.
The overheating protection operates when there is a lot of loss inside the regulator (Ambient temperature high, heat
radiation bad, etc.). The output current and the output voltage will drop when the protection circuit operates. When
joint temperature (Tj) reaches the set temperature, IC stops the operation. However, operation begins at once when
joint temperature (Tj) decreases.
・The thermal resistance when mounted on PCB
The chip joint temperature during operation is shown by Tj=JA×Pd+Ta. Joint part temperature (Tj) of AP1151ADS
is limited around 150C with the overheating protection circuit. Pd is the value when the overheating protection
circuit starts operation.
When you assume the ambient temperature to be 25C,
150=JA  Pd(W)+25
JA  Pd=125
JA=125/Pd (C /W)
Figure 5. Example of mounting substrate
PCB Material: Two-layer glass epoxy substrate (x=30mm,y=30mm,t=1.0mm,Copper pattern thickness 35um)
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[AP1151ADS]
・Method of obtaining Pd easily
Connect output terminal to GND (short circuited), and measure the input current by increasing the input voltage
gradually up to 10V. The input current will reach the maximum output current, but will decrease soon according to
the chip temperature rising, and will finally enter the state of thermal equilibrium (natural air cooling).The input
current and the input voltage of this state will be used to calculate the Pd. When the device is mounted, mostly
achieve 500mW or more.
Pd(mW)  Vin (V)  Iin (mA)
The maximum output current at the highest operating temperature will be Iout  DPd  (Vinmax-Vout). Please use
the device at low temperature with better radiation. The lower temperature provides better quality.
In the case that the power, Vin Ishort (Short Circuit Current), becomes more than the maximum rating of its power
dissipation in a moment, there is a possibility that the IC is destroyed before internal thermal protection works.
Procedure (When mounted on PCB).
Pd(mW)
2
Pd
D Pd
5
3
4
0
25
50
75
Ta (℃)
100
150
1.Find Pd (VinIin when the output is short-circuited).
2. Plot Pd against 25C.
3. Connect Pd to the point corresponding to the 150C
with a straight line.
4. Pull a vertical line from the maximum operating
temperature in your design (e.g., 75C).
5. Read the value of Pd against the point at which
the vertical line intersects the derating
curve(DPd).
6.DPd(Vinmax-Vout)=Iout (at 75C)
Figure 6. Obtaining Pd
11.10
ON/OFF Control
It is recommended to turn the regulator off when the circuit following the regulator is not operating. A design with
small electric power loss can be implemented. Because the control current is small, it is possible to control it directly
by CMOS logic.
Table 1.
Control Terminal Voltage (Vcont)
Vcont > 1.8V
Vcont < 0.35V
11.11
ON/OFF State
ON
OFF
Noise Bypass
The noise characteristics depend on the capacitance on the Np terminal.A standard value is Cnp=0.001F. Increase
Cnp in a design with important output noise requirements. The IC will not be damaged even the capacitor value is
increased. The on/off switching speed changes depending on the Np terminal capacitance. The switching speed
slows when the capacitance is large.
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11.12
The notes of the evaluation when output terminal is short-circuit to GND
By the resonance phenomenon by Cout (C ingredient) and the short circuit line (L ingredient), which are attached to
an output terminal, an output terminal changes with minus potential. In order that Parasitism Tr arises within Bip IC,
and a latch rise phenomenon may occur within IC when the worst if it goes into an output terminal's minus side, it
results in damage by fire (white smoke) and breakage of a package. (f0 = 1 / 2 (L C))
The above-mentioned resonance phenomenon appears notably in a ceramic capacitor with the small ESR value, etc.
A resonance phenomenon can be reduced by connecting resistance (around 2ohms or more) in series with a short
circuit line. Thereby, the latch rise phenomenon within IC can be prevented.
Generally, when using tantalum or large electrolysis capacitor, the influence of resonance phenomenon can be
reduced due to the large ESR (2ohms or more)
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12. Definition of term
 Relating Characteristic
Each characteristic will be measured in a short period not to be influenced by joint temperature (Tj).
・Output voltage (Vout)
The output voltage is specified with Vin= VoutTYP+1V and Iout=5mA
・Output current (Iout)
Output current, which can be used continuously (It is the range where overheating protection of the IC does
not operate.)
・Maximum output current (IoutMAX)
The rated output current is specified under the condition where the output voltage drops 90% by increasing
the output current, compared to the value specified at Vin=VoutTYP+1V.
・Dropout voltage (Vdrop)
It is an I/O voltage difference when the circuit stops the stable operation by decreasing the input voltage.
It is measured when the output voltage drops 100mV from its nominal value by decreasing the input voltage
gradually.
・Line Regulation (LinReg)
It is the fluctuations of the output voltage value when the input voltage is changed.
・Load Regulation (LoaReg)
It is the fluctuations of the output voltage value when the input voltage is assumed to be Vout TYP +1V, and
the load current is changed.
・Ripple Rejection (R.R)
Ripple rejection is the ability of the regulator to attenuate the ripple content of the input voltage at the output.
It is measured with the condition of Vin=Vout+1.5V. Ripple rejection is the ratio of the ripple content
between the output vs. input and is expressed in dB.
・Standby current (Istandby)
It is an input current, which flows to the control terminal, when the IC is turned off.
 Relating Protection Circuit
・Over Current Protection
It is a function to protect the IC by limiting the output current when excessive current flows to IC, such as the
output is connected to GND, etc.
・Thermal Protection
It protects the IC not to exceed the permissible power consumption of the package in case of large power loss
inside the regulator.
The output is turned off when the chip reaches around 150C, but it turns on again when the temperature of the
chip decreases.
・Reverse Voltage Protection
Reverse voltage protection prevents damage due to the output voltage being higher than the input voltage. This
fault condition can occur when the output capacitor remains charged and the input is reduced to zero, or when an
external voltage higher than the input voltage is applied to the output side. Generally, a LDO regulator has
a diode in the input direction from an output. If an input falls from an output in an input-GND short circuit
etc. and this diode turns on, current will flow for an input terminal from an output terminal. In the case of
excessive current, IC may break. In order to prevent this, it is necessary to connect an Schottky Diode etc.
outside. This product is equipped with reverse bias over-current prevention, and excessive current does not
flow in to IC. Therefore, no need to connect diode outside.
Vin
Vout
Figure 7.
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13. Recommended External Circuits
■External Circuit
R1
R2
Vout
120k
Cfb
100pF
3
2
Vin
FB
1
Vout  Vfb 
Vout
R1  R2
R1
(VfbTYP = 1.27V)
Vin
Cin
+
Cout
1.0F
Vcont
GND
Np
4
5
6
1.3V  VoutTYP  13.0V
+
1.0F
Cnp
Vcont
0.001F
Figure 8. External Circuit
Note 6. In the actual application, either ceramic or tantalum capacitor can be used for Cin and Cout. Please
set feedback resistor R1, R2 current larger than 10A. The current is fixed withVfb/R1.Please fix R2 value
smaller than 510k. In case of high output voltage, please adjust R1 value in order to make R2 value smaller
than 510k.Recommended capacitor value for Cfb: Cfb=100pF
■Test Circuit
R1
R2
Cfb
100pF
3
2
Vin
FB
1
Iin
A
Vin
+
Vout
Cin
Cout
1.0F
Vcont
GND
Np
4
5
6
Icont
A
+
Iout
Vout
V
1.0F
Cnp
Vcont
0.001F
Figure 9. Test Circuit (R1=51k, R2=68k (VoutTYP=3.0V))
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[AP1151ADS]
14. Package
■ Outline Dimensions
Index
Mark
Lot No.
6
4
1
1.6 0.1
+0.2
R00
xxx
3
0.4 +
 0.1
0.95
0.95
015000867-E-00
+0.10
0.125 0.05
0 ~0.15
1.1 +
 0.1
 0.2
2.9 +
+0.2
0.4 +
 0.2
2.8 0.3
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[AP1151ADS]
15. Revise History
Date
(YY/MM/DD)
15/01/21
015000867-E-00
Revision
Page
Contents
00
-
First edition
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[AP1151ADS]
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