GS8161FZ18/32/36BD 18Mb Flow Through Synchronous NBT SRAM 165-Bump BGA Commercial Temp Industrial Temp Functional Description The GS8161FZ18/32/36BD is configured to operate in Flow Through mode. The GS8161FZ18/32/36BDis implemented with GSI's high performance CMOS technology and is available in JEDECstandard 165-bump FP-BGA package. Ne w De sig The GS8161FZ18/32/36BD is an 18Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable, ZZ and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. n— Di sco nt inu ed Pr od u • Flow Through mode • NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization • Fully pin-compatible with flow through NtRAM™, NoBL™ and ZBT™ SRAMs • IEEE 1149.1 JTAG-compatible Boundary Scan • 2.5 V or 3.3 V +10%/–10% core power supply • LBO pin for Linear or Interleave Burst mode • Pin-compatible with 2M, 4M, and 8M devices • Byte write operation (9-bit Bytes) • 3 chip enable signals for easy depth expansion • ZZ pin for automatic power-down • JEDEC-standard 165-bump FP-BGA package • RoHS-compliant 165-bump BGA package available ct Features 5.5 ns–7.5 ns 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O Parameter Synopsis -6.5 -7.5 Unit tKQ tCycle 5.5 5.5 6.5 6.5 7.5 7.5 ns ns Curr (x18) Curr (x32/x36) 225 255 200 220 185 205 mA mA me nd ed for -5.5 No t Re co m Flow Through 2-1-1-1 Rev: 1.00a 2/2008 1/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS8161FZ18/32/36BD 2 3 4 5 6 7 8 9 10 11 A NC A E1 BB NC E3 CKE ADV A A A A B NC A E2 NC BA CK W G A A NC B C NC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPA C D NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA D E NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA E F NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA F G NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA G H NC MCH NC VDD VSS VSS VSS VDD NC NC ZZ H J DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC J K DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC K L DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC L M DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC M N DQPB NC P NC NC R LBO NC me nd ed for Ne w n— Di sco nt inu ed Pr od u ct 1 De sig 165 Bump BGA—x18 Commom I/O—Top View (Package D) VSS NC NC NC VSS VDDQ NC NC N A A TDI A1 TDO A A A NC P A A TMS A0 TCK A A A A R Re co m VDDQ No t 11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch Rev: 1.00a 2/2008 2/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS8161FZ18/32/36BD 165 Bump BGA—x32 Common I/O—Top View (Package D) 2 3 4 5 6 7 8 9 10 11 A NC A E1 BC BB E3 CKE ADV A A NC B NC A E2 BD BA CK W G A A C NC NC VDDQ VSS VSS VSS VSS VSS VDDQ D DQC DQC VDDQ VDD VSS VSS VSS VDD E DQC DQC VDDQ VDD VSS VSS VSS F DQC DQC VDDQ VDD VSS VSS G DQC DQC VDDQ VDD VSS H NC MCH NC VDD J DQD DQD VDDQ K DQD DQD L DQD M A B NC NC C VDDQ DQB DQB D VDD VDDQ DQB DQB E VSS VDD VDDQ DQB DQB F VSS VSS VDD VDDQ DQB DQB G VSS VSS VSS VDD NC NC ZZ H VDD VSS VSS VSS VDD VDDQ DQA DQA J VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA K DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA L DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA M N NC NC P NC NC R LBO NC me nd ed for Ne w n— Di sco nt inu ed Pr od u NC De sig ct 1 VSS NC NC NC VSS VDDQ NC NC N A A TDI A1 TDO A A A NC P A A TMS A0 TCK A A A A R Re co m VDDQ No t 11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch Rev: 1.00a 2/2008 3/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS8161FZ18/32/36BD 165 Bump BGA—x36 Common I/O—Top View (Package D) 2 3 4 5 6 7 8 9 10 11 A NC A E1 BC BB E3 CKE ADV A A NC B NC A E2 BD BA CK W G A A C DQPC NC VDDQ VSS VSS VSS VSS VSS VDDQ D DQC DQC VDDQ VDD VSS VSS VSS VDD E DQC DQC VDDQ VDD VSS VSS VSS F DQC DQC VDDQ VDD VSS VSS G DQC DQC VDDQ VDD VSS H NC MCH NC VDD J DQD DQD VDDQ K DQD DQD L DQD M A B NC DQPB C VDDQ DQB DQB D VDD VDDQ DQB DQB E VSS VDD VDDQ DQB DQB F VSS VSS VDD VDDQ DQB DQB G VSS VSS VSS VDD NC NC ZZ H VDD VSS VSS VSS VDD VDDQ DQA DQA J VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA K DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA L DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA M N DQPD NC P NC NC R LBO NC me nd ed for Ne w n— Di sco nt inu ed Pr od u NC De sig ct 1 VSS NC NC NC VSS VDDQ NC DQPA N A A TDI A1 TDO A A A NC P A A TMS A0 TCK A A A A R Re co m VDDQ No t 11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch Rev: 1.00a 2/2008 4/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS8161FZ18/32/36BD GS8161FZ18/32/36BD 165-Bump BGA Pin Description Type Description A 0, A 1 I Address field LSBs and Address Counter Preset Inputs A I Address Inputs DQA DQB DQC DQD I/O BA , BB , BC , BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low NC — No Connect CK I CKE I Clock Input Buffer Enable; active low W I Write Enable; active low E1 I E3 I E2 I G I ADV I ZZ I LBO I TMS I TDI I TDO O TCK I MCH — VDD I VSS I VDDQ I n— Di sco nt inu ed Pr od u ct Symbol Data Input and Output pins Clock Input Signal; active high Chip Enable; active low Chip Enable; active low Chip Enable; active high Output Enable; active low De sig Burst address counter advance enable; active high Sleep mode control; active high me nd ed for Ne w Linear Burst Order mode; active low Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Must Connect High Core power supply I/O and Core Ground No t Re co m Output driver power supply Rev: 1.00a 2/2008 5/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology Rev: 1.00a 2/2008 W Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 6/28 G CKE CK E3 E2 E1 BD BC BB BA ADV No LBO t A0–An K K Q K SA1 SA0 Control Logic Data Coherency Read, Write and Match Register 1 Write Address K 18 SA1’ SA0’ Ne w Register 2 Write Drivers Sense Amps K K D Q K NC Write Data Register 1 Write Data Register 2 n— Di sco nt inu ed Pr od u Memory Array De sig Write Address Burst Counter me nd ed for Re co m K D ct DQa–DQn GS8161FZ18/32/36BD GS8161FZ18/32/36B NBT SRAM Functional Block Diagram © 2006, GSI Technology GS8161FZ18/32/36BD Functional Details ct Clocking Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation. n— Di sco nt inu ed Pr od u Flow Through Mode Read and Write Operations Flow Through NBT SRAMs are equipped with rising-edge-triggered input registers that capture data-in, address, and control input signals, but do not have a data output register like the one found on pipelined NBT SRAMs. Once a read command and an associated read address is clocked into the RAM, the read operation proceeds and, if the Output Enable pin is driven active low, culminates with the read data appearing on the RAM output pins, even if no additional clocks are sent to the RAM. A write operation in a Flow Through NBT SRAM begins when a write command and write address are clocked into the RAM. Next, data-in for that write address must be applied to the input pins and held for capture by the very next rising edge of clock. A write protocol like the one used on Flow Through NBT SRAMs—the capture of the write address and write command on one clock and the capture of the write data-in on the next clock—is often described as a Late Write protocol. No t Re co m me nd ed for Ne w De sig It is the combination of the Flow Through read protocol and the Late Write write protocol that allows the Flow Through NBT SRAM to achieve seamless back-to-back, read-write-read transitions on a bi-directional data bus without requiring the user to insert dead cycles to prevent bus contention during the transition from read to write or write to read. Rev: 1.00a 2/2008 7/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS8161FZ18/32/36BD Synchronous Truth Table Type Address CK CKE ADV W Bx E1 E2 E3 G ZZ External L-H L Read Cycle, Continue Burst B Next L-H L NOP/Read, Begin Burst R External L-H L Dummy Read, Continue Burst B Next L-H L Write Cycle, Begin Burst W External L-H L Write Cycle, Continue Burst B Next L-H L Write Abort, Continue Burst B Next L-H L Deselect Cycle, Power Down D None L-H L Deselect Cycle, Power Down D None L-H L Deselect Cycle, Power Down D None L-H L Deselect Cycle D None L-H L Deselect Cycle, Continue D None L-H None X Current L-H Clock Edge Ignore, Stall Ne w Sleep Mode L H X L H L L DQ L Q ct R Notes H X X X X X L L Q 1,10 L H X L H L H L High-Z 2 H X X X X X H L High-Z 1,2,10 L L L L H L X L D 3 H X L X X X X L D 1,3,10 H X H X X X X L High-Z 1,2,3,10 L X X H X X X L High-Z L X X X X H X L High-Z L X X X L X X L High-Z L L H L H L X L High-Z De sig Read Cycle, Begin Burst n— Di sco nt inu ed Pr od u Operation L H X X X X X X L High-Z X X X X X X X X H High-Z H X X X X X X X L - 1 1 4 No t Re co m me nd ed for Notes: 1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect cycle is executed first. 2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active so no write operation is performed. 3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write cycles. 4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus will remain in High Z. 5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals are Low 6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge. 7. Wait states can be inserted by setting CKE high. 8. This device contains circuitry that ensures all outputs are in High Z during power-up. 9. A 2-bit burst counter is incorporated. 10. The address counter is incriminated for all Burst continue cycles. Rev: 1.00a 2/2008 8/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS8161FZ18/32/36BD Flow Through Mode Data I/O State Diagram R B R High Z (Data In) Data Out (Q Valid) n— Di sco nt inu ed Pr od u W ct B W D D W R High Z B Key Ne w Input Command Code ƒ Transition Current State (n) me nd ed for Re co m Command n+1 ƒ Current State Notes: 1. The Hold command (CKE Low) is not shown because it prevents any state change. 2. W, R, B, and D represent input command codes as indicated in the Truth Tables. Next State (n+1) n Clock (CK) De sig D n+2 ƒ n+3 ƒ ƒ Next State No t Current State and Next State Definition for: Pipeline and Flow through Read Write Control State Diagram Rev: 1.00a 2/2008 9/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS8161FZ18/32/36BD n— Di sco nt inu ed Pr od u ct Burst Cycles Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode. Burst Order The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables below for details. Mode Pin Functions Mode Name Pin Name Burst Order Control LBO Power Down Control ZZ State Function L Linear Burst H Interleaved Burst L or NC Active H Standby, IDD = ISB Ne w De sig Note: There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above table. Linear Burst Sequence Interleaved Burst Sequence me nd ed for Burst Counter Sequences A[1:0] A[1:0] A[1:0] A[1:0] 00 01 2nd address 01 10 3rd address 10 11 4th address 11 00 Re co m 1st address A[1:0] A[1:0] A[1:0] A[1:0] 10 11 1st address 00 01 10 11 11 00 2nd address 01 00 11 10 00 01 3rd address 10 11 00 01 01 10 4th address 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. No t Note: The burst counter wraps to initial state on the 5th clock. Rev: 1.00a 2/2008 BPR 1999.05.18 10/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS8161FZ18/32/36BD ct Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. n— Di sco nt inu ed Pr od u Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. Sleep Mode Timing Diagram tKH tKC tKL CK tZZR tZZS tZZH No t Re co m me nd ed for Ne w De sig ZZ Rev: 1.00a 2/2008 11/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS8161FZ18/32/36BD Absolute Maximum Ratings (All voltages reference to VSS) Description Value Unit VDD Voltage on VDD Pins –0.5 to 4.6 V VDDQ Voltage in VDDQ Pins –0.5 to VDD VI/O Voltage on I/O Pins VIN Voltage on Other Input Pins IIN Input Current on Any Pin IOUT Output Current on Any I/O Pin PD Package Power Dissipation TSTG Storage Temperature TBIAS Temperature Under Bias n— Di sco nt inu ed Pr od u ct Symbol V –0.5 to VDDQ +0.5 (≤ 4.6 V max.) V –0.5 to VDD +0.5 (≤ 4.6 V max.) V +/–20 mA +/–20 mA 1.5 W –55 to 125 o –55 to 125 o C C De sig Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Parameter Symbol Min. Typ. Max. Unit 3.3 V Supply Voltage Ne w Power Supply Voltage Ranges VDD3 3.0 3.3 3.6 V VDD2 2.3 2.5 2.7 V me nd ed for 2.5 V Supply Voltage 3.3 V VDDQ I/O Supply Voltage VDDQ3 3.0 3.3 VDD V 2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 VDD V Notes No t Re co m Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.00a 2/2008 12/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS8161FZ18/32/36BD Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 2.0 — VDD + 0.3 V 1 VDD Input Low Voltage VIL –0.3 — 0.8 V 1 VDDQ I/O Input High Voltage VIHQ 2.0 — VDD + 0.3 V 1,3 VDDQ I/O Input Low Voltage VILQ –0.3 — 0.8 V 1,3 n— Di sco nt inu ed Pr od u Parameter ct VDDQ3 Range Logic Levels Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Parameter Symbol Typ. Max. Unit Notes VDD Input High Voltage VIH 0.6*VDD — VDD + 0.3 V 1 VDD Input Low Voltage VIL –0.3 — 0.3*VDD V 1 VDDQ I/O Input High Voltage VIHQ 0.6*VDD — VDD + 0.3 V 1,3 VDDQ I/O Input Low Voltage –0.3 — 0.3*VDD V 1,3 De sig Min. Ne w VDDQ2 Range Logic Levels VILQ me nd ed for Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Recommended Operating Temperatures Symbol Min. Typ. Max. Unit Notes Ambient Temperature (Commercial Range Versions) TA 0 25 70 °C 2 Ambient Temperature (Industrial Range Versions) TA –40 25 85 °C 2 Re co m Parameter No t Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.00a 2/2008 13/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS8161FZ18/32/36BD Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 20% tKC VDD + 2.0 V VSS n— Di sco nt inu ed Pr od u 50% ct 50% VDD VSS – 2.0 V 20% tKC VIL Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF AC Test Conditions Conditions Input high level VDD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDD/2 Output load me nd ed for Output reference level Ne w Parameter De sig Note: These parameters are sample tested. VDDQ/2 Fig. 1 Output Load 1 DQ No t Re co m Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. 50Ω 30pF* VDDQ/2 * Distributed Test Jig Capacitance Rev: 1.00a 2/2008 14/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS8161FZ18/32/36BD DC Electrical Characteristics Symbol Test Conditions Min Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA ZZ Input Current IIN1 VDD ≥ VIN ≥ VIH 0 V ≤ VIN ≤ VIH Output Leakage Current IOL Output High Voltage VOH2 Output High Voltage VOH3 Output Low Voltage VOL ct Parameter 1 uA 100 uA Output Disable, VOUT = 0 to VDD –1 uA 1 uA IOH = –8 mA, VDDQ = 2.375 V 1.7 V — IOH = –8 mA, VDDQ = 3.135 V 2.4 V — IOL = 8 mA — 0.4 V No t Re co m me nd ed for Ne w De sig n— Di sco nt inu ed Pr od u –1 uA –1 uA Rev: 1.00a 2/2008 15/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS8161FZ18/32/36BD Operating Currents -5.5 -7.5 Symbol –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 215 15 190 15 200 15 mA Test Conditions Operating Current Device Selected; All other inputs ≥VIH or ≤ VIL Output open (x32/ x36) Flow Through IDD IDDQ 235 20 245 20 205 15 (x18) Flow Through IDD IDDQ 215 10 225 10 190 10 200 10 175 10 185 10 mA Standby Current ZZ ≥ VDD – 0.2 V — Flow Through ISB 40 50 40 50 40 50 mA Deselect Current Device Deselected; All other inputs ≥ VIH or ≤ VIL — Flow Through IDD 60 65 50 55 50 55 mA ct Parameter n— Di sco nt inu ed Pr od u Mode -6.5 0 to 70°C Unit Notes: 1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation. 2. All parameters listed are worst case scenario. Parameter Symbol Clock Cycle Time tKC -5.5 -6.5 -7.5 Min Max Min Max Min Max 5.5 — 6.5 — 7.5 — Unit ns tKQ — 5.5 — 6.5 — 7.5 ns tKQX 2.0 — 2.0 — 2.0 — ns tLZ1 2.0 — 2.0 — 2.0 — ns Setup time tS 1.5 — 1.5 — 1.5 — ns Hold time tH 0.5 — 0.5 — 0.5 — ns Clock HIGH Time tKH 1.3 — 1.3 — 1.5 — ns Clock LOW Time tKL 1.5 — 1.5 — 1.7 — ns Clock to Output in High-Z tHZ1 1.5 2.5 1.5 3.0 1.5 3.0 ns G to Output Valid tOE — 2.5 — 3.0 — 3.8 ns me nd ed for Clock to Output in Low-Z Ne w Clock to Output Valid Clock to Output Invalid Flow Through De sig AC Electrical Characteristics 0 — 0 — 0 — ns G to output in High-Z 1 — 2.5 — 3.0 — 3.8 ns 2 5 — 5 — 5 — ns ZZ hold time tZZH 2 1 — 1 — 1 — ns ZZ recovery tZZR 20 — 20 — 20 — ns Re co m G to output in Low-Z tOLZ1 No t ZZ setup time tOHZ tZZS Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.00a 2/2008 16/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS8161FZ18/32/36BD Flow Through Mode Timing (NBT) Write A Write B Write B+1 Read C Cont Read D Write E Read F Write G tKL tKC ct tKH tH tS CKE tH tS E* tH tS ADV tH tS W tH tS Bn tH A0–An B C tH tS D(A) D(B) D(B+1) Ne w DQ D tKQ tLZ G E F tKQX De sig tS A n— Di sco nt inu ed Pr od u CK tHZ Q(C) Q(D) G tKQ tLZ D(E) tKQX Q(F) D(G) tOLZ tOE tOHZ JTAG Port Operation me nd ed for *Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1 Re co m Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. No t Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. Rev: 1.00a 2/2008 17/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS8161FZ18/32/36BD JTAG Pin Descriptions Pin Name I/O Description TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS Test Mode Select In The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. In The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. Test Data In TDO Test Data Out n— Di sco nt inu ed Pr od u TDI ct Pin Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. JTAG Port Registers Ne w De sig Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. me nd ed for Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible. No t Re co m Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.00a 2/2008 18/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS8161FZ18/32/36BD · · · · · · · n— Di sco nt inu ed Pr od u · ct JTAG TAP Block Diagram Boundary Scan Register · · 1 · 2 1 0 0 M* 0 Bypass Register Instruction Register TDI TDO ID Code Register · · ·· 2 1 0 De sig 31 30 29 Control Signals TMS Test Access Port (TAP) Controller Ne w TCK * For the value of M, see the BSDL file, which is available at by contacting us at [email protected]. Bit # No t Re co m ID Register Contents GSI Technology JEDEC Vendor ID Code Not Used Presence Register me nd ed for Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X 1 X X Rev: 1.00a 2/2008 X X X X X X X X X X X X X X X X X 0 19/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 0 0 1 1 0 1 1 0 0 1 © 2006, GSI Technology GS8161FZ18/32/36BD Tap Controller Instruction Set n— Di sco nt inu ed Pr od u ct Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. JTAG Tap Controller State Diagram Test Logic Reset 1 0 0 Run Test Idle 1 Select DR 1 Select IR 0 0 1 De sig Shift DR Ne w 1 me nd ed for 1 0 Shift IR 0 1 1 Exit1 DR 0 Exit1 IR 0 0 Pause DR 1 Exit2 DR 1 Update DR 1 Capture IR 0 0 Pause IR 1 Exit2 IR 0 1 0 0 Update IR 1 0 No t Re co m 1 Capture DR 0 1 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Rev: 1.00a 2/2008 20/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS8161FZ18/32/36BD n— Di sco nt inu ed Pr od u ct SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins. Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state. De sig Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. Ne w IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. me nd ed for SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU No t Re co m These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.00a 2/2008 21/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS8161FZ18/32/36BD JTAG TAP Instruction Set Summary Code Description Notes EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1 IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2 SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. 1 RFU 011 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 SAMPLE/ PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 1 GSI 101 GSI private instruction. 1 RFU 110 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. n— Di sco nt inu ed Pr od u ct Instruction 1 No t Re co m me nd ed for Ne w De sig BYPASS 111 Places Bypass Register between TDI and TDO. Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. 1 Rev: 1.00a 2/2008 22/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS8161FZ18/32/36BD JTAG Port Recommended Operating Conditions and DC Characteristics (2.5/3.3 V Version) Symbol Min. Max. Unit Notes 2.5 V Test Port Input High Voltage VIHJ2 0.6 * VDD2 VDD2 +0.3 V 1 2.5 V Test Port Input High Voltage VIHJ2 0.6 * VDD2 VDD2 +0.3 V 1 3.3 V Test Port Input High Voltage VIHJ3 2.0 VDD3 +0.3 V 1 VILJ3 –0.3 0.8 V 1 IINHJ –300 1 uA 2 IINLJ –1 100 uA 3 IOLJ –1 1 uA 4 VOHJ 1.7 — V 5, 6 VOLJ — 0.4 V 5, 7 VOHJC VDDQ – 100 mV — V 5, 8 VOLJC — 100 mV V 5, 9 n— Di sco nt inu ed Pr od u ct Parameter 3.3 V Test Port Input Low Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output High Voltage Test Port Output Low Voltage Test Port Output CMOS High Test Port Output CMOS Low me nd ed for Ne w De sig Notes: 1. Input Under/overshoot voltage must be –2 V < Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ ≤ VIN ≤ VDDn 3. 0 V ≤ VIN ≤ VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = –4 mA 7. IOLJ = + 4 mA 8. IOHJC = –100 uA 9. IOLJC = +100 uA JTAG Port AC Test Conditions Parameter Input high level Input low level Re co m Input slew rate Conditions VDD – 0.2 V JTAG Port AC Test Load DQ 0.2 V 50Ω 1 V/ns Input reference level VDDQ/2 Output reference level VDDQ/2 30pF* VDDQ/2 * Distributed Test Jig Capacitance No t Notes: 1. Include scope and jig capacitance. 2. Test conditions as shown unless otherwise noted. Rev: 1.00a 2/2008 23/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS8161FZ18/32/36BD JTAG Port Timing Diagram tTKC tTKH tTKL ct TCK TDI tTH tTS TMS tTKQ TDO tTH tTS JTAG Port AC Electrical Characteristics De sig Parallel SRAM input n— Di sco nt inu ed Pr od u tTH tTS Symbol Min Max Unit TCK Cycle Time tTKC 50 — ns TCK Low to TDO Valid tTKQ — 20 ns TCK Low Pulse Width TDI & TMS Set Up Time tTKH 20 — ns tTKL 20 — ns tTS 10 — ns tTH 10 — ns Re co m TDI & TMS Hold Time me nd ed for TCK High Pulse Width Ne w Parameter No t Boundary Scan (BSDL Files) For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications Engineering Department at: [email protected]. Rev: 1.00a 2/2008 24/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS8161FZ18/32/36BD Package Dimensions—165-Bump FPBGA (Package D) A1 BOTTOM Ø0.10M C Ø0.25M C A B Ø0.40~0.60 A1 ct TOP 1 2 3 4 5 6 7 8 9 10 14. 1.0 1.0 10. 13±0.0 0.20(4 0.36~0.4 1.40 SEATING B 1.0 A B C D E F G H J K L M N P R me nd ed for 0.15 C Ne w A De sig 15±0.0 1.0 A B C D E F G H J K L M N P R n— Di sco nt inu ed Pr od u 11 10 9 8 7 6 5 4 3 2 No t Re co m C Rev: 1.00a 2/2008 25/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS8161FZ18/32/36BD TA3 5.5 C 165 BGA 6.5 C 165 BGA 7.5 C 165 BGA 5.5 C 165 BGA 6.5 C 165 BGA 7.5 C 165 BGA 5.5 C 165 BGA 6.5 C 165 BGA 7.5 C 165 BGA 5.5 I 165 BGA 6.5 I 165 BGA 7.5 I 165 BGA 5.5 I 165 BGA 6.5 I Flow Through 165 BGA 7.5 I GS8161FZ36BD-5.5I Flow Through 165 BGA 5.5 I 512K x 36 GS8161FZ36BD-6.5I Flow Through 165 BGA 6.5 I 512K x 36 GS8161FZ36BD-7.5I Flow Through 165 BGA 7.5 I 1M x 18 GS8161FZ18BGD-5.5 Flow Through RoHS-compliant 165 BGA 5.5 C 1M x 18 GS8161FZ18BGD-6.5 Flow Through RoHS-compliant 165 BGA 6.5 C 1M x 18 GS8161FZ18BGD-7.5 Flow Through RoHS-compliant 165 BGA 7.5 C 512K x 32 GS8161FZ32BGD-5.5 Flow Through RoHS-compliant 165 BGA 5.5 C 512K x 32 GS8161FZ32BGD-6.5 Flow Through RoHS-compliant 165 BGA 6.5 C 512K x 32 GS8161FZ32BGD-7.5 Flow Through RoHS-compliant 165 BGA 7.5 C 512K x 36 GS8161FZ36BGD-5.5 Flow Through RoHS-compliant 165 BGA 5.5 C 512K x 36 GS8161FZ36BGD-6.5 Flow Through RoHS-compliant 165 BGA 6.5 C 512K x 36 GS8161FZ36BGD-7.5 Flow Through RoHS-compliant 165 BGA 7.5 C 1M x 18 GS8161FZ18BGD-5.5I Flow Through RoHS-compliant 165 BGA 5.5 I Part Number1 Type Package 1M x 18 GS8161FZ18BD-5.5 Flow Through 165 BGA 1M x 18 GS8161FZ18BD-6.5 Flow Through 1M x 18 GS8161FZ18BD-7.5 Flow Through 512K x 32 GS8161FZ32BD-5.5 Flow Through 512K x 32 GS8161FZ32BD-6.5 Flow Through 512K x 32 GS8161FZ32BD-7.5 Flow Through 512K x 36 GS8161FZ36BD-5.5 Flow Through 512K x 36 GS8161FZ36BD-6.5 Flow Through 512K x 36 GS8161FZ36BD-7.5 Flow Through 1M x 18 GS8161FZ18BD-5.5I Flow Through 1M x 18 GS8161FZ18BD-6.5I Flow Through 1M x 18 GS8161FZ18BD-7.5I Flow Through 512K x 32 GS8161FZ32BD-5.5I Flow Through 512K x 32 GS8161FZ32BD-6.5I Flow Through 512K x 32 GS8161FZ32BD-7.5I 512K x 36 me nd ed for Ne w De sig n— Di sco nt inu ed Pr od u Org ct Speed2 (ns) Re co m Ordering Information for GSI Synchronous Burst RAMs No t 1M x 18 GS8161FZ18BGD-6.5I Flow Through RoHS-compliant 165 BGA 6.5 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.00a 2/2008 26/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS8161FZ18/32/36BD Ordering Information for GSI Synchronous Burst RAMs (Continued) Part Number1 Type Package Speed2 (ns) TA3 1M x 18 GS8161FZ18BGD-7.5I Flow Through RoHS-compliant 165 BGA 7.5 I 512K x 32 GS8161FZ32BGD-5.5I Flow Through RoHS-compliant 165 BGA 5.5 I 512K x 32 GS8161FZ32BGD-6.5I Flow Through RoHS-compliant 165 BGA 6.5 I 512K x 32 GS8161FZ32BGD-7.5I Flow Through RoHS-compliant 165 BGA 7.5 I 512K x 36 GS8161FZ36BGD-5.5I Flow Through RoHS-compliant 165 BGA 5.5 I 512K x 36 GS8161FZ36BGD-6.5I Flow Through RoHS-compliant 165 BGA 6.5 I n— Di sco nt inu ed Pr od u ct Org No t Re co m me nd ed for Ne w De sig 512K x 36 GS8161FZ36BGD-7.5I Flow Through RoHS-compliant 165 BGA 7.5 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.00a 2/2008 27/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology GS8161FZ18/32/36BD 18Mb Sync SRAM Data Sheet Revision History Types of Changes Format or Content Page;Revisions;Reason • Creation of new datasheet • Rev1.00a: updated coplanarity for 165 BGA mechanical, removed Status column from Ordering Information table. ct DS/DateRev. Code: Old; New No t Re co m me nd ed for Ne w De sig n— Di sco nt inu ed Pr od u 8161FZxxB_r1 Rev: 1.00a 2/2008 28/28 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2006, GSI Technology