GS832018/32/36T-250/225/200/166/150/133 250 MHz–133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O 2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 100-Pin TQFP Commercial Temp Industrial Temp Features Functional Description ct Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. De sig Applications The GS832018/32/36T is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. n— Di sco nt inu ed Pr od u • FT pin for user-configurable flow through or pipeline operation • Single Cycle Deselect (SCD) operation • 2.5 V or 3.3 V +10%/–10% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 100-lead TQFP package • RoHS-compliant 100-lead TQFP package available cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Ne w Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. me nd ed for Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst Core and Interface Voltages The GS832018/32/36T operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible. Re co m Parameter Synopsis tKQ tCycle Curr (x18) Curr (x32/x36) tKQ Flow tCycle Through (x18) Curr 2-1-1-1 Curr (x32/x36) No t Pipeline 3-1-1-1 Rev: 1.03b 12/2007 -250 -225 -200 -166 -150 -133 Unit 2.5 2.7 3.0 3.5 3.8 4.0 ns 4.0 4.4 5.0 6.0 6.6 7.5 ns 285 350 265 320 245 295 220 210 185 mA 260 240 215 mA 6.5 6.5 205 235 7.0 7.0 195 225 7.5 7.5 185 210 8.0 8.5 8.5 ns 8.0 8.5 8.5 ns 175 165 155 mA 200 190 175 mA 1/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832018/32/36T-250/225/200/166/150/133 n— Di sco nt inu ed Pr od u ct A A E1 E2 NC NC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS832018 100-Pin TQFP Pinout NC NC NC Rev: 1.03b 12/2007 Ne w me nd ed for A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC A A A A1 A0 NC A VSS VDD A A A A A A A A A Re co LBO m A No t VSS NC NC DQB DQB VSS VDDQ DQB DQB FT VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC De sig VDDQ 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 2M x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 2/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832018/32/36T-250/225/200/166/150/133 n— Di sco nt inu ed Pr od u ct A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS832032 100-Pin TQFP Pinout NC DQC DQC VDDQ Rev: 1.03b 12/2007 Ne w me nd ed for NC DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA NC A A A A1 A0 NC A VSS VDD A A A A A A A A A Re co LBO m A No t FT VDD NC VSS DQD DQD VDDQ VSS DQD3 DQD DQD DQD VSS VDDQ DQD DQD NC De sig VSS DQC DQC DQC DQC VSS VDDQ DQC DQC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 1M x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 3/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832018/32/36T-250/225/200/166/150/133 n— Di sco nt inu ed Pr od u ct A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS832036 100-Pin TQFP Pinout DQPC DQC DQC VDDQ Rev: 1.03b 12/2007 Ne w me nd ed for DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA A A A A1 A0 NC A VSS VDD A A A A A A A A A Re co LBO m A No t FT VDD NC VSS DQD DQD VDDQ VSS DQD3 DQD DQD DQD VSS VDDQ DQD DQD DQPD De sig VSS DQC DQC DQC DQC VSS VDDQ DQC DQC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 1M x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 4/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832018/32/36T-250/225/200/166/150/133 TQFP Pin Description Type Description A 0, A 1 I Address field LSBs and Address Counter preset Inputs A I Address Inputs DQA DQB1 DQC DQD I/O n— Di sco nt inu ed Pr od u ct Symbol Data Input and Output pins NC No Connect BW I Byte Write—Writes all enabled bytes; active low BA , BB I Byte Write Enable for DQA, DQB Data I/Os; active low BC , BD I Byte Write Enable for DQC, DQD Data I/Os; active low CK I Clock Input Signal; active high GW I Global Write Enable—Writes all bytes; active low E 1, E 3 I Chip Enable; active low E2 I G I ADV I ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep Mode control; active high FT I LBO I VDD I VSS I VDDQ I Chip Enable; active high De sig Output Enable; active low me nd ed for Ne w Burst address counter advance enable; active low Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground No t Re co m Output driver power supply Rev: 1.03b 12/2007 5/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832018/32/36T-250/225/200/166/150/133 GS832018/32/36 Block Diagram Register D Q A0 A0 D0 Q0 A1 D1 Q1 Counter Load n— Di sco nt inu ed Pr od u A1 ct A0–An A LBO ADV Memory Array CK ADSC ADSP Q Register GW BW BA D Q Register D D 36 Q BB 36 D Ne w D Q Register BD Q Register D De sig Q BC Q Register D Register 4 Register me nd ed for D Q Register E1 E2 E3 D Q Register FT G 1 Power Down No t ZZ Q Re co m D Control DQx1–DQx9 Note: Only x36 version shown for simplicity. Rev: 1.03b 12/2007 6/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832018/32/36T-250/225/200/166/150/133 Mode Pin Functions Burst Order Control LBO Output Register Control FT Power Down Control ZZ Single/Dual Cycle Deselect Control SCD FLXDrive Output Impedance Control ZQ 9th Bit Enable PE State Function L Linear Burst H Interleaved Burst L Flow Through ct Pin Name n— Di sco nt inu ed Pr od u Mode Name H or NC Pipeline L or NC Active H Standby, IDD = ISB L Dual Cycle Deselect H or NC Single Cycle Deselect L High Drive (Low Impedance) H or NC Low Drive (High Impedance) L or NC Activate DQPx I/Os (x18/x3672 mode) H Deactivate DQPx I/Os (x16/x3272 mode) Burst Counter Sequences Linear Burst Sequence De sig Note: There is a are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so thosethis input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Interleaved Burst Sequence 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 4th address 11 00 01 A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 01 3rd address 10 11 00 01 10 4th address 11 10 01 00 me nd ed for 1st address Ne w A[1:0] A[1:0] A[1:0] A[1:0] Note: The burst counter wraps to initial state on the 5th clock. Re co m Note: The burst counter wraps to initial state on the 5th clock. No t BPR 1999.05.18 Rev: 1.03b 12/2007 7/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832018/32/36T-250/225/200/166/150/133 Function GW BW BA BB BC BD Notes Read H H X X X X 1 Read H L H H H H 1 Write byte a H L L H H H ct Write byte b H L H Write byte c H L H Write byte d H L H Write all bytes H L L n— Di sco nt inu ed Pr od u Byte Write Truth Table 2, 3 L H H 2, 3 H L H 2, 3, 4 H H L 2, 3, 4 L L L 2, 3, 4 No t Re co m me nd ed for Ne w De sig Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x32 and x36 versions. Rev: 1.03b 12/2007 8/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832018/32/36T-250/225/200/166/150/133 Operation Address Used State Diagram Key5 E1 E2 Deselect Cycle, Power Down None X H X Deselect Cycle, Power Down None X Deselect Cycle, Power Down None X Read Cycle, Begin Burst External R Read Cycle, Begin Burst External R Write Cycle, Begin Burst External W Read Cycle, Continue Burst Next CR Read Cycle, Continue Burst Next CR Write Cycle, Continue Burst Next CW Write Cycle, Continue Burst Next CW Read Cycle, Suspend Burst Current Read Cycle, Suspend Burst Current Write Cycle, Suspend Burst Current n— Di sco nt inu ed Pr od u Synchronous Truth Table X L ADV ct ADSP ADSC X W3 DQ4 X High-Z L F L X X X High-Z L F H L X X High-Z L T L X X X Q L T H L X F Q L T H L X T D X X H H L F Q H X X H L F Q X X H H L T D H X X H L T D X X H H H F Q H X X H H F Q X X H H H T D No t Re co m me nd ed for Ne w De sig Write Cycle, Suspend Burst Current H X X H H T D Notes: 1. X = Don’t Care, H = High, L = Low 2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.03b 12/2007 9/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832018/32/36T-250/225/200/166/150/133 Simplified State Diagram ct X W R R R First Write CR De sig CW Ne w W First Read X CR R R X Burst Write me nd ed for Simple Burst Synchronous Operation Simple Synchronous Operation W X n— Di sco nt inu ed Pr od u Deselect Burst Read X CR CW CR No t Re co m Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low. Rev: 1.03b 12/2007 10/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832018/32/36T-250/225/200/166/150/133 Simplified State Diagram with G ct X W R W X n— Di sco nt inu ed Pr od u Deselect R R First Write CR First Read CW X CR W Burst Write me nd ed for X Ne w De sig CW W R CR CW R W Burst Read X CW CR No t Re co m Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.03b 12/2007 11/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832018/32/36T-250/225/200/166/150/133 Absolute Maximum Ratings (All voltages reference to VSS) Description Value Unit VDD Voltage on VDD Pins –0.5 to 4.6 V VDDQ Voltage in VDDQ Pins –0.5 to 4.6 VI/O Voltage on I/O Pins VIN Voltage on Other Input Pins IIN Input Current on Any Pin IOUT Output Current on Any I/O Pin PD Package Power Dissipation TSTG Storage Temperature TBIAS Temperature Under Bias n— Di sco nt inu ed Pr od u Note: ct Symbol V –0.5 to VDDQ +0.5 (≤ 4.6 V max.) V –0.5 to VDD +0.5 (≤ 4.6 V max.) V +/–20 mA +/–20 mA 1.5 W –55 to 125 o –55 to 125 o C C De sig Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Parameter Symbol Min. Typ. Max. Unit 3.3 V Supply Voltage Ne w Power Supply Voltage Ranges VDD3 3.0 3.3 3.6 V VDD2 2.3 2.5 2.7 V me nd ed for 2.5 V Supply Voltage 3.3 V VDDQ I/O Supply Voltage VDDQ3 3.0 3.3 3.6 V 2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 2.7 V Notes No t Re co m Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.03b 12/2007 12/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832018/32/36T-250/225/200/166/150/133 Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 2.0 — VDD + 0.3 V 1 VDD Input Low Voltage VIL –0.3 — 0.8 V 1 VDDQ I/O Input High Voltage VIHQ 2.0 — VDDQ + 0.3 V 1,3 VDDQ I/O Input Low Voltage VILQ –0.3 — 0.8 V 1,3 n— Di sco nt inu ed Pr od u Parameter ct VDDQ3 Range Logic Levels Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Parameter Symbol Typ. Max. Unit Notes VDD Input High Voltage VIH 0.6*VDD — VDD + 0.3 V 1 VDD Input Low Voltage VIL –0.3 — 0.3*VDD V 1 VDDQ I/O Input High Voltage VIHQ 0.6*VDD — VDDQ + 0.3 V 1,3 VDDQ I/O Input Low Voltage –0.3 — 0.3*VDD V 1,3 De sig Min. Ne w VDDQ2 Range Logic Levels VILQ me nd ed for Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Recommended Operating Temperatures Symbol Min. Typ. Max. Unit Notes Ambient Temperature (Commercial Range Versions) TA 0 25 70 °C 2 Ambient Temperature (Industrial Range Versions) TA –40 25 85 °C 2 Re co m Parameter No t Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.03b 12/2007 13/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832018/32/36T-250/225/200/166/150/133 Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 20% tKC VDD + 2.0 V VSS n— Di sco nt inu ed Pr od u 50% ct 50% VDD VSS – 2.0 V 20% tKC VIL Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF AC Test Conditions Conditions Input high level VDD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Output reference level Output load me nd ed for Input reference level Ne w Parameter De sig Note: These parameters are sample tested. VDDQ/2 VDDQ/2 Fig. 1 Output Load 1 DQ No t Re co m Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. 50Ω 30pF* VDDQ/2 * Distributed Test Jig Capacitance Rev: 1.03b 12/2007 14/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832018/32/36T-250/225/200/166/150/133 DC Electrical Characteristics Symbol Test Conditions Min Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –2 uA 2 uA ZZInput Current IIN1 VDD ≥ VIN ≥ VIH 0 V ≤ VIN ≤ VIH FTInput Current IIN2 Output Leakage Current (x36/x72) IOL Output Leakage Current (x18) IOL Output High Voltage VOH2 Output High Voltage VOH3 Output Low Voltage VOL ct Parameter 1 uA 100 uA VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL –100 uA –1 uA 1 uA 1 uA Output Disable, VOUT = 0 to VDD –1 uA 1 uA Output Disable, VOUT = 0 to VDD –1 uA 1 uA IOH = –8 mA, VDDQ = 2.375 V 1.7 V — IOH = –8 mA, VDDQ = 3.135 V 2.4 V — IOL = 8 mA — 0.4 V No t Re co m me nd ed for Ne w De sig n— Di sco nt inu ed Pr od u –1 uA –1 uA Rev: 1.03b 12/2007 15/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Rev: 1.03b 12/2007 IL Pipeline Mode IDD Symbol 300 0 to 70°C — Device Deselected; All other inputs ≥ VIH or ≤ VIL Deselect Current Flow Through IDD 85 IDD Pipeline 100 115 100 ISB ISB Flow Through 60 80 190 15 260 25 210 25 295 45 –40 to 85°C 85 90 60 60 170 15 225 20 190 20 255 40 0 to 70°C 105 80 80 180 15 245 20 200 20 275 40 –40 to 85°C -200 85 60 60 160 15 200 20 180 20 225 35 0 to 70°C 100 80 80 170 15 220 20 190 20 245 35 –40 to 85°C -166 85 60 60 150 15 190 20 170 20 210 30 0 to 70°C 100 80 80 160 15 210 20 180 20 230 30 –40 to 85°C -150 80 60 60 140 15 170 15 160 15 190 25 0 to 70°C 85 95 80 80 150 15 190 15 170 15 210 25 –40 to 85°C -133 n 80 95 80 95 75 90 70 100 — Di sco nt inu ed Pr od uc t D60 e 80 95 s110 ig 60 180 15 200 15 Ne80 w 60 80 DD 240 25 280 25 DDQ Pipeline DD DDQ 200 25 220 25 Notes: 1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation. 2. All parameters listed are worst case scenario. — ZZ ≥ VDD – 0.2 V IH DDQ DD DDQ 275 45 0 to 70°C -225 320 50 –40 to 85°C -250 I 50 Re (x32/ cx36) I Flow 210 Device Selected; o m I Through 25 All other inputs m ≥V or ≤ V en II 26025 Pipeline Output open de (x18) Id Flow fo19015r I Through No t Test Conditions Standby Current Operating Current Parameter Operating Currents mA mA mA mA mA mA mA mA Unit Preliminary GS832018/32/36T-250/225/200/166/150/133 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 16/25 © 2003, GSI Technology GS832018/32/36T-250/225/200/166/150/133 AC Electrical Characteristics -225 -200 -166 -150 -133 Min Max Min Max Min Max Min Max Min tKC 4.0 — 4.4 — 5.0 — 6.0 — ct Clock Cycle Time -250 Clock to Output Valid tKQ — 2.5 — Clock to Output Invalid tKQX 1.5 — 1.5 1 1.5 — 1.5 Setup time tS 1.2 — 1.3 Hold time tH 0.2 — 0.3 Clock Cycle Time tKC 6.5 — 7.0 Clock to Output Valid tKQ — 6.5 — Clock to Output Invalid tKQX 3.0 — 3.0 Clock to Output in Low-Z tLZ1 3.0 — 3.0 Setup time tS 1.5 — 1.5 Hold time tH 0.5 — 0.5 Clock HIGH Time tKH 1.3 — 1.3 Clock LOW Time tKL 1.5 — Clock to Output in High-Z tHZ1 1.5 2.5 G to Output Valid tOE — G to output in Low-Z tOLZ1 0 G to output in High-Z tOHZ1 ZZ setup time ZZ hold time ZZ recovery n— Di sco nt inu ed Pr od u tLZ 6.7 Max Unit Min Max — 7.5 — ns 2.7 — 3.0 — 3.5 — 3.8 — 4.0 ns — 1.5 — 1.5 — 1.5 — 1.5 — ns — 1.5 — 1.5 — 1.5 — 1.5 — ns — 1.4 — 1.5 — 1.5 — 1.5 — ns — 0.4 — 0.5 — 0.5 — 0.5 — ns — 7.5 — 8.0 — 8.5 — 8.5 — ns 7.0 — 7.5 — 8.0 — 8.5 — 8.5 ns — 3.0 — 3.0 — 3.0 — 3.0 — ns — 3.0 — 3.0 — 3.0 — 3.0 — ns — 1.5 — 1.5 — 1.5 — 1.5 — ns — 0.5 — 0.5 — 0.5 — 0.5 — ns — 1.3 — 1.3 — 1.5 — 1.7 — ns De sig Clock to Output in Low-Z 1.5 — 1.5 — 1.5 — 1.7 — 2 — ns 1.5 2.7 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 ns 2.5 — 2.7 — 3.0 — 3.5 — 3.8 — 4.0 ns — 0 — 0 — 0 — 0 — 0 — ns — 2.5 — 2.7 — 3.0 — 3.0 — 3.0 — 3.0 ns tZZS2 5 — 5 — 5 — 5 — 5 — 5 — ns tZZH2 1 — 1 — 1 — 1 — 1 — 1 — ns tZZR 20 — 20 — 20 — 20 — 20 — 20 — ns Ne w Flow Through Symbol me nd ed for Pipeline Parameter No t Re co m Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.03b 12/2007 17/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832018/32/36T-250/225/200/166/150/133 Pipeline Mode Timing Cont Cont Deselect Write B Single Read Read C+1 Read C+2 Read C+3 Cont Single Write tKL tKH tKC CK ADSP tS tH Deselect Burst Read ADSC initiated read ADSC tS tH ADV tS tH A0–An Read C ct Read A n— Di sco nt inu ed Pr od u Begin A B tS GW tS C tH De sig BW tH tS tS tH E1 tH E2 tS tH E3 Re co m G me nd ed for tS E1 masks ADSP E2 and E3 only sampled with ADSP and ADSC tOE tS tOHZ Q(A) tKQ tH D(B) tKQX tLZ tHZ Q(C) Q(C+1) Q(C+2) Q(C+3) No t DQa–DQd Deselected with E1 Ne w Ba–Bd Rev: 1.03b 12/2007 18/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832018/32/36T-250/225/200/166/150/133 Flow Through Mode Timing Begin Read A Cont Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont Deselect tKL tKC ct tKH n— Di sco nt inu ed Pr od u CK ADSP Fixed High tS tH tS tH initiated read ADSC ADSC tS tH ADV tS tH A0–An A B C tS tH tS tH BW Ba–Bd tS E1 tS tH E2 tS tH E3 E2 and E3 only sampled with ADSC Re co m G tH tS tOE tOHZ Q(A) D(B) tKQ tLZ tHZ tKQX Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C) No t DQa–DQd Deselected with E1 me nd ed for tH Ne w tS tH De sig GW Rev: 1.03b 12/2007 19/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832018/32/36T-250/225/200/166/150/133 Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time. n— Di sco nt inu ed Pr od u ct Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. Sleep Mode Timing Diagram tKH tKC tKL CK Setup Hold ADSP De sig ADSC tZZS No t Re co m me nd ed for Ne w ZZ tZZR tZZH Rev: 1.03b 12/2007 20/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832018/32/36T-250/225/200/166/150/133 TQFP Package Drawing (Package T) A1 Standoff 0.05 0.10 0.15 A2 Body Thickness 1.35 1.40 1.45 b Lead Width 0.20 0.30 0.40 c Lead Thickness 0.09 — 0.20 D Terminal Dimension 21.9 22.0 22.1 D1 Package Body 19.9 20.0 20.1 E Terminal Dimension 15.9 16.0 16.1 E1 Package Body 13.9 14.0 14.1 e Lead Pitch — 0.65 — L Foot Length 0.45 0.60 0.75 L1 Lead Length — 1.00 — Y Coplanarity θ Lead Angle n— Di sco nt inu ed Pr od u Min. Nom. Max e b A2 Y De sig A1 0.10 0° — 7° E1 E No t Re co m me nd ed for Ne w Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. D D1 Description c Pin 1 Symbol L1 θ ct L Rev: 1.03b 12/2007 21/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832018/32/36T-250/225/200/166/150/133 Ordering Information for GSI Synchronous Burst RAMs TA3 250/6.5 C TQFP 225/7 C Pipeline/Flow Through TQFP 200/7.5 C GS832018T-166 Pipeline/Flow Through TQFP 166/8 C 2M x 18 GS832018T-150 Pipeline/Flow Through TQFP 150/8.5 C 2M x 18 GS832018T-133 Pipeline/Flow Through TQFP 133/8.5 C 1M x 32 GS832032T-250 Pipeline/Flow Through TQFP 250/6.5 C 1M x 32 GS832032T-225 Pipeline/Flow Through TQFP 225/7 C 1M x 32 GS832032T-200 Pipeline/Flow Through TQFP 200/7.5 C 1M x 32 GS832032T-166 Pipeline/Flow Through TQFP 166/8 C 1M x 32 GS832032T-150 Pipeline/Flow Through TQFP 150/8.5 C 1M x 32 GS832032T-133 Pipeline/Flow Through TQFP 133/8.5 C 1M x 36 GS832036T-250 Pipeline/Flow Through TQFP 250/6.5 C 1M x 36 GS832036T-225 Pipeline/Flow Through TQFP 225/7 C 1M x 36 GS832036T-200 Pipeline/Flow Through TQFP 200/7.5 C 1M x 36 GS832036T-166 Pipeline/Flow Through TQFP 166/8 C 1M x 36 GS832036T-150 Pipeline/Flow Through TQFP 150/8.5 C 1M x 36 GS832036T-133 Pipeline/Flow Through TQFP 133/8.5 C 2M x 18 GS832018T-250I Pipeline/Flow Through TQFP 250/6.5 I 2M x 18 GS832018T-225I Pipeline/Flow Through TQFP 225/7 I 2M x 18 GS832018T-200I Pipeline/Flow Through TQFP 200/7.5 I 2M x 18 GS832018T-166I Pipeline/Flow Through TQFP 166/8 I 2M x 18 GS832018T-150I Pipeline/Flow Through TQFP 150/8.5 I 2M x 18 GS832018T-133I Pipeline/Flow Through TQFP 133/8.5 I 1M x 32 GS832032T-250I Pipeline/Flow Through TQFP 250/6.5 I 1M x 32 GS832032T-225I Pipeline/Flow Through TQFP 225/7 I 1M x 32 GS832032T-200I Pipeline/Flow Through TQFP 200/7.5 I 1M x 32 GS832032T-166I Pipeline/Flow Through TQFP 166/8 I Type Package 2M x 18 GS832018T-250 Pipeline/Flow Through TQFP 2M x 18 GS832018T-225 Pipeline/Flow Through 2M x 18 GS832018T-200 2M x 18 Re co m me nd ed for Ne w De sig n— Di sco nt inu ed Pr od u Part Number1 ct Speed2 (MHz/ns) Org No t 1M x 32 GS832032T-150I Pipeline/Flow Through TQFP 150/8.5 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832018T-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.03b 12/2007 22/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832018/32/36T-250/225/200/166/150/133 Part Number1 Type Package Speed2 (MHz/ns) TA3 1M x 32 GS832032T-133I Pipeline/Flow Through TQFP 133/8.5 I 1M x 36 GS832036T-250I Pipeline/Flow Through TQFP 250/6.5 I 1M x 36 GS832036T-225I Pipeline/Flow Through TQFP 225/7 I 1M x 36 GS832036T-200I Pipeline/Flow Through TQFP 200/7.5 I 1M x 36 GS832036T-166I Pipeline/Flow Through TQFP 166/8 I 1M x 36 GS832036T-150I Pipeline/Flow Through TQFP 150/8.5 I 1M x 36 GS832036T-133I Pipeline/Flow Through TQFP 133/8.5 I 2M x 18 GS832018GT-250 Pipeline/Flow Through RoHS-compliant TQFP 250/6.5 C 2M x 18 GS832018GT-225 Pipeline/Flow Through RoHS-compliant TQFP 225/7 C 2M x 18 GS832018GT-200 Pipeline/Flow Through RoHS-compliant TQFP 200/7.5 C 2M x 18 GS832018GT-166 Pipeline/Flow Through RoHS-compliant TQFP 166/8 C 2M x 18 GS832018GT-150 Pipeline/Flow Through RoHS-compliant TQFP 150/8.5 C 2M x 18 GS832018GT-133 Pipeline/Flow Through RoHS-compliant TQFP 133/8.5 C 1M x 32 GS832032GT-250 Pipeline/Flow Through RoHS-compliant TQFP 250/6.5 C 1M x 32 GS832032GT-225 Pipeline/Flow Through RoHS-compliant TQFP 225/7 C 1M x 32 GS832032GT-200 Pipeline/Flow Through RoHS-compliant TQFP 200/7.5 C 1M x 32 GS832032GT-166 Pipeline/Flow Through RoHS-compliant TQFP 166/8 C 1M x 32 GS832032GT-150 Pipeline/Flow Through RoHS-compliant TQFP 150/8.5 C 1M x 32 GS832032GT-133 Pipeline/Flow Through RoHS-compliant TQFP 133/8.5 C 1M x 36 GS832036GT-250 Pipeline/Flow Through RoHS-compliant TQFP 250/6.5 C 1M x 36 GS832036GT-225 Pipeline/Flow Through RoHS-compliant TQFP 225/7 C 1M x 36 GS832036GT-200 Pipeline/Flow Through RoHS-compliant TQFP 200/7.5 C 1M x 36 GS832036GT-166 Pipeline/Flow Through RoHS-compliant TQFP 166/8 C 1M x 36 GS832036GT-150 Pipeline/Flow Through RoHS-compliant TQFP 150/8.5 C 1M x 36 GS832036GT-133 Pipeline/Flow Through RoHS-compliant TQFP 133/8.5 C 2M x 18 GS832018GT-250I Pipeline/Flow Through RoHS-compliant TQFP 250/6.5 I 2M x 18 GS832018GT-225I Pipeline/Flow Through RoHS-compliant TQFP 225/7 I 2M x 18 GS832018GT-200I Pipeline/Flow Through RoHS-compliant TQFP 200/7.5 I 2M x 18 GS832018GT-166I Pipeline/Flow Through RoHS-compliant TQFP 166/8 I 2M x 18 GS832018GT-150I Pipeline/Flow Through RoHS-compliant TQFP 150/8.5 I n— Di sco nt inu ed Pr od u De sig me nd ed for Re co m ct Org Ne w Ordering Information for GSI Synchronous Burst RAMs No t 2M x 18 GS832018GT-133I Pipeline/Flow Through RoHS-compliant TQFP 133/8.5 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832018T-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.03b 12/2007 23/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832018/32/36T-250/225/200/166/150/133 Ordering Information for GSI Synchronous Burst RAMs Part Number1 Type Package Speed2 (MHz/ns) TA3 1M x 32 GS832032GT-250I Pipeline/Flow Through RoHS-compliant TQFP 250/6.5 I 1M x 32 GS832032GT-225I Pipeline/Flow Through RoHS-compliant TQFP 225/7 I 1M x 32 GS832032GT-200I Pipeline/Flow Through RoHS-compliant TQFP 200/7.5 I 1M x 32 GS832032GT-166I Pipeline/Flow Through RoHS-compliant TQFP 166/8 I 1M x 32 GS832032GT-150I Pipeline/Flow Through RoHS-compliant TQFP 150/8.5 I 1M x 32 GS832032GT-133I Pipeline/Flow Through RoHS-compliant TQFP 133/8.5 I 1M x 36 GS832036GT-250I Pipeline/Flow Through RoHS-compliant TQFP 250/6.5 I 1M x 36 GS832036GT-225I Pipeline/Flow Through RoHS-compliant TQFP 225/7 I 1M x 36 GS832036GT-200I Pipeline/Flow Through RoHS-compliant TQFP 200/7.5 I 1M x 36 GS832036GT-166I Pipeline/Flow Through RoHS-compliant TQFP 166/8 I 1M x 36 GS832036GT-150I Pipeline/Flow Through RoHS-compliant TQFP 150/8.5 I n— Di sco nt inu ed Pr od u ct Org No t Re co m me nd ed for Ne w De sig 1M x 36 GS832036GT-133I Pipeline/Flow Through RoHS-compliant TQFP 133/8.5 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832018T-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.03b 12/2007 24/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832018/32/36T-250/225/200/166/150/133 36Mb Sync SRAM Datasheet Revision History Types of Changes Format or Content • Creation of new datasheet 832018_r1 832018_r1; 832018_r1_01 Content ct Page;Revisions;Reason n— Di sco nt inu ed Pr od u DS/DateRev. Code: Old; New • Updated AC Characteristics table • Updated FT power numbers • Corrected Absolute Maximum Ratings table • Corrected Capacitance table • Updated tKQ (PL) numbers in table on page 1 • Updated DC Electrical Characteristics table • Removed Output Load 2 diagram on page 15 • Updated standby current numbers in Operating Currents table Content/Format • Updated format • Added RoHS-compliant information for TQFP package • (Rev. 1.02b: Removed status column from ordering information table) 832018_r1_02; 832018_r1_03 Content/Format • Updated format • (Rev. 1.03b: Removed status column from ordering information table) No t Re co m me nd ed for Ne w De sig 832018_r1_01; 832018_r1_02 Rev: 1.03b 12/2007 25/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology