GS832218/36/72(B/E/C)-xxxV 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs 119-, 165-, & 209-Pin BGA Commercial Temp Industrial Temp Features Functional Description ct SCD and DCD Pipelined Reads The GS832218/36/72-xxxV is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input. De sig Applications The GS832218/36/72-xxxV is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register. n— Di sco nt inu ed Pr od u • FT pin for user-configurable flow through or pipeline operation • Single/Dual Cycle Deselect selectable • IEEE 1149.1 JTAG-compatible Boundary Scan • ZQ mode pin for user-selectable high/low output drive • 1.8 V or 2.5 V core power supply • 1.8 V or 2.5 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to SCD x18/x36 Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 119-, 165-, and 209-bump BGA package • RoHS-compliant packages available 250 MHz–133 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O Ne w Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Controls Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edgetriggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. No t Re co m me nd ed for FLXDrive™ The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details. Pipeline 3-1-1-1 Flow Through 2-1-1-1 Rev: 1.07 9/2008 Core and Interface Voltages The GS832218/36/72-xxxV operates on a 1.8 V or 2.5 V power supply. All inputs are 1.8 V or 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 1.8 V or 2.5 V compatible. Parameter Synopsis -250 -225 -200 -166 -150 -133 Unit tKQ tCycle 3.0 4.0 3.0 4.4 3.0 5.0 3.5 6.0 3.8 6.7 4.0 7.5 ns ns Curr (x18) Curr (x36) Curr (x72) 285 350 440 265 320 410 245 295 370 220 260 320 210 240 300 185 215 265 mA mA mA tKQ tCycle 6.5 6.5 7.0 7.0 7.5 7.5 8.0 8.0 8.5 8.5 8.5 8.5 ns ns Curr (x18) Curr (x36) Curr (x72) 205 235 315 195 225 295 185 210 265 175 200 255 165 190 240 155 175 230 mA mA mA 1/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV 209-Bump BGA—x72 Common I/O—Top View (Package C) 2 3 4 5 6 7 8 9 10 11 A DQG DQG A E2 ADSP ADSC ADV E3 A DQB DQB A B DQG DQG BC BG NC BW A BB BF DQB DQB B C DQG DQG BH BD NC E1 NC BE BA DQB DQB C D DQG DQG VSS NC NC G GW NC VSS DQB DQB D E DQPG DQPC VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPF DQPB E F DQC DQC VSS VSS VSS ZQ VSS VSS VSS DQF DQF F G DQC DQC VDDQ VDDQ VDD MCH VDD VDDQ VDDQ DQF DQF G H DQC DQC VSS VSS VSS MCL VSS VSS VSS DQF DQF H J DQC DQC VDDQ VDDQ VDD MCL VDD VDDQ VDDQ DQF DQF J K NC NC CK NC VSS MCL VSS NC NC NC NC K L DQH DQH VDDQ VDDQ VDD FT VDD VDDQ VDDQ DQA DQA L M DQH DQH VSS VSS VSS MCL VSS VSS VSS DQA DQA M N DQH DQH VDDQ VDDQ VDD SCD VDD VDDQ VDDQ DQA DQA N P DQH DQH VSS VSS VSS ZZ VSS VSS VSS DQA DQA P R DQPD DQPH VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPA DQPE R T DQD DQD VSS NC NC LBO NC NC VSS DQE DQE T U DQD DQD NC A A A A A A DQE DQE U V DQD DQD A A A A1 A A A DQE DQE V W DQD DQD TMS TDI A A0 A TDO TCK DQE DQE W n— Di sco nt inu ed Pr od u De sig Ne w me nd ed for ct 1 No t Re co m 11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch Rev: 1.07 9/2008 2/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV GS832272C-xxxV 209-Bump BGA Pin Description Type Description A 0, A 1 I Address field LSBs and Address Counter Preset Inputs. An I Address Inputs DQA DQB DQC DQD DQE DQF DQG DQH I/O BA, BB I Byte Write Enable for DQA, DQB I/Os; active low BC,BD I Byte Write Enable for DQC, DQD I/Os; active low BE, BF, BG,BH I Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low NC — No Connect CK I GW I E1 I E3 I E2 I G I ADV I ADSP, ADSC I ZZ I FT I LBO I SCD I MCH I n— Di sco nt inu ed Pr od u Data Input and Output pins Clock Input Signal; active high Ne w De sig Global Write Enable—Writes all bytes; active low Chip Enable; active low Chip Enable; active low Chip Enable; active high Output Enable; active low me nd ed for Burst address counter advance enable; active low Re co m MCL ct Symbol Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Single Cycle Deselect/Dual Cycle Deselect Mode Control Must Connect High Must Connect Low I Byte Enable; active low I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) I Scan Test Mode Select I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock BW TMS TDI No t ZQ Rev: 1.07 9/2008 3/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV Type Description VDD I Core power supply VSS I I/O and Core Ground VDDQ I Output driver power supply No t Re co m me nd ed for Ne w De sig n— Di sco nt inu ed Pr od u Symbol ct GS832272C-xxxV 209-Bump BGA Pin Description (Continued) Rev: 1.07 9/2008 4/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV 2 3 4 5 6 7 8 9 10 11 A NC A E1 BB NC E3 BW ADSC ADV A A A B NC A E2 NC BA CK GW G ADSP A NC B C NC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPA C D NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA D E NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA E F NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA F G NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA G H FT MCL NC VDD VSS VSS VSS VDD NC ZQ ZZ H J DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC J K DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC K L DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC L M DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC M N DQPB SCD P NC NC R LBO A me nd ed for Ne w n— Di sco nt inu ed Pr od u ct 1 De sig 165-Bump BGA—x18 Commom I/O—Top View (Package E) VSS NC A NC VSS VDDQ NC NC N A A TDI A1 TDO A A A A P A A TMS A0 TCK A A A A R Re co m VDDQ No t 11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch Rev: 1.07 9/2008 5/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV 165-Bump BGA—x36 Common I/O—Top View (Package E) 2 3 4 5 6 7 8 9 10 11 A NC A E1 BC BB E3 BW ADSC ADV A NC B NC A E2 BD BA CK GW G ADSP A C DQPC NC VDDQ VSS VSS VSS VSS VSS VDDQ D DQC DQC VDDQ VDD VSS VSS VSS VDD E DQC DQC VDDQ VDD VSS VSS VSS F DQC DQC VDDQ VDD VSS VSS G DQC DQC VDDQ VDD VSS H FT MCL NC VDD J DQD DQD VDDQ K DQD DQD L DQD M A B NC DQPB C VDDQ DQB DQB D VDD VDDQ DQB DQB E VSS VDD VDDQ DQB DQB F VSS VSS VDD VDDQ DQB DQB G VSS VSS VSS VDD NC ZQ ZZ H VDD VSS VSS VSS VDD VDDQ DQA DQA J VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA K DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA L DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA M N DQPD SCD P NC NC R LBO A me nd ed for Ne w n— Di sco nt inu ed Pr od u NC De sig ct 1 VSS NC A NC VSS VDDQ NC DQPA N A A TDI A1 TDO A A A A P A A TMS A0 TCK A A A A R Re co m VDDQ No t 11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch Rev: 1.07 9/2008 6/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV GS832218/36E-xxxV 165-Bump BGA Pin Description Type Description A 0, A 1 I Address field LSBs and Address Counter Preset Inputs An I Address Inputs DQA DQB DQC DQD I/O BA , BB , BC , BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low (x36 Version) NC — No Connect CK I BW I Byte Write—Writes all enabled bytes; active low GW I Global Write Enable—Writes all bytes; active low E1 I Chip Enable; active low E3 I E2 I G I ADV I ADSC, ADSP I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep mode control; active high FT I LBO I ZQ I TMS I TDI I TDO O TCK I MCL — VDD n— Di sco nt inu ed Pr od u Clock Input Signal; active high Chip Enable; active low Chip Enable; active high Output Enable; active low Ne w De sig Burst address counter advance enable; active l0w Rev: 1.07 9/2008 Flow Through or Pipeline mode; active low Linear Burst Order mode; active low me nd ed for FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Must Connect Low — Single Cycle Deselect/Dual Cyle Deselect Mode Control I Core power supply I I/O and Core Ground I Output driver power supply No t VSS VDDQ Data Input and Output pins Re co m SCD ct Symbol 7/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV 119-Bump BGA—x36 Common I/O—Top View 1 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B NC A A ADSC A A NC C NC A A VDD A A NC C D DQC DQPC VSS ZQ VSS DQPB DQB D E DQC DQC VSS E1 VSS DQB DQB E F VDDQ DQC VSS G VSS DQB VDDQ F G DQC2 DQC BC ADV BB DQB DQB G H DQC DQC VSS GW VSS DQB DQB H J VDDQ VDD NC VDD NC VDD VDDQ J K DQD DQD VSS CK VSS DQA DQA K L DQD DQD BD SCD BA DQA DQA L M VDDQ DQD VSS BW VSS DQA VDDQ M N DQD DQD A1 VSS DQA DQA N P DQD DQPD VSS A0 VSS DQPA DQA P R NC A LBO VDD FT A NC R T NC NC A A A A ZZ T U VDDQ TMS TDI TCK TDO NC VDDQ U ct n— Di sco nt inu ed Pr od u De sig Ne w B 7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch No t Re co m me nd ed for VSS A Rev: 1.07 9/2008 8/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV 119-Bump BGA—x18 Common I/O—Top View 1 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B NC A A ADSC A A NC C NC A A VDD A A NC C D DQB NC VSS ZQ VSS DQPA NC D E NC DQB VSS E1 VSS NC DQA E F VDDQ NC VSS G VSS DQA VDDQ F G NC DQB BB ADV NC NC DQA G H DQB NC VSS GW VSS DQA NC H J VDDQ VDD NC VDD NC VDD VDDQ J K NC DQB VSS CK VSS NC DQA K L DQB NC NC SCD BA DQA NC L M VDDQ DQB VSS BW VSS NC VDDQ M N DQB NC A1 VSS DQA NC N P NC DQPB VSS A0 VSS NC DQA P R NC A LBO VDD FT A NC R T NC A A A A A ZZ T U VDDQ TMS TDI TCK TDO NC VDDQ U ct n— Di sco nt inu ed Pr od u De sig Ne w B 7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch No t Re co m me nd ed for VSS A Rev: 1.07 9/2008 9/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV GS832218/36B-xxxV 119-Bump BGA Pin Description Type Description A 0, A 1 I Address field LSBs and Address Counter Preset Inputs An I Address Inputs DQA DQB DQC DQD I/O BA , BB , BC , BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low NC — No Connect CK I BW I Byte Write—Writes all enabled bytes; active low GW I Global Write Enable—Writes all bytes; active low E1 I Chip Enable; active low G I ADV I ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep mode control; active high FT I LBO I ZQ I SCD I TMS I TDI I TDO O TCK I VSS n— Di sco nt inu ed Pr od u Clock Input Signal; active high Output Enable; active low Ne w De sig Burst address counter advance enable; active low Rev: 1.07 9/2008 Flow Through or Pipeline mode; active low Linear Burst Order mode; active low me nd ed for FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) Single Cycle Deselect/Dual Cyle Deselect Mode Control Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock I Core power supply I I/O and Core Ground I I/O and Core Ground No t VSS VDDQ Data Input and Output pins Re co m VDD ct Symbol I Output driver power supply 10/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV GS832218/36/72-xxxV Block Diagram Register D Q A0 A0 D0 Q0 A1 ct A0–An A1 n— Di sco nt inu ed Pr od u D1 Q1 Counter Load A LBO ADV Memory Array CK ADSC ADSP Q Register GW BW BA D Q 36 Register D D Q BB 36 D Ne w D Q Register Q 36 36 me nd ed for D Register BD Q Register D Q Q De sig D BC Register 4 Register Register E1 D Q 36 Register Re co m D FT G Power Down No t ZZ Control Q 36 DCD=S CD DQx1–DQx9 Note: Only x36 version shown for simplicity. Rev: 1.07 9/2008 11/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV Mode Pin Functions Burst Order Control LBO Output Register Control FT Power Down Control ZZ Single/Dual Cycle Deselect Control SCD FLXDrive Output Impedance Control ZQ State Function L Linear Burst H Interleaved Burst L Flow Through ct Pin Name n— Di sco nt inu ed Pr od u Mode Name H or NC Pipeline L or NC Active H Standby, IDD = ISB L Dual Cycle Deselect H or NC Single Cycle Deselect L High Drive (Low Impedance) H or NC Low Drive (High Impedance) De sig Note: There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above table. There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences Ne w Linear Burst Sequence Interleaved Burst Sequence 1st address 00 01 2nd address 01 10 3rd address 10 11 4th address 11 00 me nd ed for A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] 10 11 1st address 00 01 10 11 11 00 2nd address 01 00 11 10 00 01 3rd address 10 11 00 01 01 10 4th address 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Re co m Note: The burst counter wraps to initial state on the 5th clock. No t BPR 1999.05.18 Rev: 1.07 9/2008 12/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV GW BW BA BB BC BD Notes Read H H X X X X 1 Write No Bytes H L H H H H 1 Write byte a H L L Write byte b H L H Write byte c H L H Write byte d H L H Write all bytes H L L ct Function n— Di sco nt inu ed Pr od u Byte Write Truth Table H H H 2, 3 L H H 2, 3 H L H 2, 3, 4 H H L 2, 3, 4 L L L 2, 3, 4 No t Re co m me nd ed for Ne w De sig Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs, BA, BB, BC and/or BD. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x32 and x36 versions. Rev: 1.07 9/2008 13/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV Synchronous Truth Table E1 None X L Deselect Cycle, Power Down None X L Deselect Cycle, Power Down None X L Deselect Cycle, Power Down None X L Deselect Cycle, Power Down None X H Read Cycle, Begin Burst External R L Read Cycle, Begin Burst External R L Write Cycle, Begin Burst External W L Read Cycle, Continue Burst Next CR X Read Cycle, Continue Burst Next CR H Write Cycle, Continue Burst Next CW Write Cycle, Continue Burst Next CW Read Cycle, Suspend Burst Current Read Cycle, Suspend Burst Current Write Cycle, Suspend Burst Current Current ADSP ADSC ADV W DQ3 H X L X X High-Z L X X L X X High-Z X H L X X X High-Z L X L X X X High-Z X X X L X X High-Z H L L X X X Q H L H L X F Q H L H L X T D X X H H L F Q X X X H L F Q X X X H H L T D H X X X H L T D X X X H H H F Q H X X X H H F Q X X X H H H T D H X X X H H T D Ne w me nd ed for Write Cycle, Suspend Burst E3 X De sig Deselect Cycle, Power Down E2 ct Operation n— Di sco nt inu ed Pr od u State Address Diagram Used Key No t Re co m Notes: 1. X = Don’t Care, H = High, L = Low 2. E = T (True) if E2 = 1 and E1 = E3 = 0; E = F (False) if E2 = 0 or E1 = 1 or E3 = 1 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.07 9/2008 14/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV Simplified State Diagram n— Di sco nt inu ed Pr od u ct X Deselect W R X R R First Write CR X CR Ne w De sig CW First Read me nd ed for W X R R Burst Write Burst Read X CR CW CR Re co m Simple Burst Synchronous Operation Simple Synchronous Operation W No t Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and assumes ADSP is tied high and ADV is tied low. Rev: 1.07 9/2008 15/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV Simplified State Diagram with G ct X W R W X n— Di sco nt inu ed Pr od u Deselect R R First Write CR First Read CW X CR W Burst Write me nd ed for X Ne w De sig CW W R CR CW R W Burst Read X CW CR No t Re co m Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.07 9/2008 16/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV Absolute Maximum Ratings (All voltages reference to VSS) Description Value Unit VDD Voltage on VDD Pins –0.5 to 4.6 V VDDQ Voltage on VDDQ Pins –0.5 to VDD VI/O Voltage on I/O Pins VIN Voltage on Other Input Pins IIN Input Current on Any Pin IOUT Output Current on Any I/O Pin PD Package Power Dissipation TSTG Storage Temperature TBIAS Temperature Under Bias n— Di sco nt inu ed Pr od u ct Symbol V –0.5 to VDDQ +0.5 (≤ 4.6 V max.) V –0.5 to VDD +0.5 (≤ 4.6 V max.) V +/–20 mA +/–20 mA 1.5 W –55 to 125 o –55 to 125 o C C De sig Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges (1.8 V/2.5 V Version) Symbol Min. Typ. Max. Unit VDD1 1.7 1.8 2.0 V VDD2 2.3 2.5 2.7 V 1.8 V VDDQ I/O Supply Voltage VDDQ1 1.7 1.8 VDD V 2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 VDD V 1.8 V Supply Voltage me nd ed for 2.5 V Supply Voltage Ne w Parameter Notes No t Re co m Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.07 9/2008 17/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 0.6*VDD — VDD + 0.3 V 1 VDD Input Low Voltage VIL –0.3 — 0.3*VDD 1 n— Di sco nt inu ed Pr od u Parameter ct VDDQ2 & VDDQ1 Range Logic Levels V Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Recommended Operating Temperatures Parameter Symbol Ambient Temperature (Commercial Range Versions) TA Ambient Temperature (Industrial Range Versions) TA Min. Typ. Max. Unit Notes 0 25 70 °C 2 –40 25 85 °C 2 De sig Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. VSS 50% VSS – 2.0 V Re co m 20% tKC Capacitance 20% tKC VDD + 2.0 V me nd ed for VIH Overshoot Measurement and Timing Ne w Undershoot Measurement and Timing 50% VDD VIL (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 8 10 pF Input/Output Capacitance CI/O VOUT = 0 V 12 14 pF No t Parameter Note: These parameters are sample tested. Rev: 1.07 9/2008 18/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV AC Test Conditions Parameter Conditions Input high level VDD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDD/2 Output reference level VDDQ/2 Output load Fig. 1 DQ DC Electrical Characteristics IIL FT, SCD, ZQ, ZZ Input Current IIN Output Leakage Current IOL * Distributed Test Jig Capacitance Test Conditions Min Max VIN = 0 to VDD –1 uA 1 uA VDD ≥ VIN ≥ 0 V –100 uA 100 uA Output Disable, VOUT = 0 to VDD –1 uA 1 uA Symbol Test Conditions Min Max VOH1 IOH = –4 mA, VDDQ = 1.7 V VDDQ – 0.4 V — VOH2 IOH = –8 mA, VDDQ = 2.375 V 1.7 V — VOL1 IOL = 4 mA — 0.4 V VOL2 IOL = 8 mA — 0.4 V De sig Input Leakage Current (except mode pins) VDDQ/2 Ne w Symbol 30pF* 50Ω Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. Parameter n— Di sco nt inu ed Pr od u Output Load 1 ct Figure 1 Parameter 1.8 V Output High Voltage 2.5 V Output High Voltage 1.8 V Output Low Voltage No t Re co m 2.5 V Output Low Voltage me nd ed for DC Output Characteristics (1.8 V/2.5 V Version) Rev: 1.07 9/2008 19/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology Rev: 1.07 9/2008 IDD 85 100 IDD Pipeline Flow Through 60 60 ISB ISB Pipeline - 100 115 80 80 85 95 60 60 170 15 225 20 190 20 255 40 235 30 320 50 0 to 70°C - 180 15 245 20 200 20 275 40 245 30 340 50 –40 to 85°C 160 15 200 20 180 20 225 35 225 30 280 40 0 to 70°C - 170 15 220 20 190 20 245 35 235 30 300 40 –40 to 85°C 150 15 190 20 170 20 210 30 210 30 260 40 0 to 70°C - 160 15 210 20 180 20 230 30 220 30 280 40 –40 to 85°C 140 15 170 15 160 15 190 25 210 20 235 30 0 to 70°C - n— 60 80 60 80 60 80 60 Di80 60 80 60 80 60 80 60 sco 110 90 105 85 nt 100 85 100 80 in95u 75 90 70 100 80 95 80 ed Pr od uc t 80 210 25 295 45 265 40 370 60 –40 to 85°C N280 e25w 24025 26025 D 190 200 180e 190 15 15 15 si15 g 260 25 Flow Through IDDQ IDD IDDQ IDD Flow Through Pipeline DDQ DD Notes: 1. IDD and IDDQ apply to any combination of VDD1, VDD2, VDDQ1, and VDDQ2 operation. 2. All parameters listed are worst case scenario. — Device Deselected; All other inputs ≥ VIH or ≤ VIL Deselect Current (x18) — IL ZZ ≥ VDD – 0.2 V IH DDQ 200 25 275 45 320 50 DD DDQ 220 25 255 40 285 40 DD DDQ 380 350 60 No t IDD 400 60 0 to 70°C 60 Re (x72) Pipeline I co Flow I 275 mThrough me II 30040 Device Selected; Pipelinen 50 deI All other inputs (x36) ≥V or ≤ V Id Flow fo21025r Output open I Through Symbol –40 to 85°C Mode 0 to 70°C Test Conditions Standby Current Operating Current Parameter Operating Currents 85 95 80 80 150 15 190 15 170 15 210 25 220 20 255 30 –40 to 85°C mA mA mA mA mA mA mA mA mA mA Unit Preliminary GS832218/36/72(B/E/C)-xxxV Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 20/42 © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV AC Electrical Characteristics Clock Cycle Time -250 -225 -200 -166 -150 -133 Unit Max Min Max Min Max Min Max Min Max Min Max tKC 4.0 — 4.4 — 5.0 — 6.0 — 6.7 — 7.5 — ns Clock to Output Valid tKQ — 3.0 — 3.0 — 3.0 — 3.5 — 3.8 — 4.0 ns Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns Clock to Output in Low-Z tLZ1 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns Setup time tS 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns Hold time tH 0.2 — 0.3 — 0.4 — 0.5 — 0.5 — 0.5 — ns Clock Cycle Time tKC 6.5 — 7.0 — 7.5 — 8.0 — 8.5 — 8.5 — ns Clock to Output Valid tKQ — 6.5 — 7.0 — 7.5 — 8.0 — 8.5 — 8.5 ns Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns Clock to Output in Low-Z tLZ1 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns Setup time tS 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns Clock HIGH Time tKH 1.3 — Clock LOW Time tKL 1.7 — Clock to Output in High-Z (x18/x36) tHZ1 1.5 Clock to Output in High-Z (x72) tHZ1 1.5 G to Output Valid (x18/x36) De sig n— Di sco nt inu ed Pr od u ct Min 1.3 — 1.3 — 1.3 — 1.5 — 1.7 — ns 1.7 — 1.7 — 1.7 — 1.7 — 2 — ns 2.5 1.5 2.7 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 ns 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 ns Ne w Flow Through Symbol me nd ed for Pipeline Parameter tOE — 2.5 — 2.7 — 3.0 — 3.5 — 3.8 — 4.0 ns tOE — 3.0 — 3.0 — 3.0 — 3.5 — 3.8 — 4.0 ns tOLZ1 0 — 0 — 0 — 0 — 0 — 0 — ns tOHZ1 — 2.5 — 2.7 — 3.0 — 3.0 — 3.0 — 3.0 ns G to output in High-Z (x72) tOHZ1 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 ns ZZ setup time tZZS2 5 — 5 — 5 — 5 — 5 — 5 — ns ZZ hold time tZZH2 1 — 1 — 1 — 1 — 1 — 1 — ns tZZR 20 — 20 — 20 — 20 — 20 — 20 — ns G to Output Valid (x72) G to output in Low-Z No t Re co m G to output in High-Z (x18/x36) ZZ recovery Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.07 9/2008 21/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV Pipeline Mode Timing (SCD) Cont Cont Deselect Write B Single Read Read C+1 Read C+2 Read C+3 Cont Single Write tKL tKH tKC CK ADSP tS tH Deselect Burst Read ADSC initiated read ADSC tS tH ADV tS tH A0–An Read C ct Read A n— Di sco nt inu ed Pr od u Begin A B tS GW tS C tH De sig BW tH tS tS tH E1 tH E2 tS tH E3 Re co m G me nd ed for tS E1 masks ADSP E2 and E3 only sampled with ADSP and ADSC tOE tS tOHZ Q(A) tKQ tH D(B) tKQX tLZ tHZ Q(C) Q(C+1) Q(C+2) Q(C+3) No t DQa–DQd Deselected with E1 Ne w Ba–Bd Rev: 1.07 9/2008 22/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV Flow Through Mode Timing (SCD) Begin Read A Cont Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont Deselect tKL tKC ct tKH n— Di sco nt inu ed Pr od u CK ADSP Fixed High tS tH tS tH initiated read ADSC ADSC tS tH ADV tS tH A0–An A B C tS tH tS tH BW Ba–Bd tS E1 tS tH E2 tS tH E3 E2 and E3 only sampled with ADSC Re co m G tH tS tOE tOHZ Q(A) D(B) tKQ tLZ tHZ tKQX Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C) No t DQa–DQd Deselected with E1 me nd ed for tH Ne w tS tH De sig GW Rev: 1.07 9/2008 23/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV Pipeline Mode Timing (DCD) Read A Cont Deselect Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont tKC CK ADSP tS ADSC initiated read tH ADSC tS tH ADV tS tH Ao–An A B C tS GW tS tH BW Ba–Bd tS tH Deselected with E1 Ne w E1 De sig tH tS tS E2 and E3 only sampled with ADSC tH tS tH E3 G me nd ed for E2 tS tOE Hi-Z tOHZ Q(A) tKQ tH D(B) tHZ tLZ tKQX Q(C) Q(C+1) Q(C+2) Q(C+3) No t Re co m DQa–DQd n— Di sco nt inu ed Pr od u tKL tKH Deselect Deselect ct Begin Rev: 1.07 9/2008 24/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV Flow Through Mode Timing (DCD) Read A Cont Deselect Write B Read C tKH tKC CK ADSP tS tH ADSC initiated read ADSC tH tS tS ADV tS tH A B C tS tH tS tH BW Ba–Bd tS tH tS tH E2 tS tH E3 E2 and E3 only sampled with ADSP and ADSC Re co m G Deselected with E1 E1 masks ADSP me nd ed for E1 Ne w tH tS tH De sig GW E1 masks ADSP tH tS tOE tKQ tOHZ Q(A) tKQX tHZ tLZ D(B) Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C) No t DQa–DQd Deselect Fixed High tS tH Ao–An Read C+1 Read C+2 Read C+3 Read C n— Di sco nt inu ed Pr od u tKL ct Begin Rev: 1.07 9/2008 25/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. n— Di sco nt inu ed Pr od u ct Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. Sleep Mode Timing tKH tKC tKL CK Setup Hold ADSP De sig ADSC tZZS Ne w ZZ tZZR tZZH me nd ed for Application Tips Re co m Single and Dual Cycle Deselect SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention. JTAG Port Operation No t Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. Rev: 1.07 9/2008 26/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV JTAG Pin Descriptions Pin Name I/O Description TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS Test Mode Select In The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. In The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. Test Data In TDO Test Data Out n— Di sco nt inu ed Pr od u TDI ct Pin Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. JTAG Port Registers Ne w De sig Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. me nd ed for Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible. No t Re co m Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.07 9/2008 27/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV · · · · · · · n— Di sco nt inu ed Pr od u · ct JTAG TAP Block Diagram Boundary Scan Register · · 1 · 2 1 0 0 M* 0 Bypass Register Instruction Register TDI TDO ID Code Register · · · · 2 1 0 De sig 31 30 29 Control Signals TMS Test Access Port (TAP) Controller Ne w TCK * For the value of M, see the BSDL file, which is available at by contacting us at [email protected]. Bit # No t Re co m ID Register Contents GSI Technology JEDEC Vendor ID Code Not Used Presence Register me nd ed for Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X 1 X Rev: 1.07 9/2008 X X X X X X X X X X X X X X X X X X 0 28/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 0 0 1 1 0 1 1 0 0 1 © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV Tap Controller Instruction Set n— Di sco nt inu ed Pr od u ct Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. JTAG Tap Controller State Diagram Test Logic Reset 1 0 0 Run Test Idle 1 Select DR 1 Select IR 0 0 1 De sig Shift DR Ne w 1 me nd ed for 1 0 Shift IR 0 1 1 Exit1 DR 0 Exit1 IR 0 0 Pause DR 1 Exit2 DR 1 Update DR 1 Capture IR 0 0 Pause IR 1 Exit2 IR 0 1 0 0 Update IR 1 0 No t Re co m 1 Capture DR 0 1 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Rev: 1.07 9/2008 29/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV n— Di sco nt inu ed Pr od u ct SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins. Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state. De sig Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. Ne w IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. me nd ed for SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU No t Re co m These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.07 9/2008 30/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV JTAG TAP Instruction Set Summary Code Description Notes EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1 IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2 SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. 1 RFU 011 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 SAMPLE/ PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 1 GSI 101 GSI private instruction. 1 RFU 110 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. n— Di sco nt inu ed Pr od u ct Instruction 1 No t Re co m me nd ed for Ne w De sig BYPASS 111 Places Bypass Register between TDI and TDO. Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. 1 Rev: 1.07 9/2008 31/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV JTAG Port Recommended Operating Conditions and DC Characteristics (1.8/2.5 V Version) Symbol Min. Max. Unit Notes 1.8 V Test Port Input Low Voltage VILJ1 –0.3 0.3 * VDD1 V 1 2.5 V Test Port Input Low Voltage VILJ2 –0.3 0.3 * VDD2 V 1 1.8 V Test Port Input High Voltage VIHJ1 0.6 * VDD1 VDD1 +0.3 V 1 VIHJ2 0.6 * VDD2 VDD2 +0.3 V 1 IINHJ –300 1 uA 2 IINLJ –1 100 uA 3 IOLJ –1 1 uA 4 VOHJ 1.7 — V 5, 6 VOLJ — 0.4 V 5, 7 VOHJC VDDQ – 100 mV — V 5, 8 VOLJC — 100 mV V 5, 9 n— Di sco nt inu ed Pr od u ct Parameter 2.5 V Test Port Input High Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output High Voltage Test Port Output Low Voltage Test Port Output CMOS High Test Port Output CMOS Low me nd ed for Ne w De sig Notes: 1. Input Under/overshoot voltage must be –2 V < Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ ≤ VIN ≤ VDDn 3. 0 V ≤ VIN ≤ VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = –4 mA 7. IOLJ = + 4 mA 8. IOHJC = –100 uA 9. IOLJC = +100 uA JTAG Port AC Test Conditions Parameter Input high level Input low level Re co m Input slew rate Conditions VDD – 0.2 V JTAG Port AC Test Load DQ 0.2 V 50Ω 1 V/ns Input reference level VDDQ/2 Output reference level VDDQ/2 30pF* VDDQ/2 * Distributed Test Jig Capacitance No t Notes: 1. Include scope and jig capacitance. 2. Test conditions as shown unless otherwise noted. Rev: 1.07 9/2008 32/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV JTAG Port Timing Diagram tTKC tTKH tTKL TCK tTH tTS TMS tTKQ TDO tTH tTS Parallel SRAM input JTAG Port AC Electrical Characteristics Symbol Min Max TCK Cycle Time tTKC 50 — TCK Low to TDO Valid tTKQ — TCK High Pulse Width tTKH 20 TCK Low Pulse Width tTKL 20 TDI & TMS Set Up Time tTS 10 ns — ns Ne w tTH ns 20 — ns — ns — ns me nd ed for TDI & TMS Hold Time Unit De sig Parameter n— Di sco nt inu ed Pr od u tTH tTS ct TDI 10 No t Re co m Boundary Scan (BSDL Files) For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications Engineering Department at: [email protected]. Rev: 1.07 9/2008 33/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV Package Dimensions—209-Bump BGA (Package C) 14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array 1 2 TOP VIEW 3 4 5 6 7 11 8 9 10 11 Ø0.50~0.70 (209x) 9 8 7 6 5 18.0 Ne w De sig 22.0 1.0 1.0 A B C D E F G H J K L M N P R T U V W 10 n— Di sco nt inu ed Pr od u A1 CORNER BOTTOM VIEW ct Ø0.10 M C Ø0.30 M C A B me nd ed for 2 1 A B C D E F G H J K L M N P R T U V W 1.0 10.0 A 14.0 0.15 C 0.20(4x) SEATING PLANE No t C Rev: 1.07 9/2008 3 0.40~0.60 1.70 MAX. Re co m 1.0 B 4 34/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV Package Dimensions—119-Bump FPBGA (Package B, Variation 2) TOP VIEW 2 3 4 5 6 7 7 6 5 4 3 2 1 20.32 De sig 22±0.10 1.27 A B C D E F G H J K L M N P R T U ct 1 BOTTOM VIEW A1 Ø0.10S C Ø0.30S C AS B S Ø0.60~0.90 (119x) n— Di sco nt inu ed Pr od u A1 A B C D E F G H J K L M N P R T U 1.27 7.62 A 0.20(4x) 14±0.10 SEATING PLANE No t Re co m C 0.50~0.70 1.86.±0.13 me nd ed for 0.15 C Ne w B Rev: 1.07 9/2008 35/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV Package Dimensions—165-Bump FPBGA (Package D) A1 CORNER TOP VIEW BOTTOM VIEW Ø0.10 M C Ø0.25 M C A B Ø0.40~0.60 (165x) 1 2 3 4 5 6 7 8 9 10 11 A1 CORNER 14.0 1.0 1.0 10.0 13±0.05 0.20(4x) No t Re co m 0.36~0.46 1.40 MAX. SEATING PLANE C B 1.0 A B C D E F G H J K L M N P R me nd ed for 0.15 C Ne w A De sig 15±0.05 1.0 A B C D E F G H J K L M N P R n— Di sco nt inu ed Pr od u ct 11 10 9 8 7 6 5 4 3 2 1 Rev: 1.07 9/2008 36/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV Ordering Information for GSI Synchronous Burst RAMs TA3 250/6.5 C 119 BGA (var.2) 225/7 C 1.8 V or 2.5 V 119 BGA (var.2) 200/7.5 C SCD/DCD 1.8 V or 2.5 V 119 BGA (var.2) 166/8 C GS832218B-150V SCD/DCD 1.8 V or 2.5 V 119 BGA (var.2) 150/8.5 C 2M x 18 GS832218B-133V SCD/DCD 1.8 V or 2.5 V 119 BGA (var.2) 133/8.5 C 2M x 18 GS832218E-250V SCD/DCD 1.8 V or 2.5 V 165 BGA 250/6.5 C 2M x 18 GS832218E-225V SCD/DCD 1.8 V or 2.5 V 165 BGA 225/7 C 2M x 18 GS832218E-200V SCD/DCD 1.8 V or 2.5 V 165 BGA 200/7.5 C 2M x 18 GS832218E-166V SCD/DCD 1.8 V or 2.5 V 165 BGA 166/8 C 2M x 18 GS832218E-150V SCD/DCD 1.8 V or 2.5 V 165 BGA 150/8.5 C 2M x 18 GS832218E-133V SCD/DCD 1.8 V or 2.5 V 165 BGA 133/8.5 C 1M x 36 GS832236B-250V SCD/DCD 1.8 V or 2.5 V 119 BGA (var.2) 250/6.5 C 1M x 36 GS832236B-225V SCD/DCD 1.8 V or 2.5 V 119 BGA (var.2) 225/7 C 1M x 36 GS832236B-200V SCD/DCD 1.8 V or 2.5 V 119 BGA (var.2) 200/7.5 C 1M x 36 GS832236B-166V SCD/DCD 1.8 V or 2.5 V 119 BGA (var.2) 166/8 C 1M x 36 GS832236B-150V SCD/DCD 1.8 V or 2.5 V 119 BGA (var.2) 150/8.5 C 1M x 36 GS832236B-133V SCD/DCD 1.8 V or 2.5 V 119 BGA (var.2) 133/8.5 C 1M x 36 GS832236E-250V SCD/DCD 1.8 V or 2.5 V 165 BGA 250/6.5 C 1M x 36 GS832236E-225V SCD/DCD 1.8 V or 2.5 V 165 BGA 225/7 C 1M x 36 GS832236E-200V SCD/DCD 1.8 V or 2.5 V 165 BGA 200/7.5 C 1M x 36 GS832236E-166V SCD/DCD 1.8 V or 2.5 V 165 BGA 166/8 C 1M x 36 GS832236E-150V SCD/DCD 1.8 V or 2.5 V 165 BGA 150/8.5 C Type Voltage Option Package 2M x 18 GS832218B-250V SCD/DCD 1.8 V or 2.5 V 119 BGA (var.2) 2M x 18 GS832218B-225V SCD/DCD 1.8 V or 2.5 V 2M x 18 GS832218B-200V SCD/DCD 2M x 18 GS832218B-166V 2M x 18 De sig Ne w me nd ed for No t Re co m n— Di sco nt inu ed Pr od u Part Number1 ct Speed2 (MHz/ns) Org Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832218B-150IVT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.07 9/2008 37/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV Part Number1 Type Voltage Option Package Speed2 (MHz/ns) TA3 1M x 36 GS832236E-133V SCD/DCD 1.8 V or 2.5 V 165 BGA 133/8.5 C 512K x 72 GS832272C-250V SCD/DCD 1.8 V or 2.5 V 209 BGA 250/6.5 C 512K x 72 GS832272C-225V SCD/DCD 1.8 V or 2.5 V 209 BGA 225/7 C 512K x 72 GS832272C-200V SCD/DCD 1.8 V or 2.5 V 209 BGA 200/7.5 C 512K x 72 GS832272C-166V SCD/DCD 1.8 V or 2.5 V 209 BGA 166/8 C 512K x 72 GS832272C-150V SCD/DCD 1.8 V or 2.5 V 209 BGA 150/8.5 C 512K x 72 GS832272C-133V SCD/DCD 1.8 V or 2.5 V 209 BGA 133/8.5 C 2M x 18 GS832218B-250IV SCD/DCD 1.8 V or 2.5 V 119 BGA (var.2) 250/6.5 I 2M x 18 GS832218B-225IV SCD/DCD 1.8 V or 2.5 V 119 BGA (var.2) 225/7 I 2M x 18 GS832218B-200IV SCD/DCD 1.8 V or 2.5 V 119 BGA (var.2) 200/7.5 I 2M x 18 GS832218B-166IV SCD/DCD 1.8 V or 2.5 V 119 BGA (var.2) 166/8 I 2M x 18 GS832218B-150IV SCD/DCD 1.8 V or 2.5 V 119 BGA (var.2) 150/8.5 I 2M x 18 GS832218B-133IV SCD/DCD 1.8 V or 2.5 V 119 BGA (var.2) 133/8.5 I 2M x 18 GS832218E-250IV SCD/DCD 1.8 V or 2.5 V 165 BGA 250/6.5 I 2M x 18 GS832218E-225IV SCD/DCD 1.8 V or 2.5 V 165 BGA 225/7 I 2M x 18 GS832218E-200IV SCD/DCD 1.8 V or 2.5 V 165 BGA 200/7.5 I 2M x 18 GS832218E-166IV SCD/DCD 1.8 V or 2.5 V 165 BGA 166/8 I 2M x 18 GS832218E-150IV SCD/DCD 1.8 V or 2.5 V 165 BGA 150/8.5 I 2M x 18 GS832218E-133IV SCD/DCD 1.8 V or 2.5 V 165 BGA 133/8.5 I 1M x 36 GS832236B-250IV SCD/DCD 1.8 V or 2.5 V 119 BGA (var.2) 250/6.5 I 1M x 36 GS832236B-225IV SCD/DCD 1.8 V or 2.5 V 119 BGA (var.2) 225/7 I 1M x 36 GS832236B-200IV SCD/DCD 1.8 V or 2.5 V 119 BGA (var.2) 200/7.5 I 1M x 36 GS832236B-166IV SCD/DCD 1.8 V or 2.5 V 119 BGA (var.2) 166/8 I 1M x 36 GS832236B-150IV SCD/DCD 1.8 V or 2.5 V 119 BGA (var.2) 150/8.5 I 1M x 36 GS832236B-133IV SCD/DCD 1.8 V or 2.5 V 119 BGA (var.2) 133/8.5 I n— Di sco nt inu ed Pr od u De sig Ne w me nd ed for No t ct Org Re co m Ordering Information for GSI Synchronous Burst RAMs (Continued) Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832218B-150IVT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.07 9/2008 38/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV Ordering Information for GSI Synchronous Burst RAMs (Continued) Part Number1 Type Voltage Option Package Speed2 (MHz/ns) TA3 1M x 36 GS832236E-250IV SCD/DCD 1.8 V or 2.5 V 165 BGA 250/6.5 I 1M x 36 GS832236E-225IV SCD/DCD 1.8 V or 2.5 V 165 BGA 225/7 I 1M x 36 GS832236E-200IV SCD/DCD 1.8 V or 2.5 V 165 BGA 200/7.5 I 1M x 36 GS832236E-166IV SCD/DCD 1.8 V or 2.5 V 165 BGA 166/8 I 1M x 36 GS832236E-150IV SCD/DCD 1.8 V or 2.5 V 165 BGA 150/8.5 I 1M x 36 GS832236E-133IV SCD/DCD 1.8 V or 2.5 V 165 BGA 133/8.5 I 512K x 72 GS832272C-250IV SCD/DCD 1.8 V or 2.5 V 209 BGA 250/6.5 I 512K x 72 GS832272C-225IV SCD/DCD 1.8 V or 2.5 V 209 BGA 225/7 I 512K x 72 GS832272C-200IV SCD/DCD 1.8 V or 2.5 V 209 BGA 200/7.5 I 512K x 72 GS832272C-166IV SCD/DCD 1.8 V or 2.5 V 209 BGA 166/8 I 512K x 72 GS832272C-150IV SCD/DCD 1.8 V or 2.5 V 209 BGA 150/8.5 I 512K x 72 GS832272C-133IV SCD/DCD 1.8 V or 2.5 V 209 BGA 133/8.5 I 2M x 18 GS832218GB-250V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 119 BGA (var.2) 250/6.5 C 2M x 18 GS832218GB-225V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 119 BGA (var.2) 225/7 C 2M x 18 GS832218GB-200V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 119 BGA (var.2) 200/7.5 C 2M x 18 GS832218GB-166V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 119 BGA (var.2) 166/8 C 2M x 18 GS832218GB-150V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 119 BGA (var.2) 150/8.5 C 2M x 18 GS832218GB-133V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 119 BGA (var.2) 133/8.5 C 2M x 18 GS832218GE-250V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 165 BGA 250/6.5 C 2M x 18 GS832218GE-225V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 165 BGA 225/7 C 2M x 18 GS832218GE-200V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 165 BGA 200/7.5 C 2M x 18 GS832218GE-166V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 165 BGA 166/8 C 2M x 18 GS832218GE-150V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 165 BGA 150/8.5 C 2M x 18 GS832218GE-133V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 165 BGA 133/8.5 C 1M x 36 GS832236GB-250V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 119 BGA (var.2) 250/6.5 C n— Di sco nt inu ed Pr od u De sig Ne w me nd ed for Re co m No t ct Org Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832218B-150IVT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.07 9/2008 39/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV Ordering Information for GSI Synchronous Burst RAMs (Continued) Part Number1 Type Voltage Option Package Speed2 (MHz/ns) TA3 1M x 36 GS832236GB-225V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 119 BGA (var.2) 225/7 C 1M x 36 GS832236GB-200V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 119 BGA (var.2) 200/7.5 C 1M x 36 GS832236GB-166V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 119 BGA (var.2) 166/8 C 1M x 36 GS832236GB-150V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 119 BGA (var.2) 150/8.5 C 1M x 36 GS832236GB-133V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 119 BGA (var.2) 133/8.5 C 1M x 36 GS832236GE-250V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 165 BGA 250/6.5 C 1M x 36 GS832236GE-225V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 165 BGA 225/7 C 1M x 36 GS832236GE-200V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 165 BGA 200/7.5 C 1M x 36 GS832236GE-166V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 165 BGA 166/8 C 1M x 36 GS832236GE-150V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 165 BGA 150/8.5 C 1M x 36 GS832236GE-133V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 165 BGA 133/8.5 C 512K x 72 GS832272GC-250V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 209 BGA 250/6.5 C 512K x 72 GS832272GC-225V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 209 BGA 225/7 C 512K x 72 GS832272GC-200V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 209 BGA 200/7.5 C 512K x 72 GS832272GC-166V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 209 BGA 166/8 C 512K x 72 GS832272GC-150V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 209 BGA 150/8.5 C 512K x 72 GS832272GC-133V SCD/DCD 1.8 V or 2.5 V RoHS-compliant 209 BGA 133/8.5 C 2M x 18 GS832218GB-250IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 119 BGA (var.2) 250/6.5 I 2M x 18 GS832218GB-225IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 119 BGA (var.2) 225/7 I 2M x 18 GS832218GB-200IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 119 BGA (var.2) 200/7.5 I 2M x 18 GS832218GB-166IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 119 BGA (var.2) 166/8 I 2M x 18 GS832218GB-150IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 119 BGA (var.2) 150/8.5 I 2M x 18 GS832218GB-133IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 119 BGA (var.2) 133/8.5 I 2M x 18 GS832218GE-250IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 165 BGA 250/6.5 I 2M x 18 GS832218GE-225IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 165 BGA 225/7 I n— Di sco nt inu ed Pr od u De sig Ne w me nd ed for Re co m No t ct Org Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832218B-150IVT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.07 9/2008 40/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV Ordering Information for GSI Synchronous Burst RAMs (Continued) Part Number1 Type Voltage Option Package Speed2 (MHz/ns) TA3 2M x 18 GS832218GE-200IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 165 BGA 200/7.5 I 2M x 18 GS832218GE-166IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 165 BGA 166/8 I 2M x 18 GS832218GE-150IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 165 BGA 150/8.5 I 2M x 18 GS832218GE-133IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 165 BGA 133/8.5 I 1M x 36 GS832236GB-250IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 119 BGA (var.2) 250/6.5 I 1M x 36 GS832236GB-225IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 119 BGA (var.2) 225/7 I 1M x 36 GS832236GB-200IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 119 BGA (var.2) 200/7.5 I 1M x 36 GS832236GB-166IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 119 BGA (var.2) 166/8 I 1M x 36 GS832236GB-150IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 119 BGA (var.2) 150/8.5 I 1M x 36 GS832236GB-133IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 119 BGA (var.2) 133/8.5 I 1M x 36 GS832236GE-250IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 165 BGA 250/6.5 I 1M x 36 GS832236GE-225IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 165 BGA 225/7 I 1M x 36 GS832236GE-200IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 165 BGA 200/7.5 I 1M x 36 GS832236GE-166IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 165 BGA 166/8 I 1M x 36 GS832236GE-150IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 165 BGA 150/8.5 I 1M x 36 GS832236GE-133IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 165 BGA 133/8.5 I 512K x 72 GS832272GC-250IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 209 BGA 250/6.5 I 512K x 72 GS832272GC-225IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 209 BGA 225/7 I 512K x 72 GS832272GC-200IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 209 BGA 200/7.5 I 512K x 72 GS832272GC-166IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 209 BGA 166/8 I 512K x 72 GS832272GC-150IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 209 BGA 150/8.5 I 512K x 72 GS832272GC-133IV SCD/DCD 1.8 V or 2.5 V RoHS-compliant 209 BGA 133/8.5 I n— Di sco nt inu ed Pr od u De sig Ne w me nd ed for Re co m ct Org No t Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832218B-150IVT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.07 9/2008 41/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology GS832218/36/72(B/E/C)-xxxV 36Mb Sync SRAM Data Sheet Revision History Types of Changes Format or Content Page;Revisions;Reason • Creation of new datasheet • Updated AC Characteristics table with +1 numbers • Removed address pin numbers (except 0 and 1) • Corrected “E” package mechanical drawing thickness to 1.4 mm n— Di sco nt inu ed Pr od u 8322Vxx_r1 ct DS/DateRev. Code: Old; New 8322Vxx_r1; 8322Vxx_r1_01 Content 8322Vxx_r1_01; 8322Vxx_r1_02 Content/Format • Updated Thermal Characteristics table • Basic format updates 8322Vxx_r1_02; 8322Vxx_r1_03 Content/Format • Updated format • Updated mechanicals 8322Vxx_r1_03; 8322Vxx_r1_04 Content 8322Vxx_r1_04; 8322xx_V_r1_05 Content • Updated entire document to reflect change in part nomenclature 8322Vxx_r1_05; 8322xx_V_r1_06 Content • Updated Truth Tables (pg. 13, 14) • Rev1.06a: updated coplanarity for 119, 165 and 209 BGA mechanical, removed Status column from Ordering Information table. 8322Vxx_r1_06; 8322xx_V_r1_07 Content De sig • Pb-free information added No t Re co m me nd ed for Ne w • Changed VDD3 and VDDQ3 to VDD1 and VDDQ1 in footnote on Operating Currents table Rev: 1.07 9/2008 42/42 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology