GS816218/36B(B/D) 1M x 18, 512K x 36 18MbS/DCD Sync Burst SRAMs Features Flow Through/Pipeline Reads Functional Description Applications SCD and DCD Pipelined Reads The GS816218/36B(B/D) is an SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Ne w De sig The GS816218/36B(B/D) is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. The function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register. n— Di sco nt inu ed Pr od u • FT pin for user-configurable flow through or pipeline operation • Single/Dual Cycle Deselect selectable • IEEE 1149.1 JTAG-compatible Boundary Scan • ZQ mode pin for user-selectable high/low output drive • 2.5 V or 3.3 V +10%/–10% core power supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to SCD x18/x36 Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 119-bump and 165-bump BGA packages • RoHs-compliant 119-bump and 165-bump BGA packages available 250 MHz–150 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O ct 119-- & 165-Bump BGA Commercial Temp Industrial Temp Controls No t Re co m me nd ed for Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Pipeline 3-1-1-1 Flow Through 2-1-1-1 Rev: 1.07 9/2008 FLXDrive™ The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS816218/36B(B/D) operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible. Parameter Synopsis -250 -200 -150 Unit tKQ tCycle 2.5 4.0 3.0 5.0 3.8 6.7 ns ns Curr (x18) Curr (x36) 295 345 245 285 200 225 mA mA tKQ tCycle 5.5 5.5 6.5 6.5 7.5 7.5 ns ns Curr (x18) Curr (x36) 225 255 200 220 185 205 mA mA 1/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) 3 A VDDQ A A B NC A A C NC A A D DQC DQPC VSS E DQC DQC VSS F VDDQ DQC VSS G DQC DQC BC H DQC DQC J VDDQ K DQD1 4 5 6 7 ADSP A A VDDQ ADSC A A NC VDD A A NC ZQ VSS DQPB DQB E1 VSS DQB DQB G VSS DQB VDDQ ADV BB DQB DQB GW VSS DQB DQB n— Di sco nt inu ed Pr od u 2 De sig 1 NC VDD NC VDD VDDQ DQD5 VSS CK VSS DQA DQA DQD2 DQD6 BD SCD BA DQA DQA VDDQ DQD7 VSS BW VSS DQA VDDQ DQD3 DQD8 VSS A1 VSS DQA DQA P DQD4 DQD9 VSS A0 VSS DQPA DQA R NC A LBO VDD FT A NC T NC NC A A A NC ZZ U VDDQ TMS TDI TCK TDO NC VDDQ L M Re co m N me nd ed for VDD No t Ne w VSS Rev: 1.07 9/2008 ct GS816236B Pad Out—119-Bump BGA—Top View (Package B) 2/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B NC A A ADSC A A NC C NC A A VDD A A NC D DQB NC VSS ZQ VSS DQPA NC E NC DQB VSS E1 VSS NC DQA F VDDQ NC VSS G VSS DQA VDDQ G NC DQB BB ADV NC NC DQA H DQB NC J VDDQ VDD K NC L DQB De sig n— Di sco nt inu ed Pr od u 1 GW VSS DQA NC NC VDD NC VDD VDDQ Ne w VSS VSS CK VSS NC DQA NC NC SCD BA DQA NC VDDQ DQB VSS BW VSS NC VDDQ DQB NC VSS A1 VSS DQA NC NC DQPB VSS A0 VSS NC DQA R NC A LBO VDD FT A NC T NC A A NC A A ZZ VDDQ TMS TDI TCK TDO NC VDDQ N No t Re co m P me nd ed for DQB M U ct GS816218B Pad Out—119-Bump BGA—Top View (Package B) BPR1999.05.18 Rev: 1.07 9/2008 3/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) 2 3 4 5 6 7 8 9 10 11 A NC A E1 BB NC E3 BW ADSC ADV A A A B NC A E2 NC BA CK GW G ADSP A NC B C NC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPA C D NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA D E NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA E F NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA F G NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA G H FT MCL NC VDD VSS VSS VSS VDD NC ZQ ZZ H J DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC J K DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC K L DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC L M DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC M N DQPB SCD P NC NC R LBO NC me nd ed for Ne w n— Di sco nt inu ed Pr od u ct 1 De sig 165 Bump BGA—x18 Commom I/O—Top View (Package D) VSS NC A NC VSS VDDQ NC NC N A A TDI A1 TDO A A A A P A A TMS A0 TCK A A A A R Re co m VDDQ No t 11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch Rev: 1.07 9/2008 4/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) 165 Bump BGA—x36 Common I/O—Top View (Package D) 2 3 4 5 6 7 8 9 10 11 A NC A E1 BC BB E3 BW ADSC ADV A NC B NC A E2 BD BA CK GW G ADSP A C DQPC NC VDDQ VSS VSS VSS VSS VSS VDDQ D DQC DQC VDDQ VDD VSS VSS VSS VDD E DQC DQC VDDQ VDD VSS VSS VSS F DQC DQC VDDQ VDD VSS VSS G DQC DQC VDDQ VDD VSS H FT MCL NC VDD J DQD DQD VDDQ K DQD DQD L DQD M A B NC DQPB C VDDQ DQB DQB D VDD VDDQ DQB DQB E VSS VDD VDDQ DQB DQB F VSS VSS VDD VDDQ DQB DQB G VSS VSS VSS VDD NC ZQ ZZ H VDD VSS VSS VSS VDD VDDQ DQA DQA J VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA K DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA L DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA M N DQPD SCD P NC NC R LBO NC me nd ed for Ne w n— Di sco nt inu ed Pr od u NC De sig ct 1 VSS NC A NC VSS VDDQ NC DQPA N A A TDI A1 TDO A A A A P A A TMS A0 TCK A A A A R Re co m VDDQ No t 11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch Rev: 1.07 9/2008 5/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) GS816218/36B BGA Pin Description Type Description A 0, A 1 I Address field LSBs and Address Counter Preset Inputs A I Address Inputs DQA DQB DQC DQD I/O BA , BB , BC , BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low NC — No Connect CK I BW I Byte Write—Writes all enabled bytes; active low GW I Global Write Enable—Writes all bytes; active low E1 I Chip Enable; active low G I ADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep mode control; active high FT I LBO I ZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) SCD I Single Cycle Deselect/Dual Cyle Deselect Mode Control TMS I TDI I TDO O TCK I VDD I VSS I VDDQ I n— Di sco nt inu ed Pr od u ct Symbol Data Input and Output pins Clock Input Signal; active high De sig Output Enable; active low Flow Through or Pipeline mode; active low me nd ed for Ne w Linear Burst Order mode; active low Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply I/O and Core Ground Re co m Output driver power supply — Must connect low (165 BGA only) No t MCL Scan Test Mode Select Rev: 1.07 9/2008 6/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) GS816218/36B Block Diagram Register Q A0 A0 D0 A1 Q0 A1 D1 Q1 Counter Load ct D n— Di sco nt inu ed Pr od u A0–An A LBO ADV Memory Array CK ADSC ADSP Q Register GW BW BA D Q 36 Register D D Q BB 36 D Ne w D Q Register Q 36 36 me nd ed for D Register BD Q Register D Q Q De sig D BC Register 4 Register Register E1 D Q 36 Register Re co m D FT G Power Down No t ZZ Q 36 SCD DQx1–DQx9 Control Note: Only x36 version shown for simplicity. Rev: 1.07 9/2008 7/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) Mode Pin Functions Burst Order Control LBO Output Register Control FT Power Down Control ZZ Single/Dual Cycle Deselect Control SCD FLXDrive Output Impedance Control ZQ State Function L Linear Burst H Interleaved Burst L Flow Through H or NC Pipeline L or NC Active H Standby, IDD = ISB L Dual Cycle Deselect H or NC Single Cycle Deselect L High Drive (Low Impedance) H or NC Low Drive (High Impedance) ct Pin Name n— Di sco nt inu ed Pr od u Mode Name Note: There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. De sig Burst Counter Sequences Linear Burst Sequence Interleaved Burst Sequence 00 01 10 11 2nd address 01 10 11 3rd address 10 11 4th address 11 00 A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 00 2nd address 01 00 11 10 00 01 3rd address 10 11 00 01 01 10 4th address 11 10 01 00 me nd ed for 1st address Ne w A[1:0] A[1:0] A[1:0] A[1:0] Note: The burst counter wraps to initial state on the 5th clock. Re co m Note: The burst counter wraps to initial state on the 5th clock. No t BPR 1999.05.18 Rev: 1.07 9/2008 8/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) GW BW BA BB BC BD Notes Read H H X X X X 1 Write No Bytes H L H H H H 1 Write byte a H L L Write byte b H L H Write byte c H L H Write byte d H L H Write all bytes H L L ct Function n— Di sco nt inu ed Pr od u Byte Write Truth Table H H H 2, 3 L H H 2, 3 H L H 2, 3, 4 H H L 2, 3, 4 L L L 2, 3, 4 No t Re co m me nd ed for Ne w De sig Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs, BA, BB, BC and/or BD. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x32 and x36 versions. Rev: 1.07 9/2008 9/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) Synchronous Truth Table DQ3 X X High-Z L X X High-Z L X X X High-Z X L X X X High-Z X X X L X X High-Z H L L X X X Q H L H L X F Q H L H L X T D X X H H L F Q X X X H L F Q X X H H L T D E2 E3 X H X L L X X X H L None X L Deselect Cycle, Power Down None X L Deselect Cycle, Power Down None X L Deselect Cycle, Power Down None X L Deselect Cycle, Power Down None X H Read Cycle, Begin Burst External R L Read Cycle, Begin Burst External R L Write Cycle, Begin Burst External W L Read Cycle, Continue Burst Next CR X Read Cycle, Continue Burst Next CR H Write Cycle, Continue Burst Next CW X Write Cycle, Continue Burst Next CW Read Cycle, Suspend Burst Current Read Cycle, Suspend Burst Current Write Cycle, Suspend Burst Current Write Cycle, Suspend Burst Current De sig Deselect Cycle, Power Down ADSP ADSC ADV H X X X H L T D X X X H H H F Q H X X X H H F Q X X X H H H T D H X X X H H T D Ne w me nd ed for W E1 ct Operation n— Di sco nt inu ed Pr od u State Address Diagram Used Key No t Re co m Notes: 1. X = Don’t Care, H = High, L = Low 2. E = T (True) if E2 = 1 and E1 = E3 = 0; E = F (False) if E2 = 0 or E1 = 1 or E3 = 1 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.07 9/2008 10/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) Simplified State Diagram n— Di sco nt inu ed Pr od u ct X Deselect W R X R R First Write CR X CR Ne w De sig CW First Read me nd ed for W X R R Burst Write Burst Read X CR CW CR Re co m Simple Burst Synchronous Operation Simple Synchronous Operation W No t Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and assumes ADSP is tied high and ADV is tied low. Rev: 1.07 9/2008 11/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) Simplified State Diagram with G ct X W R W X n— Di sco nt inu ed Pr od u Deselect R R First Write CR First Read CW X CR W Burst Write me nd ed for X Ne w De sig CW W R CR CW R W Burst Read X CW CR No t Re co m Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.07 9/2008 12/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) Absolute Maximum Ratings (All voltages reference to VSS) Description Value Unit VDD Voltage on VDD Pins –0.5 to 4.6 V VDDQ Voltage in VDDQ Pins –0.5 to 4.6 VI/O Voltage on I/O Pins VIN Voltage on Other Input Pins IIN Input Current on Any Pin IOUT Output Current on Any I/O Pin PD Package Power Dissipation TSTG Storage Temperature TBIAS Temperature Under Bias n— Di sco nt inu ed Pr od u ct Symbol V –0.5 to VDDQ +0.5 V –0.5 to VDD +0.5 V +/–20 mA +/–20 mA 1.5 W –55 to 125 oC –55 to 125 oC De sig Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges Symbol Min. Typ. Max. Unit 3.3 V Supply Voltage VDD3 3.3 3.6 V VDD2 2.3 2.5 2.7 V 3.3 V VDDQ I/O Supply Voltage VDDQ3 3.0 3.3 3.6 V 2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 2.7 V me nd ed for 3.0 2.5 V Supply Voltage Ne w Parameter Notes No t Re co m Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+1.5 V maximum, with a pulse width not to exceed 50% tKC. Rev: 1.07 9/2008 13/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 2.0 — VDD + 0.3 V 1 VDD Input Low Voltage VIL –0.3 — 0.8 V 1 VDDQ I/O Input High Voltage VIHQ 2.0 — VDDQ + 0.3 V 1,3 VDDQ I/O Input Low Voltage VILQ –0.3 — 0.8 V 1,3 n— Di sco nt inu ed Pr od u Parameter ct VDDQ3 Range Logic Levels Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+1.5 V maximum, with a pulse width not to exceed 50% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Parameter Symbol Typ. Max. Unit Notes VDD Input High Voltage VIH 0.6*VDD — VDD + 0.3 V 1 VDD Input Low Voltage VIL –0.3 — 0.3*VDD V 1 VDDQ I/O Input High Voltage VIHQ 0.6*VDD — VDDQ + 0.3 V 1,3 VDDQ I/O Input Low Voltage –0.3 — 0.3*VDD V 1,3 De sig Min. Ne w VDDQ2 Range Logic Levels VILQ me nd ed for Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+1.5 V maximum, with a pulse width not to exceed 50% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Recommended Operating Temperatures Symbol Min. Typ. Max. Unit Notes Ambient Temperature (Commercial Range Versions) TA 0 25 70 °C 2 Ambient Temperature (Industrial Range Versions) TA –40 25 85 °C 2 Re co m Parameter No t Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+1.5 V maximum, with a pulse width not to exceed 50% tKC. Rev: 1.07 9/2008 14/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 50% tKC VDD +1.5 V VSS n— Di sco nt inu ed Pr od u 50% ct 50% VDD VSS – 2.0 V 50% tKC VIL Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF AC Test Conditions Conditions Input high level VDD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDD/2 Output load me nd ed for Output reference level Ne w Parameter De sig Note: These parameters are sample tested. VDDQ/2 Fig. 1 Output Load 1 DQ No t Re co m Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. 50Ω 30pF* VDDQ/2 * Distributed Test Jig Capacitance Rev: 1.07 9/2008 15/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) DC Electrical Characteristics Symbol Test Conditions Min Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA ZZ Input Current IIN1 VDD ≥ VIN ≥ VIH 0 V ≤ VIN ≤ VIH FT, SCD, ZQ Input Current IIN2 Output Leakage Current IOL Output High Voltage VOH2 Output High Voltage VOH3 Output Low Voltage VOL ct Parameter 1 uA 100 uA VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL –100 uA –1 uA 1 uA 1 uA Output Disable, VOUT = 0 to VDD –1 uA 1 uA IOH = –8 mA, VDDQ = 2.375 V 1.7 V — IOH = –8 mA, VDDQ = 3.135 V 2.4 V — IOL = 8 mA — 0.4 V No t Re co m me nd ed for Ne w De sig n— Di sco nt inu ed Pr od u –1 uA –1 uA Rev: 1.07 9/2008 16/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) Operating Currents -250 Mode Symbol Operating Current ZZ ≥ VDD – 0.2 V — Deselect Current Device Deselected; All other inputs ≥ VIH or ≤ VIL — 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C Unit IDD IDDQ 305 40 315 40 255 30 265 30 205 20 215 20 mA Flow Through IDD IDDQ 235 20 245 20 205 15 215 15 190 15 200 15 mA Pipeline IDD IDDQ 275 20 285 20 230 15 240 15 185 15 195 15 mA Flow Through IDD IDDQ 215 10 225 10 190 10 200 10 175 10 185 10 mA Pipeline ISB 40 50 40 50 40 50 mA Flow Through ISB 40 50 40 50 40 50 mA Pipeline IDD 85 90 75 80 60 65 mA Flow Through IDD 60 65 50 55 50 55 mA (x18) Standby Current –40 to 85°C Pipeline (x36) Device Selected; All other inputs ≥VIH or ≤ VIL Output open 0 to 70°C ct Test Conditions -150 n— Di sco nt inu ed Pr od u Parameter -200 No t Re co m me nd ed for Ne w De sig Notes: 1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation. 2. All parameters listed are worst case scenario. Rev: 1.07 9/2008 17/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) AC Electrical Characteristics Clock to Output Valid tKQ Clock to Output Invalid tKQX Clock to Output in Low-Z tLZ1 Setup time tS Hold time tH Clock Cycle Time tKC Clock to Output Valid tKQ Clock to Output Invalid tKQX Clock to Output in Low-Z tLZ1 Setup time tS Hold time tH Clock HIGH Time tKH Clock LOW Time tKL Clock to Output in High-Z tHZ1 G to Output Valid -150 Min Max Min Max Min Max 4.0 — 5.0 — 6.7 — ct tKC -200 Unit ns — 2.5 — 3.0 — 3.8 ns 1.5 — 1.5 — 1.5 — ns 1.5 — 1.5 — 1.5 — ns 1.2 — 1.4 — 1.5 — ns 0.2 — 0.4 — 0.5 — ns 5.5 — 6.5 — 7.5 — ns — 5.5 — 6.5 — 7.5 ns 2.0 — 2.0 — 2.0 — ns 2.0 — 2.0 — 2.0 — ns 1.5 — 1.5 — 1.5 — ns n— Di sco nt inu ed Pr od u Clock Cycle Time -250 0.5 — 0.5 — 0.5 — ns 1.3 — 1.3 — 1.5 — ns 1.5 — 1.5 — 1.7 — ns 1.5 2.5 1.5 3.0 1.5 3.0 ns tOE — 2.5 — 3.0 — 3.8 ns G to output in Low-Z tOLZ1 0 — 0 — 0 — ns G to output in High-Z tOHZ1 — 2.5 — 3.0 — 3.8 ns tZZS2 5 — 5 — 5 — ns tZZH2 1 — 1 — 1 — ns tZZR 20 — 20 — 20 — ns ZZ setup time me nd ed for ZZ hold time De sig Flow Through Symbol Ne w Pipeline Parameter ZZ recovery No t Re co m Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.07 9/2008 18/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) Pipeline Mode Timing (SCD) Cont Cont Deselect Write B Single Read Read C+1 Read C+2 Read C+3 Cont Single Write tKL tKH tKC CK ADSP tS tH Deselect Burst Read ADSC initiated read ADSC tS tH ADV tS tH A0–An Read C ct Read A n— Di sco nt inu ed Pr od u Begin A B tS GW tS C tH De sig BW tH tS tS tH E1 tH E2 tS tH E3 Re co m G me nd ed for tS E1 masks ADSP E2 and E3 only sampled with ADSP and ADSC tOE tS tOHZ Q(A) tKQ tH D(B) tKQX tLZ tHZ Q(C) Q(C+1) Q(C+2) Q(C+3) No t DQa–DQd Deselected with E1 Ne w Ba–Bd Rev: 1.07 9/2008 19/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) Flow Through Mode Timing (SCD) Begin Read A Cont Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont Deselect tKL tKC ct tKH n— Di sco nt inu ed Pr od u CK ADSP Fixed High tS tH tS tH initiated read ADSC ADSC tS tH ADV tS tH A0–An A B C tS tH tS tH BW Ba–Bd tS E1 tS tH E2 tS tH E3 E2 and E3 only sampled with ADSC Re co m G tH tS tOE tOHZ Q(A) D(B) tKQ tLZ tHZ tKQX Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C) No t DQa–DQd Deselected with E1 me nd ed for tH Ne w tS tH De sig GW Rev: 1.07 9/2008 20/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) Pipeline Mode Timing (DCD) Read A Cont Deselect Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont tKC CK ADSP tS ADSC initiated read tH ADSC tS tH ADV tS tH Ao–An A B C tS GW tS tH BW Ba–Bd tS tH tS E2 and E3 only sampled with ADSC tH tH G me nd ed for E2 E3 tS tOE Hi-Z tOHZ Q(A) tKQ tH D(B) tHZ tLZ tKQX Q(C) Q(C+1) Q(C+2) Q(C+3) No t Re co m DQa–DQd Deselected with E1 Ne w E1 De sig tH tS tS n— Di sco nt inu ed Pr od u tKL tKH Deselect Deselect ct Begin Rev: 1.07 9/2008 21/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) Flow Through Mode Timing (DCD) Read A Cont Deselect Write B Read C tKH tKC CK ADSP tS tH ADSC initiated read ADSC tH tS tS ADV tS tH A B C tS tH tS tH BW Ba–Bd tS tH tS tH E2 tS tH E3 E2 and E3 only sampled with ADSP and ADSC Re co m G Deselected with E1 E1 masks ADSP me nd ed for E1 Ne w tH tS tH De sig GW E1 masks ADSP tH tS tOE tKQ tOHZ Q(A) tKQX tHZ tLZ D(B) Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C) No t DQa–DQd Deselect Fixed High tS tH Ao–An Read C+1 Read C+2 Read C+3 Read C n— Di sco nt inu ed Pr od u tKL ct Begin Rev: 1.07 9/2008 22/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. n— Di sco nt inu ed Pr od u ct Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. Sleep Mode Timing tKH tKC tKL CK Setup Hold De sig ADSP ADSC tZZR tZZH Ne w tZZS ZZ me nd ed for Application Tips No t Re co m Single and Dual Cycle Deselect SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention. Rev: 1.07 9/2008 23/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) JTAG Port Operation n— Di sco nt inu ed Pr od u ct Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. JTAG Port Registers JTAG Pin Descriptions Pin Name I/O TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS Test Mode Select In The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. In The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. TDO Test Data Out Ne w Test Data In Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. me nd ed for TDI Description De sig Pin Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. Re co m Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. No t Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible. Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the Rev: 1.07 9/2008 24/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. · · · · · Boundary Scan Register · · · · 1 · 0 Bypass Register 2 1 0 0 108 n— Di sco nt inu ed Pr od u · ct JTAG TAP Block Diagram De sig Instruction Register TDI TDO ID Code Register · · ·· 2 1 0 Ne w 31 30 29 TCK me nd ed for Control Signals TMS Test Access Port (TAP) Controller No t Re co m Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. Rev: 1.07 9/2008 25/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) GSI Technology JEDEC Vendor ID Code I/O Configuration n— Di sco nt inu ed Pr od u Not Used ct Die Revision Code Presence Register Tap Controller Instruction Set ID Register Contents Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x36 X X X X 0 0 0 X 1 0 0 1 0 0 x18 X X X X 0 0 0 X 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. No t Re co m me nd ed for Ne w De sig When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. Rev: 1.07 9/2008 26/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) JTAG Tap Controller State Diagram Test Logic Reset 1 0 Run Test Idle 1 Select DR 1 0 1 Capture DR 0 Capture IR 0 Shift DR 1 1 ct 0 1 Shift IR 0 1 1 Exit1 DR 0 Exit1 IR 0 0 Pause DR 1 Exit2 DR De sig 1 Update DR 0 0 Pause IR 1 Exit2 IR 0 1 0 0 Update IR 1 0 Ne w 1 1 Select IR n— Di sco nt inu ed Pr od u 0 me nd ed for Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. No t Re co m SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins. Rev: 1.07 9/2008 27/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state. n— Di sco nt inu ed Pr od u ct Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU No t Re co m me nd ed for Ne w De sig These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.07 9/2008 28/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) JTAG Port AC Test Conditions Conditions Input high level VDD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDDQ/2 Output reference level VDDQ/2 JTAG Port AC Test Load DQ n— Di sco nt inu ed Pr od u ct Parameter 50Ω 30pF* VDDQ/2 * Distributed Test Jig Capacitance Notes: 1. Include scope and jig capacitance. 2. Test conditions as shown unless otherwise noted. JTAG TAP Instruction Set Summary Code Description Notes EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1 IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2 SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. 1 RFU 011 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 SAMPLE/ PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 1 GSI 101 GSI private instruction. 1 RFU 110 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 me nd ed for Ne w De sig Instruction 1 No t Re co m BYPASS 111 Places Bypass Register between TDI and TDO. Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.07 9/2008 29/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) JTAG Port Recommended Operating Conditions and DC Characteristics Symbol Min. Max. 3.3 V Test Port Input High Voltage VIHJ3 2.0 VDD3 +0.3 V 1 3.3 V Test Port Input Low Voltage VILJ3 –0.3 0.8 V 1 2.5 V Test Port Input High Voltage VIHJ2 0.6 * VDD2 VDD2 +0.3 V 1 2.5 V Test Port Input Low Voltage VILJ2 –0.3 0.3 * VDD2 V 1 IINHJ –300 1 uA 2 IINLJ –1 100 uA 3 IOLJ –1 1 uA 4 VOHJ 1.7 — V 5, 6 VOLJ — 0.4 V 5, 7 VOHJC VDDQ – 100 mV — V 5, 8 VOLJC — 100 mV V 5, 9 n— Di sco nt inu ed Pr od u TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output High Voltage Test Port Output Low Voltage Test Port Output CMOS High Test Port Output CMOS Low Unit Notes ct Parameter Ne w De sig Notes: 1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +1.5 V maximum, with a pulse width not to exceed 50% tTKC. 2. VILJ ≤ VIN ≤ VDDn 3. 0 V ≤ VIN ≤ VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = –4 mA 7. IOLJ = + 4 mA 8. IOHJC = –100 uA 9. IOHJC = +100 uA me nd ed for JTAG Port Timing Diagram tTKC TCK tTKH tTKL tTH tTS TDI tTH TMS TDO Re co m tTS tTKQ tTH tTS No t Parallel SRAM input Rev: 1.07 9/2008 30/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) Symbol Min Max Unit TCK Cycle Time tTKC 50 — ns TCK Low to TDO Valid tTKQ — 20 ns TCK High Pulse Width tTKH 20 — TCK Low Pulse Width tTKL 20 — TDI & TMS Set Up Time tTS 10 — TDI & TMS Hold Time tTH 10 — n— Di sco nt inu ed Pr od u Parameter ct JTAG Port AC Electrical Characteristics ns ns ns ns No t Re co m me nd ed for Ne w De sig Boundary Scan (BSDL Files) For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications Engineering Department at: [email protected]. Rev: 1.07 9/2008 31/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) Package Dimensions—119-Bump FPBGA (Package B, Variation 2) TOP VIEW 2 3 4 5 6 7 7 6 5 4 3 2 1 20.32 De sig 22±0.10 1.27 A B C D E F G H J K L M N P R T U ct 1 BOTTOM VIEW A1 Ø0.10S C Ø0.30S C AS B S Ø0.60~0.90 (119x) n— Di sco nt inu ed Pr od u A1 A B C D E F G H J K L M N P R T U 1.27 7.62 A 0.20(4x) 14±0.10 SEATING PLANE No t Re co m C 0.50~0.70 1.86.±0.13 me nd ed for 0.15 C Ne w B Rev: 1.07 9/2008 32/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) Package Dimensions—165-Bump FPBGA (Package D) A1 TOP BOTTOM Ø0.10M C Ø0.25M C A B Ø0.40~0.60 ct 1 2 3 4 5 6 7 8 9 10 A1 SEATING 14. 1.0 1.0 10. 13±0.0 0.20(4 No t Re co m 0.36~0.4 1.40 C B 1.0 A B C D E F G H J K L M N P R me nd ed for 0.15 C Ne w A De sig 15±0.0 1.0 A B C D E F G H J K L M N P R n— Di sco nt inu ed Pr od u 11 10 9 8 7 6 5 4 3 2 Rev: 1.07 9/2008 33/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) Ordering Information for GSI Synchronous Burst RAMs TA3 119 BGA (Var. 2) 250/5.5 C 119 BGA (Var. 2) 200/6.5 C 119 BGA (Var. 2) 150/7.5 C 119 BGA (Var. 2) 250/5.5 C 119 BGA (Var. 2) 200/6.5 C 119 BGA (Var. 2) 150/7.5 C 119 BGA (Var. 2) 250/5.5 I 119 BGA (Var. 2) 200/6.5 I 119 BGA (Var. 2) 150/7.5 I 119 BGA (Var. 2) 250/5.5 I 119 BGA (Var. 2) 200/6.5 I Pipeline/Flow Through 119 BGA (Var. 2) 150/7.5 I GS816218BGB-250 Pipeline/Flow Through RoHS-compliant 119 BGA (Var. 2) 250/5.5 C 1M x 18 GS816218BGB-200 Pipeline/Flow Through RoHS-compliant 119 BGA (Var. 2) 200/6.5 C 1M x 18 GS816218BGB-150 Pipeline/Flow Through RoHS-compliant 119 BGA (Var. 2) 150/7.5 C 512K x 36 GS816236BGB-250 Pipeline/Flow Through RoHS-compliant 119 BGA (Var. 2) 250/5.5 C 512K x 36 GS816236BGB-200 Pipeline/Flow Through RoHS-compliant 119 BGA (Var. 2) 200/6.5 C 512K x 36 GS816236BGB-150 Pipeline/Flow Through RoHS-compliant 119 BGA (Var. 2) 150/7.5 C 1M x 18 GS816218BGB-250I Pipeline/Flow Through RoHS-compliant 119 BGA (Var. 2) 250/5.5 I 1M x 18 GS816218BGB-200I Pipeline/Flow Through RoHS-compliant 119 BGA (Var. 2) 200/6.5 I 1M x 18 GS816218BGB-150I Pipeline/Flow Through RoHS-compliant 119 BGA (Var. 2) 150/7.5 I 512K x 36 GS816236BGB-250I Pipeline/Flow Through RoHS-compliant 119 BGA (Var. 2) 250/5.5 I 512K x 36 GS816236BGB-200I Pipeline/Flow Through RoHS-compliant 119 BGA (Var. 2) 200/6.5 I 512K x 36 GS816236BGB-150I Pipeline/Flow Through RoHS-compliant 119 BGA (Var. 2) 150/7.5 I Part Number1 Type 1M x 18 GS816218BB-250 Pipeline/Flow Through 1M x 18 GS816218BB-200 Pipeline/Flow Through 1M x 18 GS816218BB-150 Pipeline/Flow Through 512K x 36 GS816236BB-250 Pipeline/Flow Through 512K x 36 GS816236BB-200 Pipeline/Flow Through 512K x 36 GS816236BB-150 Pipeline/Flow Through 1M x 18 GS816218BB-250I Pipeline/Flow Through 1M x 18 GS816218BB-200I Pipeline/Flow Through 1M x 18 GS816218BB-150I Pipeline/Flow Through 512K x 36 GS816236BB-250I Pipeline/Flow Through 512K x 36 GS816236BB-200I Pipeline/Flow Through 512K x 36 GS816236BB-150I 1M x 18 De sig Ne w me nd ed for Re co m No t n— Di sco nt inu ed Pr od u Package ct Speed2 (MHz/ns) Org Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816236BD-200IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings Rev: 1.07 9/2008 34/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) Ordering Information for GSI Synchronous Burst RAMs (Continued) Part Number1 Type Package Speed2 (MHz/ns) TA3 1M x 18 GS816218BGB-150 Pipeline/Flow Through RoHS-compliant 119 BGA (Var. 2) 150/7.5 C 512K x 36 GS816236BGB-250 Pipeline/Flow Through RoHS-compliant 119 BGA (Var. 2) 250/5.5 C 512K x 36 GS816236BGB-200 Pipeline/Flow Through RoHS-compliant 119 BGA (Var. 2) 200/6.5 C 512K x 36 GS816236BGB-150 Pipeline/Flow Through RoHS-compliant 119 BGA (Var. 2) 150/7.5 C 1M x 18 GS816218BGB-250I Pipeline/Flow Through RoHS-compliant 119 BGA (Var. 2) 250/5.5 I 1M x 18 GS816218BGB-200I Pipeline/Flow Through RoHS-compliant 119 BGA (Var. 2) 200/6.5 I 1M x 18 GS816218BGB-150I Pipeline/Flow Through RoHS-compliant 119 BGA (Var. 2) 150/7.5 I 512K x 36 GS816236BGB-250I Pipeline/Flow Through RoHS-compliant 119 BGA (Var. 2) 250/5.5 I 512K x 36 GS816236BGB-200I Pipeline/Flow Through RoHS-compliant 119 BGA (Var. 2) 200/6.5 I 512K x 36 GS816236BGB-150I Pipeline/Flow Through RoHS-compliant 119 BGA (Var. 2) 150/7.5 I 1M x 18 GS816218BD-250 Pipeline/Flow Through 165 BGA 250/5.5 C 1M x 18 GS816218BD-200 Pipeline/Flow Through 165 BGA 200/6.5 C 1M x 18 GS816218BD-150 Pipeline/Flow Through 165 BGA 150/7.5 C 512K x 36 GS816236BD-250 Pipeline/Flow Through 165 BGA 250/5.5 C 512K x 36 GS816236BD-200 Pipeline/Flow Through 165 BGA 200/6.5 C 512K x 36 GS816236BD-150 Pipeline/Flow Through 165 BGA 150/7.5 C 1M x 18 GS816218BD-250I Pipeline/Flow Through 165 BGA 250/5.5 I 1M x 18 GS816218BD-200I Pipeline/Flow Through 165 BGA 200/6.5 I 1M x 18 GS816218BD-150I Pipeline/Flow Through 165 BGA 150/7.5 I 512K x 36 GS816236BD-250I Pipeline/Flow Through 165 BGA 250/5.5 I 512K x 36 GS816236BD-200I Pipeline/Flow Through 165 BGA 200/6.5 I 512K x 36 GS816236BD-150I Pipeline/Flow Through 165 BGA 150/7.5 I 1M x 18 GS816218BGD-250 Pipeline/Flow Through RoHS-compliant 165 BGA 250/5.5 C 1M x 18 GS816218BGD-200 Pipeline/Flow Through RoHS-compliant 165 BGA 200/6.5 C 1M x 18 GS816218BGD-150 Pipeline/Flow Through RoHS-compliant 165 BGA 150/7.5 C 512K x 36 GS816236BGD-250 Pipeline/Flow Through RoHS-compliant 165 BGA 250/5.5 C n— Di sco nt inu ed Pr od u De sig Ne w me nd ed for Re co m No t ct Org Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816236BD-200IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings Rev: 1.07 9/2008 35/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) Ordering Information for GSI Synchronous Burst RAMs (Continued) Part Number1 Type Package Speed2 (MHz/ns) TA3 512K x 36 GS816236BGD-200 Pipeline/Flow Through RoHS-compliant 165 BGA 200/6.5 C 512K x 36 GS816236BGD-150 Pipeline/Flow Through RoHS-compliant 165 BGA 150/7.5 C 1M x 18 GS816218BGD-250I Pipeline/Flow Through RoHS-compliant 165 BGA 250/5.5 I 1M x 18 GS816218BGD-200I Pipeline/Flow Through RoHS-compliant 165 BGA 200/6.5 I 1M x 18 GS816218BGD-150I Pipeline/Flow Through RoHS-compliant 165 BGA 150/7.5 I 512K x 36 GS816236BGD-250I Pipeline/Flow Through RoHS-compliant 165 BGA 250/5.5 I 512K x 36 GS816236BGD-200I Pipeline/Flow Through RoHS-compliant 165 BGA 200/6.5 I 512K x 36 GS816236BGD-150I Pipeline/Flow Through RoHS-compliant 165 BGA 150/7.5 I 512K x 36 GS816236BGD-250 Pipeline/Flow Through RoHS-compliant 165 BGA 250/5.5 C 512K x 36 GS816236BGD-200 Pipeline/Flow Through RoHS-compliant 165 BGA 200/6.5 C 512K x 36 GS816236BGD-150 Pipeline/Flow Through RoHS-compliant 165 BGA 150/7.5 C 1M x 18 GS816218BGD-250I Pipeline/Flow Through RoHS-compliant 165 BGA 250/5.5 I 1M x 18 GS816218BGD-200I Pipeline/Flow Through RoHS-compliant 165 BGA 200/6.5 I 1M x 18 GS816218BGD-150I Pipeline/Flow Through RoHS-compliant 165 BGA 150/7.5 I 512K x 36 GS816236BGD-250I Pipeline/Flow Through RoHS-compliant 165 BGA 250/5.5 I 512K x 36 GS816236BGD-200I Pipeline/Flow Through RoHS-compliant 165 BGA 200/6.5 I 512K x 36 GS816236BGD-150I Pipeline/Flow Through RoHS-compliant 165 BGA 150/7.5 I n— Di sco nt inu ed Pr od u De sig Ne w ct Org No t Re co m me nd ed for Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816236BD-200IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings Rev: 1.07 9/2008 36/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology GS816218/36B(B/D) 18Mb Sync SRAM Datasheet Revision History Types of Changes Format or Content Page;Revisions;Reason • Creation of new datasheet Content 8162xxB_r1_01; 8162xxB_r1_02 Content 8162xxB_r1_02; 8162xxB_r1_03 Content 8162xxB_r1_03; 8162xxB_r1_04 Content 8162xxB_r1_04; 8162xxB_r1_05 Content Content 8162xxB_r1_06; 8162xxB_r1_07 Content • Added 300 MHz speed bin • Added 165 BGA package • Added status column for ordering information • Changed Pb-free to RoHS-compliant • Removed 300 MHz speed bin • Changed Pin 16 from VDD to NC • Added (MCL) Must Connect Low to pin description • Rev. 1.06a Updated Mechanical Drawing • Rev. 1.06a Removed Status column from Ordering Information table • Updated for MP status No t Re co m me nd ed for Ne w 8162xxB_r1_05; 8162xxB_r1_06 • Updated overshoot/undershoot information • Added Pb-Free 119 BGA information n— Di sco nt inu ed Pr od u 8162xxB_r1; 8162xxB_r1_01 De sig 8162xxB_r1 ct DS/DateRev. Code: Old; New Rev: 1.07 9/2008 37/37 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2004, GSI Technology