DM8806/DM8806I - Davicom Semiconductor Inc.

DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
DAVICOM Semiconductor, Inc.
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
DATA SHEET
Preliminary
Version: DM8806-14-3-DS-P02
January 9, 2013
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
1
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
CONTENT
1.
2.
3.
General Description ...................................................................................................... 9
Block Diagram............................................................................................................... 9
Features ....................................................................................................................... 10
4.
Pin Configuration ........................................................................................................ 12
4.1
Pin Diagram ........................................................................................................ 12
4.2
Pin Description .................................................................................................. 13
4.2.1
LED Pins ......................................................................................................... 13
4.2.2
4.2.3
4.2.4
EEPROM Interface .......................................................................................... 15
Clock Interface................................................................................................ 15
Network Interface ........................................................................................... 16
4.2.5
4.2.6
4.2.7
4.2.8
Port 4 MAC MII/RevMII/RMII and PHY MII/RMII Interfaces ........................... 17
Port 5 MAC Interfaces .................................................................................... 20
Miscellaneous Pins ........................................................................................ 22
Power Pins ...................................................................................................... 23
4.3
Strap Pins Table ................................................................................................. 24
5.
Control and Status Register Set ................................................................................ 26
5.1
Register Table .................................................................................................... 26
5.2
Internal PHY Registers ...................................................................................... 32
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
Port 0~4 PHY Control Register...................................................................... 32
Port 0~4 PHY Status Register ....................................................................... 33
Port 0~4 PHY Identifier 1 Register ................................................................ 34
Port 0~4 PHY Identifier 2 Register ................................................................ 34
Port 0~4 PHY Auto-Negotiation Advertisement Register............................ 35
Port 0~4 PHY Auto-Negotiation Link Partner Ability Register.................... 36
5.2.7
5.2.8
Port 0~4 PHY Auto-Negotiation Expansion Register .................................. 37
Port 0~4 PHY Specific Control 1 Register .................................................... 38
5.2.9
Port 0~4 PHY Specific Control 2 Register .................................................... 39
5.2.10 Port 0~4 PHY Power Saving Control Register ............................................. 40
5.3
Switch Per-Port Registers ................................................................................. 41
5.3.1
Per Port Status Data Register ....................................................................... 41
5.3.2
Per Port Basic Control 0 Register ................................................................. 41
5.3.3
5.3.4
5.3.5
Per Port Basic Control 1 Register ................................................................. 43
Per Port Block Control 0 Register................................................................. 45
Per Port Block Control 1 Register................................................................. 46
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January 9, 2013
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DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.3.6
5.3.7
Per Port Bandwidth Control Register ........................................................... 47
Per Port VLAN Tag Infomation Register ....................................................... 49
5.3.8
5.3.9
5.3.10
Per Port Priority and VLAN Control Register ............................................... 50
Per Port Security Control Register ............................................................... 52
Per Port Advanced Control Register ............................................................ 52
5.3.11 Per Port Memory Control Register................................................................ 54
5.3.12 Per Port Discard Limitation Register ............................................................ 54
5.3.13 Per Port Energy Efficient Ethernet Control Register................................... 55
5.4
Switch Engine Registers ................................................................................... 56
5.4.1
5.4.2
5.4.3
5.4.4
Switch Status Register (210h) ....................................................................... 56
Switch Reset Register (211h) ........................................................................ 56
Switch Control Register Register (212h) ...................................................... 57
CPU Port & Mirror Control Register (213h) .................................................. 58
5.4.5
5.4.6
5.4.7
Special Tag Ether-Type Register (214h) ....................................................... 58
Global Learning & Aging Control Register (215h) ....................................... 59
VLAN Priority Map Register (217H)............................................................... 60
5.4.8
5.4.9
5.4.10
5.4.11
TOS Priority Map 0 Register (218h) .............................................................. 61
TOS Priority Map 1 Register (219h) .............................................................. 61
TOS Priority Map 2 Register (21Ah) .............................................................. 62
TOS Priority Map 3 Register (21Bh) .............................................................. 62
5.4.12
5.4.13
5.4.14
5.4.15
5.4.16
5.4.17
TOS Priority Map 4 Register (21Ch) .............................................................. 63
TOS Priority Map 5 Register (21Dh) .............................................................. 63
TOS Priority Map 6 Register (21Eh) .............................................................. 64
TOS Priority Map 7 Register (21Fh) .............................................................. 64
MIB Counter Disable Register (230h) ........................................................... 65
MIB Counter Control Register (231h) ........................................................... 65
5.4.18
5.4.19
MIB Counter Data Low Register (232h) ........................................................ 65
MIB Counter Data High Register (233h) ....................................................... 65
5.4.20
5.4.21
5.4.22
5.4.23
5.4.24
Special Packet Control 0 Register (234h)..................................................... 66
Special Packet Control 1 Register (235h)..................................................... 67
Special Packet Control 2 Register (236h)..................................................... 68
Special Packet Control 3 Register (237h)..................................................... 69
Special Packet Control 4 Register (238h)..................................................... 70
5.4.25
5.4.26
5.4.27
Special Packet Control 5 Register (239h)..................................................... 71
Special Packet Control 6 Register (23Ah) .................................................... 72
Special Packet Control 7 Register (23Bh) .................................................... 73
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6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.28
5.4.29
Special Packet Control 8 Register (23Ch) .................................................... 74
QinQ TPID Register (23Dh) ............................................................................ 75
5.4.30
5.4.31
5.4.32
VLAN Mode and Rule Control Register (23Eh) ............................................ 75
VLAN Table - Valid Control Register (23Fh) ................................................. 77
VLAN Table - ID_0H Register (250h) ............................................................. 77
5.4.33
5.4.34
5.4.35
5.4.36
VLAN Table - ID_1H Register (251h) ............................................................. 77
VLAN Table - ID_2H Register (252h) ............................................................. 77
VLAN Table - ID_3H Register (253h) ............................................................. 77
VLAN Table - ID_4H Register (254h) ............................................................. 77
5.4.37
5.4.38
5.4.39
5.4.40
VLAN Table - ID_5H Register (255h) ............................................................. 78
VLAN Table - ID_6H Register (256h) ............................................................. 78
VLAN Table - ID_7H Register (257h) ............................................................. 78
VLAN Table - ID_8H Register (258h) ............................................................. 78
5.4.41
5.4.42
5.4.43
VLAN Table - ID_9H Register (259h) ............................................................. 78
VLAN Table - ID_AH Register (25Ah) ............................................................ 78
VLAN Table - ID_BH Register (25Bh) ............................................................ 79
5.4.44
5.4.45
5.4.46
5.4.47
VLAN Table - ID_CH Register (25Ch) ............................................................ 79
VLAN Table - ID_DH Register (25Dh) ............................................................ 79
VLAN Table - ID_EH Register (25Eh) ............................................................ 79
VLAN Table - ID_FH Register (25Fh)............................................................. 79
5.4.48
5.4.49
5.4.50
5.4.51
5.4.52
5.4.53
VLAN Table - MEMBER_0H Register (270h) ................................................. 80
VLAN Table - MEMBER_1H Register (271h) ................................................. 80
VLAN Table - MEMBER_2H Register (272h) ................................................. 80
VLAN Table - MEMBER_3H Register (273h) ................................................. 81
VLAN Table - MEMBER_4H Register (274h) ................................................. 81
VLAN Table - MEMBER_5H Register (275h) ................................................. 81
5.4.54
5.4.55
VLAN Table - MEMBER_6H Register (276h) ................................................. 81
VLAN Table - MEMBER_7H Register (277h) ................................................. 82
5.4.56
5.4.57
5.4.58
5.4.59
5.4.60
VLAN Table - MEMBER_8H Register (278h) ................................................. 82
VLAN Table - MEMBER_9H Register (279h) ................................................. 82
VLAN Table - MEMBER_AH Register (27Ah)................................................ 82
VLAN Table - MEMBER_BH Register (27Bh)................................................ 83
VLAN Table - MEMBER_CH Register (27Ch)................................................ 83
5.4.61
5.4.62
5.4.63
VLAN Table - MEMBER_DH Register (27Dh)................................................ 83
VLAN Table - MEMBER_EH Register (27Eh) ................................................ 83
VLAN Table - MEMBER_FH Register (27Fh) ................................................ 84
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6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.64
5.4.65
VLAN Table - Priority Enable Register (290h) .............................................. 84
VLAN Table - STP Index Enable Register (292h) ......................................... 84
5.4.66
5.4.67
5.4.68
VLAN Table - Misc_0 Register (293h) ........................................................... 85
VLAN Table - Misc_1 Register (294h) ........................................................... 85
VLAN Table - Misc_2 Register (295h) ........................................................... 86
5.4.69
5.4.70
5.4.71
5.4.72
VLAN Table - Misc_3 Register (296h) ........................................................... 86
VLAN Table - Misc_4 Register (297h) ........................................................... 87
VLAN Table - Misc_5 Register (298h) ........................................................... 87
VLAN Table - Misc_6 Register (299h) ........................................................... 88
5.4.73
5.4.74
5.4.75
5.4.76
VLAN Table - Misc_7 Register (29Ah) ........................................................... 88
Snooping Control 0 Register (29Bh)............................................................. 89
Snooping Control 1 Register (29Ch)............................................................. 90
Address Table Control & Status Register (2B0h) ........................................ 91
5.4.77
5.4.78
5.4.79
Address Table Data 0 Register (2B1h) ......................................................... 92
Address Table Data 1 Register (2B2h) ......................................................... 92
Address Table Data 2 Register (2B3h) ......................................................... 92
5.4.80
5.4.81
5.4.82
5.4.83
Address Table Data 3 Register (2B4h) ......................................................... 92
Address Table Data 4 Register (2B5h) ......................................................... 92
Ethernet Address Register 0 for Magic Packet (2B8h)................................ 93
Ethernet Address Register 1 for Magic Packet (2B9h)................................ 93
5.4.84 Ethernet Address Register 2 for Magic Packet (2BAh) ............................... 93
5.4.85 WoL Control Register (2BBh) ........................................................................ 94
5.4.86 General Purpose I/O Control Register (2D0h) .............................................. 95
5.5
Chip Control and Status Registers................................................................... 96
5.5.1
Vendor ID Register (310h) ............................................................................. 96
5.5.2
Product ID Register (311h) ............................................................................ 96
5.5.3
5.5.4
Port 4 MAC Control Register (314h) ............................................................. 97
Port 5 MAC Control Register (315h) ............................................................. 98
5.5.5
5.5.6
5.5.7
5.5.8
5.5.9
Fiber Control Register (316h) ........................................................................ 99
IRQ and LED Control Register (317h) ......................................................... 100
Interrupt Status Register (318h) .................................................................. 101
Interrupt Mask & Control Register (319h) .................................................. 101
EEPROM Control & Address Register (31Ah) ............................................ 102
5.5.10
5.5.11
5.5.12
EEPROM Data Register (31Bh).................................................................... 102
Monitor Register 1 (31Ch) ............................................................................ 103
Monitor Register 2 (31Dh) ............................................................................ 103
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DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
6.
5.5.13
5.5.14
Monitor Register 3 (31Eh) ............................................................................ 104
Debug Monitor Pin Register (31Fh) ............................................................ 104
5.5.15
5.5.16
5.5.17
Memory Access Enable Register (330h) .................................................... 105
Memory Address Register (331h) ............................................................... 105
Memory Dummy Data Register (332h) ........................................................ 105
5.5.18
5.5.19
5.5.20
5.5.21
Memory Read Data Register (333h) ............................................................ 105
Memory Write Data Register (334h) ............................................................ 105
Memory Write Data Low Byte Register (335h) ........................................... 106
Memory Write Data High Byte Register (336h) .......................................... 106
5.5.22
5.5.23
5.5.24
5.5.25
System Clock Select Register (338h) ......................................................... 107
Serial Bus Error Check Register (339h) ..................................................... 107
Serial Bus Control Register (33Ah)............................................................. 107
Virtual PHY Control Register (33Dh)........................................................... 108
5.5.26 PHY Control Test Register (33Eh)............................................................... 108
5.5.27 Disable Port Control Register (399h) .......................................................... 109
EEPROM Format ....................................................................................................... 110
7.
Function Description ................................................................................................ 117
7.1
Switch Functions ............................................................................................. 117
7.1.1
Address Learning ......................................................................................... 117
7.1.2
Address Aging .............................................................................................. 117
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
Packet Forwarding ....................................................................................... 117
Inter-Packet Gap (IPG) ................................................................................. 118
Back-off Algorithm ....................................................................................... 118
Late Collision ................................................................................................ 118
Half Duplex Flow Control ............................................................................. 118
Full Duplex Flow Control ............................................................................. 118
7.1.9
7.1.10
Partition Mode .............................................................................................. 119
Broadcast Storm Filtering ........................................................................... 119
7.1.11
7.1.12
7.1.13
7.1.14
7.1.15
Bandwidth Control ....................................................................................... 119
Port Monitoring Support .............................................................................. 120
VLAN Support ............................................................................................... 121
Special Tag ................................................................................................... 122
Priority Support ............................................................................................ 124
7.1.16
7.1.17
7.1.18
Address Table Accessing............................................................................ 124
IGMP Snooping............................................................................................. 129
IPv6 MLD Snooping...................................................................................... 129
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6-Port 10/100Mb Fast Ethernet Smart Switch
7.1.19
7.1.20
STP / RSTP Support ..................................................................................... 130
Port Trunking Description ........................................................................... 132
7.2
Internal PHY Functions ................................................................................... 133
7.2.1
100Base-TX Operation ................................................................................. 133
7.2.2
100Base-TX Receiver ................................................................................... 136
7.2.3
7.2.4
7.2.5
7.2.6
10Base-T Operation ..................................................................................... 137
Collision Detection ....................................................................................... 137
Carrier Sense ................................................................................................ 138
Auto-Negotiation .......................................................................................... 138
7.2.7
Auto-MDIX Functional Description ............................................................. 138
7.2.8
Link Fault Pass-through and Far End Fault Functional Description ....... 139
7.3
Host SMI Interface............................................................................................ 140
7.3.1
Host SMI Bus Error Check Function........................................................... 141
7.4
LED Mode Control............................................................................................ 142
8.
DC and AC Electrical Characteristics ..................................................................... 145
8.1
Absolute Maximum Ratings ............................................................................ 145
8.2
Operating Conditions ...................................................................................... 145
8.3
DC Electrical Characteristics .......................................................................... 146
8.4
AC Characteristics ........................................................................................... 147
8.4.1
Power On Reset Timing ............................................................................... 147
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
MAC MII/RevMII Interface Transmit Timing ................................................ 148
MAC MII/RevMII Interface Receive Timing ................................................. 148
PHY MII Interface Transmit Timing ............................................................. 149
PHY MII Interface Receive Timing ............................................................... 149
MAC RMII Interface Transmit Timing .......................................................... 150
MAC RMII Interface Receive Timing ........................................................... 150
8.4.8
8.4.9
PHY RMII Interface Transmit Timing........................................................... 151
PHY RMII Interface Receive Timing ............................................................ 151
8.4.10 Host SMI Interface Timing ........................................................................... 152
8.4.11 PHY SMI Interface Timing ............................................................................ 153
8.4.12 EEPROM Timing ........................................................................................... 154
9.
Application Information............................................................................................ 155
9.1
Application of Reverse MII .............................................................................. 155
9.2
Application of Reduce MII to PHY .................................................................. 156
9.3
Application of Reduce MII to MAC.................................................................. 156
10. Package Information ................................................................................................ 157
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6-Port 10/100Mb Fast Ethernet Smart Switch
11.
Ordering Information ................................................................................................ 158
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DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
1. General Description
The DM8806 is a fully integrated and cost-effective industrial-temperature (DM8806I only) fast Ethernet
switch controller with five 10/100Mb PHY, and five 10/100Mb MAC plus one 10/100Mb MAC with
MII/RevMII/RMII.
The controller provides basic Layer-2 switch functions and advance IEEE 802.1Q VLAN, priority queuing
scheme, IEEE 802.3az Energy Efficient Ethernet, IGMP snooping protocol, Spanning Tree protocol. The
integrated 5 ports PHY are compliant with IEEE 802.3u standards. The MII/RMII/Reverse MII interface
provides the flexibility to connect Ethernet 10/100M PHY devices.
2. Block Diagram
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DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
3. Features
Ethernet Switch Ports:
Five 10/100Mb PHY built-in, that can be used for Copper or Fiber application
Port 4 support MII/RMII/RevMII interface to MAC or MII/RMII interface to internal
PHY
Port 5 support MII/RMII/RevMII interface to MAC
Supports auto crossover function - HP Auto-MDIX
Supports auto-polarity for 10Mbps
Supports Store-and-Forward and Cut-Through switching approach
Supports up to 2K accessible MAC address table
Automatic aging scheme
Flow control fully supported:
IEEE 802.3x flow control in full-duplex mode
Back Pressure flow control in half-duplex mode
Supports packet length up to 1536(default)/1552/1800/2032 bytes
Supports bandwidth control. Ingress and egress rate limit on each port.
Supports broadcast storming filter function for broadcast, multicast and
unknown unicast packets
Supports source address filtering
Supports high performance QoS function on each port:
4-level priority queues
Two type queue scheduling: Weighted Round Robin(WRR) and Strict
Priority(SP)
Port-based, 802.1p, IPv6 ToS Priority
Supports up to 16 VLAN groups:
802.1Q port-base and tag-based VLAN
Full 12-bit VID, 4-bit FID
Shared VLAN Learning (SVL) and Independent VLAN Learning(IVL)
VLAN tag Insert/Remove function
Leaky VLAN for unicast packets
VLAN priority replace function
Supports double tag (QinQ)
Supports trunk ports
Supports port-based and MAC-based mirror
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DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
Supports hardware IGMP v1,v2 Snooping
Supports hardware MLD v1 Snooping
Supports IEEE 802.3az Energy Efficient Ethernet (EEE)
Supports Link Fault Pass-through (LFP) and Far End Fault (FEF)
Supports spanning tree function:
IEEE 802.1D Spanning Tree Protocol (STP)
IEEE 802.1w Rapid STP (RSTP)
IEEE 802.1s Multiple STP (MSTP)
Supports 802.1x security function
Supports WOL standby mode
Supports Turbo RevMII mode on Port 4
Supports internal generated RMII 50MHz clock output
Supports optional EEPROM interface for configuration
Supports 64-bit MIB counters for diagnostic
Supports Serial Management Interface (SMI) for programming and
diagnostics
Supports interrupt pin for CPU application
Supports special tag to carry control and status between Switch and CPU
Supports four type LED display mode
Commercial temperature range: -0°°C to +70°°C
Industrial temperature range: -40°°C to +85°°C
25MHz Crystal
3.3V I/O with 5V tolerant
0.18um technology, 1.8/3.3V power supply
128-pin QFP package
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6-Port 10/100Mb Fast Ethernet Smart Switch
4. Pin Configuration
4.1 Pin Diagram
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6-Port 10/100Mb Fast Ethernet Smart Switch
4.2
Pin Description
Buffer type:
I = Input,
I/O = Input / Output,
ANA = Analog,
PU = Internal pull-up (about 50K Ohm),
PUR= Internal pull-up during PWRST# period,
# = Asserted Low
4.2.1
O = Output,
O/D = Open Drain,
P = Power,
PD = Internal pull-down,
PDR = Internal pull-down during PWRST# period,
LED Pins
Pin No.
Pin Name
Buffer
Type
PU
6mA
I/O
Description
42
P0_LNK_LED
O
P0_SPD_LED
PUR
6mA
O
113
P0_FDX_LED
PUR
6mA
O
43
P1_LNK_LED
PUR
6mA
O
104
P1_SPD_LED
PUR
6mA
O
112
P1_FDX_LED
PDR
6mA
O
47
P2_LNK_LED
PUR
6mA
O
103
P2_SPD_LED
PUR
6mA
O
111
P2_FDX_LED
PUR
6mA
O
48
P3_LNK_LED
PUR
6mA
O
PHY 0 LED (output after reset)
LED behavior can be configurable, see the LED
Control Register 317h. By default, this pin is used to
indicate Port 0 Link/Active status.
PHY 0 LED (output after reset)
LED behavior can be configurable, see the LED
Control Register 317h. By default, this pin is used to
indicate Port 0 Speed status.
PHY 0 LED (output after reset)
LED behavior can be configurable, see the LED
Control Register 317h. By default, this pin is used to
indicate Port 0 Duplex status.
PHY 1 LED (output after reset)
LED behavior can be configurable, see the LED
Control Register 317h. By default, this pin is used to
indicate Port 1 Link/Active status.
PHY 1 LED (output after reset)
LED behavior can be configurable, see the LED
Control Register 317h. By default, this pin is used to
indicate Port 1 Speed status.
PHY 1 LED (output after reset)
LED behavior can be configurable, see the LED
Control Register 317h. By default, this pin is used to
indicate Port 1 Duplex status.
PHY 2 LED (output after reset)
LED behavior can be configurable, see the LED
Control Register 317h. By default, this pin is used to
indicate Port 2 Link/Active status.
PHY 2 LED (output after reset)
LED behavior can be configurable, see the LED
Control Register 317h. By default, this pin is used to
indicate Port 2 Speed status.
PHY 2 LED (output after reset)
LED behavior can be configurable, see the LED
Control Register 317h. By default, this pin is used to
indicate Port 2 Duplex status.
PHY 3 LED (output after reset)
LED behavior can be configurable, see the LED
Control Register 317h. By default, this pin is used to
indicate Port 3 Link/Active status.
105
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6-Port 10/100Mb Fast Ethernet Smart Switch
102
P3_SPD_LED
PUR
6mA
O
110
P3_FDX_LED
PUR
6mA
O
51
P4_LNK_LED
PUR
6mA
O
101
P4_SPD_LED
PUR
6mA
O
107
P4_FDX_LED
PUR
6mA
O
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PHY 3 LED (output after reset)
LED behavior can be configurable, see the LED
Control Register 317h. By default, this pin is used to
indicate Port 3 Speed status.
PHY 3 LED (output after reset)
LED behavior can be configurable, see the LED
Control Register 317h. By default, this pin is used to
indicate Port 3 Duplex status.
PHY 4 LED (output after reset)
LED behavior can be configurable, see the LED
Control Register 317h. By default, this pin is used to
indicate Port 4 Link/Active status.
PHY 4 LED (output after reset)
LED behavior can be configurable, see the LED
Control Register 317h. By default, this pin is used to
indicate Port 4 Speed status.
PHY 4 LED (output after reset)
LED behavior can be configurable, see the LED
Control Register 317h. By default, this pin is used to
indicate Port 4 Duplex status.
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DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
4.2.2
EEPROM Interface
Pin No.
Pin Name
79
EEDIO
81
EECK
80
EECS
4.2.3
Buffer
Type
PD
4mA
PDR
4mA
PD
4mA
I/O
I/O
Description
I
O
25 MHz Crystal /Oscillator Input
Variation is limited to +/- 50 ppm.
25 MHz Crystal Output
When X1 is connected to oscillator, this pin should
be left unconnected.
I/O
O
O
Description
EEPROM Data In/Output
Drive/Read data to/from EEPROM
EEPROM Serial Clock
Drive clock to EEPROM
EEPROM Chip Selection.
Drive chip selection to EEPROM
Clock Interface
Pin No.
Pin Name
120
X1
Buffer
Type
ANA
121
X2
ANA
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
15
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
4.2.4
Network Interface
Pin No.
Pin Name
Buffer
Type
ANA
I/O
Description
2
3
P0_TXP0_TX+
I/O
P0_RXP0_RX+
ANA
I/O
10
11
P1_TXP1_TX+
ANA
I/O
14
15
P1_RXP1_RX+
ANA
I/O
18
19
P2_TXP2_TX+
ANA
I/O
21
22
P2_RXP2_RX+
ANA
I/O
25
26
P3_TXP3_TX+
ANA
I/O
29
30
P3_RXP3_RX+
ANA
I/O
32
33
P4_RX+
P4_RX-
ANA
I/O
36
37
P4_TX+
P4_TX-
ANA
I/O
127
BGRES
ANA
I/O
124
125
VCNTL
VREF
ANA
ANA
I/O
O
Port 0 TP TX
These two pins are the Twisted Pair transmit in
MDI mode or receive in MDIX mode.
Port 0 TP RX
These two pins are the Twisted Pair receive in
MDI mode or transmit in MDIX mode.
Port 1 TP TX
These two pins are the Twisted Pair transmit in
MDI mode or receive in MDIX mode.
Port 1 TP RX
These two pins are the Twisted Pair receive in
MDI mode or transmit in MDIX mode.
Port 2 TP TX
These two pins are the Twisted Pair transmit in
MDI mode or receive in MDIX mode.
Port 2 TP RX
These two pins are the Twisted Pair receive in
MDI mode or transmit in MDIX mode.
Port 3 TP TX
These two pins are the Twisted Pair transmit in
MDI mode or receive in MDIX mode.
Port 3 TP RX
These two pins are the Twisted Pair receive in
MDI mode or transmit in MDIX mode.
Port 4 TP RX
These two pins are the Twisted Pair transmit in
MDI mode or receive in MDIX mode.
Port 4 TP TX
These two pins are the Twisted Pair receive in
MDI mode or transmit in MDIX mode.
Bandgap Pin
Connect a 6.8K±1% precision resistor to AGND in
application.
1.8V Voltage control to control external BJT
Voltage Reference
Connect a 0.1u capacitor to ground in application.
6
7
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
16
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
4.2.5
Port 4 MAC MII/RevMII/RMII and PHY MII/RMII Interfaces
Port4 MAC MII Pins
Pin No.
Pin Name
73
74
P4M_TXD3
P4M_TXD2
77
78
96
P4M_TXD1
P4M_TXD0
P4M_TXE
92
91
97
95
85
90
89
86
84
P4M_TXC
P4M_CRS
P4M_COL
P4M_RXC
P4M_RXDV
P4M_RXD3
P4M_RXD2
P4M_RXD1
P4M_RXD0
Buffer
Type
PDR
4mA
I/O
O
Transmit Data (bit 3 and 2)
PDR
4mA
PDR
4mA
PDR
PD
PDR
PDR
PD
O
Transmit Data (bit 1 and 0)
O
Transmit Enable
I
I
I
I
I
I
Transmit Clock.
Carrier Sense
Collision Detect.
Receive Clock
Receive Data Valid
Receive Data (bit 3 and 2)
I
Receive Data (bit 1 and 0)
PU
Port 4 MAC Reverse MII (RevMII) Pins
Pin No.
Pin Name
Buffer
Type
73
P4M_TXD3
PDR
74
P4M_TXD2
4mA
77
P4M_TXD1
PDR
78
P4M_TXD0
4mA
96
P4M_TXE
PDR
4mA
P4M_TXC
PDR
92
4mA
P4M_CRS
PD
91
4mA
P4M_COL
PDR
97
4mA
P4M_RXC
PDR
95
P4M_RXDV
85
90
P4M_RXD3
PD
89
P4M_RXD2
86
P4M_RXD1
PU
84
P4M_RXD0
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Description
I/O
Description
O
Transmit Data (bit 3 and 2)
O
Transmit Data (bit 1 and 0)
O
Transmit Enable
O
Transmit Clock.
O
Carrier Sense
O
Collision Detect.
I
I
I
Receive Clock
Receive Data Valid
Receive Data (bit 3 and 2)
I
Receive Data (bit 1 and 0)
17
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
Port 4 MAC Reduced MII (RMII) Pins
Pin No.
Pin Name
Buffer
Type
73
P4M_TXD3
PDR
74
P4M_TXD2
4mA
77
P4M_TXD1
PDR
78
P4M_TXD0
4mA
96
P4M_TXE
PDR
4mA
P4M_REFCLK_O
PDR
92
4mA
P4M_CRS
PD
91
P4M_COL
PDR
97
P4M_REFCLK_I
PDR
95
P4M_CRSDV
85
90
P4M_RXD3
PD
89
P4M_RXD2
86
P4M_RXD1
PU
84
P4M_RXD0
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
I/O
Description
O
Reserved (No connection)
O
Port4 RMII Transmit Data
O
Transmit Enable
O
Reference Clock 50MHz Output
I
I
I
I
I
Reserved (No connection)
Reserved (No connection)
Reference Clock 50MHz Input
Receive Data Valid
Reserved (No connection)
I
Receive Data
18
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
Port 4 PHY MII Pins
Pin No.
Pin Name
90
89
86
84
85
92
P4P_TXD3
P4P_TXD2
P4P_TXD1
P4P_TXD0
P4P_TXE
P4P_TXC
91
P4P_CRS
97
P4P_COL
95
P4P_RXC
96
P4P_RXDV
73
74
77
78
P4P_RXD3
P4P_RXD2
P4P_RXD1
P4P_RXD0
Buffer
Type
PD
I/O
I
Transmit Data (bit 3 and 2)
PU
I
Transmit Data (bit 1 and 0)
PDR
4mA
PD
4mA
PDR
4mA
PDR
4mA
PDR
4mA
PDR
4mA
PDR
4mA
I
O
Transmit Enable
Transmit Clock.
O
Carrier Sense
O
Collision Detect.
O
Receive Clock
O
Receive Data Valid
O
Receive Data (bit 3 and 2)
O
Receive Data (bit 1 and 0)
Port 4 PHY Reduced MII (RMII) Pins
Pin No.
Pin Name
Buffer
Type
P4P_REFCLK_I
PD
90
89
P4P_TXD2
PD
86
P4P_TXD1
PU
84
P4P_TXD0
85
P4P_TXE
P4P_TXC
PDR
92
4mA
P4P_CRS
PD
91
4mA
P4P_COL
PDR
97
4mA
P4P_REFCLK_O
PDR
95
4mA
P4P_CRSDV
PDR
96
4mA
73
P4P_RXD3
PDR
74
P4P_RXD2
4mA
77
P4P_RXD1
PDR
78
P4P_RXD0
4mA
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Description
I/O
Description
I
I
I
50MHz Input for Reference Clock
Reserved (No connection)
Transmit Data
I
O
Transmit Enable
Reserved (No connection)
O
Reserved (No connection)
O
Reserved (No connection)
O
50MHz Output for Reference Clock
O
Receive Data Valid
O
Reserved (No connection)
O
Receive Data
19
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
4.2.6
Port 5 MAC Interfaces
Port 5 MII Pins
Pin No.
Pin Name
59
60
61
63
66
P5_TXD3
P5_TXD2
P5_TXD1
P5_TXD0
P5_TXE
67
57
58
72
52
56
55
54
53
P5_TXC
P5_CRS
P5_COL
P5_RXC
P5_RXDV
P5_RXD3
P5_RXD2
P5_RXD1
P5_RXD0
Port 5 Reverse MII (RevMII) Pins
Pin No.
Pin Name
59
60
61
63
66
P5_TXD3
P5_TXD2
P5_TXD1
P5_TXD0
P5_TXE
67
P5_TXC
57
P5_CRS
58
P5_COL
72
52
56
55
54
53
P5_RXC
P5_RXDV
P5_RXD3
P5_RXD2
P5_RXD1
P5_RXD0
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Buffer
Type
PDR
4mA
I/O
Description
O
Transmit Data
PDR
4mA
PDR
PDR
PDR
PDR
PD
PD
O
Transmit Enable
I
I
I
I
I
I
Transmit Clock.
Carrier Sense
Collision Detect.
Receive Clock
Receive Data Valid
Receive Data
Buffer
Type
PDR
4mA
I/O
O
Transmit Data
PDR
4mA
PDR
4mA
PDR
4mA
PDR
4mA
PDR
PD
PD
O
Transmit Enable
O
Transmit Clock Output.
O
Carrier Sense Output
O
Collision Detect Output.
I
I
I
Receive Clock
Receive Data Valid
Receive Data
Description
20
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
Port 5 Reduced MII (RMII) pins
Pin No.
Pin Name
59
60
61
63
66
P5_TXD3
P5_TXD2
P5_TXD1
P5_TXD0
P5_TXE
67
P5_REFCLK_O
57
58
72
52
56
55
54
53
P5_CRS
P5_COL
P5_REFCLK_I
P5_CRSDV
P5_RXD3
P5_RXD2
P5_RXD1
P5_RXD0
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Buffer
Type
PDR
I/O
I
Reserved (No connection)
PDR
4mA
PDR
4mA
PDR
4mA
PDR
PDR
PDR
PD
PD
O
Transmit Data
O
Transmit Enable
O
50MHz Output for Reference Clock
I
I
I
I
I
Reserved (No connection)
Reserved (No connection)
50MHz Input for Reference Clock
Receive Data Valid
Reserved (No connection)
I
Receive Data
PD
Description
21
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
4.2.7
Miscellaneous Pins
Pin No.
Pin Name
40
SMI_DIO
44
39
SMI_CK
PHY_MDIO
68
PHY_MDC
65
93
INTR
STRAP_DIS
Buffer
Type
PD
4mA
PD
PD
4mA
PDR
4mA
PD
62
100
98
P4_CFG
P4_SET1
P4_SET0
PD
PDR
PUR
I
I
I
119
PWRST#
-
I
41
69
108
114
TEST3
TEST2
TEST1
VP_EN
PD
PD
PD
PDR
I
I
I
I
106
WOL_EN
PDR
I
115
117
GPIO0
GPIO1
PDR
4mA
I/O
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
I/O
I/O
I
I/O
O
O
I
Description
Serial Management Data Input/output as CPU
interface
Serial Management Data Clock as CPU interface
MII Serial Management Data Input/output as
External PHY interface
MII Serial Management Data Clock as External
PHY interface
Interrupt signals to external CPU
Strap pins disabled
0: Strap pins enabled
1: No strap pin function
Port 4 operation mode
{ P4_CFG, P4_SET1, P4_SET0}
0
0
0
Use internal PHY (M3A)
0
0
1
MAC MII/RMII/RevMII (M3B)
1
X
X
PHY MII/RMII (M3C)
Power on Reset
Low active with minimum 10ms
Test pins
Tie TEST3 to ground in application
Tie TEST2 and TEST1 to DVDD33 in application
Virtual PHY Enable
0: Disable
1: Enable
Wake on Lan Standby
0: Disable
1: Enable to detect WoL Magic Packet event
GPIO Pin
22
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
4.2.8
Power Pins
Pin No.
Pin Name
49, 71
88, 109
46, 75
82, 94
116
45, 50
64, 70
76, 83
87, 99
118
8, 16
23, 31
128
1, 9
17, 24
38, 122
4, 5
12, 13
20, 27
28, 34
35, 123
126
DVDD33
Buffer
Type
PWR
DVDD18
PWR
DGND
GND
AVDD33
PWR
AVDD18
PWR
AGND
GND
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
I/O
P
P
P
P
P
P
Description
Digital 3.3V power
Digital 1.8V power
Digital GND
Analog 3.3V power
Analog 1.8V power
Analog GND
23
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
4.3
Strap Pins Table
1: pull-up with 1K~10K, 0: pull-down with 1K~10K
Pin No.
Pin Name
51
P4_LNK_LED
43
P1_LNK_LED
101
P4_SPD_LED
102
103
P3_SPD_LED
P2_SPD_LED
104
105
107
P1_SPD_LED
P0_SPD_LED
P4_FDX_LED
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Description
Port 4 PHY TP mode in M3A or M3C mode
0: Fiber mode
1: Copper mode (default)
802.3az Energy Efficient Ethernet function of all ports.
0 : Disable, output high to active LED
1 : Enable, output low to active LED (default)
When in M3B and Port4 force mode
0 : Link OFF
1 : Link ON (default)
Port 4 in M3B Mode
{P3_SPD_LED, P2_SPD_LED}
0
0
RevMII with TXC4 turbo clock
0
1
RMII
1
0
MII
1
1
RevMII with TXC4 25MHz/2.5MHz clock (default)
Port 4 in M3C Mode
{P3_SPD_LED, P2_SPD_LED}
0
X
TP_RMII
1
X
TP_MII (default)
When in M3B,Port4 in force mode and (P3_SPD_LED,P2_SPD_LED)≠(0,0)
0 : 10M mode
1 : 100M mode (default)
If (P3_SPD_LED, P2_SPD_LED) = (0,0), it can be used to set P4_TXC
frequency.
{P1_SPD_LED, P0_SPD_LED}
0
0
125MHz
0
1
100MHz
1
0
50MHz
1
1
25MHz (default)
When in M3B,Port4 in force mode and
(P3_SPD_LED, P2_SPD_LED)≠(0,0)
0 : Half-duplex mode
1 : Full-duplex mode (default)
If (P3_SPD_LED, P2_SPD_LED) = (0,0)
See description of P1_SPD_LED
When Port5 in force mode and (P3_FDX_LED, P2_FDX_LED) ≠(0,0)
0 : Link OFF
1 : Link ON (default)
24
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
110
111
P3_FDX_LED,
P2_FDX_LED
112
P1_FDX_LED
113
P0_FDX_LED
115
GPIO0
80
EECS
81
EECK
68
PHY_MDC
Port 5 Operation Mode
{P3_FDX_LED, P2_FDX_LED}
0
0
Reserved
0
1
RMII
1
0
MII
1
1
RevMII (default)
When Port5 in force mode and (P3_FDX_LED, P2_FDX_LED)≠(0,0)
0 : 10M mode (default)
1 : 100M mode
When Port5 in force mode and (P3_FDX_LED, P2_FDX_LED)≠(0,0)
0 : Half-duplex mode
1 : Full-duplex mode (default)
Flow Control in PHY Register 4 bit 10
0: Enable PHY flow control (default)
1: Disable PHY flow control
Port 5 link/duplex/speed mode in MII/RMII
0: Force mode (default)
1: PHY_MDC/PHY_MDIO polling mode
When in M3B and Port 4 link/duplex/speed mode in MII/RMII
0: Force mode (default)
1: MDC_EXT/MDIO_EXT polling mode
When in M3B and Port 4 link/duplex/speed mode in RevMII
X: force mode
Only Port0 and Port1 support Trunk Ports Function
0: Disable (default)
1: Enable
More trunk setting details please refer to bit 11~8 of REG 212h
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
25
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5. Control and Status Register Set
The DM8806 implements several control and status registers (CSRs), which can be accessed by the host
SMI interface via SMI_CK and SMI_DIO pins. The serial format of host SMI can be referenced in Section 7.3.
The absolute address in the following register table is the 10-bit R9~R0 field in the SMI format. For easy to
understanding, the 10-bit absolute address can be divided to 5-bit PHY address plus 5-bit register address
like used in general MII serial format. All CSRs are set to their default values by hardware or software reset
unless specified
5.1
Register Table
Register Name
Port 0 PHY Basic Mode Control
Port 0 PHY Basic Mode Status
Port 0 PHY ID 1
Port 0 PHY ID 2
Port 0 PHY Auto-N Advertisement
Port 0 PHY Auto-N Link Partner Ability
Port 0 PHY Auto-N Expansion
Port 0 PHY Standard Reserved
Port 0 PHY Vendor Specific
Port 1 PHY Control
Port 1 PHY Status
Port 1 PHY ID 1
Port 1 PHY ID 2
Port 1 PHY Auto-N Advertisement
Port 1 PHY Auto-N Link Partner Ability
Port 1 PHY Auto-N Expansion
Port 1 PHY Standard Reserved
Port 1 PHY Vendor Specific
Port 2 PHY Control
Port 2 PHY Status
Port 2 PHY ID 1
Port 2 PHY ID 2
Port 2 PHY Auto-N Advertisement
Port 2 PHY Auto-N Link Partner Ability
Port 2 PHY Auto-N Expansion
Port 2 PHY Standard Reserved
Port 2 PHY Vendor Specific
Port 2 PHY Control
Port 3 PHY Status
Port 3 PHY ID 1
Port 3 PHY ID 2
Port 3 PHY Auto-N Advertisement
Port 3 PHY Auto-N Link Partner Ability
Port 3 PHY Auto-N Expansion
Port 3 PHY Standard Reserved
Port 3 PHY Vendor Specific
Port 3 PHY Control
Port 4 PHY Status
Port 4 PHY ID 1
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
PHY
Address
Internal PHY Registers
02h
02h
02h
02h
02h
02h
02h
02h
02h
03h
03h
03h
03h
03h
03h
03h
03h
03h
04h
04h
04h
04h
04h
04h
04h
04h
04h
05h
05h
05h
05h
05h
05h
05h
05h
05h
06h
06h
06h
Register
Address
00h
01h
02h
03h
04h
05h
06h
07h~0Fh
10h~1Fh
00h
01h
02h
03h
04h
05h
06h
07h~0Fh
10h~1Fh
00h
01h
02h
03h
04h
05h
06h
07h~0Fh
10h~1Fh
00h
01h
02h
03h
04h
05h
06h
07h~0Fh
10h~1Fh
00h
01h
02h
Absolute Address
040h
041h
042h
043h
044h
045h
046h
047h~04Fh
050h~05Fh
060h
061h
062h
063h
064h
065h
066h
067h~06Fh
070h~07Fh
080h
081h
082h
083h
084h
085h
086h
087h~08Fh
090h~09Fh
0A0h
0A1h
0A2h
0A3h
0A4h
0A5h
0A6h
0A7h~0AFh
0B0h~0BFh
0C0h
0C1h
0C2h
26
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
Port 4 PHY ID 2
06h
Port 4 PHY Auto-N Advertisement
06h
Port 4 PHY Auto-N Link Partner Ability
06h
Port 4 PHY Auto-N Expansion
06h
Port 4 PHY Standard Reserved
06h
Port 4 PHY Vendor Specific
06h
Reserved
07h
Switch Per-Port Registers
Port 0 Port Status
08h
Port 0 Basic Control 0
08h
Port 0 Basic Control 1
08h
Port 0 Block Contrl 0
08h
Port 0 Block Contrl 1
08h
Port 0 Bandwidth Control
08h
Port 0 VLAN Tag Infomation
08h
Port 0 Priority & VLAN Control
08h
Port 0 Security Control
08h
Port 0 Spanning Tree state Control
08h
Port 0 Memory Configuration
08h
Port 0 Discard packet limitation
08h
Reserved
08h
Reserved
08h
Port 0 Energy Efficient Ethernet Control
08h
Reserved
08h~09h
Port 1 Port Status
09h
Port 1 Basic Control 0
09h
Port 1 Basic Control 1
09h
Port 1 Block Contrl 0
09h
Port 1 Block Contrl 1
09h
Port 1 Bandwidth Control
09h
Port 1 VLAN Tag Infomation
09h
Port 1 Priority & VLAN Control
09h
Port 1 Security Control
09h
Port 1 Spanning Tree state Control
09h
Port 1 Memory Configuration
09h
Port 1 Discard packet limitation
09h
Reserved
09h
Reserved
09h
Port 1 Energy Efficient Ethernet Control
09h
Reserved
09h~0Ah
Port 2 Port Status
0Ah
Port 2 Basic Control 0
0Ah
Port 2 Basic Control 1
0Ah
Port 2 Block Contrl 0
0Ah
Port 2 Block Contrl 1
0Ah
Port 2 Bandwidth Control
0Ah
Port 2 VLAN Tag Infomation
0Ah
Port 2 Priority & VLAN Control
0Ah
Port 2 Security Control
0Ah
Port 2 Spanning Tree state Control
0Ah
Port 2 Memory Configuration
0Ah
Port 2 Discard packet limitation
0Ah
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
03h
04h
05h
06h
07h~0Fh
10h~1Fh
00h~1Fh
0C3h
0C4h
0C5h
0C6h
0C7h~0CFh
0D0h~0DFh
0F0h~10Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh~0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh~0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh~12Fh
130h
131h
132h
133h
134h
135h
136h
137h
138h
139h
13Ah
13Bh
13Ch
13Dh
13Eh
13Fh~14Fh
150h
151h
152h
153h
154h
155h
156h
157h
158h
159h
15Ah
15Bh
27
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
Reserved
Reserved
Port 2 Energy Efficient Ethernet Control
Reserved
Port 3 Port Status
Port 3 Basic Control 0
Port 3 Basic Control 1
Port 3 Block Contrl 0
Port 3 Block Contrl 1
Port 3 Bandwidth Control
Port 3 VLAN Tag Infomation
Port 3 Priority & VLAN Control
Port 3 Security Control
Port 3 Spanning Tree state Control
Port 3 Memory Configuration
Port 3 Discard packet limitation
Reserved
Reserved
Port 3 Energy Efficient Ethernet Control
Reserved
Port 4 Port Status
Port 4 Basic Control 0
Port 4 Basic Control 1
Port 4 Block Contrl 0
Port 4 Block Contrl 1
Port 4 Bandwidth Control
Port 4 VLAN Tag Infomation
Port 4 Priority & VLAN Control
Port 4 Security Control
Port 4 Spanning Tree state Control
Port 4 Memory Configuration
Port 4 Discard packet limitation
Reserved
Reserved
Port 4 Energy Efficient Ethernet Control
Reserved
Port 5 Port Status
Port 5 Basic Control 0
Port 5 Basic Control 1
Port 5 Block Contrl 0
Port 5 Block Contrl 1
Port 5 Bandwidth Control
Port 5 VLAN Tag Infomation
Port 5 Priority & VLAN Control
Port 5 Security Control
Port 5 Spanning Tree state Control
Port 5 Memory Configuration
Port 5 Discard packet limitation
Reserved
Port 5 Energy Efficient Ethernet Control
Reserved
Reserved
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
0Ah
0Ah
0Ah
0Ah~0Bh
0Bh
0Bh
0Bh
0Bh
0Bh
0Bh
0Bh
0Bh
0Bh
0Bh
0Bh
0Bh
0Bh
0Bh
0Bh
0Bh~0Ch
0Ch
0Ch
0Ch
0Ch
0Ch
0Ch
0Ch
0Ch
0Ch
0Ch
0Ch
0Ch
0Ch
0Ch
0Ch
0Ch~0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Eh~0Fh
1Ch
1Dh
1Eh
1Fh~0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh~0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh~0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch~1Dh
1Eh
1Fh
00h~1Fh
15Ch
15Dh
15Eh
15Fh~16Fh
170h
171h
172h
173h
174h
175h
176h
177h
178h
179h
17Ah
17Bh
17Ch
17Dh
17Eh
17Fh~18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh~1AFh
1B0h
1B1h
1B2h
1B3h
1B4h
1B5h
1B6h
1B7h
1B8h
1B9h
1BAh
1BBh
1BCh~1BDh
1BEh
1BFh
1C0h~20Fh
28
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
Switch Status
Switch Reset
Switch Control
CPU Port & Mirror Control
Special Tag Ether-Type
Global Learning & Aging Control
Reserved
VLAN Priority Map
TOS Priority Map 0
TOS Priority Map 1
TOS Priority Map 2
TOS Priority Map 3
TOS Priority Map 4
TOS Priority Map 5
TOS Priority Map 6
TOS Priority Map 7
MIB Counter Disable
MIB Counter Control
MIB Counter Data Low
MIB Counter Data High
Special Packet Control 0
Special Packet Control 1
Special Packet Control 2
Special Packet Control 3
Special Packet Control 4
Special Packet Control 5
Special Packet Control 6
Special Packet Control 7
Special Packet Control 8
QinQ TPID
VLAN Mode & Rule Control
VLAN Table – Valid Control
VLAN Table – ID_0H
VLAN Table – ID_1H
VLAN Table – ID_2H
VLAN Table – ID_3H
VLAN Table – ID_4H
VLAN Table – ID_5H
VLAN Table – ID_6H
VLAN Table – ID_7H
VLAN Table – ID_8H
VLAN Table – ID_9H
VLAN Table – ID_AH
VLAN Table – ID_BH
VLAN Table – ID_CH
VLAN Table – ID_DH
VLAN Table – ID_EH
VLAN Table – ID_FH
VLAN Table – MEMBER_0H
VLAN Table – MEMBER_1H
VLAN Table – MEMBER_2H
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Switch Engine Registers
10h
10h
10h
10h
10h
10h
10h
10h
10h
10h
10h
10h
10h
10h
10h
10h
11h
11h
11h
11h
11h
11h
11h
11h
11h
11h
11h
11h
11h
11h
11h
11h
12h
12h
12h
12h
12h
12h
12h
12h
12h
12h
12h
12h
12h
12h
12h
12h
13h
13h
13h
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
10h
11h
12h
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
21Fh
230h
231h
232h
233h
234h
235h
236h
237h
238h
239h
23Ah
23Bh
23Ch
23Dh
23Eh
23Fh
250h
251h
252h
253h
254h
255h
256h
257h
258h
259h
25Ah
25Bh
25Ch
25Dh
25Eh
25Fh
270h
271h
272h
29
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
VLAN Table – MEMBER_3H
VLAN Table – MEMBER_4H
VLAN Table – MEMBER_5H
VLAN Table – MEMBER_6H
VLAN Table – MEMBER_7H
VLAN Table – MEMBER_8H
VLAN Table – MEMBER_9H
VLAN Table – MEMBER_AH
VLAN Table – MEMBER_BH
VLAN Table – MEMBER_CH
VLAN Table – MEMBER_DH
VLAN Table – MEMBER_EH
VLAN Table – MEMBER_FH
VLAN Table – Priority Enable
VLAN Table – Priority Replace Enable
VLAN Table – STP Index Enable
VLAN Table – Misc_0
VLAN Table – Misc_1
VLAN Table – Misc_2
VLAN Table – Misc_3
VLAN Table – Misc_4
VLAN Table – Misc_5
VLAN Table – Misc_6
VLAN Table – Misc_7
Snooping Control 0
Snooping Control 1
Reserved
Address Table Control & Status
Address Table Data 0
Address Table Data 1
Address Table Data 2
Address Table Data 3
Address Table Data 4
Reserved
Address Registers for Magic Packet
WoL Control Register
Reserved
General Purpose I/O Control
Reserved
Vendor ID
Product ID
Reserved
Port 4 MAC Control
Port 5 MAC Control
Fiber Control
IRQ and LED Control
Interrupt Status Register
Interrupt Mask & Control Register
EEPROM Control & Address
EEPROM Data
Monitor Register 0
Monitor Register 1
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
13h
13h
13h
13h
13h
13h
13h
13h
13h
13h
13h
13h
13h
14h
14h
14h
14h
14h
14h
14h
14h
14h
14h
14h
14h
14h
14h~15h
15h
15h
15h
15h
15h
15h
15h
15h
15h
15h~16h
16h
16h~18h
18h
18h
18h
18h
18h
18h
18h
18h
18h
18h
18h
18h
18h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh~0Fh
10h
11h
12h
13h
14h
15h
16h~17h
18h~1Ah
1Bh
1Ch~0Fh
10h
11h~0Fh
10h
11h
12h~13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
273h
274h
275h
276h
277h
278h
279h
27Ah
27Bh
27Ch
27Dh
27Eh
27Fh
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh~2AFh
2B0h
2B1h
2B2h
2B3h
2B4h
2B5h
2B6h~2B7h
2B8h~2BAh
2BBh
2BCh~2CFh
2D0h
2D1h~30Fh
310h
311h
312h~313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
30
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
Monitor Register 2
Monitor Register 3
Memory Access Enable
Memory Address
Memory Read Data (Dummy Read)
Memory Read Data
Memory Write Data Bit 15~0 Register
Memory Write Data Bit 7~0 Register
Memory Write Data Bit 15~8 Register
Reserved
System clock Select Register
Serial Bus Error Check Register
Reserved
Virtual PHY Control
PHY Control Test
Reserved
Reserved
Reserved
18h
18h
19h
19h
19h
19h
19h
19h
19h
19h
19h
19h
19h
19h
19h
19h
1Ah~1Ch
1Ch~1Fh
1Eh
1Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah~1Dh
1Dh
1Eh
1Fh
00h~0Fh
10h~1Fh
31Eh
31Fh
330h
331h
332h
333h
334h
335h
336h
337h
338h
339h
33Ah~33Ch
33Dh
33Eh
33Fh
340h~38Fh
390h~3FFh
Note:
PHY_ADR
=
<PHY Address> fields of SMI frame
REG_ADR
=
<Register Address> fields of SMI frame
ABS_ADR
=
{ PHY_ADR[4:0], REG_ADR[4:0] }
Key to Default
In the register description that follows, the default column takes the form: <Reset Value>, <Access Type>
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
?H Bits set to hex. value
X No default value
P
S
Y
E
T
Power on reset default value
Software reset, by Reg. 211H bit 1, default
value
Default value from PHY software reset by
per port PHY register 0 bit 15
Default value from EEPROM setting
Default value from strap pin
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
<Access Type>:
RO
Read only
RW
Read/Write
R/C
Read and Clear
RW/C1 Read/Write and Cleared by write 1
WO
Write only
R/WC
Read/Write and auto-cleared
Reserved bits should be written with 0.
Reserved bits are undefined on read access.
31
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.2 Internal PHY Registers
5.2.1
Port 0~4 PHY Control Register
P0(040H), P1(060H), P2(080H), P3(0A0H), P4(0C0H)
Bit
15
14
13
12
11
10
9
8
7:0
Bit Name
Reset
Default
Description
P0
Reset
RW/SC This bit sets the status and controls the PHY registers to their default
states. This bit, which is self-clearing, will keep returning a value of one until
the reset process is completed
0: Normal operation
1: Software reset
Loopback
PY0 Loopback
RW Loop-back control enable
When in 100Mbps operation mode, setting this bit may cause the
descrambler to lose synchronization and produce a 720ms "dead time"
before any valid data appears at the MII receive outputs
0: Normal operation
1: Loop-back enabled
Speed selection PY1 Speed Select
RW Link speed may be selected either by this bit or by auto-negotiation. When
auto-negotiation is enabled (bit 12 is set), this bit will return auto-negotiation
selected medium type
0: 10Mbps
1: 100Mbps
Auto-negotiation PT1 Auto-negotiation Enable
enable
RW Enable the ability of auto-negotiation process.
0: Disable
1: Enable
Power down
PY0 Power Down
RW While in the power-down state, the PHY should respond to management
transactions. During the transition to power-down state and while in the
power-down state, the PHY should not generate spurious signals on the MII
0: Normal operation
1: Power down
Isolate
PY0 Isolate
RW Force to 0 in application.
Restart
PY0 Restart Auto-negotiation
Auto-negotiation RW/SC Re-initiates the auto-negotiation process. If the auto-negotiation ability is
disabled, this bit has no function and it should be cleared. This bit is
self-clearing.
0: Normal operation
1: Restart auto-negotiation process
Duplex mode
PY1 Duplex Mode
RW If auto-negotiation ability is disabled, this bit can be set manually
(Read/Write). If auto-negotiation ability is enabled, this bit reflects the result
of auto-negotiation (Read only).
0: Half duplex operation
1: Full duplex operation
Reserved
P0
Reserved
RO
Read as 0, ignore on write
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
32
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.2.2
Port 0~4 PHY Status Register
P0(041H), P1(061H), P2(081H), P3(0A1H), P4(0C1H)
Bit
15
14
13
12
11
10:7
6
5
4
3
2
1
0
Bit Name
100BASE-T4
Default
Description
P0
100BASE-T4 Capable
RO
0: No 100BASE-T4 capable
1: 100BASE-T4 capable
100BASE-TX
P1
100BASE-TX Full Duplex Capable
full-duplex
RO
0: No 100BASE-TX full duplex capable
1: 100BASE-TX full duplex capable
100BASE-TX
P1
100BASE-TX Half Duplex Capable
half-duplex
RO
0: No 100BASE-TX half duplex capable
1: 100BASE-TX half duplex capable
10BASE-T
P1
10BASE-T Full Duplex Capable
full-duplex
RO
0: No 10BASE-TX full duplex capable
1: 10BASE-T full duplex capable
10BASE-T
P1
10BASE-T Half Duplex Capable
half-duplex
RO
0: No 10BASE-T half duplex capable
1: 10BASE-T half duplex capable
Reserved
P0
Reserved
RO
Read as 0, ignore on write
MF preamble
PY1 MII Frame Preamble Suppression
suppression
RO
0: PHY doesn’t accept management frames with preamble suppressed
1: PHY accept management frames with preamble suppressed
Auto-negotiation PY0 Auto-negotiation Complete
Complete
RO
0: Auto-negotiation process not completed
1: Auto-negotiation process completed
Remote fault
PY0 Remote Fault
RO
0: No remote fault condition detected
1: Remote fault condition detected
Auto-negotiation
P1
Auto-Negotiation Ability
ability
RO
0: No auto-negotiation capable
1: Auto-negotiation capable
Link status
PY0 Link Status
RO
The link status bit is implemented with a latching function, so that the
occurrence of a link failure condition causes the link status bit to be cleared
and remain cleared until it is read via the management interface
0: Link is not established
1: Link is established
Jabber detect
PY0 Jabber Detect
RO
This bit works only in 10Mbps mode
0: No jabber
1: Jabber condition detected
Extended
P1
Extended Capability
capability
RO
0: Basic register capable only
1: Extended register capable
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
33
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.2.3
Port 0~4 PHY Identifier 1 Register
P0(042H), P1(062H), P2(082H), P3(0A2H), P4(0C2H)
Bit
15:0
5.2.4
Bit Name
OUI_MSB
Default
Description
PE
OUI Most Significant Bits
0181h This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of this
RO
register respectively. The most significant two bits of the OUI are ignored
(the IEEE standard refers to these as bit 1 and 2)
Port 0~4 PHY Identifier 2 Register
P0(043H), P1(063H), P2(083H), P3(0A3H), P4(0C3H)
Bit
15:10
Bit Name
OUI_LSB
9:4
VNDR_MDL
3:0
MDL_REV
Default
PE
101110
RO
PE
001011
RO
PE
0001
RO
Description
OUI Least Significant Bits
Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this register
respectively
Vendor Model Number
Five bits of vendor model number mapped to bit 9 to 4 (most significant bit
to bit 9)
Model Revision Number
Five bits of vendor model revision number mapped to bit 3 to 0 (most
significant bit to bit 4)
The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM8806. The Identifier
consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a
model revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E.
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
34
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.2.5
Port 0~4 PHY Auto-Negotiation Advertisement Register
P0(044H), P1(064H), P2(084H), P3(0A4H), P4(0C4H)
Bit
15
Bit Name
NP
Default
P0
RO
14
ACK
PY0
RO
13
RF
PY0
RW
12:11
Reserved
10
FCS
P0
RO
PT0
RW
9
T4
P0
RO
8
TX_FDX
PY1
RW
7
TX_HDX
PY1
RW
6
10_FDX
PY1
RW
5
10_HDX
PY1
RW
4:0
Selector
PY
00001
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Description
Next page Indication
The DM8806 has no next page, so this bit is permanently set to 0
0: No next page
1: Next page available
Acknowledge
The DM8806's auto-negotiation state machine will automatically control
this bit in the outgoing FLP bursts and set it at the appropriate time during
the auto-negotiation process. Software should not attempt to write to this
bit.
0: Not acknowledged
1: Link partner ability data reception acknowledged
Remote Fault
0: No fault detected
1: Local device senses a fault condition
Reserved
Write as 0, ignore on read
Flow Control Support
0: Controller chip doesn’t support flow control ability
1: Controller chip supports flow control ability
100BASE-T4 Support
The DM8806 does not support 100BASE-T4 so this bit is permanently set
to 0
0: 100BASE-T4 is not supported
1: 100BASE-T4 is supported by the local device
100BASE-TX Full Duplex Support
0: 100BASE-TX full duplex is not supported
1: 100BASE-TX full duplex is supported by the local device
100BASE-TX Support
0: 100BASE-TX half duplex is not supported
1: 100BASE-TX half duplex is supported by the local device
10BASE-T Full Duplex Support
0: 10BASE-T full duplex is not supported
1: 10BASE-T full duplex is supported by the local device
10BASE-T Support
0: 10BASE-T half duplex is not supported
1: 10BASE-T half duplex is supported by the local device
Protocol Selection Bits
These bits contain the binary encoded protocol selector supported by this
node <00001> indicates that this device supports IEEE 802.3 CSMA/CD
35
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.2.6
Port 0~4 PHY Auto-Negotiation Link Partner Ability Register
P0(045H), P1(065H), P2(085H), P3(0A5H), P4(0C5H)
Bit
15
Bit Name
NP
Default
PY0
RO
14
ACK
PY0
RO
13
RF
PY0
RO
12:11
Reserved
10
FCS
PY0
RO
PY0
RO
9
T4
PY0
RO
8
TX_FDX
PY0
RO
7
TX_HDX
PY0
RO
6
10_FDX
PY0
RO
5
10_HDX
PY0
RO
4:0
Selector
PY
00000
RO
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Description
Next Page Indication
0: Link partner, no next page available
1:Link partner, next page available
Acknowledge
The DM8806's auto-negotiation state machine will automatically control
this bit from the incoming FLP bursts. Software should not attempt to write
to this bit
0: Not acknowledged
1: Link partner ability data reception acknowledged
Remote Fault
0: No remote fault indicated by link partner
1: Remote fault indicated by link partner
Reserved
Read as 0, ignore on write
Flow Control Support
0: Controller chip doesn’t support flow control ability by link partner
1: Controller chip supports flow control ability by link partner
100BASE-T4 Support
0: 100BASE-T4 is not supported by the link partner
1:100BASE-T4 is supported by the link partner
100BASE-TX Full Duplex Support
0: 100BASE-TX full duplex is not supported by the link partner
1:100BASE-TX full duplex is supported by the link partner
100BASE-TX Support
0: 100BASE-TX half duplex is not supported by the link partner
1: 100BASE-TX half duplex is supported by the link partner
10BASE-T Full Duplex Support
0: 10BASE-T full duplex is not supported by the link partner
1: 10BASE-T full duplex is supported by the link partner
10BASE-T Support
0: 10BASE-T half duplex is not supported by the link partner
1: 10BASE-T half duplex is supported by the link partner
Protocol Selection Bits
Link partner’s binary encoded protocol selector
36
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.2.7
Port 0~4 PHY Auto-Negotiation Expansion Register
P0(046H), P1(066H), P2(086H), P3(0A6H), P4(0C6H)
Bit
15:5
Bit Name
Reserved
Default
P0
RO
PY0
RO
4
PDF
3
LP_NP_EN
PY0
RO
2
NP_ABLE
P0
RO
1
PAGE_RX
PY0
RO
0
LP_AN_EN
PY0
RO
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Description
Reserved
Read as 0, ignore on write
Local Device Parallel Detection Fault
0: No fault detected via parallel detection function
1: A fault detected via parallel detection function
Link Partner Next Page Able
0: Link partner, no next page
1: Link partner, next page available
Local Device Next Page Able
DM8806 does not support this function, so this bit is always 0
0: No next page
1: Next page available
New Page Received
A new link code word page received. This bit will be automatically cleared
when the register (register 6) is read by management
Link Partner Auto-negotiation Able
0: Link partner do not support Auto-negotiation
1: Link partner supports Auto-negotiation
37
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.2.8
Port 0~4 PHY Specific Control 1 Register
P0(050H), P1(070H), P2(090H), P3(0B0H), P4(0D0H)
Bit
15
Bit Name
BP_4B5B
14
BP_SCR
13
BP_ALIGN
12:11
Reserved
10
TX
9:5
Reserved
4
Reserved
3
Reserved
2
Reserved
1:0
Reserved
Default
Description
PY0
Bypass 4B5B Encoding and 5B4B Decoding
RW
0: Normal 4B5B and 5B4B operation
1: 4B5B encoder and 5B4B decoder function bypassed
PY0
Bypass Scrambler/Descrambler Function
RW
0: Normal scrambler and descrambler operation
1: Scrambler and descrambler function bypassed
PY0
Bypass Symbol Alignment Function
RW
0: Normal operation
1: Receive functions (descrambler, symbol alignment and symbol
decoding functions) bypassed. Transmit functions (symbol
encoder and scrambler) bypassed
PY0
Reserved
RW
PY1
100BASE-TX Mode Control
RW
0: 100BASE-FX operation (Fiber mode)
1: 100BASE-TX operation
PY0
Reserved
RW
PY1
Reserved
RW
PY0
Reserved
RW
PY1
Reserved
RW
PY0
Reserved
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
38
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.2.9
Port 0~4 PHY Specific Control 2 Register
P0(054H), P1(074H), P2(094H), P3(0B4H), P4(0D4H)
Bit
15:12
Bit Name
RESERVED
Default
PY0
RW
PY0
RW
11
PREAMBLEX
10
TX10M_PWR
PY0
RW
9
NWAY_PWR
PY0
RW
8
Reserved
7
MDIX_CNTL
P0
RO
PYX
RO
6
AutoNeg_dpbk
PY0
RW
5
Mdix_fix Value
4
MDIX_DOWN
PY0
RW
PY0
RW
3:0
Reserved
PY0
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Description
Reserved
Preamble Saving Control
When bit 11 of per port PHY register 1DH is set, 12-bit preamble bit is
reduced; otherwise 22-bit preamble bit is reduced.
0: If bit 10 is set, the 10M TX preamble count is reduced
1: 10M TX preamble bit count is normal
10M TX Power Saving Control Enable
0: Disable
1: Enable
N-Way Power Saving Control Disalbe
0: Enable
1: Disable
Reserved
Read as 0, ignore on write
The polarity of MDI/MDIX value
0: MDI mode
1: MDIX mode
Auto-negotiation Loopback
0: Normal operation
1: Test internal digital auto-negotiation Loopback
MDIX_CNTL force value:
When MDIX_DOWN = 1, MDIX_CNTL value depend on the register value.
MDIX Down
Disable HP Auto-MDIX. Force MDI/MDIX function manually.
0: Enable HP Auto-MDIX
1: Disable HP Auto-MDIX, MDIX_CNTL value depend on bit 5
Reserved
39
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.2.10
Port 0~4 PHY Power Saving Control Register
P0(05DH), P1(07DH), P2(09DH), P3(0BDH), P4(0DDH)
Bit
15:12
Bit Name
RESERVED
11
PREAMBLEX
10
RESERVED
9
TX_PWR
8:0
RESERVED
Default
P0
RO
PY0
RW
PY0
RW
PY0
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
P0
RO
Description
Reserved
Preamble Saving Control
When bit 10 of per port PHY register 14H is cleared and bit 11 of per port
PHY register 14H is set, the 10M TX preamble count is reduced.
0: 20-bit preamble bits is reduced
1: 10-bit preamble bit is reduced
Reserved
TX Power Saving Control Disabled
0: when cable is unconnected with link partner, the driving current of
transmit is reduced for power saving
1: disable TX driving power saving function
Reserved
40
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.3 Switch Per-Port Registers
5.3.1
Per Port Status Data Register
P0(110h), P1(130h), P2(150h), P3(170h), P4(190h), P5(1B0h)
Bit
Name
RESERVED
ROM
－
LP_FCS
－
3:2
SPEED
－
P0
RO
1
FDX
－
P0
RO
0
LINK
－
P0
RO
15:5
4
5.3.2
Default
P0
RO
P0
RO
Description
Reserved
Write as 0h, ignore when read
Link Partner Flow Control Enable Status
0: Link partner don't support IEEE 802.3x flow control
1: Link partner support IEEE 802.3x flow control
PHY Speed Status
00: 10Mbps
01: 100Mbps
1x: 1000Mbps
PHY Duplex Status
0: Half-duplex
1: Full-duplex
PHY Link Status
0: Link off
1: Link on
Per Port Basic Control 0 Register
P0(111h), P1(131h), P2(151h), P3(171h), P4(191h), P5(1B1h)
Bit
Name
RESERVED
ROM
－
14
UNPLUG_CLS
13
AGE_DIS
12
ADRLRN_DIS
11
DIS_PAUSE
80h.[14]
90h.[14]
A0h.[14]
B0h.[14]
C0h.[14]
D0h.[14]
80h.[13]
90h.[13]
A0h.[13]
B0h.[13]
C0h.[13]
D0h.[13]
80h.[12]
90h.[12]
A0h.[12]
B0h.[12]
C0h.[12]
D0h.[12]
80h.[11]
90h.[11]
A0h.[11]
B0h.[11]
C0h.[11]
D0h.[11]
15
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Unplug Clear Address Enable
Enable to automatically clear address record in address
table after unplug
0: Disable, retaining address record
1: Enable, clearing address record
PSE0
RW
Address Table Aging
0: Age function is enabled
1: Age function is disabled
PSE0
RW
Address Learning Disabled
0: Address learning function is enabled
1: Address learning function is disabled
PSE0
RW
Maximum PAUSE Packet from Link Partner
0: Always care PAUSE packet from link partner
1: PAUSE packet by passed after 7 continued PAUSE
packet from link partner
41
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
10
RESERVED
－
9
HOB_DIS
8
LOOPBACK
80h.[9]
90h.[9]
A0h.[9]
B0h.[9]
C0h.[9]
D0h.[9]
－
7
PAUSE_CON
6
PARTI_EN
5
FCBP_DIS
4
FC3X_DIS
3:2
MAX_PKTLEN
1
0
P0
RO
PSE0
RW
Reserved
Write as 0h, ignore when read
Head-of-Line Blocking Prevent Control
0: Disable
1: Enable
PSE0
RW
Loop-Back Mode
The transmitted packet will be forward to this port itself
0: Look-back is disabled
1: Look-back is enabled
Send PAUSE Continuously
If buffer congestion occur on full duplex, switch will send
PAUSE frames:
0: Up to 8-times
1: Continuously until alleviation
PSE0
RW
RX_DIS
80h.[7]
90h.[7]
A0h.[7]
B0h.[7]
C0h.[7]
D0h.[7]
80h.[6]
90h.[6]
A0h.[6]
B0h.[6]
C0h.[6]
D0h.[6]
80h.[5]
90h.[5]
A0h.[5]
B0h.[5]
C0h.[5]
D0h.[5]
80h.[4]
90h.[4]
A0h.[4]
B0h.[4]
C0h.[4]
D0h.[4]
80h.[3:2]
90h.[3:2]
A0h.[3:2]
B0h.[3:2]
C0h.[3:2]
D0h.[3:2]
－
TX_DIS
－
PSE0
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
PSE0
RW
Partition Detection Enable
0: Disable
1: Enable
PSE0
RW
Backpressure Flow-Control in Half Duplex Disable
0: Backpressure is enabled
1: Backpressure is disabled
PSE0
RW
IEEE 802.3x Flow Control in Full Duplex Mode
0: 802.3x flow-control is enabled
1: 802.3x flow-control is disabled
PSE0
RW
Max accept packet length by RX from this port
00: 1536-bytes
01: 1552-bytes
10: 1800-bytes
11: 2032-bytes
PSE0
RW
Packet Receive Disable
0: Receive ability is enabled
1: Receive ability is disabled
Packet Transmit Disable
0: Transmit ability is enabled
1: Transmit ability is disabled
42
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.3.3
Per Port Basic Control 1 Register
P0(112h), P1(132h), P2(152h), P3(172h), P4(192h), P5(1B2h)
Bit
15
Name
NO_DIS_RX
ROM
81h.[15]
91h.[15]
A1h.[15]
B1h.[15]
C1h.[15]
D1h.[15]
Default
PSE0
RW
14
BANDWIDTH
PSE0
RW
13
STORM_UUP
12
STORM_MP
11
MIRR_DBP
10
FIR_SPEC
9
FIR_UUSMAC
8
FIR_UUDMAC
81h.[14]
91h.[14]
A1h.[14]
B1h.[14]
C1h.[14]
D1h.[14]
81h.[13]
91h.[13]
A1h.[13]
B1h.[13]
C1h.[13]
D1h.[13]
81h.[12]
91h.[12]
A1h.[12]
B1h.[12]
C1h.[12]
D1h.[12]
81h.[11]
91h.[11]
A1h.[11]
B1h.[11]
C1h.[11]
D1h.[11]
81h.[10]
91h.[10]
A1h.[10]
B1h.[10]
C1h.[10]
D1h.[10]
81h.[9]
91h.[9]
A1h.[9]
B1h.[9]
C1h.[9]
D1h.[9]
81h.[8]
91h.[8]
A1h.[8]
B1h.[8]
C1h.[8]
D1h.[8]
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Description
Don’t Discard RX Packets when Ingress Bandwidth
Control
When received packets bandwidth reach Ingress bandwidth
threshold, the packets over the threshold are not discarded but
with flow control.
0: Don’t discard packet
1: Discard packet
Bandwidth Control Mode
0: Separated mode. Rate control of ingress and egress
is separate.
1: Combined mode. Combining the rate of ingress and
egress
PSE0
RW
Broadcast Storm Enable for Unlearned Unicast Packets
0: Disable
1: Enable
PSE0
RW
Broadcast Storm Filtering for Multicast Packets
Treat multicast packet as source of storm
0: Disable
1: Enable
PSE0
RW
Don't Mirror Broadcast/Multicast Packets
If Mirror Function is Enabled
0: Broadcast/Multicast would be mirrored
1: Broadcast/Multicast would not be mirrored
PSE0,R
W
Specific MAC Filtering Control Enable
Enable to filter packet that is specified in the address
table.
0: Disable
1: Enable
PSE0
RW
Filter Packets with Unlearned Unicast SMAC
0: Disable
1: Enable
PSE0
RW
Filter Packets with Unlearned Unicast DMAC
0: Disable
1: Enable
43
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
7
FIR_UMDMAC
6
FIR_BDMAC
5
FIR_MDMAC
4
FIR_MSMAC
3:2
MIRR_TX
1:0
MIRR_RX
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
81h.[7]
91h.[7]
A1h.[7]
B1h.[7]
C1h.[7]
D1h.[7]
81h.[6]
91h.[6]
A1h.[6]
B1h.[6]
C1h.[6]
D1h.[6]
81h.[5]
91h.[5]
A1h.[5]
B1h.[5]
C1h.[5]
D1h.[5]
81h.[4]
91h.[4]
A1h.[4]
B1h.[4]
C1h.[4]
D1h.[4]
81h.[3:2]
91h.[3:2]
A1h.[3:2]
B1h.[3:2]
C1h.[3:2]
D1h.[3:2]
81h.[1:0]
91h.[1:0]
A1h.[1:0]
B1h.[1:0]
C1h.[1:0]
D1h.[1:0]
PSE0
RW
Filter Packets with Unlearned Multicast DMAC
0: Disable
1: Enable
PSE0
RW
Filter Packets with Broadcast DMAC
0: Disable
1: Enable
PSE0
RW
Filter Packets with Multicast DMAC
0: Disable
1: Enable
PSE0
RW
Filter Packets with Multicast SMAC
0: Disable
1: Enable
PSE0
RW
TX Packet is Mirrored.
The egress packet on this port also be forward to sniffer
port.
PSE0
RW
Port TX Mirror Option
00: TX mirror function is disabled
01: All transmitted packets is mirrored
10: Packet is mirrored if
(DMAC search result is hit & ATB_MIRR==1 & Transmit
from this port)
11: Packet is mirrored if
(SMAC search result is hit & ATB_MIRR==1 & Transmit
from this port)
RX Packet is Mirrored.
The ingress packet on this port also be forward to sniffer
port.
Port RX Mirror Option
00: RX mirror function is disabled
01: All received packets is mirrored
10: Packet is mirrored if
(DMAC search result is hit & ATB_MIRR==1 & Receive
from this port)
11: Packet is mirrored if
(SMAC search result is hit & ATB_MIRR==1 & Receive
from this port)
44
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.3.4
Per Port Block Control 0 Register
P0(113h), P1(133h), P2(153h), P3(173h), P4(193h), P5(1B3h)
Bit
15:14
Name
RESERVED
ROM
－
13:8
BLK_MP
82h.[13:8]
92h.[13:8]
A2h.[13:8]
B2h.[13:8]
C2h.[13:8]
D2h.[13:8]
7:6
RESERVED
－
5:0
BLK_BP
82h.[5:0]
92h.[5:0]
A2h.[5:0]
B2h.[5:0]
C2h.[5:0]
D2h.[5:0]
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PSE0
RW
P0
RO
PSE
RW
Description
Reserved
Write as 0h, ignore when read
Block Packet with Multicast DMAC
[13]: Forward to port 5 is blocked
[12]: Forward to port 4 is blocked
[11]: Forward to port 3 is blocked
[10]: Forward to port 2 is blocked
[09]: Forward to port 1 is blocked
[08]: Forward to port 0 is blocked
0: Disable
1: Enable
Reserved
Write as 0h, ignore when read
Block Packet with Broadcast DMAC
[05]: Forward to port 5 is blocked
[04]: Forward to port 4 is blocked
[03]: Forward to port 3 is blocked
[02]: Forward to port 2 is blocked
[01]: Forward to port 1 is blocked
[00]: Forward to port 0 is blocked
0: Disable
1: Enable
45
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.3.5
Per Port Block Control 1 Register
P0(114h, P1(134h), P2(154h), P3(174h), P4(194h), P5(1B4h)
Bit
15:14
Name
RESERVED
ROM
－
13:8
BLK_UKP
83h.[13:8]
93h.[13:8]
A3h.[13:8]
B3h.[13:8]
C3h.[13:8]
D3h.[13:8]
7:6
RESERVED
－
5:0
BLK_UP
83h.[5:0]
93h.[5:0]
A3h.[5:0]
B3h.[5:0]
C3h.[5:0]
D3h.[5:0]
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PSE0
RW
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Block Packet with Unlearned Unicast DMAC
[13]: Forward to port 5 is blocked
[12]: Forward to port 4 is blocked
[11]: Forward to port 3 is blocked
[10]: Forward to port 2 is blocked
[09]: Forward to port 1 is blocked
[08]: Forward to port 0 is blocked
0: Disable
1: Enable
Reserved
Write as 0h, ignore when read
Block Packet with Unicast DMAC
[05]: Forward to port 5 is blocked
[04]: Forward to port 4 is blocked
[03]: Forward to port 3 is blocked
[02]: Forward to port 2 is blocked
[01]: Forward to port 1 is blocked
[00]: Forward to port 0 is blocked
0: Disable
1: Enable
46
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.3.6
Per Port Bandwidth Control Register
P0(115h), P1(135), P2(155h), P3(175h), P4(195h), P5(1B5h)
Bit
15:12
Name
INGRESS
ROM
84h.[15:12]
94h.[15:12]
A4h.[15:12]
B4h.[15:12]
C4h.[15:12]
D4h.[15:12]
Default
PSE0
RW
11:8
EGRESS
84h.[11:8]
94h.[11:8]
A4h.[11:8]
B4h.[11:8]
C4h.[11:8]
D4h.[11:8]
PSE0
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Description
Ingress Rate Control (Separated mode)
These bits define the bandwidth threshold that received packets
over the threshold are discarded.
0000: none
0001: 64Kbps
0010: 128Kbps
0011: 256Kbps
0100: 512Kbps
0101: 1Mbps
0110: 2Mbps
0111: 4Mbps
1000: 8Mbps
1001: 16Mbps
1010: 32Mbps
1011: 48Mbps
1100: 64Mbps
1101: 72Mbps
1110: 80Mbps
1111: 88Mbps
Egress Rate Control
These bits define the bandwidth threshold that transmitted
packets over the threshold are discarded.
0000: none
0001: 64Kbps
0010: 128Kbps
0011: 256Kbps
0100: 512Kbps
0101: 1Mbps
0110: 2Mbps
0111: 4Mbps
1000: 8Mbps
1001: 16Mbps
1010: 32Mbps
1011: 48Mbps
1100: 64Mbps
1101: 72Mbps
1110: 80Mbps
1111: 88Mbps
47
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
7:4
BSTH
84h.[7:4]
94h.[7:4]
A4h.[7:4]
B4h.[7:4]
C4h.[7:4]
D4h.[7:4]
PSE0
RW
3:0
BW_CTRL
84h.[3:0]
94h.[3:0]
A4h.[3:0]
B4h.[3:0]
C4h.[3:0]
D4h.[3:0]
PSE0
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Broadcast Storm Threshold
These bits define the bandwidth threshold that received
broadcast packets over the threshold are discarded
0000: no broadcast storm control
0001: 8K packets/sec
0010: 16K packets/sec
0011: 64K packets/sec
0100: 5%
0101: 10%
0110: 20%
0111: 30%
1000: 40%
1001: 50%
1010: 60%
1011: 70%
1100: 80%
1101: 90%
111X: no broadcast storm control
Ingress and Egress Rate Control (Combined mode)
Received and Transmitted Bandwidth Control
These bits define the bandwidth threshold that transmitted or
received packets over the threshold are discarded
0000: none
0001: 64Kbps
0010: 128Kbps
0011: 256Kbps
0100: 512Kbps
0101: 1Mbps
0110: 2Mbps
0111: 4Mbps
1000: 8Mbps
1001: 16Mbps
1010: 32Mbps
1011: 48Mbps
1100: 64Mbps
1101: 72Mbps
1110: 80Mbps
1111: 88Mbps
48
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.3.7
Per Port VLAN Tag Infomation Register
P0(116h), P1(136h), P2(156h), P3(176h), P4(196h), P5(1B6h)
Bit
15:13
Name
PPRI
12
PCFI
11:0
PVID
ROM
85h.[15:13]
95h.[15:13]
A5h.[15:13]
B5h.[15:13]
C5h.[15:13]
D5h.[15:13]
85h.[12]
95h.[12]
A5h.[12]
B5h.[12]
C5h.[12]
D5h.[12]
85h.[3:0]
95h.[3:0]
A5h.[3:0]
B5h.[3:0]
C5h.[3:0]
D5h.[3:0]
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
PSE0
RW
Description
Port VLAN Priority
PSE0
RW
Port VLAN CFI
PSE1
RW
Port VLAN Identification
49
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.3.8
Per Port Priority and VLAN Control Register
P0(117H), P1(137H), P2(157H), P3(177H), P4(197H), P5(1B7H)
Bit
15
Name
RESERVED
ROM
－
14
TAG_OUT
13
FIR_VPKT
12
UNTAG_IN
11:10
RESERVED
86h.[14]
96h.[14]
A6h.[14]
B6h.[14]
C6h.[14]
D6h.[14]
86h.[13]
96h.[13]
A6h.[13]
B6h.[13]
C6h.[13]
D6h.[13]
86h.[12]
96h.[12]
A6h.[12]
B6h.[12]
C6h.[12]
D6h.[12]
－
9:8
VLAN_IAC
86h.[9:8]
96h.[9:8]
A6h.[9:8]
B6h.[9:8]
C6h.[9:8]
D6h.[9:8]
7
RESERVED
－
6
PRI_DIS
5
WFQUE
4
TOS_PRI
86h.[6]
96h.[6]
A6h.[6]
B6h.[6]
C6h.[6]
D6h.[6]
86h.[5]
96h.[5]
A6h.[5]
B6h.[5]
C6h.[5]
D6h.[5]
86h.[4]
96h.[4]
A6h.[4]
B6h.[4]
C6h.[4]
D6h.[4]
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Output Tagging Enable
Force output tagging regardless of VLAN table setting.
0: Disable
1: Enable
PSE0
RW
Filter VLAN Packet
To filter incoming packet if its port does not exist in VLAN
member set
0: Disable
1: Enable
PSE0
RW
Input Force No Tag
Assume all received frame are untagged
0: Disable
1: Enable
P0
RO
PSE0
RW
Reserved
Write as 0h, ignore when read
VLAN Ingress Admit Only Control
00: Accept all frames
01: Accept VLAN-tagged frames only
Untagged or priority tagged(VID=0) frames will be
dropped
10: Accept untagged frames only
11: Accept frame's VID equal to ingress PVID
Reserved
Write as 0h, ignore when read
Priority Queue Disable
0: Priority Queue is enabled
1: Priority Queue is disabled
P0
RO
PSE0
RW
PSE0
RW
Priority Scheduling Method
0: Strict (Queue 3 > 2 > 1 > 0). Always highest priority
queue first.
1: Weighted Round-Robin with 8:4:2:1 ratio
PSE0
RW
Priority Classification IP ToS over VLAN
0: Priority Classification base on VLAN
1: Priority Classification base on IP ToS field
50
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
3
TOS_OFF
2
PRI_OFF
1:0
PB_PQ
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
86h.[3]
96h.[3]
A6h.[3]
B6h.[3]
C6h.[3]
D6h.[3]
86h.[2]
96h.[2]
A6h.[2]
B6h.[2]
C6h.[2]
D6h.[2]
86h.[1:0]
96h.[1:0]
A6h.[1:0]
B6h.[1:0]
C6h.[1:0]
D6h.[1:0]
PSE0
RW
IP ToS Priority Classification Disable
0: Classification is enabled
1: Classification is disabled
PSE0
RW
VLAN Priority Classification Disable
0: Classification is enabled
1: Classification is disabled
PSE0
RW
Port-based Priority Queue Number
00: Queue 0
01: Queue 1
10: Queue 2
11: Queue 3
51
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.3.9
Per Port Security Control Register
P0(118h), P1(138h), P2(158h), P3(178h), P4(198h), P5(1B8h)
Bit
15
Name
RESERVED
ROM
－
14:10
MAX_LRN
9
P_UNAUTH
8:2
RESERVED
87h.[14:10]
97h.[14:10]
A7h.[14:10]
B7h.[14:10]
C7h.[14:10]
D7h.[14:10]
87h.[9]
97h.[9]
A7h.[9]
B7h.[9]
C7h.[9]
D7h.[9]
－
1:0
PLOCK_M
5.3.10
87h.[1:0]
97h.[1:0]
A7h.[1:0]
B7h.[1:0]
C7h.[1:0]
D7h.[1:0]
Default
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Learning Restriction.
Limited number of learned MAC address
1~31, 0: Limitless
PSE0
RW
Port in Unauthorized State
0: Port is in authorized state (normal mode).
TX/RX and learning capability is enabled.
1: Port is in unauthorized state (disable mode).
TX/RX and learning capability is disabled.
Only EAPoL packet can be forwarded.
Reserved
Write as 0h, ignore when read
Port Locking Mode
00: Port Lock is disabled
01: First Lock
10: First Link Lock
11: Assign Lock
P0
RO
PSE0
RW
Per Port Advanced Control Register
P0(119h), P1(139h), P2(159h), P3(179h), P4(199h), P5(1B9h)
Bit
15:13
Name
RESERVED
ROM
－
12
CT_DHLF
11:10
CT_MODE
88h.[12]
98h.[12]
A8h.[12]
B8h.[12]
C8h.[12]
D8h.[12]
88h.[11:10]
98h.[11:10]
A8h.[11:10]
B8h.[11:10]
C8h.[11:10]
D8h.[11:10]
9
CT_EN
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
88h.[9]
98h.[9]
A8h.[9]
B8h.[9]
C8h.[9]
D8h.[9]
Default
P0
RO
PSE0
RW
PSE0
RW
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Disable Cut-Through Mode in Half-duplex
0: Enable cut-through in half-duplex
1: Disable cut-through in half-duplex
Cut-Through Mode
Cut-Through launch after how much byte of packet was
received.
00: 64-bytes
01: 64-bytes
10: 128-bytes
11: 256-bytes
Cut-Through Mode Enable
0: Disable (Store-and-Forward)
1: Enable
52
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
8
FAST_LEAVE
PSE
R0
IGMP Snooping Fast Leave Enable
0: Disable
1: Enable
STP_INDEX3
88h.[9]
98h.[9]
A8h.[9]
B8h.[9]
C8h.[9]
D8h.[9]
－
7:6
PS0
RW
5:4
STP_INDEX2
－
3:2
STP_INDEX1
－
1:0
STP_INDEX0
－
PS0
RW
PS0
RW
PS0
RW
STP/RSTP Port State associate with STP index 3
There are 4 port states for supporting STP, and 3 port
states for supporting RSTP.
00: Forwarding State, The port transmits and receives
packets normally & learning is enabled.
01: Disabled State/Discarding, The port will only
forward the packets that are to and from uP port
(span packets) & learning is disabled.
10: Learning State, The port will only forward the
packets tha are to and from uP port (span packets) &
leaning is enabled.
11: Blocking/Listening State, The port will only forward
the packets that are to and from uP port (span
packets) & learning is disabled.
STP/RSTP Port State associate with STP index 2
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
STP/RSTP Port State associate with STP index 1
STP/RSTP Port State associate with STP index 0
53
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.3.11
Per Port Memory Control Register
P0(11Ah), P1(13Ah), P2(15Ah), P3(17Ah), P4(19Ah), P5(1BAh)
Bit
15:8
Name
TDRQ_TH
7
RESERVED
6:0
RV_BLKSIZ
5.3.12
ROM
89h.[15:8]
99h.[15:8]
A9h.[15:8]
B9h.[15:8]
C9h.[15:8]
D9h.[15:8]
－
89h.[6:0]
99h.[6:0]
A9h.[6:0]
B9h.[6:0]
C9h.[6:0]
D9h.[6:0]
Default
PSE
19h
RW
P0
RO
PSE
3Ah
RW
Description
TDR output queue block threshold value, the block unit
is “128bytes”. It is used generally when Head-of-Line
Blocking, per port register 1 bit 19h, is set.
Reserved
Write as 0h, ignore when read
Per port receive buffer reserved block size, the block
unit is “128bytes”.
Use software to programming this field, the Maximum
value is 3Eh
Per Port Discard Limitation Register
P0(11Bh), P1(13Bh), P2(15Bh), P3(17Bh), P4(19BH), P5(1BBh)
Bit
15
Name
RESERVED
ROM
－
14:8
RV_HI_TH
7
RESERVED
8Ah.[14:8]
9Ah.[14:8]
AAh.[14:8]
BAh.[14:8]
CAh.[14:8]
DAh.[14:8]
－
6:0
RV_LO_TH
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
8Ah.[6:0]
9Ah.[6:0]
AAh.[6:0]
BAh.[6:0]
CAh.[6:0]
DAh.[6:0]
Default
P0
RO
PSE
20h
RW
Description
Reserved
Write as 0h, ignore when read
Per port receive buffer reserved block high water
threshold, the block unit is “128bytes”
P0
RO
PSE0
RW
Reserved
Write as 0h, ignore when read
Per port receive buffer reserved block Low water
threshold, the block unit is “128bytes”
54
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.3.13
Per Port Energy Efficient Ethernet Control Register
P0(11Eh), P1(13Eh), P2(15Eh), P3(17Eh), P4(19Eh)
Bit
15
Name
EEE_EN
14:8
EEE_EXIT
7
RESERVED
6:0
EEE_IN
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
ROM
8Bh.[15]
9Bh.[15]
ABh.[15]
BBh.[15]
CBh.[15]
DBh.[15]
8Bh.[14:8]
9Bh.[14:8]
ABh.[14:8]
BBh.[14:8]
CBh.[14:8]
DBh.[14:8]
－
Default
PS0
RW
8Bh.[6:0]
9Bh.[6:0]
ABh.[6:0]
BBh.[6:0]
CBh.[6:0]
DBh[6:0]
PS0
RW
PS0
RW
P0
RO
Description
802.3az Energy Efficient Ethernet enable
0: Disable
1: Enable
* The default value comes from the strap P1_LNK_LED
(pin 43) and EEPROM loading sequentially.
Timer to leave EEE state before transmit packet
Unit: 2us (default: 30us)
Reserved
Write as 0h, ignore when read
Timer to enter EEE state after transmit idle
Unit: 2us (default: 10us)
55
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4 Switch Engine Registers
5.4.1
Switch Status Register (210h)
Bit
15:4
Name
RESERVED
ROM
－
3
RV_NonEmpty
－
2
RESERVED
－
P0
RO
1
BIST_1
－
RO
0
BIST_0
－
RO
5.4.2
Default
P0
RO
RO
Description
Reserved
Write as 0h, ignore when read
Receive Buffer Status (Debug Only)
0: No packet in buffer
1: There are packets in buffer
Reserved
Write as 0h, ignore when read
Memory 1 BIST Status (25K)
0:Pass
1:Fail
Memory 0 BIST Status (48K)
0:Pass
1:Fail
Switch Reset Register (211h)
Bit
15:3
Name
RESERVED
ROM
－
2
PD_ANLG
－
1
RST_ANLG
－
0
RST_SW
－
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
P0
RW
P0
RW
P0
RW
Description
Reserved
Write as 0h, ignore when read
Power down all analog PHY
0: Power On
1: Power Down
Analog PHY Core Reset
Write 1 to reset, and auto-clear after 10us
Switch Core Reset
Write 1 to reset, and auto-clear after 10us
56
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.3
Switch Control Register Register (212h)
Bit
15
Name
RESERVED
ROM
－
14
MAC_1X
12h.[14]
13:12
RESERVED
－
P0
RO
11:8
TRUNK_EN
12h.[11:8]
PSE0
RW
7:6
RESERVED
－
P0
RO
5
FDX_FLOW
12h.[5]
PSE0
RW
4
NO_REG
12h.[4]
PE0
RW
3
AUTO_RST
12h.[3]
PE0
RW
2
DIS_CRCC
12h.[2]
PSE0
RW
1:0
RESERVED
－
P0
RO
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PS0,
RW
Description
Reserved
Write as 0h, ignore when read
MAC-based 802.1x Security
0: Port-based
1: MAC-based
Reserved
Write as 0h, ignore when read
Trunk Enable {P3,P2,P1,P0}
[11] 1: Port 3 trunk is enabled
0: Port 3 trunk is disabled
[10] 1: Port 2 trunk is enabled
0: Port 2 trunk is disabled
[09] 1: Port 1 trunk is enabled
0: Port 1 trunk is disabled
[08] 1: Port 0 trunk is enabled
0: Port 0 trunk is disabled
Reserved
Write as 0h, ignore when read
Flow Control Option
In full duplex operation, the flow control ability is decided
according to the result of Auto-Negotiation if this bit is asseted.
Otherwise, flow control ability is controlled by bit 4 of register
111H (131H,151H,171H,191H,1B1H).
0: Forced PAUSE
1: Symmetric PAUSE
Don’t Initialize Registers When Software Reset Command is
Launched
0: Initialize registers
1: Don’t initialize registers
Disable RV Buffer Count Checking (internal use)
0: auto switch reset if per port’s RV buffer error
RV buffer count > 31 and not changed for 40ms.
1: disable checking
CRC Checking Disable
0: CRC checking is enabled
1: CRC checking is disabled
Reserved
Write as 0h, ignore when read
57
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.4
CPU Port & Mirror Control Register (213h)
Bit
15:11
Name
RESERVED
ROM
－
10
MIRR_PAIR
13h.[10]
9:8
RESERVED
－
P0
RO
7
STAG_TXE
13h.[7]
PSE0
RW
6
STAG_RXE
13h.[6]
PSE0
RW
5:3
SNF_PORT
13h.[5:3]
PSE0
RW
2:0
CPU_PORT
13h.[2:0]
PE5
RW
5.4.5
Bit
15:0
Default
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Mirror RX/TX Pair Mode Enable
0: Disable
1: Enable
Reserved
Write as 0h, ignore when read
Special Tag Transmit Enable for CPU Port
0: Don't insert the Special Tag for outgoing packets
1: Insert the Special Tag for outgoing packets
Special Tag Receive Enable for CPU Port
0: Don't identify the Special Tag for incoming packets
1: Identifies the Special Tag for incoming packets
Sniffer Port Number
000: Sniffer Port is Port 0
001: Sniffer Port is Port 1
010: Sniffer Port is Port 2
011: Sniffer Port is Port 3
100: Sniffer Port is Port 4
101: Sniffer Port is Port 5
110: Reserved
111: Reserved
Select CPU Port Number
000: Port 0
001: Port 1
010: Port 2
011: Port 3
100: Port 4
101: Port 5
110: Port 5
111: Port 5
Special Tag Ether-Type Register (214h)
Name
STAG_ETH
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
ROM
14h.[15:0]
Default
PSE
RW
8606h
Description
Special Tag Ether-Type
58
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.6
Global Learning & Aging Control Register (215h)
Bit
15:6
Name
RESERVED
ROM
－
5
LRN_PAUSE
15h.[3]
4
LRN_VLAN
15h.[2]
PSE0
RW
3
ATB_KEY
15h.[1]
PSE0
RW
2
ATB_MODE
15h.[0]
PSE0
RW
1:0
AGE_TIME
15h.[1:0]
PSE0
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Learn PAUSE Frame
0: Disable
1: Enable
Address Learning Consider VLAN Member
0: Address learning despite VLAN member
1: Address learning is disabled if incoming port
doesn’t exist in its member set.
Address Table Hash Key
0: Use (DMAC) for searching and (SMAC) for learning
1: Use (DMAC+FID) for searching and (SMAC+FID)
for learning Note: Must clear address table after
this bit is changed.
Address Table Mode
0: Mixed mode, 2K address table for unicast or
multicast
1: Separated mode, 1K for unicast and 1K for
multicast
Note: Must clear address table after this bit is changed.
Aging Time Value
00: 512 sec ±256 sec
01: 256 sec ±128 sec
10: 128 sec ± 64 sec
11: 64 sec ± 32 sec
59
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.7
VLAN Priority Map Register (217H)
Bit
15:14
Name
VLAN_PM7
ROM
1Ch.[15:14]
Default
PSE3
RW
13:12
VLAN_PM6
1Ch.[13:12]
11:10
VLAN_PM5
1Ch.[11:10]
9:8
VLAN_PM4
1Ch.[09:08]
7:6
VLAN_PM3
1Ch.[07:06]
5:4
VLAN_PM2
1Ch [05:04]
3:2
VLAN_PM1
1Ch.[03:02]
1:0
VLAN_PM0
1Ch.[01:00]
PSE3
RW
PSE2
RW
PSE2
RW
PSE1
RW
PSE1
RW
PSE0
RW
PSE0
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Description
If packet’s VLAN tag priority value is equal to 07H, the
output priority queue is decided according to this field.
00: Queue 0
01: Queue 1
10: Queue 2
11: Queue 3
VLAN tag priority value is equal to 06H.
VLAN tag priority value is equal to 05H.
VLAN tag priority value is equal to 04H
VLAN tag priority value is equal to 03H.
VLAN tag priority value is equal to 02H
VLAN tag priority value is equal to 01H.
VLAN tag priority value is equal to 00H
60
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.8
TOS Priority Map 0 Register (218h)
Bit
15:14
Name
TOS_PM07
ROM
1Dh.[15:14]
Default
PSE0
RW
13:12
TOS_PM06
1Dh.[13:12]
11:10
TOS_PM05
1Dh.[11:10]
9:8
TOS_PM04
1Dh.[09:08]
7:6
TOS_PM03
1Dh.[07:06]
5:4
TOS_PM02
1Dh.[05:04]
3:2
TOS_PM01
1Dh.[03:02]
1:0
TOS_PM00
1Dh.[01:00]
PSE0
RW
PSE0
RW
PSE0
RW
PSE0
RW
PSE0
RW
PSE0
RW
PSE0
RW
5.4.9
Description
If packet’s IP ToS value is equal to 07H, the output
priority queue is decided according to this field.
00: Queue 0
01: Queue 1
10: Queue 2
11: Queue 3
ToS value is equal to 06H
ToS value is equal to 05H
ToS value is equal to 04H
ToS value is equal to 03H
ToS value is equal to 02H
ToS value is equal to 01H
ToS value is equal to 00H
TOS Priority Map 1 Register (219h)
Bit
15:14
Name
TOS_PM0F
ROM
1Eh.[15:14]
13:12
TOS_PM0E
1Eh.[13:12]
11:10
TOS_PM0D
1Eh.[11:10]
9:8
TOS_PM0C
1Eh.[09:08]
7:6
TOS_PM0B
1Eh.[07:06]
5:4
TOS_PM0A
1Eh.[05:04]
3:2
TOS_PM09
1Eh.[03:02]
1:0
TOS_PM08
1Eh.[01:00]
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
PSE0
RW
PSE0
RW
PSE0
RW
PSE0
RW
PSE0
RW
PSE0
RW
PSE0
RW
PSE0
RW
Description
ToS value is equal to 0FH
ToS value is equal to 0EH
ToS value is equal to 0DH
ToS value is equal to 0CH
ToS value is equal to 0BH
ToS value is equal to 0AH
ToS value is equal to 09H
ToS value is equal to 08H
61
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.10
TOS Priority Map 2 Register (21Ah)
Bit
15:14
Name
TOS_PM17
ROM
1Fh.[15:14]
13:12
TOS_PM16
1Fh.[13:12]
11:10
TOS_PM15
1Fh.[11:10]
9:8
TOS_PM14
1Fh.[09:08]
7:6
TOS_PM13
1Fh.[07:06]
5:4
TOS_PM12
1Fh.[05:04]
3:2
TOS_PM11
1Fh.[03:02]
1:0
TOS_PM10
1Fh.[01:00]
5.4.11
Default
PSE1
RW
PSE1
RW
PSE1
RW
PSE1
RW
PSE1
RW
PSE1
RW
PSE1
RW
PSE1
RW
Description
ToS value is equal to 17H
ToS value is equal to 16H
ToS value is equal to 15H
ToS value is equal to 14H
ToS value is equal to 13H
ToS value is equal to 12H
ToS value is equal to 11H
ToS value is equal to 10H
TOS Priority Map 3 Register (21Bh)
Bit
15:14
Name
TOS_PM1F
ROM
20h.[15:14]
13:12
TOS_PM1E
20h [13:12]
11:10
TOS_PM1D
20h.[11:10]
9:8
TOS_PM1C
20h.[09:08]
7:6
TOS_PM1B
20h.[07:06]
5:4
TOS_PM1A
20h.[05:04]
3:2
TOS_PM19
20h.[03:02]
1:0
TOS_PM18
20h.[01:00]
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
PSE1
RW
PSE1
RW
PSE1
RW
PSE1
RW
PSE1
RW
PSE1
RW
PSE1
RW
PSE1
RW
Description
ToS value is equal to 1FH
ToS value is equal to 1EH
ToS value is equal to 1DH
ToS value is equal to 1CH
ToS value is equal to 1BH
ToS value is equal to 1AH
ToS value is equal to 19H
ToS value is equal to 18H
62
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.12
TOS Priority Map 4 Register (21Ch)
Bit
15:14
Name
TOS_PM27
ROM
21h.[15:14]
13:12
TOS_PM26
21h.[13:12]
11:10
TOS_PM25
21h.[11:10]
9:8
TOS_PM24
21h.[09:08]
7:6
TOS_PM23
21h.[07:06]
5:4
TOS_PM22
21h.[05:04]
3:2
TOS_PM21
21h.[03:02]
1:0
TOS_PM20
21h.[01:00]
5.4.13
Default
PSE2
RW
PSE2
RW
PSE2
RW
PSE2
RW
PSE2
RW
PSE2
RW
PSE2
RW
PSE2
RW
Description
ToS value is equal to 27H
ToS value is equal to 26H
ToS value is equal to 25H
ToS value is equal to 24H
ToS value is equal to 23H
ToS value is equal to 22H
ToS value is equal to 21H
ToS value is equal to 20H
TOS Priority Map 5 Register (21Dh)
Bit
15:14
Name
TOS_PM2F
ROM
22h.[15:14]
13:12
TOS_PM2E
22h.[13:12]
11:10
TOS_PM2D
22h.[11:10]
9:8
TOS_PM2C
22h.[09:08]
7:6
TOS_PM2B
22h.[07:06]
5:4
TOS_PM2A
22h [05:04]
3:2
TOS_PM29
22h.[03:02]
1:0
TOS_PM28
22h.[01:00]
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
PSE2
RW
PSE2
RW
PSE2
RW
PSE2
RW
PSE2
RW
PSE2
RW
PSE2
RW
PSE2
RW
Description
ToS value is equal to 2FH
ToS value is equal to 2EH
ToS value is equal to 2DH
ToS value is equal to 2CH
ToS value is equal to 2BH
ToS value is equal to 2AH
ToS value is equal to 29H
ToS value is equal to 28H
63
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.14
TOS Priority Map 6 Register (21Eh)
Bit
15:14
Name
TOS_PM37
ROM
23h.[15:14]
13:12
TOS_PM36
23h.[13:12]
11:10
TOS_PM35
23h.[11:10]
9:8
TOS_PM34
23h.[09:08]
7:6
TOS_PM33
23h.[07:06]
5:4
TOS_PM32
23h.[05:04]
3:2
TOS_PM31
23h.[03:02]
1:0
TOS_PM30
23h.[01:00]
5.4.15
Default
PSE3
RW
PSE3
RW
PSE3
RW
PSE3
RW
PSE3
RW
PSE3
RW
PSE3
RW
PSE3
RW
Description
ToS value is equal to 37H
ToS value is equal to 36H
ToS value is equal to 35H
ToS value is equal to 34H
ToS value is equal to 33H
ToS value is equal to 32H
ToS value is equal to 31H
ToS value is equal to 30H
TOS Priority Map 7 Register (21Fh)
Bit
15:14
Name
TOS_PM3F
ROM
24h.[15:14]
13:12
TOS_PM3E
24h.[13:12]
11:10
TOS_PM3D
24h.[11:10]
9:8
TOS_PM3C
24h.[09:08]
7:6
TOS_PM3B
24h.[07:06]
5:4
TOS_PM3A
24h.[05:04]
3:2
TOS_PM39
24h.[03:02]
1:0
TOS_PM38
24h.[01:00]
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
PSE3
RW
PSE3
RW
PSE3
RW
PSE3
RW
PSE3
RW
PSE3
RW
PSE3
RW
PSE3
RW
Description
ToS value is equal to 3FH
ToS value is equal to 3EH
ToS value is equal to 3DH
ToS value is equal to 3CH
ToS value is equal to 3BH
ToS value is equal to 3AH
ToS value is equal to 39H
ToS value is equal to 38H
64
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.16
MIB Counter Disable Register (230h)
Bit
15:6
Name
RESERVED
ROM
－
5:0
MIB_DIS
16h.[5:0]
Default
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Per-Port MIB Counter Disable
[5]
[4]
[3]
[2]
[1]
[0]
5.4.17
MIB Counter Control Register (231h)
Bit
15
Name
MIB_READY
ROM
－
Default
PS0
RO
14:10
RESERVED
－
P0
RO
9:8
MIB_CMD
－
PS0
RW
7:5
MIB_PORT
－
4:0
MIB_OFSET
－
PS0
RW
PS0
RW
5.4.18
Bit
15:0
5.4.19
Bit
15:0
0: Port 5 MIB counter is enabled
1: Port 5 MIB counter is disabled
0: Port 4 MIB counter is enabled
1: Port 4 MIB counter is disabled
0: Port 3 MIB counter is enabled
1: Port 3 MIB counter is disabled
0: Port 2 MIB counter is enabled
1: Port 2 MIB counter is disabled
0: Port 1 MIB counter is enabled
1: Port 1 MIB counter is disabled
0: Port 0 MIB counter is enabled
1: Port 0 MIB counter is disabled
Description
Counter Data is Ready
0: Not ready
1: Ready
Reserved
Write as 0h, ignore when read
MIB Command
00: Read & Clear
01: Read only
10: Clear MIB counters of port
11: Clear MIB counters of all ports
Port Index (0~5)
Counter Offset (0~9)
MIB Counter Data Low Register (232h)
Name
MIB_DL
ROM
－
Default
PS0
RW
Description
Counter Data Low Byte (Bit 15:00)
MIB Counter Data High Register (233h)
Name
MIB_DH
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
ROM
－
Default
PS0
RW
Description
Counter Data High Byte (Bit 31:16)
65
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.20
Special Packet Control 0 Register (234h)
Bit
15
Name
RESERVED
ROM
－
14:13
SP01_ACT
26h.[14:13]
12:11
SP01_TAG
26h.[12:11]
PSE0
RW
10
SP01_OVERR
IDE
26h.[10]
PSE0
RW
9
SP01_CVLAN
26h.[09]
PSE0
RW
8
SP01_EN
26h.[08]
PSE0
RW
7
RESERVED
－
RO
6:5
SP00_ACT
26h.[06:05]
PSE0
RW
4:3
SP00_TAG
26h.[04:03]
PSE0
RW
2
SP00_OVERR
IDE
26h.[02]
PSE0
RW
1
SP00_CVLAN
26h.[01]
PSE0
RW
0
SP00_EN
26h.[00]
PSE0
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Forwarding Action for PAUSE
00: Unmodified
01: Drop
10: Trap to CPU
11: Flood excluding CPU
TX Tag Handle for PAUSE
00: Unmodified
01: Always Tagged
10: Always Untagged
11: Reserved
Override bit for PAUSE
0: Not a overriding packet
1: A Overriding packet
Cross VLAN bit for PAUSE
0: Obey VLAN constraint
1: Can cross VLAN constraint
Identify Enable for PAUSE
DMAC=0180C2-000001
0: Disable
1: Enable
Reserved
Write as 0h, ignore when read
Forwarding Action for BPDU
00: Unmodified
01: Drop
10: Trap to CPU
11: Flood excluding CPU
TX Tag Handle for BPDU
00: Unmodified
01: Always Tagged
10: Always Untagged
11: Reserved
Override bit for BPDU
0: Not a overriding packet
1: A Overriding packet
Cross VLAN bit for BPDU
0: Obey VLAN constraint
1: Can cross VLAN constraint
Identify Enable for BPDU
DMAC=0180C2-000000
0: Disable
1: Enable
66
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.21
Special Packet Control 1 Register (235h)
Bit
15
Name
RESERVED
ROM
－
14:13
SP03_ACT
27h.[14:13]
12:11
SP03_TAG
27h.[12:11]
PSE0
RW
10
SP03_OVERR
IDE
27h.[10]
PSE0
RW
9
SP03_CVLAN
27h.[09]
PSE0
RW
8
SP03_EN
27h.[08]
PSE0
RW
7
RESERVED
－
P0
RO
6:5
SP02_ACT
27h.[06:05]
PSE0
RW
4:3
SP02_TAG
27h.[04:03]
PSE0
RW
2
SP02_OVERR
IDE
27h.[02]
PSE0
RW
1
SP02_CVLAN
27h.[01]
PSE0
RW
0
SP02_EN
27h.[00]
PSE0
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Forwarding Action for EAP(802.1x)
00: Unmodified
01: Drop
10: Trap to CPU
11: Flood excluding CPU
TX Tag Handle for EAP(802.1x)
00: Unmodified
01: Always Tagged
10: Always Untagged
11: Reserved
Override bit for EAP(802.1x)
0: Not a overriding packet
1: A Overriding packet
Cross VLAN bit for EAP(802.1x)
0: Obey VLAN constraint
1: Can cross VLAN constraint
Identify Enable for EAP(802.1x)
DMAC=0180C2-000003
0: Disable
1: Enable
Reserved
Write as 0h, ignore when read
Forwarding Action for SlowProtocol
00: Unmodified
01: Drop
10: Trap to CPU
11: Flood excluding CPU
TX Tag Handle for SlowProtocol
00: Unmodified
01: Always Tagged
10: Always Untagged
11: Reserved
Override bit for SlowProtocol
0: Not a overriding packet
1: A Overriding packet
Cross VLAN bit for SlowProtocol
0: Obey VLAN constraint
1: Can cross VLAN constraint
Identify Enable for SlowProtocol
DMAC=0180C2-000002
0: Disable
1: Enable
67
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.22
Special Packet Control 2 Register (236h)
Bit
15
Name
RESERVED
ROM
－
14:13
SP05_ACT
28h.[14:13]
12:11
SP05_TAG
28h.[12:11]
PSE0
RW
10
SP05_OVERR
IDE
28h.[10]
PSE0
RW
9
SP05_CVLAN
28h.[09]
PSE0
RW
8
SP05_EN
28h.[08]
PSE0
RW
7
RESERVED
－
P0
RO
6:5
SP04_ACT
28h.[06:05]
PSE0
RW
4:3
SP04_TAG
28h.[04:03]
PSE0
RW
2
SP04_OVERR
IDE
28h.[02]
PSE0
RW
1
SP04_CVLAN
28h.[01]
PSE0
RW
0
SP04_EN
28h.[00]
PSE0
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Forwarding Action for LLDP
00: Unmodified
01: Drop
10: Trap to CPU
11: Flood excluding CPU
TX Tag Handle for LLDP
00: Unmodified
01: Always Tagged
10: Always Untagged
11: Reserved
Override bit for LLDP
0: Not a overriding packet
1: A Overriding packet
Cross VLAN bit for LLDP
0: Obey VLAN constraint
1: Can cross VLAN constraint
Identify Enable for LLDP
DMAC=0180C2-0000E
0: Disable
1: Enable
Reserved
Write as 0h, ignore when read
Forwarding Action for RESERV_B0
00: Unmodified
01: Drop
10: Trap to CPU
11: Flood excluding CPU
TX Tag Handle for RESERV_B0
00: Unmodified
01: Always Tagged
10: Always Untagged
11: Reserved
Override bit for RESERV_B0
0: Not a overriding packet
1: A Overriding packet
Cross VLAN bit for RESERV_B0
0: Obey VLAN constraint
1: Can cross VLAN constraint
Identify Enable for RESERV_B0
DMAC=0180C2-000004 ~ 0180C2-00000D & 0180C2-00000F
0: Disable
1: Enable
68
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.23
Special Packet Control 3 Register (237h)
Bit
15
Name
RESERVED
ROM
－
14:13
SP07_ACT
29h.[14:13]
12:11
SP07_TAG
29h.[12:11]
PSE0
RW
10
SP07_OVERR
IDE
29h.[10]
PSE0
RW
9
SP07_CVLAN
29h.[09]
PSE0
RW
8
SP07_EN
29h.[08]
PSE0
RW
7
RESERVED
－
P0
RO
6:5
SP06_ACT
29h.[06:05]
PSE0
RW
4:3
SP06_TAG
29h.[04:03]
PSE0
RW
2
SP06_OVERR
IDE
29h.[02]
PSE0
RW
1
SP06_CVLAN
29h.[01]
PSE0
RW
0
SP06_EN
29h.[00]
PSE0
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Forwarding Action for RESERV_B1
00: Unmodified
01: Drop
10: Trap to CPU
11: Flood excluding CPU
TX Tag Handle for RESERV_B1
00: Unmodified
01: Always Tagged
10: Always Untagged
11: Reserved
Override bit for RESERV_B1
0: Not a overriding packet
1: A Overriding packet
Cross VLAN bit for RESERV_B1
0: Obey VLAN constraint
1: Can cross VLAN constraint
Identify Enable for RESERV_B1
DMAC=0180C2-000011 ~ 0180C2-00001F
0: Disable
1: Enable
Reserved
Write as 0h, ignore when read
Forwarding Action for ABM
00: Unmodified
01: Drop
10: Trap to CPU
11: Flood excluding CPU
TX Tag Handle for ABM
00: Unmodified
01: Always Tagged
10: Always Untagged
11: Reserved
Override bit for ABM
0: Not a overriding packet
1: A Overriding packet
Cross VLAN bit for ABM
0: Obey VLAN constraint
1: Can cross VLAN constraint
Identify Enable for ABM
(All LAN Bridge Management Group Address)
DMAC=0180C2-000010
0: Disable
1: Enable
69
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.24
Special Packet Control 4 Register (238h)
Bit
15
Name
RESERVED
ROM
－
14:13
SP09_ACT
2Ah.[14:13]
12:11
SP09_TAG
2Ah.[12:11]
PSE0
RW
10
SP09_OVERR
IDE
2Ah.[10]
PSE0
RW
9
SP09_CVLAN
2Ah.[09]
PSE0
RW
8
SP09_EN
2Ah.[08]
PSE0
RW
7
RESERVED
－
P0
RO
6:5
SP08_ACT
2Ah.[06:05]
PSE0
RW
4:3
SP08_TAG
2Ah.[04:03]
PSE0
RW
2
SP08_OVERR
IDE
2Ah.[02]
PSE0
RW
1
SP08_CVLAN
2Ah.[01]
PSE0
RW
0
SP08_EN
2Ah.[00]
PSE0
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Forwarding Action for RESERV_B2
00: Unmodified
01: Drop
10: Trap to CPU
11: Flood excluding CPU
TX Tag Handle for RESERV_B2
00: Unmodified
01: Always Tagged
10: Always Untagged
11: Reserved
Override bit for RESERV_B2
0: Not a overriding packet
1: A Overriding packet
Cross VLAN bit for RESERV_B2
0: Obey VLAN constraint
1: Can cross VLAN constraint
Identify Enable for RESERV_B2
DMAC=0180C2-000022 ~ 0180C2-00002F
0: Disable
1: Enable
Reserved
Write as 0h, ignore when read
Forwarding Action for GXRP
00: Unmodified
01: Drop
10: Trap to CPU
11: Flood excluding CPU
TX Tag Handle for GXRP
00: Unmodified
01: Always Tagged
10: Always Untagged
11: Reserved
Override bit for GXRP
0: Not a overriding packet
1: A Overriding packet
Cross VLAN bit for GXRP
0: Obey VLAN constraint
1: Can cross VLAN constraint
Identify Enable for GXRP(GARP/GVRP)
DMAC=0180C2-000020, 0180C2-000021
0: Disable
1: Enable
70
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.25
Special Packet Control 5 Register (239h)
Bit
15:7
Name
RESERVED
ROM
－
6:5
SP0A_ACT
2Bh.[06:05]
4:3
SP0A_TAG
2Bh.[04:03]
PSE0
RW
2
SP0A_OVERR
IDE
2Bh.[02]
PSE0
RW
1
SP0A_CVLAN
2Bh.[01]
PSE0
RW
0
SP0A_EN
2Bh.[00]
PSE0
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Forwarding Action for RESERV_B3
00: Unmodified
01: Drop
10: Trap to CPU
11: Flood excluding CPU
TX Tag Handle for RESERV_B3
00: Unmodified
01: Always Tagged
10: Always Untagged
11: Reserved
Override bit for RESERV_B3
0: Not a overriding packet
1: A Overriding packet
Cross VLAN bit for RESERV_B3
0: Obey VLAN constraint
1: Can cross VLAN constraint
Identify Enable for RESERV_B3
DMAC=0180C2-000030 ~ 0180C2-0000FF
0: Disable
1: Enable
71
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.26
Special Packet Control 6 Register (23Ah)
Bit
15
Name
RESERVED
ROM
－
14:13
SP0D_ACT
2Ch.[14:13]
12:11
SP0D_TAG
2Ch.[12:11]
PSE0
RW
10
SP0D_OVER
RIDE
2Ch.[10]
PSE0
RW
9
SP0D_CVLAN
2Ch.[09]
PSE0
RW
8
SP0D_EN
2Ch.[08]
PSE0
RW
7
RESERVED
－
P0
RO
6:5
SP0C_ACT
2Ch.[06:05]
PSE0
RW
4:3
SP0C_TAG
2Ch.[04:03]
PSE0
RW
2
SP0C_OVER
RIDE
2Ch.[02]
PSE0
RW
1
SP0C_CVLAN
2Ch.[01]
PSE0
RW
0
SP0C_EN
2Ch.[00]
PSE0
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Forwarding Action for ARP
00: Unmodified
01: Drop
10: Trap to CPU
11: Flood excluding CPU
TX Tag Handle for ARP
00: Unmodified
01: Always Tagged
10: Always Untagged
11: Reserved
Override bit for ARP
0: Not a overriding packet
1: A Overriding packet
Cross VLAN bit for ARP
0: Obey VLAN constraint
1: Can cross VLAN constraint
Identify Enable for ARP
DMAC=FFFFFF-FFFFFF, EthType=8036
0: Disable
1: Enable
Reserved
Write as 0h, ignore when read
Forwarding Action for RARP
00: Unmodified
01: Drop
10: Trap to CPU
11: Flood excluding CPU
TX Tag Handle for RARP
00: Unmodified
01: Always Tagged
10: Always Untagged
11: Reserved
Override bit for RARP
0: Not a overriding packet
1: A Overriding packet
Cross VLAN bit for RARP
0: Obey VLAN constraint
1: Can cross VLAN constraint
Identify Enable for RARP
DMAC=FFFFFF-FFFFFF, EthType=0x8035
0: Disable
1: Enable
72
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.27
Special Packet Control 7 Register (23Bh)
Bit
15
Name
RESERVED
ROM
－
14:13
SP0F_ACT
2Dh.[14:13]
12:11
SP0F_TAG
2Dh.[12:11]
PSE0
RW
10
SP0F_OVERR
IDE
2Dh.[10]
PSE0
RW
9
SP0F_CVLAN
2Dh.[09]
PSE0
RW
8
SP0F_EN
2Dh.[08]
PSE0
RW
7
RESERVED
－
P0
RO
6:5
SP0E_ACT
2Dh.[06:05]
PSE0
RW
4:3
SP0E_TAG
2Dh.[04:03]
PSE0
RW
2
SP0E_OVERR
IDE
2Dh.[02]
PSE0
RW
1
SP0E_CVLAN
2Dh.[01]
PSE0
RW
0
SP0E_EN
2Dh.[00]
PSE0
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Forwarding Action for IPV6_MLD
00: Unmodified
01: Drop
10: Trap to CPU
11: Flood excluding CPU
TX Tag Handle for IPV6_MLD
00: Unmodified
01: Always Tagged
10: Always Untagged
11: Reserved
Override bit for IPV6_MLD
0: Not a overriding packet
1: A Overriding packet
Cross VLAN bit for IPV6_MLD
0: Obey VLAN constraint
1: Can cross VLAN constraint
Identify Enable for IPV6_MLD
DMAC==3333XX-XXXXXX, EthType=0x86DD,
IP.Version=6, Next field?
0: Disable
1: Enable
Reserved
Write as 0h, ignore when read
Forwarding Action for IP_IGMP
00: Unmodified
01: Drop
10: Trap to CPU
11: Flood excluding CPU
TX Tag Handle for IP_IGMP
00: Unmodified
01: Always Tagged
10: Always Untagged
11: Reserved
Override bit for IP_IGMP
0: Not a overriding packet
1: A Overriding packet
Cross VLAN bit for IP_IGMP
0: Obey VLAN constraint
1: Can cross VLAN constraint
Identify Enable for IP_IGMP
DMAC=01005E-XXXXXX, EthType=0x0800, IP.Version=4,
IP.Protocol=02
0: Disable
1: Enable
73
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.28
Special Packet Control 8 Register (23Ch)
Bit
15
Name
RESERVED
ROM
－
14:13
SP11_ACT
2Eh.[14:13]
12:11
SP11_TAG
2Eh.[12:11]
PSE0
RW
10
SP11_OVERR
IDE
2Eh.[10]
PSE0
RW
9
SP11_CVLAN
2Eh.[09]
PSE0
RW
8
SP11_EN
2Eh.[08]
PSE0
RW
7
RESERVED
－
P0
RO
6:5
SP10_ACT
2Eh.[06:05]
PSE0
RW
4:3
SP10_TAG
2Eh.[04:03]
PSE0
RW
2
SP10_OVERR
IDE
2Eh.[02]
PSE0
RW
1
SP10_CVLAN
2Eh.[01]
PSE0
RW
0
SP10_EN
2Eh.[00]
PSE0
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Forwarding Action for PPPoE
00: Unmodified
01: Drop
10: Trap to CPU
11: Flood excluding CPU
TX Tag Handle for PPPoE
00: Unmodified
01: Always Tagged
10: Always Untagged
11: Reserved
Override bit for PPPoE
0: Not a overriding packet
1: A Overriding packet
Cross VLAN bit for PPPoE
0: Obey VLAN constraint
1: Can cross VLAN constraint
Identify Enable for PPPoE
EthType=0x8863/0x8864
0: Disable
1: Enable
Reserved
Write as 0h, ignore when read
Forwarding Action for IP_ICMP
00: Unmodified
01: Drop
10: Trap to CPU
11: Flood excluding CPU
TX Tag Handle for IP_ICMP
00: Unmodified
01: Always Tagged
10: Always Untagged
11: Reserved
Override bit for IP_ICMP
0: Not a overriding packet
1: A Overriding packet
Cross VLAN bit for IP_ICMP
0: Obey VLAN constraint
1: Can cross VLAN constraint
Identify Enable for IP_ICMP
EthType=0x0800, IP.Version=4, IP.Protocol=01
0: Disable
1: Enable
74
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.29
Bit
15:0
5.4.30
QinQ TPID Register (23Dh)
Name
QinQ_TPID
ROM
30h.[15:0]
Default
PSE
88A8h
RW
Description
QinQ Tag Protocol Identifier
For VLAN stacking function
VLAN Mode and Rule Control Register (23Eh)
Bit
15
Name
FIR_VIDFFF
ROM
31h.[15]
Default
PSE0
RW
14
FIR_CFI
31h.[14]
PSE0
RW
13:12
VLAN_UVID
31h.[13:12]
PSE0
RW
11:9
RESERVED
－
P0
RO
8
QINQ_EN
31h.[8]
PSE0
RW
7
TOS6
31h.[7]
PE0
RW
6
RESERVED
－
P0
RO
5
UCLEAKY_EN
31h.[5]
PE0
RW
4
VLAN_RVIDFFF
31h.[4]
PSE0
RW
3
VLAN_RVID1
31h.[3]
PSE0
RW
2
VLAN_RVIDO
31h.[2]
PSE0
RW
1
VLAN_RPRI
31h.[1]
PSE0
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Description
Enable to drop Pakcet with VID==0xFFF
0: Disable
1: Enable
Enable to drop Pakcet with Nonzero CFI
Drop incoming packet, if the CFI field is not equal to zero.
0: Disable
1: Enable
Unknown VID Handle
00: Drop
01: Trap to CPU
10: Trap to Sniffer Port
11: Reserved
Reserved
Write as 0h, ignore when read
VLAN Stacking Enable (QinQ)
0: Disable
1: Enable
Full IP ToS Field for Priority Queue
0: Check most significant 3-bit only of TOS
1: Check most significant 6-bit of TOS
Reserved
Write as 0h, ignore when read
Unicast packet can across VLAN boundary.
The function allows switch without external router when
inter-VLAN communicate in switch.
0: Disable
1: Enable
Replace VIDFFF with PVID Enable
Replace VID field of VLAN tag with PVID, if VID==0xFFF
0: Disable
1: Enable
Replace VID1 with PVID Enable
Replace VID field of VLAN tag with PVID, if VID==0x001
0: Disable
1: Enable
Replace VID0 with PVID Enable
Replace VID field of VLAN tag with PVID, if VID==0x000
0: Disable
1: Enable
Replace Priority Enable
Replace priority field of VLAN tag with PPRI
0: Disable
1: Enable
75
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
0
VLAN_MODE
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
31h.[0]
PSE0
RW
VLAN_MODE
0: Port-based VLAN
1: Tag-based VLAN
76
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.31
Bit
15:0
5.4.32
VLAN Table - Valid Control Register (23Fh)
Name
VTAB_VALD
ROM
32h.[15:0]
Name
VTAB_FID0
ROM
33h.[15:12]
11:00
VTAB_VID0
33h.[11:00]
Name
VTAB_FID1
ROM
34h.[15:12]
11:00
VTAB_VID1
34h.[11:00]
Name
VTAB_FID2
ROM
35h.[15:12]
11:00
VTAB_VID2
35h.[11:00]
VID of VLAN Entry 0
Default
PSE0
RW
PSE0
RW
Description
FID of VLAN Entry 1
VID of VLAN Entry 1
Default
PSE0
RW
PSE0
RW
Description
FID of VLAN Entry 2
VID of VLAN Entry 2
VLAN Table - ID_3H Register (253h)
Bit
15:12
Name
VTAB_FID3
ROM
36h.[15:12]
11:00
VTAB_VID3
36h.[11:00]
5.4.36
Description
FID of VLAN Entry 0
VLAN Table - ID_2H Register (252h)
Bit
15:12
5.4.35
Default
PSE0
RW
PSE1
RW
VLAN Table - ID_1H Register (251h)
Bit
15:12
5.4.34
Description
Entry Vailid Bits in VLAN Table
There are 16 entries in the VLAN table. This field
indicates which entries are valid.
0: Invalid
1: Valid
VLAN Table - ID_0H Register (250h)
Bit
15:12
5.4.33
Default
PSE
01H
RW
Default
PSE0
RW
PSE0
RW
Description
FID of VLAN Entry 3
VID of VLAN Entry 3
VLAN Table - ID_4H Register (254h)
Bit
15:12
Name
VTAB_FID4
ROM
37h.[15:12]
11:00
VTAB_VID4
37h.[11:00]
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
PSE0
RW
PSE0
RW
Description
FID of VLAN Entry 4
VID of VLAN Entry 4
77
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.37
VLAN Table - ID_5H Register (255h)
Bit
15:12
Name
VTAB_FID5
ROM
38h.[15:12]
11:00
VTAB_VID5
38h.[11:00]
5.4.38
Name
VTAB_FID6
ROM
39h.[15:12]
11:00
VTAB_VID6
39h.[11:00]
Name
VTAB_FID7
ROM
3Ah.[15:12]
11:00
VTAB_VID7
3Ah.[11:00]
Name
VTAB_FID8
ROM
3Bh.[15:12]
11:00
VTAB_VID8
3Bh.[11:00]
Default
PSE0
RW
PSE0
RW
Description
FID of VLAN Entry 6
VID of VLAN Entry 6
Default
PSE0
RW
PSE0
RW
Description
FID of VLAN Entry 7
VID of VLAN Entry 7
Default
PSE0
RW
PSE0
RW
Description
FID of VLAN Entry 8
VID of VLAN Entry 8
VLAN Table - ID_9H Register (259h)
Bit
15:12
Name
VTAB_FID9
ROM
3Ch.[15:12]
11:00
VTAB_VID9
3Ch.[11:00]
5.4.42
VID of VLAN Entry 5
VLAN Table - ID_8H Register (258h)
Bit
15:12
5.4.41
FID of VLAN Entry 5
VLAN Table - ID_7H Register (257h)
Bit
15:12
5.4.40
Description
VLAN Table - ID_6H Register (256h)
Bit
15:12
5.4.39
Default
PSE0
RW
PSE0
RW
Default
PSE0
RW
PSE0
RW
Description
FID of VLAN Entry 9
VID of VLAN Entry 9
VLAN Table - ID_AH Register (25Ah)
Bit
15:12
Name
VTAB_FIDA
ROM
3Dh.[15:12]
11:00
VTAB_VIDA
3Dh.[11:00]
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
PSE0
RW
PSE0
RW
Description
FID of VLAN Entry 10
VID of VLAN Entry 10
78
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.43
VLAN Table - ID_BH Register (25Bh)
Bit
15:12
Name
VTAB_FIDB
ROM
3Eh.[15:12]
11:00
VTAB_VIDB
3Eh.[11:00]
5.4.44
Name
VTAB_FIDC
ROM
3Fh.[15:12]
11:00
VTAB_VIDC
3Fh.[11:00]
Name
VTAB_FIDD
ROM
40h.[15:12]
11:00
VTAB_VIDD
40h.[11:00]
VID of VLAN Entry 11
Default
PSE0
RW
PSE0
RW
Description
FID of VLAN Entry 12
VID of VLAN Entry 12
Default
PSE0
RW
PSE0
RW
Description
FID of VLAN Entry 13
VID of VLAN Entry 13
VLAN Table - ID_EH Register (25Eh)
Bit
15:12
Name
VTAB_FIDF
ROM
41h.[15:12]
11:00
VTAB_VIDF
41h.[11:00]
5.4.47
FID of VLAN Entry 11
VLAN Table - ID_DH Register (25Dh)
Bit
15:12
5.4.46
Description
VLAN Table - ID_CH Register (25Ch)
Bit
15:12
5.4.45
Default
PSE0
RW
PSE0
RW
Default
PSE0
RW
PSE0
RW
Description
FID of VLAN Entry 14
VID of VLAN Entry 14
VLAN Table - ID_FH Register (25Fh)
Bit
15:12
Name
VTAB_FIDF
ROM
42h.[15:12]
11:00
VTAB_VIDF
42h.[11:00]
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
PSE0
RW
PSE0
RW
Description
FID of VLAN Entry 15
VID of VLAN Entry 15
79
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.48
VLAN Table - MEMBER_0H Register (270h)
Bit
15:14
Name
RESERVED
ROM
－
13:8
VTAB_TM0
43h.[13:8]
Default
P0
RO
PSE0
RW
7:6
RESERVED
－
P0
RO
5:0
VTAB_VM0
43h.[5:0]
PSE
3Fh
RW
Description
Reserved
Write as 0h, ignore when read
Tagged Member of VLAN Entry 0
Port map indicates which ports are forced output tagging.
[13]: Port 5
[12]: Port 4 [11]: Port 3
[10]: Port 2
[09]: Port 1 [08]: Port 0
0: Disable
1: Enable
Reserved
Write as 0h, ignore when read
VLAN Member of VLAN Entry 0
Port map indicates which ports belong to this VLAN
entry.
[05]: Port 5
[04]: Port 4 [03]: Port 3
[02]: Port 2
[01]: Port 1 [00]: Port 0
0: Disable
1: Enable
5.4.49
VLAN Table - MEMBER_1H Register (271h)
Bit
15:14
Name
RESERVED
ROM
－
Default
RO
13:8
VTAB_TM1
44h.[13:8]
7:6
RESERVED
－
PSE0
RW
RO
5:0
VTAB_VM1
44h.[5:0]
5.4.50
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Tagged Member of VLAN Entry 1
Reserved
Write as 0h, ignore when read
VLAN Member of VLAN Entry 1
VLAN Table - MEMBER_2H Register (272h)
Bit
15:14
Name
RESERVED
ROM
－
13:8
VTAB_TM2
45h.[13:8]
7:6
RESERVED
－
5:0
VTAB_VM2
45h.[5:0]
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PSE0
RW
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Tagged Member of VLAN Entry 2
Reserved
Write as 0h, ignore when read
VLAN Member of VLAN Entry 2
80
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.51
VLAN Table - MEMBER_3H Register (273h)
Bit
15:14
Name
RESERVED
ROM
－
13:8
VTAB_TM3
46h.[13:8]
7:6
RESERVED
－
5:0
VTAB_VM3
46h.[5:0]
5.4.52
Name
RESERVED
ROM
－
13:8
VTAB_TM4
47h.[13:8]
7:6
RESERVED
－
5:0
VTAB_VM4
47h.[5:0]
Reserved
Write as 0h, ignore when read
Tagged Member of VLAN Entry 3
Reserved
Write as 0h, ignore when read
VLAN Member of VLAN Entry 3
Default
P0
RO
PSE0
RW
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Tagged Member of VLAN Entry 4
Reserved
Write as 0h, ignore when read
VLAN Member of VLAN Entry 4
VLAN Table - MEMBER_5H Register (275h)
Bit
15:14
Name
RESERVED
ROM
－
13:8
VTAB_TM5
48h.[13:8]
7:6
RESERVED
－
5:0
VTAB_VM5
48h.[5:0]
5.4.54
Description
VLAN Table - MEMBER_4H Register (274h)
Bit
15:14
5.4.53
Default
P0
RO
PSE0
RW
P0
RO
PSE0
RW
Default
P0
RO
PSE0
RW
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Tagged Member of VLAN Entry 5
Reserved
Write as 0h, ignore when read
VLAN Member of VLAN Entry 5
VLAN Table - MEMBER_6H Register (276h)
Bit
15:14
Name
RESERVED
ROM
－
13:8
VTAB_TM6
49h.[13:8]
7:6
RESERVED
－
5:0
VTAB_VM6
49h.[5:0]
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PSE0
RW
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Tagged Member of VLAN Entry 6
Reserved
Write as 0h, ignore when read
VLAN Member of VLAN Entry 6
81
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.55
VLAN Table - MEMBER_7H Register (277h)
Bit
15:14
Name
RESERVED
ROM
－
Default
RO
13:8
VTAB_TM7
4Ah.[13:8]
7:6
RESERVED
－
PSE0
RW
RO
5:0
VTAB_VM7
4Ah.[5:0]
5.4.56
Name
RESERVED
ROM
－
13:8
VTAB_TM8
4Bh.[13:8]
7:6
RESERVED
－
5:0
VTAB_VM8
4Bh.[5:0]
Reserved
Write as 0h, ignore when read
VLAN Member of VLAN Entry 7
Default
P0
RO
PSE0
RW
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Tagged Member of VLAN Entry 8
Reserved
Write as 0h, ignore when read
VLAN Member of VLAN Entry 8
VLAN Table - MEMBER_9H Register (279h)
Bit
15:14
Name
RESERVED
ROM
－
13:8
VTAB_TM9
4Ch.[13:8]
7:6
RESERVED
－
5:0
VTAB_VM9
4Ch.[5:0]
5.4.58
Reserved
Write as 0h, ignore when read
Tagged Member of VLAN Entry 7
VLAN Table - MEMBER_8H Register (278h)
Bit
15:14
5.4.57
PSE0
RW
Description
Default
P0
RO
PSE0
RW
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Tagged Member of VLAN Entry 9
Reserved
Write as 0h, ignore when read
VLAN Member of VLAN Entry 9
VLAN Table - MEMBER_AH Register (27Ah)
Bit
15:14
Name
RESERVED
ROM
－
13:8
VTAB_TMA
4Dh.[13:8]
7:6
RESERVED
－
5:0
VTAB_VMA
4Dh.[5:0]
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PSE0
RW
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Tagged Member of VLAN Entry 10
Reserved
Write as 0h, ignore when read
VLAN Member of VLAN Entry 10
82
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.59
VLAN Table - MEMBER_BH Register (27Bh)
Bit
15:14
Name
RESERVED
ROM
－
13:8
VTAB_TMB
4Eh.[13:8]
7:6
RESERVED
－
5:0
VTAB_VMB
4Eh.[5:0]
5.4.60
Name
RESERVED
ROM
－
13:8
VTAB_TMC
4Fh.[13:8]
7:6
RESERVED
－
5:0
VTAB_VMC
4Fh.[5:0]
Reserved
Write as 0h, ignore when read
Tagged Member of VLAN Entry 11
Reserved
Write as 0h, ignore when read
VLAN Member of VLAN Entry 11
Default
P0
RO
PSE0
RW
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Tagged Member of VLAN Entry 12
Reserved
Write as 0h, ignore when read
VLAN Member of VLAN Entry 12
VLAN Table - MEMBER_DH Register (27Dh)
Bit
15:14
Name
RESERVED
ROM
－
13:8
VTAB_TMD
50h.[13:8]
7:6
RESERVED
－
5:0
VTAB_VMD
50h.[5:0]
5.4.62
Description
VLAN Table - MEMBER_CH Register (27Ch)
Bit
15:14
5.4.61
Default
P0
RO
PSE0
RW
P0
RO
PSE0
RW
Default
P0
RO
PSE0
RW
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Tagged Member of VLAN Entry 13
Reserved
Write as 0h, ignore when read
VLAN Member of VLAN Entry 13
VLAN Table - MEMBER_EH Register (27Eh)
Bit
15:14
Name
RESERVED
ROM
－
13:8
VTAB_TME
51h.[13:8]
7:6
RESERVED
－
5:0
VTAB_VME
51h.[5:0]
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PSE0
RW
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Tagged Member of VLAN Entry 14
Reserved
Write as 0h, ignore when read
VLAN Member of VLAN Entry 14
83
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.63
VLAN Table - MEMBER_FH Register (27Fh)
Bit
15:14
Name
RESERVED
ROM
－
13:8
VTAB_TMF
52h.[13:8]
7:6
RESERVED
－
5:0
VTAB_VMF
52h.[5:0]
5.4.64
Bit
15:0
5.4.65
Bit
15:0
Default
P0
RO
PSE0
RW
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
Tagged Member of VLAN Entry 15
Reserved
Write as 0h, ignore when read
VLAN Member of VLAN Entry 15
VLAN Table - Priority Enable Register (290h)
Name
VTAB_PEN
ROM
53h.[15:0]
Default
PSE0
RW
Description
VLAN-based Priority Enable
This field is used to enable VLAN-based priority of each
entry. The priority queue number is decided in
VTAB_QUE field of register 293H to 299H.
0: Disable
1: Enable
VLAN Table - STP Index Enable Register (292h)
Name
VTAB_STPE
ROM
55h.[15:0]
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
PSE0
RW
Description
VLAN-based STP Enable
DM8806 supports four Spanning Tree Instance in MSTP
application. This field is used to enable the function of
each entry. The index of Spanning Tree Instance of each
VLAN is listed in VTAB_STPIDX field of register 293H to
299H.
0: Disable
1: Enable
84
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.66
VLAN Table - Misc_0 Register (293h)
Bit
15
Name
RESERVED
ROM
－
14:13
56h.[14:13]
12:10
VTAB_STPID
X_1
RESERVED
9:8
VTAB_QUE_1
56h.[9:8]
7
RESERVED
－
6:5
56h.[6:5]
4:2
VTAB_STPID
X_0
RESERVED
1:0
VTAB_QUE_0
56h.[1:0]
5.4.67
－
－
Default
P0
RO
PSE0
RW
P0
RO
PSE0
RW
P0
RO
PSE0
RW
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
STP Index of VLAN Entry 1
Reserved
Write as 0h, ignore when read
Priority Queue Number of VLAN Entry 1
Reserved
Write as 0h, ignore when read
STP Index of VLAN Entry 0
Reserved
Write as 0h, ignore when read
Priority Queue Number of VLAN Entry 0
VLAN Table - Misc_1 Register (294h)
Bit
15
Name
RESERVED
ROM
－
14:13
57h.[14:13]
12:10
VTAB_STPID
X_3
RESERVED
9:8
VTAB_QUE_3
57h.[9:8]
7
RESERVED
－
6:5
57h.[6:5]
4:2
VTAB_STPID
X_2
RESERVED
1:0
VTAB_QUE_2
57h.[1:0]
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
－
－
Default
P0
RO
PSE0
RW
P0
RO
PSE0
RW
P0
RO
PSE0
RW
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
STP Index of VLAN Entry 3
Reserved
Write as 0h, ignore when read
Priority Queue Number of VLAN Entry 3
Reserved
Write as 0h, ignore when read
STP Index of VLAN Entry 2
Reserved
Write as 0h, ignore when read
Priority Queue Number of VLAN Entry 2
85
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.68
VLAN Table - Misc_2 Register (295h)
Bit
15
Name
RESERVED
ROM
－
14:13
58h.[14:13]
12:10
VTAB_STPID
X_5
RESERVED
9:8
VTAB_QUE_5
58h.[9:8]
7
RESERVED
－
6:5
58h.[6:5]
4:2
VTAB_STPID
X_4
RESERVED
1:0
VTAB_QUE_4
58h.[1:0]
5.4.69
－
－
Default
P0
RO
PSE0
RW
P0
RO
PSE0
RW
P0
RO
PSE0
RW
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
STP Index of VLAN Entry 5
Reserved
Write as 0h, ignore when read
Priority Queue Number of VLAN Entry 5
Reserved
Write as 0h, ignore when read
STP Index of VLAN Entry 4
Reserved
Write as 0h, ignore when read
Priority Queue Number of VLAN Entry 4
VLAN Table - Misc_3 Register (296h)
Bit
15
Name
RESERVED
ROM
－
14:13
59h.[14:13]
12:10
VTAB_STPID
X_7
RESERVED
9:8
VTAB_QUE_7
59h.[9:8]
7
RESERVED
－
6:5
59h.[6:5]
4:2
VTAB_STPID
X_6
RESERVED
1:0
VTAB_QUE_6
59h.[1:0]
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
－
－
Default
P0
RO
PSE0
RW
P0
RO
PSE0
RW
P0
RO
PSE0
RW
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
STP Index of VLAN Entry 7
Reserved
Write as 0h, ignore when read
Priority Queue Number of VLAN Entry 7
Reserved
Write as 0h, ignore when read
STP Index of VLAN Entry 6
Reserved
Write as 0h, ignore when read
Priority Queue Number of VLAN Entry 6
86
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.70
VLAN Table - Misc_4 Register (297h)
Bit
15
Name
RESERVED
ROM
－
14:13
VTAB_STPIDX_9
5Ah.[14:13]
12:10
RESERVED
－
9:8
VTAB_QUE_9
5Ah.[9:8]
7
RESERVED
－
6:5
VTAB_STPIDX_8
5Ah.[6:5]
4:2
RESERVED
－
1:0
VTAB_QUE_8
5Ah.[1:0]
5.4.71
Default
P0
RO
PSE0
RW
P0
RO
PSE0
RW
P0
RO
PSE0
RW
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
STP Index of VLAN Entry 9
Reserved
Write as 0h, ignore when read
Priority Queue Number of VLAN Entry 9
Reserved
Write as 0h, ignore when read
STP Index of VLAN Entry 8
Reserved
Write as 0h, ignore when read
Priority Queue Number of VLAN Entry 8
VLAN Table - Misc_5 Register (298h)
Bit
15
Name
RESERVED
ROM
－
14:13
VTAB_STPIDX_B
5Bh.[14:13]
12:10
RESERVED
－
9:8
VTAB_QUE_B
5Bh.[9:8]
7
RESERVED
－
6:5
VTAB_STPIDX_A
5Bh.[6:5]
4:2
RESERVED
－
1:0
VTAB_QUE_A
5Bh.[1:0]
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PSE0
RW
P0
RO
PSE0
RW
P0
RO
PSE0
RW
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
STP Index of VLAN Entry 11
Reserved
Write as 0h, ignore when read
Priority Queue Number of VLAN Entry 11
Reserved
Write as 0h, ignore when read
STP Index of VLAN Entry 10
Reserved
Write as 0h, ignore when read
Priority Queue Number of VLAN Entry 10
87
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.72
VLAN Table - Misc_6 Register (299h)
Bit
15
Name
RESERVED
ROM
－
14:13
VTAB_STPIDX_D
5Ch.[14:13]
12:10
RESERVED
－
9:8
VTAB_QUE_D
5Ch.[9:8]
7
RESERVED
－
6:5
VTAB_STPIDX_C
5Ch.[6:5]
4:2
RESERVED
－
1:0
VTAB_QUE_C
5Ch.[1:0]
5.4.73
Default
P0
RO
PSE0
RW
P0
RO
PSE0
RW
P0
RO
PSE0
RW
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
STP Index of VLAN Entry 13
Reserved
Write as 0h, ignore when read
Priority Queue Number of VLAN Entry 13
Reserved
Write as 0h, ignore when read
STP Index of VLAN Entry 12
Reserved
Write as 0h, ignore when read
Priority Queue Number of VLAN Entry 12
VLAN Table - Misc_7 Register (29Ah)
Bit
15
Name
RESERVED
ROM
－
14:13
VTAB_STPIDX_F
12:10
RESERVED
5Dh.[14:13
]
－
9:8
VTAB_QUE_F
5Dh.[9:8]
7
RESERVED
－
6:5
VTAB_STPIDX_E
5Dh.[6:5]
4:2
RESERVED
－
1:0
VTAB_QUE_E
5Dh.[1:0]
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PSE0
RW
P0
RO
PSE0
RW
P0
RO
PSE0
RW
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
STP Index of VLAN Entry 15
Reserved
Write as 0h, ignore when read
Priority Queue Number of VLAN Entry 15
Reserved
Write as 0h, ignore when read
STP Index of VLAN Entry 14
Reserved
Write as 0h, ignore when read
Priority Queue Number of VLAN Entry 14
88
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.74
Snooping Control 0 Register (29Bh)
Bit
15:14
Name
RESERVED
ROM
－
13:8
RPP
17h.[13:8]
Default
P0
RO
PSE0
RW
7
UD_RP
17h.[7]
PSE0
RW
6
RESERVED
－
P0
RO
5:4
MC_CTRL
17h.[5:4]
PSE0
RW
3:2
UMD_CTRL
17h.[3:2]
PSE0
RW
1
MLDS_EN
17h.[1]
PSE0
RW
0
HIGS_EN
17h.[0]
PSE0
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Description
Reserved
Write as 0h, ignore when read
Router Port Portmap
[13] : Port 5
[12] : Port 4
[11] : Port 3
[10] : Port 2
[09] : Port 1
[08] : Port 0
0: Disable
1: Enable
User-defined Router Port Enable
0: Disable
1: Enable
Reserved
Write as 0h, ignore when read
Multicast Control Packet Handle
00: Forward Membership Reports to router port.
General Query to all port.
01: Mirror to CPU (Forward to CPU also)
10: Trap to CPU (Forward to CPU only)
11: Flood
Unregistered Multicast Data Packet Handle
00: As normal multicast packets
01: Dropped.
10: Trap to CPU
11: Flood except CPU
MLD Snooping Enable
0: Disable
1: Enable
Hardware IGMP Snooping Enable
0: Disable
1: Enable
89
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.75
Snooping Control 1 Register (29Ch)
Bit
15:13
Name
RESERVED
ROM
－
12
IGS_TODIS
18h.[12]
11:10
RP_TV
18h.[11:10]
PSE0
RW
9:8
IGS_RV
18h.[9:8]
PSE0
RW
7:0
IGS_QI
18h.[7:0]
PSE
7DH
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PSE0
RW
Description
Reserved
Write as 0h, ignore when read
IGMP Snooping Timeout Scheme Disable
0: Timeout is enabled
1: Timeout is disabled
Router Port Timeout Value Selection
00: 1 times of Query Interval
01: 2 times of Query Interval
10: 3 times of Query Interval (default)
11: 4 times of Query Interval
Robustness Variable
00: 1 times
01: 2 times (default)
10: 3 times
11: 4 times
Query Interval
Default = 125 (sec)
90
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.76
Address Table Control & Status Register (2B0h)
Bit
15
Name
ATB_S
ROM
－
Default
PS0
RO
14:13
ATB_CR
－
PS0
RO
12:7
RESERVED
－
P0
RO
6
ATB_CLSE_FID
－
PS0
RW
5
ATB_CLSE_PO
RT
－
PS0
RW
4:2
ATB_CMD
－
PS0
RW
1:0
ATB_IDX
－
PS0,RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Description
Address Table Access is Busy
0: Available (Access process is completed)
1: Busy (Access process is operating)
Address Table Command Result
00: Command OK, entry doesn't exist
a. Create an new entry (Write Command)
b. Do noting (Delete Command)
c. Entry is not found (Search Command)
d. Entry is invalid (Read Command)
e. Process is successful (Clear Command)
01: Command OK, entry is exist
a. Overwrite entry (Write Command)
b. Delete entry (Delete Command)
c. Entry is found (Search Command)
d. Entry is valid (Read Command)
e. Process is successful (Clear Command)
1X: Command Error
Reserved
Write as 0h, ignore when read
Enable to Clear Entries with Specified FID
0: Disable
1: Enable
Enable to Clear Entries with Specified Port Number or
Port Map (Port number for accessing unicast address
table, port map for multicast)
0: Disable
1: Enable
Command
000: Read a entry with sequence number of address
table
001: Write a entry with MAC address
010: Delete a entry with MAC address
011: Search a entry with MAC address
100: Clear one or more than one entries with Port or
FID
101,110,111: Reserved
Address Table Index
00: Unicast Address Table
01: Multicast Address Table
10: IGMP Table
11: Reserved
91
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.77
Address Table Data 0 Register (2B1h)
Bit
15:12
Name
RESERVED
ROM
－
11:8
ATB_FID
－
7:6
RESERVED
－
5:0
ATB_PORT
－
5.4.78
Bit
15:0
5.4.79
Bit
15:0
5.4.80
Bit
15:0
5.4.81
Bit
15:0
Default
P0
RO
PS0
RW
P0
RO
PS0
RW
Description
Reserved
Write as 0h, ignore when read
FID Value
Reserved
Write as 0h, ignore when read
Port Number or Port Map
Address Table Data 1 Register (2B2h)
Name
ATB_DW1
ROM
－
Default
PSE0
RW
Description
Address Table Data Word 1
Address Table Data 2 Register (2B3h)
Name
ATB_DW2
ROM
－
Default
PSE0
RW
Description
Address Table Data Word 2
Address Table Data 3 Register (2B4h)
Name
ATB_DW3
ROM
－
Default
PSE0
RW
Description
Address Table Data Word 3
Address Table Data 4 Register (2B5h)
Name
ATB_DW4
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
ROM
－
Default
PSE0
RW
Description
Address Table Data Word 4
92
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.82
Ethernet Address Register 0 for Magic Packet (2B8h)
Bit
15:8
Name
ETH_ADR1
ROM
19h.[15:8]
7:0
ETH_ADR0
19h.[7:0]
5.4.83
Description
Ethernet Address 1
Ethernet Address 0
Ethernet Address Register 1 for Magic Packet (2B9h)
Bit
15:8
Name
ETH_ADR3
ROM
1Ah.[15:8]
7:0
ETH_ADR2
1Ah.[7:0]
5.4.84
Default
PE0
RW
PE0
RW
Default
PE0
RW
PE0
RW
Description
Ethernet Address 3
Ethernet Address 2
Ethernet Address Register 2 for Magic Packet (2BAh)
Bit
15:8
Name
ETH_ADR5
ROM
1Bh.[15:8]
7:0
ETH_ADR4
1Bh.[7:0]
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
PE0
RW
PE0
RW
Description
Ethernet Address 5
Ethernet Address 4
93
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.85
WoL Control Register (2BBh)
Bit
15
Name
STANDBY
ROM
10h.[15]
Default
PS0
RW
14
SLOW_CLK
10h.[14]
PS0
RW
13
MAGIC_EN5
10h.[13]
PS0
RW
12
MAGIC_EN4
10h.[12]
PS0
RW
11
MAGIC_EN3
10h.[11]
PS0
RW
10
MAGIC_EN2
10h.[10]
PS0
RW
9
MAGIC_EN1
10h.[9]
PS0
RW
8
MAGIC_EN0
10h.[8]
PS0
RW
7:6
RESERVED
－
P0
RO
5
LNK_EN5
－
PS0
RW
4
LNK_EN4
－
PS0
RW
3
LNK_EN3
－
PS0
RW
2
LNK_EN2
－
PS0
RW
1
LNK_EN1
－
PS0
RW
0
LNK_EN0
－
PS0
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Description
WOL Standby Mode Enable
0: Disable
1: Enable
Slow Down System Clock in WOL Standby Mode
When WoL Standby Mode is enabled and this bit is set, The
system clock is down to to 3.125MHz.
0: Disable
1: Enable
Port 5 Magic Packet Interrupt Enable
0: Disable
1: Enable
Port 4 Magic Packet Interrupt Enable
0: Disable
1: Enable
Port 3 Magic Packet Interrupt Enable
0: Disable
1: Enable
Port 2 Magic Packet Interrupt Enable
0: Disable
1: Enable
Port 1 Magic Packet Interrupt Enable
0: Disable
1: Enable
Port 0 Magic Packet Interrupt Enable
0: Disable
1: Enable
Reserved
Write as 0h, ignore when read
Port 5 Link Status Change Interrupt Enable
0: Disable
1: Enable
Port 4 Link Status Change Interrupt Enable
0: Disable
1: Enable
Port 3 Link Status Change Interrupt Enable
0: Disable
1: Enable
Port 2 Link Status Change Interrupt Enable
0: Disable
1: Enable
Port 1 Link Status Change Interrupt Enable
0: Disable
1: Enable
Port 0 Link Status Change Interrupt Enable
0: Disable
1: Enable
94
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.4.86
General Purpose I/O Control Register (2D0h)
Bit
15:10
Name
RESERVED
ROM
－
Default
P0
RO
PS0
RW
9
GP1_TYPE
－
8
GP0_TYPE
－
PS0
RW
7:6
RESERVED
－
P0
RO
5
GP1_DIR
－
PS0
RW
4
GP0_DIR
－
PS0
RW
3:2
RESERVED
－
P0
RO
1
GP1_IN
－
PS0
RW
Description
Reserved
Write as 0h, ignore when read
GPIO 1 Buffer Type
0: Open-Collect output
1: Forced output
GPIO 0 Buffer Type
0: Open-Collect output
1: Forced output
Reserved
Write as 0h, ignore when read
GPIO 1 Direction
0: GPIO 1 pin is an input
1: GPIO 1 pin is an output
GPIO 0 Direction
0: GPIO 0 pin is an input
1: GPIO 0 pin is an output
Reserved
Write as 0h, ignore when read
GPIO 1 Data
If GPIO 1 pin is an input,
0: GPIO 1 pin is driven low
1: GPIO 1 pin is driven high
0
GP0_IN
－
PS0
RW
If GPIO 1 pin is an output,
0: Set GPIO 1 pin to 0
1: Set GPIO 1 pin to 1
GPIO 0 Data
If GPIO 0 pin is an input,
0: GPIO 0 pin is driven low
1: GPIO 0 pin is driven high
If GPIO 1 pin is an output,
0: Set GPIO 0 pin to 0
1: Set GPIO 0 pin to 1
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
95
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.5 Chip Control and Status Registers
5.5.1
Vendor ID Register (310h)
Bit
15:0
5.5.2
Bit
15:0
Name
VID
ROM
04h.[15:0]
Default
PE
0A46h
RO
Description
Vendor ID
Product ID Register (311h)
Name
PID
ROM
05h.[15:0]
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
PE
8606h
RO
Description
Product ID
96
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.5.3
Port 4 MAC Control Register (314h)
Bit
15:12
Name
RESERVED
ROM
－
11,10
P4_TB_SEL
0Ch.[11:10]
9:8
P4_DRIVE
0Ch.[9:8]
PET01
RW
7
P4_SLEW
0Ch.[7]
PET0
RW
6
P4_50M_IN
0Ch.[6]
PE0
RW
5
P4_50MOUT
0Ch.[5]
PET0
RW
4
RESERVED
－
P0
RO
3
P4_MODE
0Ch.[3]
PET0
RW
2
P4_LINK
0Ch.[2]
PET0
RW
1
P4_DPX
0Ch.[1]
PET0
RW
0
P4_SPEED
0Ch.[0]
PET0
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PET00
RW
Description
Reserved
Write as 0h, ignore when read
Port4 Turbo Speed in RevMII
00: Default TXCLK 25MHz(100M)/2.5MHz(10M)
01: P4 RevMII TXCLK generate 50MHz clock
10: P4 RevMII TXCLK generate 100MHz clock
11: P4 RevMII TXCLK generate 125MHz clock
Port 4 Output Pin Current Driving/Sinking Capability
00: 2mA
01: 4mA (default)
10: 6mA
11: 8mA
Port 4 Output Pin Slew Rate
0: Normal slew rate
1: Low slew rate
50MHz Clock Source Selection
Only available when Port 4 be configured as RMII or TP
RMII
0: 50MHz clock source from external
1: 50MHz clock source from Internal
50MHz Clock Output Enable
Only available when Port 4 be configured as RMII or TP
RMII
0: Disable, high impedance
1: Enable, output 50MHz clock
Reserved
Write as 0h, ignore when read
Port 4 Force Mode Enable
Only available for MII/RevMII/RMII
0: Disable, auto-negotiation mode
1: Enable, force mode
Port 4 Force Link
Only available in force mode
0: Link ON
1: Link OFF
Port 4 Force Duplex
Only available in force mode
0: Full-duplex mode
1: Half-duplex mode
Port 4 Force Speed
Only availabe in force mode
0: 100M mode
1: 10M mode
97
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.5.4
Port 5 MAC Control Register (315h)
Bit
15:10
Name
RESERVED
ROM
－
9:8
P5_DRIVE
0Dh.[9:8]
7
P5_SLEW
0Dh.[7]
PET0
RW
6
P5_50M_IN
0Dh.[6]
PE0
RW
5
P5_50M_OUT
0Dh.[5]
PET0
RW
4
RESERVED
－
P0
RO
3
P5_MODE
0Dh.[3]
PET0
RW
2
P5_LINK
0Dh.[2]
PET0
RW
1
P5_DPX
0Dh.[1]
PET0
RW
0
P5_SPEED
0Dh.[0]
PET0
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PET01
RW
Description
Reserved
Write as 0h, ignore when read
Port 5 Output Pin Current Driving/Sinking Capability
00: 2mA
01: 4mA (default)
10: 6mA
11: 8mA
Port 5 Output Pin Slew Rate
0: Normal slew rate
1: Low slew rate
Port 5 Clock Source Selection
Only available when Port 5 be configured as RMII,
0: 50Mhz clock source from external
1: 50Mhz clock source from internal
Port 5 50MHz Clock Output Enable
Only available when Port 5 be configured as RMII,
0: Disable, high impedance
1: Enable, output 50MHz clock
Reserved
Write as 0h, ignore when read
Port 5 Force Mode Enable
Only available for MII/RevMII/RMII
0: Disable, auto-negotiation mode
1: Enable, force mode
Port 5 Force Link
Only available in force mode
0: Link ON
1: Link OFF
Port 5 Force Duplex
Only available in force mode
0: Full-duplex mode
1: Half-duplex mode
Port 5 Force Speed
Only availabe in force mode
0: 100M mode
1: 10M mode
98
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.5.5
Fiber Control Register (316h)
Bit
15
Name
P01_LFP
ROM
08h.[15]
Default
PE0
RW
14:13
RESERVED
－
P0
RO
12
P4_SD
08h.[12]
PE0
RW
11
P3_SD
08h.[11]
PE0
RW
10
P2_SD
08h.[10]
PE0
RW
9
P1_SD
08h.[9]
PE0
RW
8
P0_SD
08h.[8]
PE0
RW
7:5
RESERVED
－
P0
RO
4
P4_FIBER
08h.[4]
PET0
RW
3
P3_FIBER
08h.[3]
PE0
RW
2
P2_FIBER
08h.[2]
PE0
RW
1
P1_FIBER
08h.[1]
PE0
RW
0
P0_FIBER
08h.[0]
PE0
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Description
Port 0 and Port 1 Repeater Enable
Enable fiber repeater function with Link Fault Pass
through (LFP) ability between Port 0 and Port1.
0: Disable
1: Enable
Reserved
Write as 0h, ignore when read
Port 4 Fiber Signal Detect Selection
Select the source of Fiber SD, only available in fiber
mode.
The Port 4 operation mode must be configured as
internal PHY, i.e. pull-down P4_SET1 and P4_SET0
pins.
0: Fiber SD decode internally
1: Fiber SD input P4_SPD_LED (pin 101)
Port 3 Fiber Signal Detect Selection
Select the source of Fiber SD, only available in fiber
mode.
0: Fiber SD decode internally
1: Fiber SD input P3_SPD_LED (pin 102)
Port 2 Fiber Signal Detect Selection
Select the source of Fiber SD, only available in fiber
mode.
0: Fiber SD decode internally
1: Fiber SD input P2_SPD_LED (pin 103)
Port 1 Fiber Signal Detect Selection
Select the source of Fiber SD, only available in fiber
mode.
0: Fiber SD decode internally
1: Fiber SD input P1_SPD_LED (pin 104)
Port 0 Fiber Signal Detect Selection
Select the source of Fiber SD, only available in fiber
mode.
0: Fiber SD decode internally
1: Fiber SD input P0_SPD_LED (pin 105)
Reserved
Write as 0h, ignore when read
Port 4 Firber Mode Enable
0: Disable (Copper)
1: Enable
Port 3 Firber Mode Enable
0: Disable (Copper)
1: Enable
Port 2 Firber Mode Enable
0: Disable (Copper)
1: Enable
Port 1 Firber Mode Enable
0: Disable (Copper)
1: Enable
Port 0 Firber Mode Enable
0: Disable (Copper)
1: Enable
99
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.5.6
IRQ and LED Control Register (317h)
Bit
15
Name
IRQ_PIN
ROM
06h.[15]
Default
PSE0
RW
14
IRQ_POL
06h.[14]
PSE0
RW
13
IRQ_PULSE
06h.[13]
P0
RO
12:11
CTL_DRIVE
06h.[12:11]
PET01
RW
10
CTL_SLEW
06h.[10]
PET0
RW
9:8
LED_DRIVE
06h.[9:8]
PET10
RW
7
LED_SLEW
06h.[7]
PET1
RW
6:2
RESERVED
－
RO
1:0
LED_MODE
06h.[1:0]
PET11
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Description
IRQ Output Pin Type
0: Force output
1: Open-collected
IRQ Active Low Enable
0: Active high
1: Active low
IRQ Output Pulse
0: Assert until source event cleared
1: Assert a 1000ns pulse
Switch Control Output Pin Current Driving/Sinking Capability
00: 2mA
01: 4mA (default)
10: 6mA
11: 8mA
Switch Control Output Pin Slew Rate
0: Normal slew rate
1: Low slew rate
LED Pin Current Driving/Sinking Capability
00: 2mA
01: 4mA
10: 6mA (default)
11: 8mA
LED Pin Slew Rate
0: Normal slew rate
1: Low slew rate (default)
Reserved
Write as 0h, ignore when read
LED_MODE
00 : LED mode 0
01 : LED mode 1, dual color mode
10 : LED mode 2
11 : LED mode 3 (default)
100
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.5.7
Interrupt Status Register (318h)
Bit
15:3
Name
RESERVED
ROM
－
2
MAGIC
－
1
RESERVED
－
P0
RO
0
LNKCHG
－
PS0
RW/C1
5.5.8
Default
P0
RO
PS0
RW/C1
Description
Reserved
Write as 0h, ignore when read
Magic Packet Detected Status
0 = No interrupt request present
1 = Interrupt request present
Reserved
Write as 0h, ignore when read
Link Status Change Status
0 = No interrupt request present
1 = Interrupt request present
Interrupt Mask & Control Register (319h)
Bit
15:3
Name
RESERVED
ROM
－
2
MAGIC_IEN
10h.[2]
1
RESERVED
－
P0
RO
0
LNKCHG
－
PS0
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PS0
RW
Description
Reserved
Write as 0h, ignore when read
Magic Packet Interrupt Enable
0: Disable
1: Enable
Reserved
Write as 0h, ignore when read
Link Status Change Interrupt Enable
0: Disable
1: Enable
101
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.5.9
EEPROM Control & Address Register (31Ah)
Bit
15:8
Name
EROA
ROM
7
RESERVED
－
6
EETYPE
－
5
REEP
－
PS0
RW
4
WEP
－
PS0
RW
3
EPOS
－
PS0
RW
2
ERPRR
－
PS0
RW
1
ERPRW
－
PS0
RW
0
ERRE
－
PS0
RO
5.5.10
Bit
15:0
－
Default
PS0
RW
P0
RO
P0
RW
Description
EEPROM Address
8-bit EEPROM word address
Reserved
Write as 0h, ignore when read
EEPROM Type Selection & Status
0: 93C46
1: 93C66
Reload EEPROM
Write 1 and then write 0 to generate a pulse to active
EEPROM reload circuit
EEPROM Write Enable
0: Disable
1: Enable
Access External PHY Enable
0: Disable
1: Enable
EEPROM Read Command
Launch EEPROM read process by set this bit to one.It is
non self-clearing bit, driver need to clear after operation
ending.
EEPROM Write Command
Launch EEPROM write process by set this bit to one.It is
non self-clearing bit, driver need to clear after operation
ending.
EEPROM Access Status
0: Busy, accessing EEPROM or external PHY is in
progress
1: Idle, accessing EEPROM or external PHY is
completed.
EEPROM Data Register (31Bh)
Name
EE_DATA
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
ROM
－
Default
PS0
RW
Description
EEPROM Data
16-bit EEPROM data field
102
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.5.11
Monitor Register 1 (31Ch)
Bit
15
Name
STRP_DIS
14
RESERVED
－
－
13
TEST3
－
RO
Reserved
Write as 0h, ignore when read
Display the input value of pin 41, TEST3.
12
TEST2
－
RO
Display the input value of pin 69, TEST2.
11
TEST1
RO
Display the input value of pin 108, TEST1.
10
RESERVED
－
－
RO
9
RESERVED
－
RO
8
P2_SPD
－
RO
Reserved
Write as 0h, ignore when read
Reserved
Write as 0h, ignore when read
Display the latched value of pin 103, P2_SPD_LED.
7
P1_SPD
－
RO
Display the latched value of pin 104, P1_SPD_LED.
6
P0_SPD
RO
Display the latched value of pin 105, P0_SPD_LED.
5:3
RESERVED
－
－
RO
2
EECS
－
RO
Reserved
Write as 0h, ignore when read
Display the latched value of pin 80, EECS.
1
EECK
RO
Display the latched value of pin 81, EECK.
0
RESERVED
－
－
RO
Reserved
Write as 0h, ignore when read
5.5.12
ROM
Default
RO
RO
Description
Display the input value of pin 93, STRAP_DIS.
Monitor Register 2 (31Dh)
Bit
15
14
13
Name
SPDLED3
SPDLED4
RESERVED
ROM
－
－
－
Default
RO
RO
RO
12
11
10
9
8
7:6
FDXLED4
FDXLED3
FDXLED2
FDXLED1
FDXLED0
RESERVED
－
－
－
－
－
－
RO
RO
RO
RO
RO
RO
5
4:0
LNKLED4
RESERVED
－
－
RO
RO
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Description
Display the latched value of pin 102, P3_SPD_LED.
Display the latched value of pin 101, P4_SPD_LED.
Reserved
Write as 0h, ignore when read
Display the latched value of pin 107, P4_FDX_LED.
Display the latched value of pin 110, P3_FDX_LED.
Display the latched value of pin 111, P2_FDX_LED.
Display the latched value of pin 112, P1_FDX_LED.
Display the latched value of pin 113, P0_FDX_LED.
Reserved
Write as 0h, ignore when read
Display the latched value of pin 51, P4_LNK_LED.
Reserved
Write as 0h, ignore when read
103
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.5.13
Monitor Register 3 (31Eh)
Bit
15
14
13
12
11
10
9
8:1
Name
LNKLED3
LNKLED2
LNKLED1
LNKLED0
P4S0
CFG4
P4S1
RESERVED
ROM
－
－
－
－
－
－
－
－
Default
RO
RO
RO
RO
RO
RO
RO
RO
0
MDC_EXT
－
RO
5.5.14
Description
Display the latched value of pin 48, P3_LNK_LED.
Display the latched value of pin 47, P2_LNK_LED.
Display the latched value of pin 43, P1_LNK_LED.
Display the latched value of pin 42, P0_LNK_LED.
Display the input value of pin 98, P4_SET0.
Display the input value of pin 98, P4_CFG.
Display the latched value of pin 100, P4_SET1.
Reserved
Write as 0h, ignore when read
Display the latched value of pin 68, PHY_MDC.
Debug Monitor Pin Register (31Fh)
Bit
15:14
Name
RESERVED
ROM
－
7
MONI_EN
－
3:0
MONI_IDX
－
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PS0
RW
PS0
RW
Description
Reserved
Write as 0h, ignore when read
Debug Monitor Enable
0: Disable
1: Enable
Debug Monitor Table Index
104
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.5.15
Memory Access Enable Register (330h)
Bit
15
Name
SEL_RAM
ROM
－
Default
PS0
RW
14
RESERVED
－
P0
RO
13
WRMEM
－
PS0
RW
12:0
RESERVED
－
P0
RO
5.5.16
Bit
15:0
5.5.17
Bit
15:0
5.5.18
Bit
15:0
5.5.19
Bit
15:0
Description
Memory Access Selection
0: Select 48K SRAM
1: Select 25K SRAM
Reserved
Write as 0h, ignore when read
Memory Write Enable
0: Disable
1: Enable
Reserved
Write as 0h, ignore when read
Memory Address Register (331h)
Name
MDA
ROM
－
Default
PS0
RW
Description
Memory Data Address
Memory Dummy Data Register (332h)
Name
MDRD
ROM
－
Default
RO
Description
Memory Dummy Read Data
Memory Read Data Register (333h)
Name
MRD
ROM
－
Default
RO
Description
Memory Data Read
Memory Write Data Register (334h)
Name
MWD
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
ROM
－
Default
PS0
WO
Description
Memory Write Data
105
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.5.20
Memory Write Data Low Byte Register (335h)
Bit
15:8
Name
RESERVED
ROM
－
7:0
MWDL
－
5.5.21
Default
P0
RO
PS0
WO
Description
Reserved
Write as 0h, ignore when read
Memory Write Data Low Bits 7~0
Memory Write Data High Byte Register (336h)
Bit
15:8
Name
MWDH
ROM
－
7:0
RESERVED
－
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
PS0
WO
P0
RO
Description
Memory Write Data High Bits 15~8
Reserved
Write as 0h, ignore when read
106
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.5.22
System Clock Select Register (338h)
Bit
15:3
Name
RESERVED
ROM
－
2:0
CLK_TYPE
－
5.5.23
Description
Reserved
Write as 0h, ignore when read
Internal System Clock Rate Selection
000: 50MHz
001: 66Mhz
010: 83MHz
011: 100MHz
10X: 25MHz
11X: 3.125MHz
Serial Bus Error Check Register (339h)
Bit
15:9
Name
RESERVED
ROM
－
8
SMI_ERR
－
7:0
SMI_CSUM
－
5.5.24
Default
P0
RO
PS0
RW
Default
P0
RO
PS0
RO
PS0
RW
Description
Reserved
Write as 0h, ignore when read
SMI Bus Error Status
0: Checksum is correct
1: Checksum is wrong
Checksum field for SMI Bus Error Check
Serial Bus Control Register (33Ah)
Bit
15:1
Name
RESERVED
ROM
－
0
SMI_ECE
－
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Default
P0
RO
PS0
RW
Description
Reserved
Write as 0h, ignore when read
SMI Bus Error Check Enable
0: Disable
1: Enable
107
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.5.25
Virtual PHY Control Register (33Dh)
Bit
15:10
Name
RESERVED
ROM
－
Default
P0
RO
PS0
RW
9
VPHY_LNK_AND
－
8
VPHY_LNK_OR
－
PS1
RW
7:6
RESERVED
－
P0
RO
5:0
VPHY_PMAP
－
PS
1Fh
RW
Description
Reserved
Write as 0h, ignore when read
Virtual PHY Link with AND Mode
0: Disable
1: Enable
Virtual PHY Link with OR Mode
0: Disable
1: Enable
Reserved
Write as 0h, ignore when read
Virtual PHY Link Port Map
[05]: Port 5
[04]: Port 4 [03]: Port 3
[02]: Port 2
[01]: Port 1 [00]: Port 0
Note: Valid if Reg33DH.[9] or Reg33DH.[8] is enabled
5.5.26
PHY Control Test Register (33Eh)
Bit
15
Name
AT_MDIX0
ROM
07h.[15]
Default
P0
RW
14
AT_MDIX1
07h.[14]
P0
RW
13
AT_MDIX2
07h.[13]
P0
RW
12
AT_MDIX3
07h.[12]
P0
RW
11
AT_MDIX4
07h.[11]
P0
RW
10:4
RESERVED
－
3:0
RESERVED
－
P0
RO
P3
RW
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Description
Port 0 Auto-MDIX Control Disable
0: Disable
1: Enable
Port 1 Auto-MDIX Control Disable
0: Disable
1: Enable
Port 2 Auto-MDIX Control Disable
0: Disable
1: Enable
Port 3 Auto-MDIX Control Disable
0: Disable
1: Enable
Port 4 Auto-MDIX Control Disable
0: Disable
1: Enable
Reserved
Write as 0h, ignore when read
Reserved
Write as 3h, ignore when read
108
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
5.5.27
Disable Port Control Register (399h)
Bit
15:6
Name
RESERVED
ROM
－
5:0
PORT_DIS
－
Default
P0
RO
P0
RW
Description
Reserved
Write as 0h, ignore when read
Disable Buffer Usage of Port
It is used to release the reserved buffers on useless port for
memory utilization improvment. Notice that Switch must be
software reset after this function is applied.
[05]: Port 5
[02]: Port 2
[04]: Port 4
[01]: Port 1
[03]: Port 3
[00]: Port 0
0: Enable, reserve buffers on selected port.
1: Disable, release buffers on selected port.
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
109
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
6. EEPROM Format
Name
Signature
Word
00h
RESERVED
Load Control 0
01h~02h
03h
Vendor ID
04h
Product ID
05h
IRQ &
LED Control
PHY control
06h
Fiber control
08h
Phy Vendor ID
09h
Phy Device ID
0Ah
07h
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Description
When this word is 1049h, the EEPROM data is valid and can be
loaded to DM8806.
Reserved
EEPROM Load Control 0
Bit
Function
[01:00]
Load enable of word 04h & 05h
01b: Enable, 00b/10b/11b: Disable
[03:02]
Load enable of word 06h
01b: Enable, 00b/10b/11b: Disable
[05:04]
Load enable of word 08h
01b: Enable, 00b/10b/11b: Disable
[07:06]
Load enable of word 09h & 0Ah
01b: Enable, 00b/10b/11b: Disable
[09:08]
Load enable of word 0Bh,0Ch,0Dh
01b: Enable, 00b/10b/11b: Disable
[11:10]
Load enable of word 10h
01b: Enable, 00b/10b/11b: Disable
[13:12]
Reserved
Set to “00b” or “11b” in application
[15:14]
Load enable of word 07h
01b: Enable, 00b/10b/11b: Disable
Vendor ID (Default: 0A46h)
If bit [01:00] of word 03h is “01b”, this field will be loaded to REG 310h
Product ID
If bit [01:00] of word 03h is “01b”, this field will be loaded to REG 311h
IRQ & LED Control
If bit [03:02] of word 03h is “01b”, this field will be loaded to REG 317h
PHY Auto-MDIX Control
If bit [15:14] of word 03h is “01b”, this field will be loaded to REG 33Eh
Bit
Function
[10:00]
Reserved
[11]
Port 4 AUTO-MDIX control
1: ON, 0: OFF
[12]
Port 3 AUTO-MDIX control
1: ON, 0: OFF
[13]
Port 2 AUTO-MDIX control
1: ON, 0: OFF
[14]
Port 1 AUTO-MDIX control
1: ON, 0: OFF
[15]
Port 0 AUTO-MDIX control
1: ON 0: OFF
PHY Fiber Control
If bit [05:04] of word 03h is "01b", this field will be loaded to REG 316h
Internal PHY ID1
If bit [07:06] of word 03h is “01b”, this field will be loaded to Identifier 1
Register of all internal PHYs.
Internal PHY ID2
If bit [07:06] of word 03h is “01b”, this field will be loaded to Identifier 2
Register of all internal PHYs.
110
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
Port 4 MAC Control
0Ch
Port 5 MAC Control
0Dh
Load Control 1
0Eh
Load Control 2
0Fh
Magic Packet
Control
10h
Port 4 MAC Control
If bit [09:08] of word 03h is “01b”, this field will be loaded to REG 314h
Port 5 MAC Control
If bit [09:08] of word 03h is “01b”, this field will be loaded to REG 315h
EEPROM Load Control 1
Bit
Function
[01:00]
Load enable of word 12h ~ 16h
01b: Enable, 00b/10b/11b: Disable
[03:02]
Load enable of word 17h &18h
01b: Enable, 00b/10b/11b: Disable
[05:04]
Load enable of word 1Ch ~ 24h
01b: Enable, 00b/10b/11b: Disable
[07:06]
Load enable of word 26h ~ 2Eh
01b: Enable, 00b/10b/11b: Disable
[09:08]
Load enable of word 30h ~ 5Dh
01b: Enable, 00b/10b/11b: Disable
[11:10]
Reserved
Set to “00b” or “11b” in application
[13:12]
Reserved
Set to “00b” or “11b” in application
[15:14]
Reserved
Set to “00b” or “11b” in application
EEPROM Load Control 2
Bit
Function
[01:00]
Load enable of word 80h ~ 8Bh
01b: Enable, 00b/10b/11b: Disable
[03:02]
Load enable of word 90h ~ 9Bh
01b: Enable, 00b/10b/11b: Disable
[05:04]
Load enable of word A0h ~ ABh
01b: Enable, 00b/10b/11b: Disable
[07:06]
Load enable of word B0h ~ BBh
01b: Enable, 00b/10b/11b: Disable
[09:08]
Load enable of word C0h ~ CBh
01b: Enable, 00b/10b/11b: Disable
[11:10]
Load enable of word D0h ~ DBh
01b: Enable, 00b/10b/11b: Disable
[13:12]
Reserved
Set to “00b” or “11b in application
[15:14]
Reserved
Set to “00b” or “11b” in application
If bit [11:10] of word 03h is “01b”, this field will be loaded to registers that
is shown in the following table.
Bit
[00]
[01]
[02]
[07:03]
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
Function
Reserved
10M TX power saving in bit 10 of all PHY register PSCR
(Bit 10 of REG 054h/074h/094h/0B4h/0D4h)
1: Enable, 0: Disable
Magic packet interrupt enable
(REG 319h.[2])
1: Enable, 0: Disable
Reserved
111
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
[13:08]
[14]
[15]
RESERVED
Switch Control
CPU Port &
Mirror Control
Special Tag
Ether-Type
Global Learning &
Aging Control
MIB Counter Disable
Snoop Control 0
Snoop Control 1
ETH_ADR
VLAN Priority Map
Register
TOS Priority Map 0
TOS Priority Map 1
TOS Priority Map 2
TOS Priority Map 3
TOS Priority Map 4
TOS Priority Map 5
TOS Priority Map 6
TOS Priority Map 7
RESERVED
Special Packet
Control 0
Special Packet
Control 1
Special Packet
Control 2
Special Packet
Control 3
Special Packet
Control 4
Special Packet
Control 5
Special Packet
Control 6
Special Packet
Control 7
Special Packet
Control 8
Per port magic packet interrupt enable
(REG 2BBh.[13:08])
1: Enable, 0: Disable
Slow down system clock in WOL standby mode
(REG 2BBh.[14])
1: Enable, 0: Disable
WOL standby mode enable
(REG 2BBh.[15])
1: Enable, 0: Disable
11h
12h
13h
Reserved
If bit [01:00] of word 0Eh is “01b”, this field will be loaded to REG 212h
If bit [01:00] of word 0Eh is “01b”, this field will be loaded to REG 213h
14h
If bit [01:00] of word 0Eh is “01b”, this field will be loaded to REG 214h
15h
If bit [01:00] of word 0Eh is “01b”, this field will be loaded to REG 215h
16h
17h
18h
19h~1Bh
1Ch
If bit [01:00] of word 0Eh is “01b”, this field will be loaded to REG 230h
If bit [03:02] of word 0Eh is “01b”, this field will be loaded to REG 29Bh
If bit [03:02] of word 0Eh is “01b”, this field will be loaded to REG 29Ch
Ethernet Address for Magic Packet.
Word 19h will be loaded to REG 2B8h
Word 1Ah will be loaded to REG 2B9h
Word 1Bh will be loaded to REG 2Bah
If bit [05:04] of word 0Eh is “01b”, this field will be loaded to REG 217h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
If bit [05:04] of word 0Eh is “01b”, this field will be loaded to REG 218h
If bit [05:04] of word 0Eh is “01b”, this field will be loaded to REG 219h
If bit [05:04] of word 0Eh is “01b”, this field will be loaded to REG 21Ah
If bit [05:04] of word 0Eh is “01b”, this field will be loaded to REG 21Bh
If bit [05:04] of word 0Eh is “01b”, this field will be loaded to REG 21Ch
If bit [05:04] of word 0Eh is “01b”, this field will be loaded to REG 21Dh
If bit [05:04] of word 0Eh is “01b”, this field will be loaded to REG 21Eh
If bit [05:04] of word 0Eh is “01b”, this field will be loaded to REG 21Fh
Reserved
If bit [07:06] of word 0Eh is “01b”, this field will be loaded to REG 234h.
27h
If bit [07:06] of word 0Eh is “01b”, this field will be loaded to REG 235h.
28h
If bit [07:06] of word 0Eh is “01b”, this field will be loaded to REG 236h.
29h
If bit [07:06] of word 0Eh is “01b”, this field will be loaded to REG 237h.
2Ah
If bit [07:06] of word 0Eh is “01b”, this field will be loaded to REG 238h.
2Bh
If bit [07:06] of word 0Eh is “01b”, this field will be loaded to REG 239h.
2Ch
If bit [07:06] of word 0Eh is “01b”, this field will be loaded to REG 23Ah.
2Dh
If bit [07:06] of word 0Eh is “01b”, this field will be loaded to REG 23Bh.
2Eh
If bit [07:06] of word 0Eh is “01b”, this field will be loaded to REG 23Ch.
Preliminary
Doc No: DM8806/DM8806I -14-3-DS-P02
January 9, 2013
112
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
RESERVED
QinQ TPID Register
VLAN Mode & Rule
Control
VLAN Table - Valid
Control
VLAN Table - ID_0H
VLAN Table - ID_1H
VLAN Table - ID_2H
VLAN Table - ID_3H
VLAN Table - ID_4H
VLAN Table - ID_5H
VLAN Table - ID_6H
VLAN Table - ID_7H
VLAN Table - ID_8H
VLAN Table - ID_9H
VLAN Table - ID_AH
VLAN Table - ID_BH
VLAN Table - ID_CH
VLAN Table - ID_DH
VLAN Table - ID_EH
VLAN Table - ID_FH
VLAN Table MEMBER_0H
VLAN Table MEMBER_1H
VLAN Table MEMBER_2H
VLAN Table MEMBER_3H
VLAN Table MEMBER_4H
VLAN Table MEMBER_5H
VLAN Table MEMBER_6H
VLAN Table MEMBER_7H
VLAN Table MEMBER_8H
VLAN Table MEMBER_9H
VLAN Table MEMBER_AH
VLAN Table MEMBER_BH
VLAN Table MEMBER_CH
VLAN Table MEMBER_DH
VLAN Table MEMBER_EH
2Fh
30h
31h
Reserved
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 23Dh.
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 23Eh.
32h
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 23Fh.
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
40h
41h
42h
43h
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 250h.
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 251h.
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 252h.
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 253h.
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 254h.
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 255h.
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 256h.
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 257h.
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 258h.
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 259h.
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 25Ah.
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 25Bh.
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 25Ch.
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 25Dh.
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 25Eh.
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 25Fh.
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 270h.
44h
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 271h.
45h
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 272h.
46h
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 273h.
47h
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 274h.
48h
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 275h.
49h
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 276h.
4Ah
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 277h.
4Bh
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 278h.
4Ch
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 279h.
4Dh
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 27Ah.
4Eh
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 27Bh.
4Fh
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 27Ch.
50h
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 27Dh.
51h
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 27Eh.
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VLAN Table MEMBER_FH
VLAN Table - Priority
Enable
VLAN Table - Priority
Replace Enable
VLAN Table - STP
Index Enable
VLAN Table - Misc_0
VLAN Table - Misc_1
VLAN Table - Misc_2
VLAN Table - Misc_3
VLAN Table - Misc_4
VLAN Table - Misc_5
VLAN Table - Misc_6
VLAN Table - Misc_7
RESERVED
P0 Basic Control 0
P0 Basic Control 1
P0 Block Control 0
P0 Block Control 1
P0 Bandwidth
Control
P0 VLAN Tag
Information
P0 Priority & VLAN
Control
P0 Security Control
P0 Advanced Control
P0 Memory
Configuration
P0 Discard packet
limitation
P0 EEE Control
RESERVED
P1 Basic Control 0
P1 Basic Control 1
P1 Block Control 0
P1 Block Control 1
P1 Bandwidth
Control
P1 VLAN Tag
Information
P1 Priority & VLAN
Control
P1 Security Control
P1 Advanced Control
P1 Memory
Configuration
P1 Discard packet
limitation
P1 EEE Control
52h
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 27Fh.
53h
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 290h.
54h
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 291h.
55h
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 292h.
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh~7Fh
80h
81h
82h
83h
84h
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 293h.
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 294h.
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 295h.
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 296h.
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 297h.
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 298h.
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 299h.
If bit [09:08] of word 0Eh is “01b”, this field will be loaded to REG 29Ah.
Reserved
If bit [01:00] of word 0Fh is “01b”, this field will be loaded to REG 111h.
If bit [01:00] of word 0Fh is “01b”, this field will be loaded to REG 112h.
If bit [01:00] of word 0Fh is “01b”, this field will be loaded to REG 113h.
If bit [01:00] of word 0Fh is “01b”, this field will be loaded to REG 114h.
If bit [01:00] of word 0Fh is “01b”, this field will be loaded to REG 115h.
85h
If bit [01:00] of word 0Fh is “01b”, this field will be loaded to REG 116h.
86h
If bit [01:00] of word 0Fh is “01b”, this field will be loaded to REG 117h.
87h
88h
89h
If bit [01:00] of word 0Fh is “01b”, this field will be loaded to REG 118h.
If bit [01:00] of word 0Fh is “01b”, this field will be loaded to REG 119h.
If bit [01:00] of word 0Fh is “01b”, this field will be loaded to REG 11Ah.
8Ah
If bit [01:00] of word 0Fh is “01b”, this field will be loaded to REG 11Bh.
8Bh
8Ch~8Fh
90h
91h
92h
93h
94h
If bit [01:00] of word 0Fh is “01b”, this field will be loaded to REG 11Eh.
Reserved
If bit [03:02] of word 0Fh is “01b”, this field will be loaded to REG 131h.
If bit [03:02] of word 0Fh is “01b”, this field will be loaded to REG 132h.
If bit [03:02] of word 0Fh is “01b”, this field will be loaded to REG 133h.
If bit [03:02] of word 0Fh is “01b”, this field will be loaded to REG 134h.
If bit [03:02] of word 0Fh is “01b”, this field will be loaded to REG 135h.
95h
If bit [03:02] of word 0Fh is “01b”, this field will be loaded to REG 136h.
96h
If bit [03:02] of word 0Fh is “01b”, this field will be loaded to REG 137h.
97h
98h
99h
If bit [03:02] of word 0Fh is “01b”, this field will be loaded to REG 138h.
If bit [03:02] of word 0Fh is “01b”, this field will be loaded to REG 139h.
If bit [03:02] of word 0Fh is “01b”, this field will be loaded to REG 13Ah.
9Ah
If bit [03:02] of word 0Fh is “01b”, this field will be loaded to REG 13Bh.
9Bh
If bit [03:02] of word 0Fh is “01b”, this field will be loaded to REG 13Eh.
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RESERVED
P2 Basic Control 0
P2 Basic Control 1
P2 Block Control 0
P2 Block Control 1
P2 Bandwidth
Control
P2 VLAN Tag
Information
P2 Priority & VLAN
Control
P2 Security Control
P2 Advanced Control
P2 Memory
Configuration
P2 Discard packet
limitation
P2 EEE Control
RESERVED
P3 Basic Control 0
P3 Basic Control 1
P3 Block Control 0
P3 Block Control 1
P3 Bandwidth
Control
P3 VLAN Tag
Information
P3 Priority & VLAN
Control
P3 Security Control
P3 Advanced Control
P3 Memory
Configuration
P3 Discard packet
limitation
P3 EEE Control
RESERVED
P4 Basic Control 0
P4 Basic Control 1
P4 Block Control 0
P4 Block Control 1
P4 Bandwidth
Control
P4 VLAN Tag
Information
P4 Priority & VLAN
Control
P4 Security Control
P4 Advanced Control
P4 Memory
Configuration
9Ch~9Fh
A0h
A1h
A2h
A3h
A4h
Reserved
If bit [05:04] of word 0Fh is “01b”, this field will be loaded to REG 151h.
If bit [05:04] of word 0Fh is “01b”, this field will be loaded to REG 152h.
If bit [05:04] of word 0Fh is “01b”, this field will be loaded to REG 153h.
If bit [05:04] of word 0Fh is “01b”, this field will be loaded to REG 154h.
If bit [05:04] of word 0Fh is “01b”, this field will be loaded to REG 155h.
A5h
If bit [05:04] of word 0Fh is “01b”, this field will be loaded to REG 156h.
A6h
If bit [05:04] of word 0Fh is “01b”, this field will be loaded to REG 157h.
A7h
A8h
A9h
If bit [05:04] of word 0Fh is “01b”, this field will be loaded to REG 158h.
If bit [05:04] of word 0Fh is “01b”, this field will be loaded to REG 159h.
If bit [05:04] of word 0Fh is “01b”, this field will be loaded to REG 15Ah.
AAh
If bit [05:04] of word 0Fh is “01b”, this field will be loaded to REG 15Bh.
ABh
ACh~AFh
B0h
B1h
B2h
B3h
B4h
If bit [05:04] of word 0Fh is “01b”, this field will be loaded to REG 15Eh.
Reserved
If bit [07:06] of word 0Fh is “01b”, this field will be loaded to REG 171h.
If bit [07:06] of word 0Fh is “01b”, this field will be loaded to REG 172h.
If bit [07:06] of word 0Fh is “01b”, this field will be loaded to REG 173h.
If bit [07:06] of word 0Fh is “01b”, this field will be loaded to REG 174h.
If bit [07:06] of word 0Fh is “01b”, this field will be loaded to REG 175h.
B5h
If bit [07:06] of word 0Fh is “01b”, this field will be loaded to REG 176h.
B6h
If bit [07:06] of word 0Fh is “01b”, this field will be loaded to REG 177h.
B7h
B8h
B9h
If bit [07:06] of word 0Fh is “01b”, this field will be loaded to REG 178h.
If bit [07:06] of word 0Fh is “01b”, this field will be loaded to REG 179h.
If bit [07:06] of word 0Fh is “01b”, this field will be loaded to REG 17Ah.
BAh
If bit [07:06] of word 0Fh is “01b”, this field will be loaded to REG 17Bh.
BBh
BCh~BFh
C0h
C1h
C2h
C3h
C4h
If bit [07:06] of word 0Fh is “01b”, this field will be loaded to REG 17Eh.
Reserved
If bit [09:08] of word 0Fh is “01b”, this field will be loaded to REG 191h.
If bit [09:08] of word 0Fh is “01b”, this field will be loaded to REG 192h.
If bit [09:08] of word 0Fh is “01b”, this field will be loaded to REG 193h.
If bit [09:08] of word 0Fh is “01b”, this field will be loaded to REG 194h.
If bit [09:08] of word 0Fh is “01b”, this field will be loaded to REG 195h.
C5h
If bit [09:08] of word 0Fh is “01b”, this field will be loaded to REG 196h.
C6h
If bit [09:08] of word 0Fh is “01b”, this field will be loaded to REG 197h.
C7h
C8h
C9h
If bit [09:08] of word 0Fh is “01b”, this field will be loaded to REG 198h.
If bit [09:08] of word 0Fh is “01b”, this field will be loaded to REG 199h.
If bit [09:08] of word 0Fh is “01b”, this field will be loaded to REG 19Ah.
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P4 Discard packet
limitation
CAh
If bit [09:08] of word 0Fh is “01b”, this field will be loaded to REG 19Bh.
P4 EEE Control
RESERVED
P5 Basic Control 0
P5 Basic Control 1
P5 Block Control 0
P5 Block Control 1
P5 Bandwidth
Control
P5 VLAN Tag
Information
P5 Priority & VLAN
Control
P5 Security Control
P5 Advanced Control
P5 Memory
Configuration
P5 Discard packet
limitation
P5 EEE Control
RESERVED
CBh
CCh~CFh
D0h
D1h
D2h
D3h
D4h
If bit [09:08] of word 0Fh is “01b”, this field will be loaded to REG 19Eh.
Reserved
If bit [11:10] of word 0Fh is “01b”, this field will be loaded to REG 1B1h.
If bit [11:10] of word 0Fh is “01b”, this field will be loaded to REG 1B2h.
If bit [11:10] of word 0Fh is “01b”, this field will be loaded to REG 1B3h.
If bit [11:10] of word 0Fh is “01b”, this field will be loaded to REG 1B4h.
If bit [11:10] of word 0Fh is “01b”, this field will be loaded to REG 1B5h.
D5h
If bit [11:10] of word 0Fh is “01b”, this field will be loaded to REG 1B6h.
D6h
If bit [11:10] of word 0Fh is “01b”, this field will be loaded to REG 1B7h.
D7h
D8h
D9h
If bit [11:10] of word 0Fh is “01b”, this field will be loaded to REG 1B8h.
If bit [11:10] of word 0Fh is “01b”, this field will be loaded to REG 1B9h.
If bit [11:10] of word 0Fh is “01b”, this field will be loaded to REG 1BAh.
DAh
If bit [11:10] of word 0Fh is “01b”, this field will be loaded to REG 1BBh.
DBh
DCh~FFh
If bit [11:10] of word 0Fh is “01b”, this field will be loaded to REG 1BEh.
Reserved
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7. Function Description
7.1 Switch Functions
7.1.1
Address Learning
The DM8806 stores MAC addresses, port number and time stamp information in the Hash-based Address
Table. The table can learn up to 2K unicast address entries. The DM8806 provides two methods to learn
address in the table, self-learning and manual learning.
Self-learning
The self-learning mechanism means the DM8806 learn the MAC addresses of incoming packets in real time
without CPU’s assistance. The switch engine creates a new entry if incoming packet’s Source Address (SA)
does not exist and the packet is valid (error-free). If SA was found and incoming port mismatch with port
number in table, update the entry with SA and incoming port number. Those entries will be created, updated
or aged dynamically. Besides, the DM8806 has an option to disable address learning for individual port. This
feature can be set by bit 12 of per port register 11h (i.e. 111h, 131h, 151h, 171h, 191h, and 1B1h).
Manual Learning
The DM8806 also provides manual learning mechanism with CPU’s assistance. The CPU can create, update
or delete entry for flexible management. In addition to above, the entry can be set as static one that will not be
aged-out.
7.1.2
Address Aging
The time stamp information of address table is used in the aging process. The switch engine updates time
stamp whenever the corresponding SA receives. The switch engine would delete the entry if its time stamp is
not updated for a period of time. The period can be programmed or disabled through bit 0 & 1 of register
215h.
7.1.3
Packet Forwarding
The DM8806 forwards the incoming packet according to following decision:
(1). If Destination Address (DA) is multicast/broadcast, the packet is forwarded to all ports, except to
the port on which the packet was received.
(2). Switch engine would look up address table based on DA when incoming packets is uni-cast. If the
DA was not found in address table, the packet is treated as a multicast packet and forward to other
ports. If the DA was found and its destination port number is different to source port number, the
packet is forward to destination port.
(3). Switch engine also look up VLAN, Port Monitor setting and other forwarding constraints for the
forwarding decision, more detail will discuss in later sections.
The DM8806 will filter incoming packets under following conditions:
(1). Error packets, including CRC errors, alignment errors, illegal size errors.
(2). IEEE 802.3X PAUSE packets.
(3). If incoming packet is uni-cast and its destination port number is equal to source port number
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7.1.4
Inter-Packet Gap (IPG)
IPG is the idle time between any two valid packets at the same port. The typical number is 96 bits time. In
other word, the value is 9.6u sec for 10Mbps and 960n sec for 100Mbps.
7.1.5
Back-off Algorithm
The DM8806 implements the binary exponential back-off algorithm in half-duplex mode compliant to IEEE
standard 802.3.
7.1.6
Late Collision
Late Collision is a type of collision. If a collision error occurs after the first 512 bit times of data are transmitted,
the packet is dropped.
7.1.7
Half Duplex Flow Control
The DM8806 supports half-duplex backpressure. The inducement is the same as full duplex mode. When
flow control is required, the DM8806 sends jam pattern and results in a collision.
7.1.8
Full Duplex Flow Control
The DM8806 supports IEEE standard 802.3x flow control frames on both transmit and receive sides. On the
receive side, The DM8806 will defer transmitting next normal frames, if it receives a pause frame from link
partner. On the transmit side, The DM8806 issues pause frame with maximum pause time when internal
resources such as received buffers, transmit queue and transmit descriptor ring are unavailable. Once
resources are available, The DM8806 sends out a pause frame with zero pause time allows traffic to resume
immediately.
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7.1.9
Partition Mode
The DM8806 provides a partition mode for each port. The port enters partition mode when more than 64
consecutive collisions are occurred. In partition mode the port continuous to transmit but it will not receive.
The port returned to normal operation mode when a good packet is seen on the wire. The detail description of
partition mode represent following:
Entering Partition State
A port will enter the Partition State when either of the following conditions occurs:
(1). The port detects a collision on every one of 64 consecutive re-transmit attempts to the same
packet.
(2). The port detects a single collision which occurs for more than 512 bit times.
(3). Transmit defer timer time out, which indicates the transmitting packet is deferred to long.
While in Partition State
The port will continue to transmit its pending packet, regardless of the collision detection, and will not allow
the usual Back-off Algorithm. Additional packets pending for transmission will be transmitted, while ignoring
the internal collision indication. This frees up the ports transmit buffers which would otherwise be filled up at
the expense of other ports buffers. The assumption is that the partition is signifying a system failure situation
(bad connection/cable/station), thus dropping packets is a small price to pay vs. the cost of halting the switch
due to a buffer full condition.
Exiting from Partition State
The Port exits from Partition State, following the end of a successful packet transmission. A successful
packet transmission is defined as no collisions were detected on the first 512 bits of the transmission.
7.1.10
Broadcast Storm Filtering
The DM8806 has an option to limit the traffic of broadcast or multicast packets, to protect the switch from
lower bandwidth availability. There are two types of broadcast storm control, one is throttling broadcast
packet only, the other includes multicast. This feature can be set through bit 12 of per port register 12h. The
broadcast storm threshold can be programmed by EEPROM or per port register 5h, the default setting is no
broadcast storm protecting.
7.1.11
Bandwidth Control
The DM8806 supports two types of bandwidth control for each port. One is the ingress and egress bandwidth
rate can be controlled separately, the other is combined together, this function can be set through bit 14 of per
port register 12h. The bandwidth control is disabled by default. To separate bandwidth control mode, the
threshold rate is defined in per port register 5h. For combined mode, it is defined in bit 3~0 of per port register
15h.
The behavior of bandwidth control as below:
(1). For the ingress control, if flow control function is enabled, Pause or Jam packet will be transmitted.
The ingress packets will be dropped if flow control is disabled.
(2). For the egress control, the egress port will not transmit any packets. On the other hand, the
ingress bandwidth of source port will be throttled that prevent packets from forwarding.
(3). In combined mode, if the sum of ingress and egress bandwidth over threshold, the bandwidth will
be throttled.
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7.1.12
Port Monitoring Support
The DM8806 supports “Port Monitoring” function on per port base, detail as below:
Sniffer Port and Monitor Port
There is only one port can be selected as “sniffer port” by bit 5~3 of register 213h, multiple ports can be set as
“receive monitor port” or “transmit monitor port” in per-port register 11h.
Receive monitor
All packets received on the “receive monitor port” are send a copy to “sniffer port”. For example, port 0 is set
as “receive monitor port” and port 2 is selected as a “sniffer port”. If a packet is received form port 0 and
predestined to port 1 after forwarding decision, the DM8806 will forward it to port 1 and port 2 in the end.
Transmit monitor
All packets transmitted on the “transmit monitor port” are send a copy to “sniffer port”. For example, port 1 is
set as “transmit monitor port” and port 2 is selected as “sniffer port”. If a packet is received from port 0 and
predestined to port 1 after forwarding decision, the DM8806 will forward it to port 1 and port 2 in the end.
Exception
The DM8806 has an optional setting that broadcast/multicast packets are not monitored (see bit 11 of per port
register 12h). It’s useful to avoid unnecessary bandwidth.
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7.1.13
VLAN Support
Port-Based VLAN
The DM8806 supports port-based VLAN as default, up to 16 groups. Each port has a default VID called PVID
(Port VID, in bit 11~0 of per port register 16H). The DM8806 used 12 bits PVID as index and mapped with
registers 250H~25FH to define the VLAN groups.
802.1q-Based VLAN
Regarding IEEE 802.1Q standard, Tag-based VLAN uses an extra tag to identify the VLAN membership of a
frame across VLAN-aware switch/router. A tagged frame is four bytes longer than an untagged frame and
contains two bytes of TPID (Tag Protocol Identifier) and two bytes of TCI (Tag Control Information).
Dest.
Src.
Length/Type
Dest.
Src.
TPID
TCI
Data
Length / Type
Standard frame
Data
Tagged frame
0x8100
2 bytes
Priority
3 bits
CFI
1 bits
VID
12 bits
The DM8806 also supports 16 802.1Q-based VLAN groups, as specified in bit 0 of register 23Eh. It’s obvious
that the tagged packets can be assigned to several different VLANs which are determined according to the
VID inside the VLAN Tag. Therefore, the operation is similar to port-based VLAN. The DM8806 used full 12
bits VID of received packet with VLAN tag and VLAN table ID registers (250h~25Fh) and then define
members by VLAN Group Mapping Register (270h~27Fh) to configure the VLAN partition. If the destination
port of received packet is not same VLAN group with received port, it will be discarded.
Tag/Untag
User can define each port as Tag port or Un-tag port by bit 14 of per port register 17h in 802.1Q-based VLAN
mode. The operation of Tag and Un-tag can explain as below conditions:
(1). Receive untagged packet and forward to Un-tag port.
Received packet will forward to destination port without modification.
(2). Receive tagged packet and forward to Un-tag port.
The DM8806 will remove the tag from the packet and recalculate CRC before sending it out.
(3). Receive untagged packet and forward to Tag port.
The DM8806 will insert the PVID tag when an untagged packet enters the port, and recalculate CRC before
delivering it.
(4). Receive tagged packet and forward to Tag port.
Received packet will forward to destination port without modification.
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7.1.14
Special Tag
The Special Tag function provided by the DM8806 is used to exchange control and status information
between Switch and CPU within frame. An extra 4-bytes tag is added into frame to carry different content
according to direction of special tag frame. Received special tag (CPU
Switch) specifies the desired port
mapping of packet sent by CPU and some configurations about frame handle rules. Transmitted special tag
(Switch
CPU) indicates the source port number of incoming frame.
The following figure shows special tag frame format. In left 2 bytes of special tag field, there is an identifier
called Special Tag Ether-Type that can use to recognize special tag frame. The value of this field can be set
by REG 23DH.
The detail information carried by received special tag is described as below. Through received special tag,
CPU can tell switch the handle rule per frame over the internal setting. This feature can be enabled through
REG 213H bit 6.
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Received Special Tag(CPU
Switch) 4-byte Format:
Byte 0/1
[15:0]
Special Tag Ether-Type (Default: 0x8086)
Byte 2
[7]
Reserved
Byte 2
[6]
ST_PMAP_en, ST_PMAP Enable
Byte 2
[5:0]
ST_PMAP, Force to assign forwarding port map
Byte 3
[7]
Reserved
Byte 3
[6]
ST_CVLAN, Cross VLAN
0: This frame obeys VLAN boundary.
1: This frame can cross VLAN boundary.
Byte 3
[5]
ST_LRN_DIS, Disable learning
0: This frame will be learned
1: This frame will not be learned
Byte 3
[4]
ST_PRI_EN, ST_PRI Enable
Byte 3
[3:2]
ST_PRI, Priority Queue Number (0~3)
00: Queue 0
01: Queue 1
10: Queue 2
11: Queue 3
Byte 3
[1:0]
ST_TAG
00: Unmodified
01: Always Tagged
10: Always Untagged
11: Reserved
Beside, transmitted special tag is used to indicate source port number. CPU can use this message to judge
the incoming port number of the frame. REG 213H bit 7 can enable this feature by setting to 1.
Transmitted Special Tag (Switch
CPU) 4-byte Format:
Byte 0/1
[15:0]
Special Tag Ether-Type (Default: 0x8086)
Byte 2
[7:3]
Reserved
Byte 2
[2:0]
ST_SPORT, Source Port Number (0~5)
Byte 3
[7:0]
Reserved
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7.1.15
Priority Support
The DM8806 supports Quality of Service (QoS) mechanism for multimedia communication such as VoIP and
video conferencing. The DM8806 provides three priority classifications: Port-based, 802.1p-based and
DiffServ-based priority. See next section for more detail. The DM8806 offers four level queues for transmit on
per-port based.
The DM8806 provides two packet scheduling algorithms: Weighted Fair Queuing and Strict Priority Queuing.
Weighted Fair Queuing (WFQ) based on their priority and queue weight. Queues with larger weights get more
service than smaller. This mechanism can get highly efficient bandwidth and smooth the traffic. Strict Priority
Queuing (SPQ) based on priority only. The Packet on the highest priority queue is transmitted first. The next
highest-priority queue is work until last queue empties, and so on. This feature can be set in bit 5 of per port
register 17H.
Port-Based Priority
Port based priority is the simplest scheme and as default. Each port has a 2-bit priority value as index for
splitting ingress packets to the corresponding transmit queue. This value can be set in bit 1~0 of per port
register 17H.
802.1p-Based Priority
The DM8806 extracts 3-bit priority field from received packet with 802.1p VLAN tag, and maps this field
against VLAN Priority Map Registers 217H to determine which transmit queue is designated. The VLAN
Priority Map is programmable.
DiffServ-Based Priority
DiffServ based priority uses the most significant 6-bit of the ToS field in standard IPv4 header, and maps this
field against ToS Priority Map Registers (218H~21FH) to determine which transmit queue is designated. The
ToS Priority Map is programmable too. In addition, User can only refer to most significant 3-bit of the ToS field
optionally, see bit 7 of register 23EH.
7.1.16
Address Table Accessing
Type of Address Table
There are three types of address table in the DM8806. The description is represented below:
(1). Unicast Address Table
This table is used for destination MAC address lookup and source MAC address learning. The table can have
up to 2048 entries. If the table is full, the latest one will kick out the eldest one. The programming method can
refer to next section.
(2). Multicast Address Table
The table that stores multicast addresses shares with unicast address table and can be maintained by host
CPU for custom filtering and forwarding multicast packets. If the table is full, the latest one will kick out the
eldest one. All of entries in multicast address table are static one. In addition to host CPU, multicast address
table can be manipulated by internal switch engine, if hardware-based IGMP Snooping function is enabled.
(3). IGMP Membership Table
This table is used to establish IPv4 multicast forwarding rule under IGMP protocol if hardware-based IGMP
Snooping function is enabled. It is automatic maintained by internal engine according to snooping IGMP
control packets, and can only support to read out by the host CPU. The maximum of entries of table is 32. If
the table is full, never join anymore.
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Access Rules of Address Table
In DM8806, unicast and multicast address table support “Write”, “Delete”, ”Search”, “Read” and “Clear”
commands. However, for IGMP membership table, there are only three different type commands such as
“Write”, “Delete” and “Read”. The DM8806 procedure and flow chart of Entry Access is described as
following:
Entry Write
(1). Check the busy bit of Address Table Control & Status Register (Reg2B0H.15) to seek the
availability of access engine. Waiting until engine is available and to keep on following.
(2). Write the MAC address to the Address Table Data 1~3 Registers (Reg2B2H~2B4H).
(3). Write the Port Number or Port Map to Address Table Data 0 Register (Reg2B1.[2:0]).
(4). If need, write the entry’s attribute such as static to Address Table Data 4 Register (Reg2B5H.0).
(5). Write the “WRITE” command and assign the target table to Address Table Control & Status
Register (Reg2B0H.[4:0]) to start the operation.
(6). Check the busy bit again, wait for available.
(7). Read the command status from Address Table Control & Status Register (Reg2B0H.[14:13])
Entry Delete
(1). Check the busy bit of Address Table Control & Status Register (Reg2B0H.15) to seek the
availability of access engine. Waiting until engine is available and to keep on following.
(2). Write the MAC address to the Address Table Data 1~3 Registers (Reg2B2H~2B4H).
(3). Write the “DELETE” command and assign the target table to Address Table Control & Status
Register (Reg2B0H.[4:0]) to start the operation
(4). Check the busy bit again, wait for available.
(5). Read the command status from Address Table Control & Status Register (Reg2B0H.[14:13]).
Entry Search
(1). Check the busy bit of Address Table Control & Status Register (Reg2B0H.15) to seek the
availability of access engine. Waiting until engine is available and to keep on following.
(2). Write the MAC address to the Address Table Data 1~3 Registers (Reg2B2H~2B4H).
(3). Write the “SEARCH” command and assign the target table to Address Table Control & Status
Register (Reg2B0H.[4:0]) to start the operation.
(4). Check the busy bit again, wait for available.
(5). Read the command status from Address Table Control & Status Register (Reg2B0H.[14:13]).
(6). Read the Port Number or Port Map to Address Table Data 0 Register (Reg2B1.[2:0]).
(7). If need, read the entry sequence (the sequence number of entry in address table) from Address
Table Data 1 Register (Reg2B2H).
(8). If need, read the entry’s attributes that include static (unicast address table only) and IGMP Entry
(multicast address table only) from Address Table Data 4 Register (Reg2B5H.0 for static and
Reg2B5h.12 for IGMP Entry).
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Entry Read
(1). Check the busy bit of Address Table Control & Status Register (Reg2B0H.15) to seek the
availability of access engine. Waiting until engine is available and to keep on following.
(2). Write the entry sequence to the Address Table Data 1 Register (Reg2B2H).
(3). Write the “READ” command and assign the target table to Address Table Control & Status
Register (Reg2B0H.[4:0]) to start the operation.
(4). Check the busy bit again, wait for available.
(5). Read the command status from Address Table Control & Status Register (Reg2B0H.[14:13]).
(6). Read the Port Number or Port Map to Address Table Data 0 Register (Reg2B1.[2:0]).
(7). If target is unicast or multicast address table, read the entry’s MAC address from Address Table
Data 1~3 Register (Reg2B2H~2B4H). If target is IGMP membership table, read the real memory
address from Address Table Data 1 Register (Reg2B2H.[10:0]).
(8). If target is unicast address table, read the entry’s attributes such as static from Address Table Data
4 Register (Reg2B5H.0). For multicast address table, IGMP Entry can be read from Address Table
Data 4 Register (Reg2B5H.[12]). For IGMP membership table, IGMP valid signal and per-port
aged timer can be read from Address Table Data 2~3 Register (Reg2B3H.[2:0], Reg2B4H.[5:0]).
Entry Clear
(1). Check the busy bit of Address Table Control & Status Register (Reg2B0H.15) to seek the
availability of access engine. Waiting until engine is available and to keep on following.
(2). Write the “Clear” command and assign the target table to Address Table Control & Status Register
(Reg2B0H.[4:0]) to start the operation.
(3). Wait at least 4.5ms for clear procedure is done.
(4). Check the busy bit again, wait for available.
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7.1.17
IGMP Snooping
The Internet Group Management Protocol (IGMP) is a communications protocol used to manage the
membership of Internet Protocol multicast groups. IGMP is used by IP hosts and adjacent multicast routers to
establish multicast group memberships. There are three versions of IGMP, as defined by "Request for
Comments" (RFC) documents of the Internet Engineering Task Force (IETF). IGMP v1 is defined by RFC
1112, IGMP v2 is defined by RFC 2236 and IGMP v3 is defined by RFC 3376.
IGMP snooping is a feature that allows the switch to "listen in" on the IGMP protocol conversation between
hosts and routers. The IGMP snooping switch hears an IGMP report from a host with a given multicast group
address. It adds the host's port number to the multicast list for that group, and when the switch hears an
IGMP Leave, it removes the host's port from the table entry. Finally, switch will only forward multicast traffic to
the hosts interested in that traffic. Therefore, this function can effectively reduce multicast traffic.
Hardware-Based IGMP Snooping
The DM8806 supports IGMP v1/v2 snooping and the maximal group is 32 without any software effort in this
mode. The DM8806 automatically manipulates and updates IGMP membership table and Multicast table
according to IGMP control packets, such as membership report and leave.
If IGMP membership table is full, the later incoming IGMP Membership Report (Join) packet will be ignored
and the group address won’t be registered into multicast address table. After that, the unregistered IP
multicast packets (the destination MAC address can not be found in the multicast address table) will be
treated as normal multicast packets by default. The additional forwarding control method can see the register
Reg29BH.[3:2].
The DM8806 supports router ports auto-detect and auto-aging mechanism. The port which receives IGMP
Query packets will be treated as router port by default. The router port also can be define as static one by
user (see Reg29BH.7) and the port map of the router port can be programmed at Reg29BH.[10:8]. Keep in
mind that the CPU port is never treated as router port. The DM8806 leaves the router port if the time (Router
Present Timeout, 400sec by default) is expired that the port never receives IGMP Query during this period.
If receiving V1REPORT or V2REPORT (group join), DM8806 creates new or updates the entry. If receiving
LEAVE, DM8806 deletes the entry directly when Fast Leave is enabled, or waiting until timeout.
DM8806 removes the entry that was never updated after the timer of host timeout (Group Membership
Interval) is expired. This timer is programmable in DM8806 and defined by RFC 2236 as ((the Robustness
Variable) times (the Query Interval)) plus (one Query Response Interval). The setting of the Robustness
Variable and the Query Interval can see Reg29CH.
7.1.18
IPv6 MLD Snooping
The DM8806 forwards the IPv6 Multicast Listener Discovery (MLD) packets to the processor port when MLD
Snooping is enabled and the MLD packets meet following scenario:
(1). IPv6 Multicast packets.
(2). The Hop Limit in IPv6 header is 1.
(3). The Next Header in IPv6 header is 0x3A (ICMPv6) or 0x00 (and next header of hop-by-hop option
header is 0x3A).
(4). The Type in ICMP header is 0x82 (Multicast Listener Query), 0x83 (Multicast Listener Report) or
0x84 (Multicast Listener Done).
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7.1.19
STP / RSTP Support
DM8806 supports both Spanning Tree Protocol(STP) and Rapid Spanning Tree Protocol(RSTP). There are
five types of STP Port State (Disabled, Blocking, Listening, Learning and Forwarding state) and three types of
RSTP Port State (Discarding, Learning and Forwarding) for these two protocols. The following figure is the
port state diagram of STP.
Pow er-on
Initialization
B locking
S tate
L istening
S tate
D isabled
State
L earning
S tate
F orw arding
S tate
But in RSTP, there are only three port states. The port states comparison between STP and RSTP are listed
as below.
STP Port State
RSTP Port State
Disabled
Discarding
Blocking
Discarding
Listening
Discarding
Learning
Learning
Forwarding
Forwarding
For compatibility and design consideration, this function needs the cooperation with external CPU. Moreover,
the behavior of Disabled/Blocking/Listening states in STP must be equal to the behavior of Discarding state in
RSTP in DM8806. The difference between STP and RSTP should be implemented by CPU. The following
statement describes the STP/RSTP port state behavior and software action in DM8806.
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Disable State:
(1). Drop all packets including BPDUs
Implemented by transmitting BPDUs to CPU and CPU drops BPDUs.
(2). Learning is disabled.
(3). Does not transmit BPDUs received from CPU
Implemented by CPU does not send BPDUs to this port
Blocking State:
(1). Drop all packets except BPDUs and transmit received BPDUs to CPU.
(2). Learning is disabled.
(3). Does not transmit BPDUs received from CPU
Listening State:
(1). Drop all packets except BPDUs and tranmit received BPDUs to CPU
(2). Learning is disabled.
(3). Forward BPDUs received from CPU
Implemented by CPU uses special tag function to send BPDUs to decided port
Learning State:
(1). Drop all packets except BPDUs and transmit received BPDUs to CPU
(2). Learning is enabled
(3). Forward BPDUs received from CPU
Forwarding State:
(1). Forward all packets
(2). Learning is enabled
(3). Forward BPDUs received from CPU
Base on the behavior of different states described above, DM8806 has a port states setting for both STP and
RSTP in per-port register 19h, . The register setting is：
00： Forwarding
01： Disabled / Discarding
10： Learning
11： Blocking / Listening
The following flow diagram shows how to configure STP/RSTP function.
Start
Set Reg292h to enable STP/RSTP
Set Port States to Per-Port Register 0x19
[1:0] STPS0
00: Forwarding
01: Disabled/Discarding
10: Learning
11: Blocking / Listening
STP/RSTP Setting
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7.1.20
Port Trunking Description
The DM8806/DM8806I supports one group trunk port which includes four 10/100Mbp ports. User can
configure two or more ports as trunking group between Port0 and Port3. For setting details, please refer to bit
11~8 of REG 212h. The DM8806/DM8806I trunk function support load balancing and fault auto recovery, the
next paragraph is detail description.
First, when balancing traffic, network administrators often wish to avoid reordering Ethernet frames. The load
balancing behavior is achieved by DA and SA L2 hash algorithm to ensure that the same flow is always sent
via the same physical link. Second, port failure recovery function on trunking can change the path from the
unlinked port to other in trunk group automatically and recover the path if the port is re-linked.
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7.2 Internal PHY Functions
7.2.1
100Base-TX Operation
The transmitter section contains the following functional blocks:
- 4B5B Encoder
- Scrambler
- Parallel to Serial Converter
- NRZ to NRZI Converter
- NRZI to MLT-3
- MLT-3 Driver
4B5B Encoder
The 4B5B encoder converts 4-bit (4B) nibble data generated by the MAC Reconciliation Layer into a 5-bit (5B)
code group for transmission, see reference Table 1. This conversion is required for control and packet data to
be combined in code groups. The 4B5B encoder substitutes the first 8 bits of the MAC preamble with a J/K
code-group pair (11000 10001) upon transmit. The 4B5B encoder continues to replace subsequent 4B
preamble and data nibbles with corresponding 5B code-groups. At the end of the transmit packet, upon the
deassertion of the Transmit Enable signal from the MAC Reconciliation layer, the 4B5B encoder injects the
T/R code-group pair (01101 00111) indicating the end of frame. After the T/R code-group pair, the 4B5B
encoder continuously injects IDLEs into the transmit data stream until Transmit Enable is asserted and the
next transmit packet is detected.
Scrambler
The scrambler is required to control the radiated emissions (EMI) by spreading the transmit energy across the
frequency spectrum at the media connector and on the twisted pair cable in 100Base-TX operation.
By scrambling the data, the total energy presented to the cable is randomly distributed over a wide frequency
range. Without the scrambler, energy levels on the cable could peak beyond FCC limitations at frequencies
related to the repeated 5B sequences, like the continuous transmission of IDLE symbols. The scrambler
output is combined with the NRZ 5B data from the code-group encoder via an XOR logic function. The result
is a scrambled data stream with sufficient randomization to decrease radiated emissions at critical
frequencies.
Parallel to Serial Converter
The Parallel to Serial Converter receives parallel 5B scrambled data from the scrambler, and serializes it
(converts it from a parallel to a serial data stream). The serialized data stream is then presented to the NRZ to
NRZI encoder block
NRZ to NRZI Encoder
After the transmit data stream has been scrambled and serialized, the data must be NRZI encoded for
compatibility with the TP-PMD standard, for 100Base -TX transmission over Category-5 unshielded twisted
pair cable.
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MLT-3 Converter
The MLT-3 conversion is accomplished by converting the data stream output, from the NRZI encoder into two
binary data streams, with alternately phased logic one event.
MLT-3 Driver
The two binary data streams created at the MLT-3 converter are fed to the twisted pair output driver, which
converts these streams to current sources and alternately drives either side of the transmit transformer’s
primary winding, resulting in a minimal current MLT-3 signal.
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4B5B Code Group
Symbol
Meaning
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data A
Data B
Data C
Data D
Data E
Data F
4B code
3210
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
5B Code
43210
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
I
J
K
T
R
H
Idle
SFD (1)
SFD (2)
ESD (1)
ESD (2)
Error
undefined
0101
0101
undefined
undefined
undefined
11111
11000
10001
01101
00111
00100
V
V
V
V
V
V
V
V
V
V
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
00000
00001
00010
00011
00101
00110
01000
01100
10000
11001
Table 1
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7.2.2
100Base-TX Receiver
The 100Base-TX receiver contains several function blocks that convert the scrambled 125Mb/s serial data to
synchronous 4-bit nibble data.
The receive section contains the following functional blocks:
- Signal Detect
- Digital Adaptive Equalization
- MLT-3 to Binary Decoder
- Clock Recovery Module
- NRZI to NRZ Decoder
- Serial to Parallel
- Descrambler
- Code Group Alignment
- 4B5B Decoder
Signal Detect
The signal detect function meets the specifications mandated by the ANSI XT12 TP-PMD 100Base-TX
standards for both voltage thresholds and timing parameters.
Adaptive Equalization
When transmitting data over copper twisted pair cable at high speed, attenuation based on frequency
becomes a concern. In high speed twisted pair signaling, the frequency content of the transmitted signal can
vary greatly during normal operation based on the randomness of the scrambled data stream. This variation
in signal attenuation, caused by frequency variations, must be compensated for to ensure the integrity of the
received data. In order to ensure quality transmission when employing MLT-3 encoding, the compensation
must be able to adapt to various cable lengths and cable types depending on the installed environment. The
selection of long cable lengths for a given implementation requires significant compensation, which will be
over-killed in a situation that includes shorter, less attenuating cable lengths. Conversely, the selection of
short or intermediate cable lengths requiring less compensation will cause serious under-compensation for
longer length cables. Therefore, the compensation or equalization must be adaptive to ensure proper
conditioning of the received signal independent of the cable length.
MLT-3 to NRZI Decoder
The DM8806 decodes the MLT-3 information from the Digital Adaptive Equalizer into NRZI data.
Clock Recovery Module
The Clock Recovery Module accepts NRZI data from the MLT-3 to NRZI decoder. The Clock Recovery
Module locks onto the data stream and extracts the 125MHz reference clock. The extracted and
synchronized clock and data are presented to the NRZI to NRZ decoder.
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NRZI to NRZ
The transmit data stream is required to be NRZI encoded for compatibility with the TP-PMD standard for
100Base-TX transmission over Category-5 unshielded twisted pair cable. This conversion process must be
reversed on the receive end. The NRZI to NRZ decoder, receives the NRZI data stream from the Clock
Recovery Module and converts it to a NRZ data stream to be presented to the Serial to Parallel conversion
block.
Serial to Parallel
The Serial to Parallel Converter receives a serial data stream from the NRZI to NRZ converter. It converts the
data stream to parallel data to be presented to the descrambler.
Descrambler
Because of the scrambling process requires to control the radiated emissions of transmit data streams, the
receiver must descramble the receive data streams. The descrambler receives scrambled parallel data
streams from the Serial to Parallel converter, and it descrambles the data streams, and presents the data
streams to the Code Group alignment block.
Code Group Alignment
The Code Group Alignment block receives un-aligned 5B data from the descrambler and converts it into 5B
code group data. Code Group Alignment occurs after the J/K is detected, and subsequent data is aligned on
a fixed boundary.
4B5B Decoder
The 4B5B Decoder functions as a look-up table that translates incoming 5B code groups into 4B (Nibble) data.
When receiving a frame, the first 2 5-bit code groups receive the start-of-frame delimiter (J/K symbols). The
J/K symbol pair is stripped and two nibbles of preamble pattern are substituted. The last two code groups are
the end-of-frame delimiter (T/R Symbols).
The T/R symbol pair is also stripped from the nibble, presented to the Reconciliation layer.
7.2.3
10Base-T Operation
The 10Base-T transceiver is IEEE 802.3u compliant. When the DM8806 is operating in 10Base-T mode, the
coding scheme is Manchester. Data processed for transmit is presented in nibble format, converted to a serial
bit stream, then the Manchester encoded. When receiving, the bit stream, encoded by the Manchester, is
decoded and converted into nibble format.
7.2.4
Collision Detection
For half-duplex operation, a collision is detected when the transmit and receive channels are active
simultaneously. Collision detection is disabled in full duplex operation.
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7.2.5
Carrier Sense
Carrier Sense (CRS) is asserted in half-duplex operation during transmission or reception of data. During
full-duplex mode, CRS is asserted only when receiving operations.
7.2.6
Auto-Negotiation
The objective of Auto-negotiation is to provide a means to exchange information between linked devices and
to automatically configure both devices to take maximum advantage of their abilities. It is important to note
that Auto-negotiation does not test the characteristics of the linked segment. The Auto-Negotiation function
provides a means for a device to advertise supported modes of operation to a remote link partner,
acknowledge the receipt and understanding of common modes of operation, and to reject un-shared modes
of operation. This allows devices on both ends of a segment to establish a link at the best common mode of
operation. If more than one common mode exists between the two devices, a mechanism is provided to allow
the devices to resolve to a single mode of operation using a predetermined priority resolution function.
Auto-negotiation also provides a parallel detection function for devices that do not support the
Auto-negotiation feature. During Parallel detection there is no exchange of information of configuration.
Instead, the receive signal is examined. If it is discovered that the signal matches a technology, which the
receiving device supports, a connection will be automatically established using that technology. This allows
devices not to support Auto-negotiation but support a common mode of operation to establish a link.
7.2.7
Auto-MDIX Functional Description
The DM8806 supports the automatic detect cable connection type, MDI/MDIX (straight through/cross over)
for internal port 0 ~ 4 PHY. A manual configuration by register bit for MDI or MDIX is still accepted.
When set to automatic, the polarity of MDI/MDIX controlled timing is generated by a 16-bits LFSR. The
switching cycle time is located from 200ms to 420ms. The polarity control is always switch until detect
received signal. After selected MDI or MDIX, this feature is able to detect the required cable connection
type.( straight through or crossed over ) and make correction automatically.
RX + /- from DM8806
RX+/- to RJ45
TX + /- from DM8806
TX+/- to RJ45
* MDI : __________
* MDIX : - - - - - - - - -
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7.2.8
Link Fault Pass-through and Far End Fault Functional Description
The DM8806/DM8806I pairs Port 0 and Port 1 for media converter application and supports Link Fault Pass-through
(LFP) and Far End Fault (FEF) troubleshooting features. The LFP allows the DM8806/DM8806I to monitor both the fiber
and TP ports for loss of signal. In case of a loss of RX signal on one media port, the DM8806/DM8806I will automatically
disable the TX signal to the other media port, thus passing through the link fault. FEF enables the DM8806/DM8806I to
stop sending link pulse to the link partner once a loss of the fiber RX signal is encountered. Then the link partner will
synchronously stop sending data. FEF prevents loss of valuable data transmitted over invalid link. Combining those two
functions of DM8806/DM8806I, both end devices can be notified of a loss of fiber link
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7.3
Host SMI Interface
Host SMI
SMI_CK
SMI_DIO
MDC
MDIO
Host / MAC
Only one host is allowed to acccess the SMI_CK, SMI_DIO
DM8806/
DM8206
DM8806I
Host SMI - Read Frame Structure
SMI_CK
SMI_DIO Read
32 "1"s
Idle
0
Preamble
1
SFD
1
0
R9
R8
R7
R6
R5
Z
Register Address
Op Code
//
//
R0
0
D15
D14
D1
Turn Around
D0
Idle
Data
Read
Write
Host SMI - Write Frame Structure
SMI_CK
SMI_DIO Write
32 "1"s
Idle
Preamble
0
1
SFD
0
1
Op Code
R9
R8
R7
R6
Register Address
Write
R5
R0
1
0
Turn Around
D15
D14
Data
D1
D0
Idle
The internal registers of DM8806 can be accessed by Host Serial Management Interface (SMI). The
application of SMI illustrated as below.
The Host SMI consists of two pins, one is SMI_CK and another is SMI_DIO. User can access DM8806’s
EEPROM, PHY registers, MIB counters and Configuration registers through Host SMI. The format is following.
32 bit “1” preamble field, “01” <SFD> field, <OpCode> field (“10” for read, “”01” for write), the <Register
Address> field of the frame is mapped to address of control and status register set of DM8806, and the 16-bit
<Data> field for read/writ data.
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DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
7.3.1
Host SMI Bus Error Check Function
To prevent the host SMI bus to be interfered by noise on board-level. This function is used to check the
command validity to suppress the mistaken command. In write procedure, the written value in register will be
applied until the correct checksum is written (error proofing) and user can read status for validation (error
detecting). In read procedure, user can compare hardware calculated checksum with software calculated one
to validate the result.
For example:
Write Procedure
(1). Set register 33AH.[0] = 1 to enable SMI Bus Error Check function
(2). Write data to DM8806's register (general write command)
(3). CPU calculate checksum (CSUM[7:0]) and write it to register 339H.[7:0]
(4). Check function status in register 339H.[8]
Read Procedure
(1). Set register 33AH.[0] = 1 to enable SMI Bus Error Check function
(2). Read data from DM8806's register (general read command)
(3). Read hardware calculated checksum from register 339H.[7:0] and compare it with CPU calculated
one (CSUM[7:0])
Checksum calculate formula:
CSUM[0]
=
D[0]
^
D[8]
^
R[0]
^
R[8]
CSUM[1]
=
D[1]
^
D[9]
^
R[1]
^
R[9]
CSUM[2]
=
D[2]
^
D[10]
^
R[2]
^
OP[0]
CSUM[3]
=
D[3]
^
D[11]
^
R[3]
^
OP[1]
CSUM[4]
=
D[4]
^
D[12]
^
R[4]
CSUM[5]
=
D[5]
^
D[13]
^
R[5]
CSUM[6]
=
D[6]
^
D[14]
^
R[6]
CSUM[7]
=
D[7]
^
D[15]
^
R[7]
Note:
D[15:0]
=
<Data> field of SMI frame
R[9:0]
=
<Register Address> field of SMI frame
OP[1:0]
=
<Op Code> field of SMI frame
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DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
7.4
LED Mode Control
LED mode
Bit [1:0] of register 317H
P0~4_LNK_LED
P0~4_SPD_LED
P0~4_FDX_LED
P0~4_LNK_LED
P0~4_SPD_LED
“00” : LED mode 0
“01” : LED mode 1, dual color mode
“10” : LED mode 2
“11” : LED mode 3 (default)
LED mode 0
100M link + Activity
OFF: 100M link fail
ON : 100M link ok and no TX/RX activity
BLINK: 100M link ok and TX/RX activity
Collision
OFF: no collision
BLINK: collision
10M link + Activity
OFF: 10M link fail
ON: 10M link ok and no TX/RX activity
BLINK: 10M link ok and TX/RX activity
LED mode 1 (Dual color mode)
Application circuit :
LNK_LED
100M link/act
10M link/act
SPD_LED
LNK_LED
SPD_LED
link off
HI
HI
100M link
HI
LO
BLINK
LO
10M link
LO
HI
10M link / activity
LO
BLINK
100M link / activity
P0~4_FDX_LED
Full / half duplex mode
OFF: half-duplex
ON: full-duplex
BLINK: half-duplex and collision
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DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
P0~4_LNK_LED
P0~4_SPD_LED
P0~4_FDX_LED
LED mode 2
100M link + Activity
OFF: 100M link fail
ON: 100M link ok and no TX/RX activity
BLINK: 100M link ok and TX/RX activity
Full / half duplex mode
OFF: half-duplex
ON: full-duplex
BLINK: half-duplex and collision
10M link + Activity
OFF: 10M link fail
ON: 10M link ok and no TX/RX activity
BLINK: 10M link ok and TX/RX activity
LED mode 3 (Default)
link + Activity
OFF: link fail
ON,: link ok and no TX/RX activity
BLINK: link ok and TX/RX activity
P0~4_SPD_LED
Speed
OFF: 10M mode or link OFF
ON: 100M mode link
P0~4_FDX_LED
Full / half duplex mode
OFF: half-duplex
ON: full-duplex
BLINK: half-duplex and collision
Where OFF means in floating state
ON means in ground state if LED is low active, or in high voltage state if LED is high active
BLINK means in toggle state with ON 20ms and OFF 80ms
HI means in high voltage state
LO means in ground state
P0~4_LNK_LED
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DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
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DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
8. DC and AC Electrical Characteristics
8.1 Absolute Maximum Ratings
Symbol
DVDD33
DVDD18
AVDD33
AVDD18
VIN
TSTG
TA
TA
LT
8.2
Parameter
3.3V Supply Voltage
1.8V core power supply
Analog power supply 3.3V
Analog power supply 1.8V
DC Input Voltage (VIN)
Storage Temperature range
Ambient Temperature
Ambient Temperature
Lead Temperature
(TL, soldering, 10 sec.).
Min.
3.135
1.71
3.135
1.71
3.135
-65
0
-40
-
Max.
3.6
1.95
3.6
1.95
3.6
+150
+70
+85
+245
Unit
V
V
V
V
V
°C
°C
°C
°C
Max.
3.465
1.89
3.465
1.89
-
Unit
V
V
V
V
mA
mA
mA
mA
Conditions
DM8806
DM8806I
Lead-free Device
Operating Conditions
Symbol
DVDD33
DVDD18
AVDD33
AVDD18
PD
(Power
Dissipation)
Parameter
3.3V Supply Voltage
1.8V core power supply
Analog power supply 3.3V
Analog power supply 1.8V
5 ports 100BASE-TX
5 ports10BASE-TX
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Min.
3.135
1.71
3.135
1.71
-
Typ.
3.30
1.80
3.30
1.80
471
243
549
66
Conditions
1.8V only
3.3V only
1.8V only
3.3V only
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DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
8.3
DC Electrical Characteristics
Symbol
Inputs
VIL
VIH
IIL
IIH
Outputs
VOL
VOH
Receiver
VICM
Parameter
Min.
Typ.
Max.
Input Low Voltage
Input High Voltage
Input Low Leakage Current
Input High Leakage Current
2.0
-1
-
-
0.8
1
V
V
uA
uA
Vcond1
Vcond1
VIN = 0.0V, Vcond1
VIN = 3.3V, Vcond1
Output Low Voltage
Output High Voltage
2.4
-
0.4
-
V
V
IOL = 4mA
IOH = -4mA
-
1.8
-
V
100 Ω Termination
Across
1.9
4.4
│19│
│44│
2.0
5
│20│
│50│
2.1
5.6
│21│
│56│
V
V
mA
mA
RX+/RX- Common Mode Input
Voltage
Transmitter
VTD100 100TX+/- Differential Output Voltage
VTD10 10TX+/- Differential Output Voltage
ITD100 100TX+/- Differential Output Current
ITD10
10TX+/- Differential Output Current
Unit
Conditions
Peak to Peak
Peak to Peak
Absolute Value
Absolute Value
Note: Vcond1 = DVDD33 = 3.3V, DVDD18 = 1.8V, AVDD33 = 3.3V, AVDD18 = 1.8V.
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DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
8.4 AC Characteristics
8.4.1
Power On Reset Timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
39.995
40
40.005
ns
-
T1
X1 Period
T2
X1 High Time
18
-
22
ns
T3
X1 Low Time
18
-
22
ns
T4
Reset Low Duration
1
-
-
ms
T5
Power On Reset Duration
10
-
-
ms
T6
100
-
-
ns
200
-
-
ns
T8
Strap Valid Setup to PWRST#
Rising
Strap Valid Hold from PWRST#
Rising
PWRST# high to EECS high
-
5
-
us
T9
EEPROM Load Duration
-
-
21
ms
T7
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DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
8.4.2
MAC MII/RevMII Interface Transmit Timing
Symbol
Parameter
Min.
Typ.
100M MII Transmit Clock Period
40
T1
10M MII Transmit Clock Period
400
T2
TXE, TXD3~0 Output Delay to TXC Rising
4
8
Note: TXC stand for pin P4M_TXC in port 4 and pin P5_TXC in port 5
TXE stand for pin P4M_TXE in port 4 and pin P5_TXE in port 5
TXD_3~0 stand for pin P4M_TXD3~0 in port 4 and pin P5_TXD3~0 in port 5
8.4.3
Symbol
T1
T2
T3
Max.
12
Unit
ns
ns
ns
Max.
-
Unit
ns
ns
ns
ns
MAC MII/RevMII Interface Receive Timing
Parameter
100M MII Receive Clock Period
10M MII Receive Clock Period
RXDV, RXD3~0 Setup Time to RXC
RXDV, RXD3~0 Hold Time to RXC
Min.
5
5
Typ.
40
400
-
Note: RXC stand for pin P4M_RXC in port 4 and pin P5_RXC in port 5
RXDV stand for pin P4M_RXDV in port 4 and pin P5_RXDV in port 5
RXD_3~0 stand for pin P4M_RXD3~0 in port 4 and pin P5_RXD3~0 in port 5
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DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
8.4.4
Symbol
T1
T2
PHY MII Interface Transmit Timing
Parameter
100M MII Receive Clock Period
10M MII Receive Clock Period
RXDV, RXD3~0 Output Delay to RXC Rising
Min.
4
Typ.
40
400
8
Max.
12
Unit
ns
ns
ns
Min.
5
5
Typ.
40
400
-
Max.
-
Unit
ns
ns
ns
ns
Note: RXC stand for pin P4P_RXC in port 4
RXDV stand for pin P4P_RXDV in port 4
RXD_3~0 stand for pin P4P_RXD3~0 in port 4
8.4.5
PHY MII Interface Receive Timing
Symbol
Parameter
100M MII Transmit Clock Period
T1
10M MII Transmit Clock Period
T2
TXE, TXD3~0 to TXC Setup Time
T3
TXE, TXD3~0 to TXC Hold Time
Note: TXC stand for pin P4P_TXC in port 4
TXE stand for pin P4P_TXE in port 4
TXD_3~0 stand for pin P4P_TXD3~0 in port 4
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DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
8.4.6
Symbol
T1
T2
MAC RMII Interface Transmit Timing
Parameter
RMII REFCLK_I Period
TXE, TXD1~0 Output Delay to REFCLK_I Rising
Min.
4
Typ.
20
8
Max.
12
Unit
ns
ns
Max.
-
Unit
ns
ns
ns
Note: REFCLK_I stand for pin P4M_ REFCLK_I in port 4 and pin P5_ REFCLK_I in port 5
TXE stand for pin P4M_TXE in port 4 and pin P5_TXE in port 5
TXD_1~0 stand for pin P4M_TXD1~0 in port 4 and pin P5_TXD1~0 in port 5
8.4.7
Symbol
T1
T2
T3
MAC RMII Interface Receive Timing
Parameter
RMII REFCLK_I Period
CRSDV, RXD1~0 Setup Time to REFCLK_I
CRSDV, RXD1~0 Hold Time to REFCLK_I
Min.
4
2
Typ.
20
-
Note: REFCLK_I stand for pin P4M_ REFCLK_I in port 4 and pin P5_ REFCLK_I in port 5
CRSDV stand for pin P4M_CRSDV in port 4 and pin P5_CRSDV in port 5
RXD_1~0 stand for pin P4M_RXD1~0 in port 4 and pin P5_RXD1~0 in port 5
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DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
8.4.8
Symbol
T1
T2
PHY RMII Interface Transmit Timing
Parameter
RMII REFCLK_I Period
CRSDV, RXD1~0 Output Delay to REFCLK_I Rising
Min.
4
Typ.
20
8
Max.
12
Unit
ns
ns
Min.
4
2
Typ.
20
-
Max.
-
Unit
ns
ns
ns
Note: REFCLK_I stand for pin P4P_ REFCLK_I in port 4
CRSDV stand for pin P4P_CRSDV in port 4
RXD_1~0 stand for pin P4P_RXD1~0 in port 4
8.4.9
Symbol
T1
T2
T3
PHY RMII Interface Receive Timing
Parameter
RMII REFCLK_I Period
TXE, TXD1~0 Setup Time to REFCLK_I
TXE, TXD1~0 Hold Time to REFCLK_I
Note: REFCLK_I stand for pin P4P_ REFCLK_I in port 4
TXE stand for pin P4P_TXE in port 4
TXD_1~0 stand for pin P4P_TXD1~0 in port 4
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DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
8.4.10
Symbol
T1
T2
T3
T4
Host SMI Interface Timing
Parameter
SMI_CK Period
SMI_DIO to SMI_CK Setup Time on Input State
SMI_DIO to SMI_CK Hold Time on Input State
SMI_DIO to SMI_CK Rising Output Delay on Output
State
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Min.
80
10
10
-
Typ.
5
Max.
-
Unit
ns
ns
ns
ns
152
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
8.4.11
Symbol
T1
T2
T3
T4
PHY SMI Interface Timing
Parameter
PHY_MDC Period
PHY_MDIO to PHY_MDC Setup Time on Input State
PHY_MDIO to PHY_MDC Hold Time on Input State
PHY_MDIO to PHY_MDC Rising Output Delay on
Output State
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Min.
40
40
-
Typ.
1920
960
Max.
-
Unit
ns
ns
ns
ns
153
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
8.4.12
Symbol
T1
T2
T3
T4
T5
EEPROM Timing
Parameter
EECK Period
EECS to EECK Rising Output Delay
EEDIO to EECK Rising Output Delay on Output State
EEDIO to EECK Rising Setup Time on Input State
EEDIO to EECK Rising Hold Time on Input State
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Min.
200
200
Typ.
2560
2080
2100
-
Max.
-
Unit
ns
ns
ns
ns
ns
154
DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
9. Application Information
9.1 Application of Reverse MII
NC
NC
NC
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DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
9.2
Application of Reduce MII to PHY
RMII MAC I/F
RMII PHY I/F
SMI_CK
SMI_DIO
PHY_MDC
MDC
PHY_MDIO
MDIO
TXD1~0
TXE
TX_EN
RXD1~0
RXD[1:0]
CRS
CRS_DV
RXC
REF_CLK
TXC
RX_ER*
Application of Reduce MII to MAC
DM8806
9.3
TXD[1:0]
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DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
10. Package Information
128 Pins QFP Package Outline Information:
Symbol
A
A1
A2
B
C
D
D1
E
E1
e
L
L1
y
θ
Dimension in mm
Min
Nom
Max
－
－
3.40
0.25
－
－
2.73
2.85
2.97
0.17
0.22
0.27
0.09
－
0.20
23.00 23.20 23.40
19.90 20.00 20.10
17.00 17.20 17.40
13.90 14.00 14.10
0.50 BSC
0.73
0.88
1.03
1.60 BSC
－
－
0.10
o
o
0
－
7
Dimension in inch
Min
Nom
Max
－
－
0.134
0.010
－
－
0.107
0.112 0.117
0.007
0.009 0.011
0.004
－
0.008
0.906
0.913 0.921
0.783
0.787 0.791
0.669
0.677 0.685
0.547
0.551 0.555
0.020 BSC
0.029
0.035 0.041
0.063 BSC
－
－
0.004
o
o
0
－
7
1. Dimension D1 and E1 do not include resin fin.
2. All dimensions are base on metric system.
3. General appearance spec should base on its final visual inspection spec.
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DM8806/DM8806I
6-Port 10/100Mb Fast Ethernet Smart Switch
11. Ordering Information
Part Number
Temperature
Range
DM8806FP
0℃ to 70℃
DM8806IFP
－40℃ to ＋85℃
Package
128-Pin QFP
(Pb-Free)
128-Pin QFP
(Pb-Free)
Disclaimer
The information appearing in this publication is
believed to be accurate. Integrated circuits sold by
DAVICOM Semiconductor are covered by the
warranty and patent indemnification provisions
stipulated in the terms of sale only. DAVICOM
makes no warranty, express, statutory, implied or by
description regarding the information in this
publication or regarding the information in this
publication or regarding the freedom of the
described chip(s) from patent infringement.
FURTHER, DAVICOM MAKES NO WARRANTY
OF MERCHANTABILITY OR FITNESS FOR ANY
PURPOSE. DAVICOM reserves the right to halt
production or alter the specifications and prices at
any time without notice. Accordingly, the reader is
cautioned to verify that the data sheets and other
information in this publication are current before
placing orders. Products described herein are
intended for use in normal commercial applications.
Applications involving unusual environmental or
reliability requirements, e.g. military equipment or
medical life support equipment, are specifically not
recommended without additional processing by
DAVICOM for such applications. Please note that
application circuits illustrated in this document are
for reference purposes only.
DAVICOM’s terms and conditions printed on the
order acknowledgment govern all sales by
DAVICOM. DAVICOM will not be bound by any
terms inconsistent with these unless DAVICOM
agrees otherwise in writing. Acceptance of the
buyer’s orders shall be based on these terms.
Company Overview
DAVICOM Semiconductor Inc. develops and
manufactures integrated circuits for integration into
data communication products. Our mission is to
design and produce IC products that are the
industry’s best value for Data, Audio, Video, and
Internet/Intranet applications. To achieve this goal,
we have built an organization that is able to develop
chipsets in response to the evolving technology
requirements of our customers while still delivering
products that meet their cost requirements.
Products
We offer only products that satisfy high performance
requirements and which are compatible with major
hardware and software standards. Our currently
available and soon to be released products are
based on our proprietary designs and deliver high
quality, high performance chipsets that comply with
modem communication standards and Ethernet
networking standards.
Contact Windows
For additional information about DAVICOM products, contact the Sales department at:
Headquarters
Hsin-chu Office:
No.6 Li-Hsin Rd. VI,
Science-based Industrial Park,
Hsin-chu City, Taiwan, R.O.C.
TEL: +886-3-5798797
FAX: +886-3-5646929
MAIL: [email protected]
HTTP: http://www.davicom.com.tw
WARNING
Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near
the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and function.
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