DM8606C/DM8606CI - Davicom Semiconductor Inc.

DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
DAVICOM Semiconductor, Inc.
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
DATA SHEET
Preliminary
Version: DM8606C/DM8606CI-12-3-DS-P01
November 22, 2012
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
1
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
CONTENT
1.
Features ............................................................................................................................ 9
1.1
System Description .............................................................................................. 10
2.
Block Diagram and Block Description ........................................................................... 11
3. Pin Configuration ............................................................................................................... 12
3.1 Pin Diagram ................................................................................................................. 12
3.2 Pin Description ............................................................................................................. 13
3.2.1 LED Pins .............................................................................................................. 13
3.2.2 EEPROM Interface .............................................................................................. 14
3.2.3 Clock Interface ..................................................................................................... 14
3.2.4 Network Interface ................................................................................................. 14
3.2.5 Port 4 MAC MII/RevMII/RMII and PHY MII interfaces .......................................... 15
3.2.6 Port 5 MII/RevMII/RMII interfaces ........................................................................ 17
3.2.7 Miscellaneous Pins .............................................................................................. 18
3.2.8 Power Pins ........................................................................................................... 19
3.3 Strap Pins Table........................................................................................................... 20
4. Control and Status Register Set ........................................................................................ 22
4.1 Port0~Port4 PHY Registers (000H~0FFH)................................................................... 24
4.1.1 Basic Mode Control Register (BMCR) (040H,060H,080H,0A0H,0C0H) .............. 24
4.1.2 Basic Mode Status Register (BMSR) (041H,061H,081H,0A1H,0C1H) ................ 25
4.1.3 PHY ID Identifier Register #1 (PHYID1) (042H,062H,082H,0A2H,0C2H)............ 26
4.1.4 PHY ID Identifier Register #2 (PHYID2) (043H,063H,083H,0A3H,0C3H)............ 26
4.1.5 Auto-Nego. Advertised Register (ANAR) (044H,064H,084H,0A4H,0C4H) .......... 26
4.1.6 Auto-Nego. Partner Ability Register (ANPAR) (045H,065H,085H,0A5H,0C5H) .. 28
4.1.7 Auto-Nego. Expansion Register (ANER) (046H,066H,086H,0A6H,0C6H) .......... 29
4.1.8 Specified Control 1 Register (SC1R) (050H,070H,090H,0B0H,0D0H) ................ 29
4.1.9 Specified Control 2 Register (SC2R) (054H,074H,094H,0B4H,0D4H) ................ 30
4.1.10 Power Saving Control Register (PSCR) (05DH,07DH,09DH,0BDH,0DDH) ............ 30
4.2 Switch Per-Port Registers (100H~1FFH) ..................................................................... 31
4.2.1 Per Port Status Data Register (110H,130H,150H,170H,190H,1B0H) .................. 31
4.2.2 Per Port Basic Control 0 Register (111H,131H,151H,171H,191H,1B1H) ............ 31
4.2.3 Per Port Basic Control 1 Register (112H,132H,152H,172H,192H,1B2H) ............ 33
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DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.2.4 Per Port Block Control 0 Register (113H,133H,153H,173H,193H,1B3H) ............ 35
4.2.5 Per Port Block Control 1 Register (114H,134H,154H,174H,194H,1B4H) ............ 35
4.2.6 Per Port Bandwidth Control Register (115H,135H,155H,175H,195H,1B5H) ....... 36
4.2.7 Per Port VLAN Tag Infomation Register (116H,136H,156H,176H,196H,1B6H) .. 38
4.2.8 Per Port Priority and VLAN Control Register (117H,137H,157H,177H,197H,1B7H)
...................................................................................................................................... 38
4.2.9 Per Port Security Control Register (118H,138H,158H,178H,198H,1B8H) ........... 40
4.2.10 Per Port Advanced Control register (119H,139H,159H,179H,199H,1B9H), ...... 41
4.2.11 Per Port Memory Control Register (11AH,13AH,15AH,17AH,19AH,1BAH),...... 42
4.2.12 Per Port Discard Limitation Register (11BH,13BH,15BH,17BH,19BH,1BBH) .... 42
4.3 Switch Engine Registers (200H~2FFH) ....................................................................... 43
4.3.1 Switch Status Register (210H) ............................................................................. 43
4.3.2 Switch Reset Register (211H) .............................................................................. 43
4.3.3 Switch Control Register Register (212H) ............................................................. 43
4.3.4 CPU Port & Mirror Control Register (213H) ......................................................... 44
4.3.5 Special Tag Ether-Type Register (214H) ............................................................. 45
4.3.6 Global Learning & Aging Control Register (215H) ............................................... 45
4.3.7 VLAN Priority Map Register (217H) ..................................................................... 45
4.3.8 TOS Priority Map 0 Register (218H) .................................................................... 46
4.3.9 TOS Priority Map 1 Register (219H) .................................................................... 46
4.3.10 TOS Priority Map 2 Register (21AH) .................................................................. 46
4.3.11 TOS Priority Map 3 Register (21BH) .................................................................. 47
4.3.12 TOS Priority Map 4 Register (21CH).................................................................. 47
4.3.13 TOS Priority Map 5 Register (21DH).................................................................. 47
4.3.14 TOS Priority Map 6 Register (21EH) .................................................................. 47
4.3.15 TOS Priority Map 7 Register (21FH) .................................................................. 48
4.3.16 MIB Counter Disable Register (230H)................................................................ 49
4.3.17 MIB Counter Control Register (231H) ................................................................ 49
4.3.18 MIB Counter Data Low Register (232H) ............................................................ 50
4.3.19 MIB Counter Data High Register (233H)............................................................ 50
4.3.20 QinQ TPID Register (23DH) .............................................................................. 51
4.3.21 VLAN Mode and Rule Control Register (23EH) ................................................. 51
4.3.22 VLAN Table - Valid Control Register (23FH) ..................................................... 52
4.3.23 VLAN Table - ID_0H Register (250H) ................................................................ 52
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DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.3.24 VLAN Table - ID_1H Register (251H) ................................................................ 52
4.3.25 VLAN Table - ID_2H Register (252H) ................................................................ 52
4.3.26 VLAN Table - ID_3H Register (253H) ................................................................ 52
4.3.27 VLAN Table - ID_4H Register (254H) ................................................................ 52
4.3.28 VLAN Table - ID_5H Register (255H) ................................................................ 52
4.3.29 VLAN Table - ID_6H Register (256H) ................................................................ 52
4.3.30 VLAN Table - ID_7H Register (257H) ................................................................ 52
4.3.31 VLAN Table - ID_8H Register (258H) ................................................................ 53
4.3.32 VLAN Table - ID_9H Register (259H) ................................................................ 53
4.3.33 VLAN Table - ID_AH Register (25AH) ............................................................... 53
4.3.34 VLAN Table - ID_BH Register (25BH) ............................................................... 53
4.3.35 VLAN Table - ID_CH Register (25CH) ............................................................... 53
4.3.36 VLAN Table - ID_DH Register (25DH) ............................................................... 53
4.3.37 VLAN Table - ID_EH Register (25EH) ............................................................... 53
4.3.38 VLAN Table - ID_FH Register (25FH)................................................................ 53
4.3.39 VLAN Table - MEMBER_0H Register (270H) .................................................... 54
4.3.40 VLAN Table - MEMBER_1H Register (271H) .................................................... 54
4.3.41 VLAN Table - MEMBER_2H Register (272H) .................................................... 54
4.3.42 VLAN Table - MEMBER_3H Register (273H) .................................................... 54
4.3.43 VLAN Table - MEMBER_4H Register (274H) .................................................... 55
4.3.44 VLAN Table - MEMBER_5H Register (275H) .................................................... 55
4.3.45 VLAN Table - MEMBER_6H Register (276H) .................................................... 55
4.3.46 VLAN Table - MEMBER_7H Register (277H) .................................................... 55
4.3.47 VLAN Table - MEMBER_8H Register (278H) .................................................... 56
4.3.48 VLAN Table - MEMBER_9H Register (279H) .................................................... 56
4.3.49 VLAN Table - MEMBER_AH Register (27AH) ................................................... 56
4.3.50 VLAN Table - MEMBER_BH Register (27BH) ................................................... 56
4.3.51 VLAN Table - MEMBER_CH Register (27CH) ................................................... 57
4.3.52 VLAN Table - MEMBER_DH Register (27DH) ................................................... 57
4.3.53 VLAN Table - MEMBER_EH Register (27EH) ................................................... 57
4.3.54 VLAN Table - MEMBER_FH Register (27FH) ................................................... 57
4.3.55 VLAN Table - Priority Enable Register (290H) ................................................... 58
4.3.56 VLAN Table - STP Index Enable Register (292H) ............................................. 58
4.3.57 VLAN Table - Misc_0 Register (293H) ............................................................... 58
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DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.3.58 VLAN Table - Misc_1 Register (294H) ............................................................... 58
4.3.59 VLAN Table - Misc_2 Register (295H) ............................................................... 58
4.3.60 VLAN Table - Misc_3 Register (296H) ............................................................... 58
4.3.61 VLAN Table - Misc_4 Register (297H) ............................................................... 59
4.3.62 VLAN Table - Misc_5 Register (298H) ............................................................... 59
4.3.63 VLAN Table - Misc_6 Register (299H) ............................................................... 59
4.3.64 VLAN Table - Misc_7 Register (29AH) .............................................................. 59
4.3.65 Snooping Control 0 Register (29BH).................................................................. 60
4.3.66 Snooping Control 1 Register (29CH) ................................................................. 60
4.3.67 Address Table Control & Status Register (2B0H) .............................................. 61
4.3.68 Address Table Data 0 Register (2B1H).............................................................. 62
4.3.69 Address Table Data 1 Register (2B2H).............................................................. 62
4.3.70 Address Table Data 2 Register (2B3H).............................................................. 62
4.3.71 Address Table Data 3 Register (2B4H).............................................................. 62
4.3.72 Address Table Data 4 Register (2B5H).............................................................. 62
4.4 Chip Control and Status Registers (300H~3FFH) ........................................................ 63
4.4.1 Vendor ID Register (310H) .................................................................................. 63
4.4.2 Product ID Register (311H) .................................................................................. 63
4.4.3 Chip Revision ID Register (312H) ........................................................................ 63
4.4.4 Port 4 MAC Control Register (314H).................................................................... 63
4.4.5 Port 5 MAC Control Register (315H).................................................................... 64
4.4.6 LED Control Register (317H) ............................................................................... 64
4.4.7 Interrupt Status Register (318H) .......................................................................... 65
4.4.8 Interrupt Mask & Control Register (319H) ............................................................ 65
4.4.9 EEPROM Control & Address Register (31AH) ..................................................... 66
4.4.10 EEPROM Data Register (31BH) ........................................................................ 66
4.4.11 Monitor Register 1 (31CH) ................................................................................. 66
4.4.12 Monitor Register 2 (31DH) ................................................................................. 67
4.4.13 Monitor Register 3 (31EH) ................................................................................. 67
4.4.14 System Clock Select Register (338H) ................................................................ 68
4.4.15 Serial Bus Error Check Register (339H) ............................................................ 68
4.4.16 Serial Bus Control Register (33AH) ................................................................... 68
4.4.17 Virtual PHY Control Register (33DH) ................................................................. 69
4.4.18 PHY Control Test Register (33EH) .................................................................... 69
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DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
5. EEPROM Format ............................................................................................................... 70
5.1 EEPROM Words 4K (256 x 16) .................................................................................... 70
6. Function Description .......................................................................................................... 76
6.1 Switch function .......................................................................................................... 76
6.1.1 Address Learning ................................................................................................. 76
6.1.2 Address Aging ..................................................................................................... 76
6.1.3 Packet Forwarding ............................................................................................... 76
6.1.4 Inter-Packet Gap (IPG) ........................................................................................ 76
6.1.5 Back-off Algorithm ............................................................................................... 77
6.1.6 Late Collision ....................................................................................................... 77
6.1.7 Half Duplex Flow Control ..................................................................................... 77
6.1.8 Full Duplex Flow Control ...................................................................................... 77
6.1.9 Partition Mode ...................................................................................................... 77
6.1.10 Broadcast Storm Filtering .................................................................................. 78
6.1.11 Bandwidth Control.............................................................................................. 78
6.1.12 Port Monitoring Support ..................................................................................... 78
6.1.13 VLAN Support .................................................................................................... 79
6.1.13.1 Port-Based VLAN............................................................................................ 79
6.1.13.2 802.1q-Based VLAN ....................................................................................... 79
6.1.13.3 Tag/Untag ....................................................................................................... 79
6.1.14 Special Tag ........................................................................................................ 80
6.1.15 Priority Support .................................................................................................. 82
6.1.15.1 Port-Based Priority .......................................................................................... 82
6.1.15.2 802.1p-Based Priority ..................................................................................... 82
6.1.15.3 DiffServ-Based Priority.................................................................................... 82
6.1.16 Address Table Accessing .................................................................................. 82
6.1.16.1 Type of Address Table .................................................................................... 82
6.1.16.2 Access Rules of Address Table ...................................................................... 83
6.1.17 IGMP Snooping ................................................................................................. 87
6.1.17.1 Software-Based IGMP Snooping .................................................................... 87
6.1.17.2 Hardware-Based IGMP Snooping ................................................................... 87
6.1.18 IPv6 MLD Snooping ........................................................................................... 88
6.1.19 STP / RSTP Support .......................................................................................... 88
6.2 Host SMI Interface ..................................................................................................... 91
Preliminary
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DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
6.2.2 Host SMI Bus Error Check Function .................................................................... 92
6.3 LED Mode Control ........................................................................................................ 93
6.4 Internal PHY functions ................................................................................................. 96
6.4.1 100Base-TX Operation ........................................................................................ 96
6.4.1.1 4B5B Encoder ................................................................................................... 96
6.4.1.2 Scrambler ......................................................................................................... 96
6.4.1.3 Parallel to Serial Converter ............................................................................... 96
6.4.1.4 NRZ to NRZI Encoder ....................................................................................... 96
6.4.1.5 MLT-3 Converter ............................................................................................... 96
6.4.1.6 MLT-3 Driver ..................................................................................................... 97
6.4.1.7 4B5B Code Group............................................................................................. 97
6.4.2 100Base-TX Receiver .......................................................................................... 98
6.4.2.1 Signal Detect .................................................................................................... 98
6.4.2.2 Adaptive Equalization ....................................................................................... 98
6.4.2.3 MLT-3 to NRZI Decoder .................................................................................... 98
6.4.2.4 Clock Recovery Module .................................................................................... 98
6.4.2.5 NRZI to NRZ ..................................................................................................... 98
6.4.2.6 Serial to Parallel ................................................................................................ 99
6.4.2.7 Descrambler ..................................................................................................... 99
6.4.2.8 Code Group Alignment ..................................................................................... 99
6.4.2.9 4B5B Decoder .................................................................................................. 99
6.4.3 10Base-T Operation............................................................................................. 99
6.4.4 Collision Detection ............................................................................................... 99
6.4.5 Carrier Sense ....................................................................................................... 99
6.4.6 Auto-Negotiation .................................................................................................. 99
6.4.7 Auto-MDIX Functional Description ..................................................................... 100
7.
DC and AC Electrical Characteristics ............................................................................ 101
7.1 Absolute Maximum Ratings ..................................................................................... 101
7.2 Operating Conditions ............................................................................................... 101
7.3 DC Electrical Characteristics ................................................................................... 102
7.4 AC Characteristics ..................................................................................................... 103
7.4.1 Power On Reset Timing ..................................................................................... 103
7.4.2 Port 4,5 MII Interface Transmit Timing ............................................................... 104
7.4.3 Port 4,5 MII Interface Receive Timing ................................................................ 104
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DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
7.4.4 Port 4,5 RevMII Interface Transmit Timing ........................................................ 105
7.4.5 Port 4,5 RevMII Interface Receive Timing ......................................................... 105
7.4.6 Port 4,5 RMII Interface Transmit Timing ............................................................ 106
7.4.7 Port 4,5 RMII Interface Receive Timing ............................................................. 106
7.4.8 Port 4 PHY MII Interface Receive Timing .......................................................... 107
7.4.9 Port 4 PHY MII Interface Transmit Timing ......................................................... 107
7.4.10 Host SMI Interface Timing ............................................................................... 108
7.4.11 PHY SMI Interface Timing ............................................................................... 109
7.4.12 EEPROM Timing.............................................................................................. 110
8. Package Information ........................................................................................................ 111
9. Ordering Information ........................................................................................................ 112
Preliminary
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DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
1. Features

IEEE 802.3 10BASE-T/ IEEE 802.3u 100BASE-TX compatible

Ethernet Switch Ports

Five 10/100Mb PHY built-in, that can be used for Copper or Fiber application

Port 4 support MII/RMII/RevMII interface to MAC or MII interface to internal PHY

Port 5 support MII/RMII/RevMII interface to MAC

Each internal PHY supports HP Auto-MDIX

Support bandwidth, ingress and egress rate control on a per MAC port basis

Priority transmit queues for QoS is supported per each MAC port:

Each port have four queues with strict or weight ratio priority schemes

IEEE 802.1p VLAN, Port based, MAC based, IPv4 TOS, Special Tag

Per port support broadcast storming filter function for broadcast, multicast –
and unknown unicast packets

Flow Control:

Supports IEEE 802.3x Flow Control in full-duplex mode

Supports Back Pressure Flow Control in half-duplex mode

Support special Tag to communication with CPU

Record up to 2K Uni/Multi-cast MAC addresses

IEEE 802.1Q VLAN up-to 16 VLAN groups

Full 12-bit VID, 4-bit FID, Tag/untag,

Support SVL/IVL

Support hardware IGMP snooping v1/v2 and MLD v1

Support STP/RSTP

Support automatic aging scheme

Support trunk ports

Support EEPROM interface for power up configurations

Support serial data management interface and MIB counter for diagnostic

Supports industrial-temperature (-40℃ ~ +85℃)

128 pin PQFP package using 0.18um process, with 1.8V internal core and 3.3V
I/Os that are 5V tolerant
Preliminary
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DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
1.1 System Description
The embedded DM8606C/DM8606CI is a industrial-temperature (DM8606CI only) high
performance and cost-effective 6-port 10/100Mbps Fast Ethernet smart switch. The smart
switch incorporates five internal 10/100Mbps Ethernet PHY/ two media-independent interface
(MII/RMII/RevMII/PHYMII) accesses with six 10/100Mbps MAC.
The DM8606C/DM8606CI management features include IEEE 802.1q VLAN, IEEE 802.1p
Class of Service (CoS), Uni/Multi-cast MAC addresses, and IPv4 TOS. The five PHYs are all
fully compliant with IEEE 802.3 10BASE-T Ethernet, IEEE802.3u 100BASE-TX Fast Ethernet,
and IEEE802.3x Flow Control. EEPROM interface is used for convenient of registers default
configurations.
Preliminary
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DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
2.
Block Diagram and Block Description
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DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
3. Pin Configuration
P5_RXC
DVDD33
DGND
TEST2
PHY_MDC
P5_TXC
P5_TXE
INTR
72
71
70
69
68
67
66
65
P4_TXD[2]
P4_TXD[3]
73
DVDD18
75
74
76
P4_TXD[0]
P4_TXD[1]
DGND
EEDIO
77
EECS
80
79
78
DVDD18
EECK
DGND
81
P4_RXD[0]
84
83
82
P4_RXD[1]
P4_RXDV
86
85
DVDD33
P4_RXD[2]
89
DGND
P4_RXD[3]
91
90
87
P4_CRS
92
88
STRAP_DIS
P4_TXC
93
P4_RXC
P4_TXE
DVDD18
P4_COL
97
96
94
DGND
P4_SET0
99
95
P4_SET1
100
98
P3_SPD_LE
D
P4_SPD_LED
102
P2_SPD_LE
D
P1_SPD_LE
101
3.1 Pin Diagram
64
DGND
D
P0_SPD_LED
104
105
63
P5_TXD[0]
62
P4_CFG
NC1
106
61
P5_TXD[1]
P4_FDX_LED
107
60
P5_TXD[2]
TEST1
108
59
P5_TXD[3]
DVDD3
109
58
P5_COL
P3_FDX_LED
110
57
P5_CRS
P2_FDX_LED
111
56
P5_RXD[3]
P1_FDX_LED
112
55
P5_RXD[2]
P0_FDX_LED
113
54
P5_RXD[1]
53
P5_RXD[0]
52
P5_RXDV
51
P4_LNK_LED
103
DM8606CFP/
DM8606CIFP
V_P
114
NC3
115
DVDD18
116
NC4
117
50
DGND
DGND
118
49
DVDD33
PWRST#
X1
119
48
47
P3_LNK_LED
120
X2
121
46
DVDD18
AVDD18
122
45
DGND
AGND
123
44
SMI_CK
VCNTL
124
43
VREF
125
42
P1_LNK_LED
P0_LNK_LED
P2_LNK_LED
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29
30
31
32
33
34
35
36
37
38
P3_RX+
AVDD33
P4_RX+
P4_RX-
AGND
AGND
P4_TX+
P4_TX-
AVDD18
26
P3_TX+
P3_RX-
25
P3_TX-
28
24
AVDD18
27
23
AVDD33
AGND
AGND
22
18
P2_TX-
P2_RX+
17
AVDD18
21
16
P2_RX-
15
P1_RX+
AVDD33
19
14
P1_RX-
20
13
AGND
AGND
12
AGND
P2_TX+
10
11
P1_TX-
9
AVDD18
Preliminary
P1_TX+
8
AVDD33
AGND
P0_TX-
AVDD18
7
PHY_MDIO
6
39
P0_RX-
128
P0_RX+
AVDD33
5
SMI_DIO
AGND
TEST3
40
3
4
41
127
P0_TX+
126
1
2
AGND
BGRES
12
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
3.2 Pin Description
Buffer type:
I = Input, O = Output, I/O = Input / Output, O/D = Open Drain, P = Power, # = asserted Low, ANA=Analog
PD= always internal pull – low (about 50K Ohm), PU=always internal pull-high,
Pd= internal pull-low during pwrst# period, Pu=internal pull-high during pwrst# period
3.2.1 LED Pins
Pin No.
Pin Name
42
P0_LNK_LED
105
P0_SPD_LED
113
P0_FDX_LED
43
P1_LNK_LED
104
P1_SPD_LED
112
P1_FDX_LED
47
P2_LNK_LED
103
P2_SPD_LED
111
P2_FDX_LED
48
P3_LNK_LED
102
P3_SPD_LED
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Buffer
I/O Description
Type
PU,6mA ODX Port 0 Link / Active LED
It is the combined LED of link and carrier sense
signal of the internal PHY0
Pu,6mA ODX Port 0 Speed LED
Its active state indicates that the internal PHY0 is
operated in 100Mbps, or it is floating for the 10Mbps
mode of the internal PHY0
Pu,6mA ODX Port 0 Full-duplex LED
Its active state indicates that the internal PHY0 is
operated in full-duplex mode, or it is floating for the
half-duplex mode of the internal PHY0
Pu,6mA ODX Port 1 Link / Active LED
It is the combined LED of link and carrier sense
signal of the internal PHY1
Pu,6mA ODX Port 1 Speed LED
Its active state indicates that the internal PHY1 is
operated in 100Mbps, or it is floating for the 10Mbps
mode of the internal PHY1
Pd,6mA ODX Port 1 Full-duplex LED
Its active state indicates that the internal PHY1 is
operated in full-duplex mode, or it is floating for the
half-duplex mode of the internal PHY1
Pu,6mA ODX Port 2 Link / Active LED
It is the combined LED of link and carrier sense
signal of the internal PHY2
Pu,6mA ODX Port 2 Speed LED
Its active state indicates that the internal PHY2 is
operated in 100Mbps, or it is floating for the 10Mbps
mode of the internal PHY2
Pu,6mA ODX Port 2 Full-duplex LED
Its active state indicates that the internal PHY2 is
operated in full-duplex mode, or it is floating for the
half-duplex mode of the internal PHY2
Pu,6mA ODX Port 3 Link / Active LED
It is the combined LED of link and carrier sense
signal of the internal PHY3
Pu,6mA ODX Port 3 Speed LED
Its active state indicates that the internal PHY3 is
operated in 100Mbps, or it is floating for the 10Mbps
13
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
110
P3_FDX_LED
Pu,6mA
51
P4_LNK_LED
Pu,6mA
101
P4_SPD_LED
Pu,6mA
107
P4_FDX_LED
Pu,6mA
3.2.2 EEPROM Interface
Pin No.
Pin Name
mode of the internal PHY3
ODX Port 3 Full-duplex LED
Its active state indicates that the internal PHY3 is
operated in full-duplex mode, or it is floating for the
half-duplex mode of the internal PHY3
ODX Port 4 Link / Active LED
It is the combined LED of link and carrier sense
signal of the internal PHY4
ODX Port 4 Speed LED
Its active state indicates that the internal PHY4 is
operated in 100Mbps, or it is floating for the 10Mbps
mode of the internal PHY4.
ODX Port 4 Full-duplex LED
Its active state indicates that the internal PHY4 is
operated in full-duplex mode, or it is floating for the
half-duplex mode of the internal PHY4
79
EEDIO
Buffer
Type
PD,4mA
81
EECK
Pd,4mA
O
80
EECS
PD,4mA
O,
3.2.3 Clock Interface
Pin No.
Pin Name
I/O
120
X1
Buffer
Type
ANA
121
X2
ANA
O
25 MHz Crystal /Oscillator Input
Variation is limited to +/- 50 ppm.
25 MHz Crystal Output
When X1 is connected to oscillator, this pin should
left unconnected.
Pin Name
Buffer
Type
ANA
I/O
Description
I/O
Port 0 TP TX
These two pins are the Twisted Pair transmit in
MDI mode or receive in MDIX mode.
Port 0 TP RX
These two pins are the Twisted Pair receive in MDI
mode or transmit in MDIX mode.
Port 1 TP TX
These two pins are the Twisted Pair transmit in
MDI mode or receive in MDIX mode.
3.2.4 Network Interface
Pin No.
I/O
Description
I/O
EEPROM Data In/Output
Drive/Read data to/from EEPROM
EEPROM Serial Clock
Drive clock to EEPROM
EEPROM Chip Selection.
Drive chip selection to EEPROM
I
2
3
P0_TXP0_TX+
6
7
P0_RXP0_RX+
ANA
I/O
10
11
P1_TXP1_TX+
ANA
I/O
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
Description
14
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
14
15
P1_RXP1_RX+
ANA
I/O
18
19
P2_TXP2_TX+
ANA
I/O
21
22
P2_RXP2_RX+
ANA
I/O
25
26
P3_TXP3_TX+
ANA
29
30
P3_RXP3_RX+
ANA
I/O
32
33
P4_RX+
P4_RX-
ANA
I/O
36
37
P4_TX+
P4_TX-
ANA
I/O
127
BGRES
ANA
I/O
124
125
VCNTL
VREF
ANA
ANA
I/O
O
I/O
Port 1 TP RX
These two pins are the Twisted Pair receive in MDI
mode or transmit in MDIX mode.
Port 2 TP TX
These two pins are the Twisted Pair transmit in
MDI mode or receive in MDIX mode.
Port 2 TP RX
These two pins are the Twisted Pair receive in MDI
mode or transmit in MDIX mode.
Port 3 TP TX
These two pins are the Twisted Pair transmit in
MDI mode or receive in MDIX mode.
Port 3 TP RX
These two pins are the Twisted Pair receive in MDI
mode or transmit in MDIX mode.
Port 4 TP RX
These two pins are the Twisted Pair transmit in
MDI mode or receive in MDIX mode.
Port 4 TP TX
These two pins are the Twisted Pair receive in MDI
mode or transmit in MDIX mode.
Bandgap Pin
Connect a 6.8K 1% precision resistor to AGND in
application.
1.8V Voltage control to control external BJT
Voltage Reference
Connect a 0.1u capacitor to ground in application.
3.2.5 Port 4 MAC MII/RevMII/RMII and PHY MII interfaces
PORT4 MAC MII pins
Pin No.
Pin Name
73,74,77,78
96
92
91
97
95
85
90,89,86,84
P4_TXD[3:0]
P4_TXE
P4_TXC
P4_CRS
P4_COL
P4_RXC
P4_RXDV
P4_RXD[3:0]
PORT4 MAC Reverse MII pins
Pin No.
Pin Name
73,74,77,78
96
P4_TXD[3:0]
P4_TXE
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
Buffer
Type
Pd,4mA
Pd,4mA
Pd
PD
Pd
Pd
PD,PD
PU,PU
I/O
Description
O
O
I
I
I
I
I
I
Transmit Data
Transmit Enable
Transmit Clock.
Carrier Sense
Collision Detect.
Receive Clock
Receive Data Valid
Receive Data
Buffer
Type
Pd,4mA
Pd,4mA
I/O
Description
O
O
Transmit Data
Transmit Enable
15
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
92
91
97
95
85
90,89,86,84
P4_TXC
P4_CRS
P4_COL
P4_RXC
P4_RXDV
P4_RXD[3:0]
PORT4 MAC Reduced MII pins
Pin No.
Pin Name
73,74
77,78
96
92
91
97
95
85
86,84
90,89
P4_TXD[3:2]
P4_TXD[1:0]
P4_TXE
OSC50M4
P4_CRS
P4_COL
50MCLK4
P4_CRSDV
P4_RXD[1:0]
P4_RXD[3:2]
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
Pd,4mA
PD,4mA
Pd,4mA
Pd
PD,PD
PU,PU
O
O
O
I
I
I
Transmit Clock.
Carrier Sense
Collision Detect.
Receive Clock
Receive Data Valid
Receive Data
Buffer
Type
Pd,4mA
Pd,4mA
Pd,4mA
Pd,4mA
PD
Pd
Pd
PU
PD
I/O
Description
O
O
O
O
I
I
I
I
I
I
Reserved (No connection)
Port4 RMII Transmit Data
Transmit Enable
50MHz clock for Port 4 RMII
Reserved (No connection)
Reserved (No connection)
50MHz clock for Port4 RMII
Receive Data Valid
Receive Data
Reserved (No connection)
16
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
PORT4 PHY MII pins
Pin No.
Pin Name
90,89,86,84
P4_TXD[3:0]
85
92
91
97
95
96
73,74,77,78
P4_TXE
P4_TXC
P4_CRS
P4_COL
P4_RXC
P4_RXDV
P4_RXD[3:0]
Buffer
Type
PD,PD
PU,PU
Pd,4mA
PD,4mA
Pd,4mA
Pd,4mA
Pd,4mA
Pd,4mA
I/O
Buffer
Type
Pd,4mA
Pd,4mA
Pd
Pd
Pd
Pd
PD
PD
Description
I
Transmit Data
I
O
O
O
O
O
O
Transmit Enable
Transmit Clock.
Carrier Sense
Collision Detect.
Receive Clock
Receive Data Valid
Receive Data
I/O
Description
O
O
I
I
I
I
I
I
Transmit Data
Transmit Enable
Transmit Clock.
Carrier Sense
Collision Detect.
Receive Clock
Receive Data Valid
Receive Data
3.2.6 Port 5 MII/RevMII/RMII interfaces
PORT5 MII pins
Pin No.
59, 60 ,61, 63
66
67
57
58
72
52
56 ,55 ,54 ,53
Pin Name
P5_TXD[3:0]
P5_TXE
P5_TXC
P5_CRS
P5_COL
P5_RXC
P5_RXDV
P5_RXD[3:0]
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
17
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
PORT5 Reverse MII pins
Pin No.
Pin Name
59, 60 ,61, 63
66
67
57
58
72
52
56 ,55 ,54 ,53
P5_TXD[3:0]
P5_TXE
P5_TXC
P5_CRS
P5_COL
P5_RXC
P5_RXDV
P5_RXD[3:0]
PORT5 Reduced MII pins
Pin No.
Pin Name
Buffer
Type
Pd,4mA
Pd,4mA
Pd,4mA
Pd,4mA
Pd,4mA
Pd
PD
PD
I/O
Description
O
O
O
O
O
I
I
I
Transmit Data
Transmit Enable
Transmit Clock Output.
Carrier Sense Output
Collision Detect Output.
Receive Clock
Receive Data Valid
Receive Data
I/O
Description
I
Reserved (No connection)
Transmit Data
Transmit Enable
50MHz Clock Output.
Reserved (No connection)
Reserved (No connection)
50MHz clock for Reference Clock
Receive Data Valid
Receive Data
Reserved (No connection)
59,60
P5_TXD[3:2]
Buffer
Type
Pd
61,63
66
67
57
58
72
52
54 ,53
56 ,55
P5_TXD[1:0]
P5_TXE
OSC50M5
P5_CRS
P5_COL
50MCLK5
P5_CRSDV
P5_RXD[1:0]
P5_RXD[3:2]
Pd,4mA
Pd,4mA
Pd,4mA
Pd
Pd
Pd
PD
PD
PD
O
O
O
I
I
I
I
I
I
I/O Description
3.2.7 Miscellaneous Pins
Pin No.
Pin Name
40
SMI_DIO
Buffer
Type
PD,4mA
44
39
SMI_CK
PHY_MDIO
PD,4mA
PD,4mA
68
PHY_MDC
Pd,4mA
65
93
INTR
STRAP_DIS
PD
62,
98,
100
CFG4,
P4_SET0,
P4_SET1
PD
Pu
Pd
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
I/O Serial Management Data Input/output as CPU
interface
I
Serial Management Data Clock as CPU interface
I/O MII Serial Management Data Input/output as
External PHY interface
O MII Serial Management Data Clock as External PHY
interface
O Interrupt signals to external CPU
I
Strap pins disabled
0: strap pins enabled
1: no strap pin function
I
Port 4 operation mode
I
CFG4 P4_SET1 P4_SET0
I
0
0
0 use internal PHY
18
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
119
PWRST#
-
I
41,
69,
108
114
TEST3,
TEST2,
TEST1
V_P
PD
PD
PD
Pd
I
I
I
I
106,
115,
117
NC1,
NC3,
NC4
Pd
Pd
Pd
I
I
I
Pin Name
I/O
DVDD33
DVDD18
DGND
Buffer
Type
PWR
PWR
GND
AVDD33
AVDD18
AGND
PWR
PWR
GND
3.2.8 Power Pins
Pin No.
49, 71 ,88, 109
46, 75 ,82, 94 ,116
50, 64 , 70, 76,
83, 87, 99,118,
8,16,23,31,128
1,9,17,24,38.,122
4, 5, 12, 13, 20,27,
28, 34, 35, 123, 126
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
0
0
1 MAC MII/RMII/RevMII
1
X
X PHY MII
Power on Reset
Low active with minimum 10ms
Test pins
Tie TEST3 to ground in application
Tie TEST2 and TEST1 to DVDD33 in application
Virtual PHY
0: Disable
1: Enable
NO Connection
Pull low to these pins in application, unless the strap
pin is used.
Description
Digital 3.3V power
Digital 1.8V power
Digital GND
Analog 3.3V power
Analog 1.8V power
Analog GND
19
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
3.3 Strap Pins Table
1: pull-high 1K~10K, 0: floating
Pin No.
Pin Name
51
P4_LNK_LED
101
102,103
Description
Port 4 PHY
1: Copper mode
0: Fiber mode
P4_SPD_LED When in Port4 in force mode
0 : link OFF
1 : link ON
P3_SPD_LED, When Port 4 in MAC MII/RMII/RevMII
P3_SPD_LED P2_SPD_LED
P2_SPD_LED
0
0
RevMII with P4_TXC turbo clock
0
1
RMII
1
0
MII
1
1
RevMII with P4_TXC 25MHz/2.5MHz clock
When Port 4 PHY MII mode
P3_SPD_LED P2_SPD_LED
0
X
1
X
When,Port4 in force mode
0: 10M mode
1: 100M mode
104
P1_SPD_LED
105
P0_SPD_LED
When,Port4 in force mode
0: Half-duplex mode
1: Full-duplex mode
107
P4_FDX_LED
When Port5 in force mode
0 : link OFF
1 : link ON
110,111
112
P3_FDX_LED, Port 5 Mode
P3_FDX_LED P2_FDX_LED
P2_FDX_LED
0
0
0
1
1
0
1
1
When
Port5
in
force
mode
P1_FDX_LED
0: 10M mode
1: 100M mode
113
P0_FDX_LED
115
NC3
Reserved
PHY_MII
Reserved
RMII
MII
RevMII
When Port5 in force mode
0: Half-duplex mode
1: Full-duplex mode
Flow Control in PHY Register 4 bit 10
0: bit value is “1”
1: bit value is “0”
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
20
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
117
NC4
80
EECS
81
EECK
Reserved
Port 5 link/duplex/speed mode in MII/RMII
0: force mode
1: PHY_MDC/PHY_MDIO polling mode
If Port 5 link/duplex/speed mode in RevMII mode,
Port 5 always in force mode
When Port 4 link/duplex/speed mode in MII/RMII
0: force mode
1: PHY_MDC/PHY_MDIO polling mode
When Port 4 link/duplex/speed mode in RevMII mode,
Port 4 always in force mode
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
21
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4. Control and Status Register Set
The DM8606C/DM8606CI implements several control and status registers (CSRs), which can be accessed by the host SMI
interface via SMI_CK and SMI_DIO pins. The serial format of host SMI can be referenced in Section 6.2. The absolute
address in the following register table is the 10-bit R9~R0 field in the SMI format. For easy to understanding, the 10-bit
absolute address can be divided to 5-bit PHY address plus 5-bit register address like used in general MII serial format. All
CSRs are set to their default values by hardware or software reset unless specified
Register table
Register
name
PHY
address
register
address
P0 PHY Control
P0 PHY Status
P0 PHY ID 1
P0 PHY ID 2
P0 PHY Auto-N Advertisement
P0 PHY Auto-N Link Partner Ability
P0 PHY Auto-N Expansion
P0 PHY Standard Reserved
P0 PHY Vendor Registers
Port 1 PHY Registers
Port 2 PHY Registers
Port 3 PHY Registers
Port 4 PHY Registers
Port 5 External PHY Registers
P0 Port Status
P0 Basic Control 0
P0 Basic Control 1
P0 Block Contrl 0
P0 Block Contrl 1
P0 Bandwidth Control
P0 VLAN Tag Infomation
P0 Priority & VLAN Control
P0 Security Control
P0 Spanning Tree state Control
P0 Memory Configuration
P0 Discard packet limitation
Port 1 Registers
Port 2 Registers
Port 3 Registers
Port 4 Registers
Port 5 Registers
Switch Status
Switch Reset
02H
02H
02H
02H
02H
02H
02H
02H
02H
03H
04H
05H
06H
07H
08H
08H
08H
08H
08H
08H
08H
08H
08H
08H
08H
08H
09H
0AH
0BH
0CH
0DH
10H
10H
00H
01H
02H
03H
04H
05H
06H
07H~0FH
10H~1FH
00H~1FH
00H~1FH
00H~1FH
00H~1FH
00H~1FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
10H~1FH
10H~1FH
10H~1FH
10H~1FH
10H~1FH
10H
11H
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
absolute
address
040H
041H
042H
043H
044H
045H
046H
047H~04FH
050H~05FH
060H~07FH
080H~09FH
0A0H~0BFH
0C0H~0DFH
0E0H~0FFH
110H
111H
112H
113H
114H
115H
116H
117H
118H
119H
11AH
11BH
130H~14FH
150H~16FH
170H~18FH
190H~1AFH
1B0H~1CFH
210H
211H
22
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
Switch Control
CPU Port & Mirror Control
Special Tag Ether-Type
Global Learning & Aging Control
VLAN Priority Map
TOS Priority Map 0~7
MIB Counter Disable
MIB Counter Control
MIB Counter Data Low
MIB Counter Data High
QinQ TPID
VLAN Mode & Rule Control
VLAN Table - Valid Control
VLAN Table - ID_0H~FH
VLAN Table - MEMBER_0H~FH
VLAN Table - Priority Enable
VLAN Table - Priority Replace Enable
VLAN Table - STP Index Enable
VLAN Table - Misc_0~7
Snooping Control 0
Snooping Control 1
Address Table Control & Status
Address Table Data 0~4
Vendor ID
Product ID
Chip Revision
Port 4 MAC Control
Port 5 MAC Control
LED Control
Interrupt Status Register
Interrupt Mask & Control Register
EEPROM Control & Address
EEPROM Data
Monitor Register 1 ~ 3
System Clock Select Register
Serial Bus Error Check Registers
Virtual PHY Control Register
PHY Control Test
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
10H
10H
10H
10H
10H
10H
11H
11H
11H
11H
11H
11H
11H
12H
13H
14H
14H
14H
14H
14H
14H
15H
15H
18H
18H
18H
18H
18H
18H
18H
18H
18H
18H
18H
19H
19H
19H
19H
12H
13H
14H
15H
17H
18H~1FH
10H
11H
12H
13H
1DH
1EH
1FH
10H~1FH
10H~1FH
10H
11H
12H
13H~1AH
1BH
1CH
10H
11H~15H
10H
11H
12H
14H
15H
17H
18H
19H
1AH
1BH
1CH~1EH
18H
19H~1AH
1DH
1EH
212H
213H
214H
215H
217H
218H~21FH
230H
231H
232H
233H
23DH
23EH
23FH
250H~25FH
270H~27FH
290H
291H
292H
293H~29AH
29BH
29CH
2B0H
2B1H~2B5H
310H
311H
312H
314H
315H
317H
318H
319H
31AH
31BH
31CH~31EH
338H
339H~33AH
33DH
33EH
23
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
Key to Default
In the register description that follows, the default column
takes the form:
<Reset Value>, <Access Type>
Where:
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
?H
Bits set to hex. value
X
No default value
P = power on reset default value
S = software reset, by Reg. 211H bit 1, default value
Y = default value from PHY software reset by per port PHY
register 0 bit 15
E = default value from EEPROM setting
T = default value from strap pin
<Access Type>:
RO = Read only
RW = Read/Write
R/C = Read and Clear
RW/C1=Read/Write and Cleared by write 1
WO = Write only
R/WC = Read/Write and auto-cleared
Reserved bits should be written with 0.
Reserved bits are undefined on read access.
4.1 Port0~Port4 PHY Registers (000H~0FFH)
4.1.1 Basic Mode Control Register (BMCR) (040H,060H,080H,0A0H,0C0H)
Bit
Bit Name
Default Description
15
Reset
P0,
Reset
RW/SC 1: Software reset
0: Normal operation
This bit sets the status and controls the PHY registers to their default
states. This bit, which is self-clearing, will keep returning a value of one until
the reset process is completed
14
Loopback
PY0, RW Loopback
Loop-back control register
1: Loop-back enabled
0: Normal operation
When in 100Mbps operation mode, setting this bit may cause the
descrambler to lose synchronization and produce a 720ms "dead time"
before any valid data appears at the MII receive outputs
13
Speed
PY1, RW Speed Select
selection
1: 100Mbps
0: 10Mbps
Link speed may be selected either by this bit or by auto-negotiation. When
auto-negotiation is enabled (bit 12 is set), this bit will return auto-negotiation
selected medium type
12
Auto-negotia PT1, RW Auto-negotiation Enable
tion enable
1: Auto-negotiation is enabled, bit 8 and 13 will be in auto-negotiation
status
0: Auto-negotiation is disabled
11
Power down PY0, RW Power Down
While in the power-down state, the PHY should respond to management
transactions. During the transition to power-down state and while in the
power-down state, the PHY should not generate spurious signals on the MII
1: Power down
0: Normal operation
10
Isolate
PY0,RW Isolate
1: Reserved in DM8606C/DM8606CI
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
24
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
9
8
7
6:0
0: Normal operation
Restart
PY0,RW/S Restart Auto-negotiation
Auto-negotia
C
1: Restart auto-negotiation. Re-initiates the auto-negotiation process.
tion
When auto-negotiation is disabled (bit 12 of this register cleared), this bit
has no function and it should be cleared. This bit is self-clearing and it
will keep returning to a value of 1 until auto-negotiation is initiated by the
DM8606C/DM8606CI. The operation of the auto-negotiation process will
not be affected by the management entity that clears this bit
0 : Normal operation
Duplex mode PY1,RW Duplex Mode
1: Full duplex operation. Duplex selection is allowed when Auto-negotiation
is disabled (bit 12 of this register is cleared). With auto-negotiation
enabled, this bit reflects the duplex capability selected by
auto-negotiation
0: Normal operation
Collision test PY0,RW Collision Test
1: Reserved in DM8606C/DM8606CI
0: Normal operation
Reserved
P0H,RO Reserved
Read as 0, ignore on write
4.1.2 Basic Mode Status Register (BMSR) (041H,061H,081H,0A1H,0C1H)
Bit
Bit Name
Default Description
15
100BASE-T4 P0,RO 100BASE-T4 Capable
1: perform in 100BASE-T4 mode
0: not able to perform in 100BASE-T4 mode
14
100BASE-T
P1,RO 100BASE-TX Full Duplex Capable
X
1: perform 100BASE-TX in full duplex mode
full-duplex
0: not able to perform 100BASE-TX in full duplex mode
P1,RO 100BASE-TX Half Duplex Capable
13
100BASE-T
1: perform 100BASE-TX in half duplex mode
X
0: not able to perform 100BASE-TX in half duplex mode
half-duplex
12
10BASE-T
P1,RO 10BASE-T Full Duplex Capable
full-duplex
1: perform 10BASE-T in full duplex mode
0: not able to perform 10BASE-TX in full duplex mode
11
10BASE-T
P1,RO 10BASE-T Half Duplex Capable
half-duplex
1: perform 10BASE-T in half duplex mode
0: not able to perform 10BASE-T in half duplex mode
10:7
Reserved
P0,RO Reserved
Read as 0, ignore on write
6
MF preamble PY1,RO MII Frame Preamble Suppression
suppression
1: PHY will accept management frames with preamble suppressed
0: PHY will not accept management frames with preamble suppressed
5
Auto-negotia PY0,RO Auto-negotiation Complete
tion
1: Auto-negotiation process completed
Complete
0: Auto-negotiation process not completed
4
Remote fault PY0, RO Remote Fault
1: Remote fault condition detected (cleared on read or by a chip reset).
This bit will set after the RF bit in the ANLPAR (bit 13, register address
05) is set
Preliminary
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25
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
3
2
Auto-negotia
tion
ability
Link status
1
Jabber
detect
0
Extended
capability
0: No remote fault condition detected
Auto Configuration Ability
1: perform auto-negotiation
0: not able to perform auto-negotiation
PY0,RO Link Status
1: Valid link is established (for either 10Mbps or 100Mbps operation)
0: Link is not established
The link status bit is implemented with a latching function, so that the
occurrence of a link failure condition causes the link status bit to be cleared
and remain cleared until it is read via the management interface
PY0, RO Jabber Detect
1: Jabber condition detected
0: No jabber
This bit works only in 10Mbps mode
P1,RO Extended Capability
1: Extended register capable
0: Basic register capable only
P1,RO
4.1.3 PHY ID Identifier Register #1 (PHYID1) (042H,062H,082H,0A2H,0C2H)
The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM8606C/DM8606CI. The
Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number,
and a model revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E.
Bit
Bit Name
Default Description
15:0
OUI_MSB PE0181H, OUI Most Significant Bits
RO
This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of this
register respectively. The most significant two bits of the OUI are ignored
(the IEEE standard refers to these as bit 1 and 2)
4.1.4 PHY ID Identifier Register #2 (PHYID2) (043H,063H,083H,0A3H,0C3H)
Bit
Bit Name
Default Description
15:10
OUI_LSB PE101110, OUI Least Significant Bits
RO
Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this register
respectively
9:4
VNDR_MDL PE001011, Vendor Model Number
RO
Five bits of vendor model number mapped to bit 9 to 4 (most significant bit
to bit 9)
3:0
MDL_REV
PE0001, Model Revision Number
RO
Five bits of vendor model revision number mapped to bit 3 to 0 (most
significant bit to bit 4)
4.1.5 Auto-Nego. Advertised Register (ANAR) (044H,064H,084H,0A4H,0C4H)
This register contains the advertised abilities of this port as they will be transmitted to its link partner during
Auto-negotiation.
Bit
Bit Name
Default
Description
15
NP
P0,RO Next page Indication
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26
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
14
ACK
PY0,RO
13
RF
PY0,RW
12:11
Reserved
X,RW
10
FCS
PT0,RW
9
T4
P0,RO
8
TX_FDX
PY1, RW
7
TX_HDX
PY1, RW
6
10_FDX
PY1, RW
5
10_HDX
PY1, RW
4:0
Selector
PY00001,
RW
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
1: Next page available
0: No next page available
The DM8606C/DM8606CI has no next page, so this bit is permanently set
to 0
Acknowledge
1: Link partner ability data reception acknowledged
0: Not acknowledged
The DM8606C/DM8606CI's auto-negotiation state machine will
automatically control this bit in the outgoing FLP bursts and set it at the
appropriate time during the auto-negotiation process. Software should not
attempt to write to this bit.
Remote Fault
1: Local device senses a fault condition
0: No fault detected
Reserved
Write as 0, ignore on read
Flow Control Support
1: Controller chip supports flow control ability
0: Controller chip doesn’t support flow control ability
100BASE-T4 Support
1: 100BASE-T4 is supported by the local device
0: 100BASE-T4 is not supported
The DM8606C/DM8606CI does not support 100BASE-T4 so this bit is
permanently set to 0
100BASE-TX Full Duplex Support
1: 100BASE-TX full duplex is supported by the local device
0: 100BASE-TX full duplex is not supported
100BASE-TX Support
1: 100BASE-TX half duplex is supported by the local device
0: 100BASE-TX half duplex is not supported
10BASE-T Full Duplex Support
1: 10BASE-T full duplex is supported by the local device
0: 10BASE-T full duplex is not supported
10BASE-T Support
1: 10BASE-T half duplex is supported by the local device
0: 10BASE-T half duplex is not supported
Protocol Selection Bits
These bits contain the binary encoded protocol selector supported by this
node
<00001> indicates that this device supports IEEE 802.3 CSMA/CD
27
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.1.6 Auto-Nego. Partner Ability Register (ANPAR) (045H,065H,085H,0A5H,0C5H)
This register contains the advertised abilities of the link partner when received during Auto-negotiation.
Bit
Bit Name
Default
Description
15
NP
PY0, RO Next Page Indication
1:Link partner, next page available
0: Link partner, no next page available
14
ACK
PY0, RO Acknowledge
1: Link partner ability data reception acknowledged
0: Not acknowledged
The DM8606C/DM8606CI's auto-negotiation state machine will
automatically control this bit from the incoming FLP bursts. Software should
not attempt to write to this bit
13
RF
PY0, RO Remote Fault
1: Remote fault indicated by link partner
0: No remote fault indicated by link partner
12:11
Reserved
PY0, RO Reserved
Read as 0, ignore on write
10
FCS
PY0, RO Flow Control Support
1: Controller chip supports flow control ability by link partner
0: Controller chip doesn’t support flow control ability by link partner
9
T4
PY0, RO 100BASE-T4 Support
1:100BASE-T4 is supported by the link partner
0: 100BASE-T4 is not supported by the link partner
8
TX_FDX
PY0, RO 100BASE-TX Full Duplex Support
1:100BASE-TX full duplex is supported by the link partner
0: 100BASE-TX full duplex is not supported by the link partner
7
TX_HDX
PY0, RO 100BASE-TX Support
1: 100BASE-TX half duplex is supported by the link partner
0: 100BASE-TX half duplex is not supported by the link partner
6
10_FDX
PY0, RO 10BASE-T Full Duplex Support
1: 10BASE-T full duplex is supported by the link partner
0: 10BASE-T full duplex is not supported by the link partner
5
10_HDX
PY0, RO 10BASE-T Support
1: 10BASE-T half duplex is supported by the link partner
0: 10BASE-T half duplex is not supported by the link partner
4:0
Selector
PY00000, Protocol Selection Bits
RO
Link partner’s binary encoded protocol selector
Preliminary
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November 22, 2012
28
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.1.7 Auto-Nego. Expansion Register (ANER) (046H,066H,086H,0A6H,0C6H)
Bit
Bit Name
Default
Description
15:5
Reserved
P0,RO Reserved
Read as 0, ignore on write
4
PDF
PY0,RO Local Device Parallel Detection Fault
1: A fault detected via parallel detection function.
0: No fault detected via parallel detection function
3
LP_NP_EN
PY0,RO Link Partner Next Page Able
1: Link partner, next page available
0: Link partner, no next page
2
NP_ABLE
P0,RO Local Device Next Page Able
1: this port next page available
0: this port no next page
DM9161C does not support this function, so this bit is always 0
1
PAGE_RX
PY0,RO New Page Received
A new link code word page received. This bit will be automatically cleared
when the register (register 6) is read by management
0
LP_AN_EN
PY0,RO Link Partner Auto-negotiation Able
1: the link partner supports Auto-negotiation
0: the link partner do not support Auto-negotiation
4.1.8 Specified Control 1 Register (SC1R) (050H,070H,090H,0B0H,0D0H)
Bit
Bit Name
Default
Description
15
BP_4B5B
PY0,RW Bypass 4B5B Encoding and 5B4B Decoding
1: 4B5B encoder and 5B4B decoder function bypassed
0: Normal 4B5B and 5B4B operation
14
BP_SCR
PY0, RW Bypass Scrambler/Descrambler Function
1: Scrambler and descrambler function bypassed
0: Normal scrambler and descrambler operation
13
BP_ALIGN PY0, RW Bypass Symbol Alignment Function
1: Receive functions (descrambler, symbol alignment and symbol decoding
functions) bypassed. Transmit functions (symbol encoder and scrambler)
bypassed
0: Normal operation
12:11
Reserved
PY0, RW Reserved
10
TX
PY1, RW 100BASE-TX Mode Control
1: 100BASE-TX operation
0: 100BASE-FX operation (Fiber mode)
9:5
Reserved
PY0, RW Reserved
4
Reserved
PY1, RW Reserved
3
Reserved
PY0, RW Reserved
2
Reserved
PY1, RW Reserved
1:0
Reserved
PY0, RW Reserved
Preliminary
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29
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.1.9 Specified Control 2 Register (SC2R) (054H,074H,094H,0B4H,0D4H)
Bit
Bit Name
Default Description
15:12 RESERVED PY0,RW Reserved
11
PREAMBLEX PY0,RW Preamble Saving Control
1: 10M TX preamble bit count is normal.
0: when bit 10 is set, the 10M TX preamble count is reduced
When bit 11 of per port PHY register 1DH is set, 12-bit preamble bit is
reduced; otherwise 22-bit preamble bit is reduced.
10
TX10M_PWR PY0,RW 10M TX Power Saving Control
1: enable 10M TX power saving
0: disable 10M TX power saving
9
NWAY_PWR PY0,RW N-Way Power Saving Control
1: disable N-Way power saving
0: enable N-Way power saving
8
Reserved
P0, RO Reserved
Read as 0, ignore on write
7
PYX,RO The polarity of MDI/MDIX value
MDIX_CNTL
1: MDIX mode
0: MDI mode
6
AutoNeg_dpbk PY0,RW Auto-negotiation Loopback
1: test internal digital auto-negotiation Loopback
0: normal.
5
Mdix_fix Value
PY0, MDIX_CNTL force value:
RW
When MDIX_DOWN = 1, MDIX_CNTL value depend on the register value.
4
Mdix_down PY0,RW MDIX Down
Manual force MDI/MDIX.
1: Disable HP Auto-MDIX , MDIX_CNTL value depend on bit 5
0: Enable HP Auto-MDIX
3:0
Reserved
PY0,RW Reserved
4.1.10 Power Saving Control Register (PSCR) (05DH,07DH,09DH,0BDH,0DDH)
Bit
Bit Name
Default Description
15:12 RESERVED
P0,RO Reserved
11
PREAMBLEX PY0,RW Preamble Saving Control
When bit 10 of per port PHY register 14H is cleared and bit 11 of
Per port PHY register 14H is set, the 10M TX preamble count is reduced.
1: 10-bit preamble bit is reduced.
0: 20-bit preamble bits is reduced.
10
RESERVED PY0,RW Reserved
9
TX_PWR
PY0.RW TX Power Saving Control Disabled
1: disable TX driving power saving function
0: when cable is unconnected with link partner, the driving current of
transmit is reduced for power saving.
8:0
RESERVED
P0,RO Reserved
Preliminary
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November 22, 2012
30
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.2 Switch Per-Port Registers (100H~1FFH)
4.2.1 Per Port Status Data Register (110H,130H,150H,170H,190H,1B0H)
Bit
Name
ROM
Default
Description
15:5
RESERVED
--P0,RO
Reserved
LP_FCS
--P0,RO
Link Partner Flow Control Enable Status
4
This bit is same as bit 10 of per port PHY register 15H.
3:2
SPEED
--P0,RO
PHY Speed Status
00: 10Mbps
01: 100Mbps
1X: Reserved
1
FDX
--P0,RO
PHY Duplex Status
0: Half-duplex
1: Full-duplex
0
LINK
--P0,RO
PHY Link Status
0: Link fail
1: Link OK
4.2.2 Per Port Basic Control 0 Register (111H,131H,151H,171H,191H,1B1H)
Bit
Name
ROM
Default
Description
15
RESERVED
--P0,RO
Reserved
PSE0,RW Unplug Clear Address Enable
14
UPLG_CLS
128[14]
Enable to automatically clear address record
14414]
in address table after unplug
160[14]
0: Disable, retaining address record
176[14]
1: Enable, clearing address record
192[14]
208[14]
PSE0,RW Address Table Aging
13
AGE_DIS
128[13]
0: Age function is enabled
144[13]
1: Age function is disabled
160[13]
176[13]
192[13]
208[13]
PSE0,RW Address Learning Disabled
12
ADLRN_DIS
128[12]
0: Source address (SMAC) learning function is enabled
144[12]
1:The SMAC field of packet will not be learned to address
160[12]
table.
176[12]
192[12]
208[12]
PSE0,RW Maximum Pause Packet from Link Partner
11
DIS_PAUSE
128[11]
0: Always care pause packet from link partner
144[11]
1: Pause packet is bypassed after 7 continued pause
160[11]
packet from link partner
176[11]
192[11]
208[11]
Preliminary
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31
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
10
9
RESERVED
HOB_DIS
--128[9]
144[9]
160[9]
176[9]
192[9]
208[9]
P0,RO
PSE0,RW
8
LOOPBACK
---
PS0,RW
7
PAUSE_CN
PSE0,RW
6
PARTI_EN
5
FCBP_DIS
4
FC3X_DIS
3:2
MAX_PKLN
1
RX_DIS
128[7]
144[7]
160[7]
176[7]
192[7]
208[7]
128[6]
144[6]
160[6]
176[6]
192[6]
208[6]
128[5]
144[5]
160[5]
176[5]
192[5]
208[5]
128[4]
144[4]
160[4]
176[4]
192[4]
208[4]
128[3:2]
144[3:2]
160[3:2]
176[3:2]
192[3:2]
208[3:2]
---
0
TX_DIS
---
PS0,RW
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
Reserved
Head-of-Line Blocking Prevent Control
0: Disable
1: Enable
Loop-Back Mode
0: Disable
1: The transmitted packets will be forward to this port itself.
Send PAUSE Continuously
If buffer congestion occur on full duplex,
switch will send PAUSE frames:
0: Up to 8-times.
1: Continuously until alleviation.
PSE0,RW
Partition Detection Enable
0: Disable
1: Enable
PSE0,RW
Back pressure Flow-Control in half duplex disable
0: Back pressure is enabled
1: Back pressure is disabled
PSE0,RW
IEEE 802.3x Flow control in full duplex mode
0: 802.3x flow-control is enabled
1: 802.3x flow-control is disabled
PSE0,RW
Max accept packet length by RX from this port
00: 1536-bytes
01: 1552-bytes
10: 1800-bytes
11: 2032-bytes
PS0,RW
Receive Disable
0: Receive is enabled
1: All received packets from this port are discarded.
Transmit Disable
0: Transmit function is enabled
1: All packets forward to this port are discarded.
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DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.2.3 Per Port Basic Control 1 Register (112H,132H,152H,172H,192H,1B2H)
Bit
Name
ROM
Default
Description
PSE0,RW RX Packet Control
15
NO_DIS_RX
129[15]
When bandwidth of RX Packets reach Ingress bandwidth
145[15]
control value:
161[15]
0: Discard RX packets
177[15]
1: Retain RX packets in memory
193[15]
209[15]
PSE0,RW Bandwidth Control Mode
14
BANDWIDTH
129[14]
0: Separated mode. Rate control of ingress
145[14]
and egress is separate.
161[14]
1: Combined mode. Combining the rate of
177[14]
ingress and egress
193[14]
209[14]
PSE0,RW Storm Control for Un-learned Unicast Packets
13
STORM_UP
129[13]
0: Disable
145[13]
1: Enable; treat the un-learned uni-cast packets as
161[13]
broadcast storm packets
177[13]
193[13]
209[13]
PSE0,RW Storm Control for Multicast Packets
12
STORM_MP
129[12]
0: Disable
145[12]
1: Enable; treat the multicast packets as broadcast storm
161[12]
packets
177[12]
193[12]
209[12]
PSE0,RW Don’t Mirror Broadcast/Multicast Packets
129[11]
11
MIRR_DBP
145[11]
If mirror function is enabled
161[11]
0: Broadcast/Multicast would be mirrored
177[11]
1: Broadcast/Multicast would not be mirrored
193[11]
209[11]
PSE0,RW Specific MAC Filtering Control Enable
10
FIR_SPEC
129[10]
Enable to filter packet with source or destination MAC
145[10]
address that is specified in the address table.
161[10]
0: Disable
177[10]
1: Enable
193[10]
209[10]
PSE0,RW Filter Packets with Un-learned Unicast SMAC
9
FIR_UUSID
129[9]
0: Disable
145[9]
1: Enable
1619]
177[9]
193[9]
209[9]
PSE0,RW Filter Packets with Un-learned Unicast DMAC
8
FIR_UUDID
129[8]
0: Disable
145[8]
1: Enable
161[8]
177[8]
193[8]
209[8]
Preliminary
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November 22, 2012
33
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
7
FIR_UMDID
6
FIR_BDMAC
5
FIR_MDMAC
4
FIR_MSMAC
3:2
MIRR_TX
1:0
MIRR_RX
129[7]
145[7]
161[7]
177[7]
193[7]
209[7]
129[6]
145[6]
161[6]
177[6]
193[6]
209[6]
129[5]
145[5]
161[5]
177[5]
193[5]
209[5]
129[4]
145[4]
161[4]
177[4]
193[4]
209[4]
129[3:2]
145[3:2]
1613:2]
177[3:2]
193[3:2]
209[3:2]
129[1:0]
145[1:0]
161[1:0]
177[1:0]
193[1:0]
209[1:0]
Preliminary
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November 22, 2012
PSE0,RW
Filter Packets with Un-learned Multicast DMAC
0: Disable
1: Enable
PSE0,RW
Filter Packets with Broadcast DMAC
0: Disable
1: Enable
PSE0,RW
Filter Packets with Multicast DMAC
0: Disable
1: Enable
PSE0,RW
Filter Packets with Multicast SMAC
0: Disable
1: Enable
PSE0,RW
Port TX Mirror Option
TX Packet is mirrored to sniffer port.
00: TX mirror function is disabled
01: All transmitted packets is mirrored
10: Packet is mirrored if
(DMAC search result is hit & ATB_MIRR==1
& Transmit from this port)
11: Packet is mirrored if
(SMAC search result is hit & ATB_MIRR==1
& Transmit from this port)
Port RX Mirror Option
RX Packet is mirrored to sniffer port.
00: RX mirror function is disabled
01: All received packets is mirrored
10: Packet is mirrored if
(DMAC search result is hit & ATB_MIRR==1
& Receive from this port)
11: Packet is mirrored if
(SMAC search result is hit & ATB_MIRR==1
& Receive from this port)
PSE0,RW
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DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.2.4 Per Port Block Control 0 Register (113H,133H,153H,173H,193H,1B3H)
Bit
Name
ROM
Default
Description
15:14 RESERVED
--P0,RO
Reserved
13:8
BLK_MP
130[13:8]
PSE0,RW Block Packet with Multicast DMAC
146[13:8]
[13]: Block such packet forward to port 5
162[13:8]
[12]: Block such packet forward to port 4
178[13:8]
[11]: Block such packet forward to port 3
194[13:8]
[10]: Block such packet forward to port 2
210[13:8]
[09]: Block such packet forward to port 1
[08]: Block such packet forward to port 0
7:6
RESERVED
--P0,RO
Reserved
PSE0,RW Block Packet with Broadcast DMAC
5:0
BLK_BP
130[5:0]
[05]: Block such packet forward to port 5
146[5:0]
[04]: Block such packet forward to port 4
162[5:0]
[03]: Block such packet forward to port 3
178[5:0]
[02]: Block such packet forward to port 2
194[5:0]
[01]: Block such packet forward to port 1
210[5:0]
[00]: Block such packet forward to port 0
4.2.5 Per Port Block Control 1 Register (114H,134H,154H,174H,194H,1B4H)
Bit
Name
ROM
Default
Description
15:14 RESERVED
--P0,RO
Reserved
PSE0,RW Block Packet with Unlearned Unicast DMAC
13:8
BLK_UKP
131[13:8]
[13]: Block such packet forward to port 5
147[13:8]
[12]: Block such packet forward to port 4
163[13:8]
[11]: Block such packet forward to port 3
179[13:8]
[10]: Block such packet forward to port 2
195[13:8]
[09]: Block such packet forward to port 1
211[13:8]
[08]: Block such packet forward to port 0
7:6
RESERVED
--P0,RO
Reserved
PSE0,RW Block Packet with Unicast DMAC
5:0
BLK_UP
131[5:0]
The received unicast packets are not forward to the
147[5:0]
assigned ports.
163[5:0]
Note that the assigned port definition: bit 0 for port 0, bit 1
179[5:0]
for port 1, bit 2 for port 2, and so on
195[5:0]
[05]: Block such packet forward to port 5
211[5:0]
[04]: Block such packet forward to port 4
[03]: Block such packet forward to port 3
[02]: Block such packet forward to port 2
[01]: Block such packet forward to port 1
[00]: Block such packet forward to port 0
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
35
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.2.6 Per Port Bandwidth Control Register (115H,135H,155H,175H,195H,1B5H)
Bit
Name
ROM
Default
Description
15:12
INGRESS
132[15:12] PSE0,RW Ingress Rate Control (Separated mode)
148[15:12]
These bits define the bandwidth threshold that received
164[15:12]
packets over the threshold are discarded.
180[15:12]
0000: none
0001: 64Kbps
196[15:12]
212[15:12]
0010: 128Kbps
0011: 256Kbps
0100: 512Kbps
0101: 1Mbps
0110: 2Mbps
0111: 4Mbps
1000: 8Mbps
1001: 16Mbps
1010: 32Mbps
1011: 48Mbps
1100: 64Mbps
1101: 72Mbps
1110: 80Mbps
1111: 88Mbps
PSE0,RW Egress Rate Control
11:8
EGRESS
132[11:8]
These bits define the bandwidth threshold that transmitted
148[11:8]
packets over the threshold are discarded.
164[11:8]
0000: none
180[11:8]
0001: 64Kbps
196[11:8]
0010: 128Kbps
212[11:8]
0011: 256Kbps
0100: 512Kbps
0101: 1Mbps
0110: 2Mbps
0111: 4Mbps
1000: 8Mbps
1001: 16Mbps
1010: 32Mbps
1011: 48Mbps
1100: 64Mbps
1101: 72Mbps
1110: 80Mbps
1111: 88Mbps
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
36
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
7:4
BSTH
132[7:4]
148[7:4]
164[7:4]
180[7:4]
196[7:4]
212[7:4]
PSE0,RW
3:0
BW_CTRL
132[3:0]
148[3:0]
164[3:0]
180[3:0]
196[3:0]
212[3:0]
PSE0,RW
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
Broadcast Storm Threshold
These bits define the bandwidth threshold that received
broadcast packets over the threshold are discarded
0000: no broadcast storm control
0001: 8K packets/sec
0010: 16K packets/sec
0011: 64K packets/sec
0100: 5%
0101: 10%
0110: 20%
0111: 30%
1000: 40%
1001: 50%
1010: 60%
1011: 70%
1100: 80%
1101: 90%
111X: no broadcast storm control
Ingress and Egress Rate Control (Combined mode)
Received and Transmitted Bandwidth Control
These bits define the bandwidth threshold that transmitted
or received packets over the threshold are discarded
0000: none
0001: 64Kbps
0010: 128Kbps
0011: 256Kbps
0100: 512Kbps
0101: 1Mbps
0110: 2Mbps
0111: 4Mbps
1000: 8Mbps
1001: 16Mbps
1010: 32Mbps
1011: 48Mbps
1100: 64Mbps
1101: 72Mbps
1110: 80Mbps
1111: 88Mbps
37
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.2.7 Per Port VLAN Tag Infomation Register (116H,136H,156H,176H,196H,1B6H)
Bit
Name
ROM
Default
Description
15:13
PPRI
133[15:13] PSE0,RW Port VLAN Priority
149[15:13]
Used for tag insertion
165[15:13]
18115:13]
197[15:13]
213[15:13]
PSE0,RW Port VLAN CFI
12
PCFI
133[12]
Used for tag insertion
149[12]
165[12]
181[12]
197[12]
213[12]
PSE1,RW Port VLAN Identification
11:0
PVID
133[11:0]
Used for tag insertion and VLAN table
149[11:0]
165[11:0]
181[11:0]
197[11:0]
213[11:0]
4.2.8 Per Port Priority and VLAN Control Register (117H,137H,157H,177H,197H,1B7H)
Bit
Name
ROM
Default
Description
15
RESERVED
--P0,RO
Reserved
PSE0,RW Output Tagging Enable
14
TAG_OUT
134[14]
Force output tagging regardless of VLAN
150[14]
table setting.
166[14]
0: Disable
182[14]
1: Enable
198[14]
214[14]
PSE0,
Filter VLAN Packet
13
FIR_VPKT
134[13]
RW
To filter incoming packet if its port does not exist in VLAN
150[13]
member set
166[13]
0: Disable
182[13]
1: Enable
198[13]
214[13]
PSE0,RW Input Force No Tag
12
UNTAG_IN
134[12]
Assume all received frame are untagged
150[12]
0: Disable
166[12]
1: Enable
182[12]
198[12]
214[12]
11:10 RESERVED
--P0,RO
Reserved
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
38
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
9:8
VLAN_IAC
7
6
RESERVED
PRI_DIS
5
WFQUE
4
TOS_PRI
3
TOS_OFF
2
PRI_OFF
1:0
PB_PQ
134[9:8]
150[9:8]
166[9:8]
182[9:8]
198[9:8]
214[9:8]
PSE0,RW
---
PSE0,RW
134[6]
150[6]
166[6]
182[6]
198[6]
214[6]
134[5]
150[5]
166[5]
182[5]
198[5]
214[5]
134[4]
150[4]
166[4]
182[4]
198[4]
214[4]
134[3]
150[3]
166[3]
182[3]
198[3]
214[3]
134[2]
150[2]
166[2]
182[2]
198[2]
214[2]
134[1:0]
150[1:0]
166[1:0]
182[1:0]
198[1:0]
214[1:0]
PSE0,RW
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
VLAN Ingress Admit Only Control
00: Accept all frames
01: Accept VLAN-tagged frames only
Untagged or priority tagged(VID=0) frames will be
dropped
10: Accept untagged frames only
11: Accept frame's VID equal to ingress PVID
Reserved
Priority Queue Disable
0: Priority Queue is enabled
1: Priority Queue is disabled
PSE0,RW
Priority Scheduling Method
0: Strict (Queue 3 > 2 > 1 > 0).
Always highest priority queue first.
1: Weighted Round-Robin with 8:4:2:1 ratio
PSE0,RW
Priority Classification IP ToS over VLAN
0: Priority Classification base on VLAN
1: Priority Classification base on IP ToS field
PSE0,RW
IP ToS Priority Classification Disable
0: Classification is enabled
1: Classification is disabled
PSE0,RW
VLAN Priority Classification Disable
0: Classification is enabled
1: Classification is disabled
PSE0,RW
Port-based Priority Queue Number
00: Queue 0
01: Queue 1
10: Queue 2
11: Queue 3
39
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.2.9 Per Port Security Control Register (118H,138H,158H,178H,198H,1B8H)
Bit
Name
ROM
Default
Description
15
RESERVED
Reserved
--P0,RO
14:10
MAX_LRN
135[14:10] PSE0,RW Learning Restriction.
151[14:10]
Limited number of learned MAC address
167[14:10]
1~31, 0: Limitless
183[14:10]
199[14:10]
215[14:10]
PSE0,RW Port in Unauthorized State
9
P_UNAUTH
135[9]
0: Port is in authorized state (normal mode).
151[9]
TX/RX and learning capability is enabled.
167[9]
1: Port is in unauthorized state (disable mode).
183[9]
TX/RX and learning capability is disabled.
199[9]
Only EAPoL packet can be forwarded.
215[9]
8:2
RESERVED
--P0,RO
Reserved
PSE0,RW Port Locking Mode
1:0
PLOCK_M
135[1:0]
00: Port Lock is disabled
151[1:0]
01: First Lock
167[1:0]
10: First Link Lock
183[1:0]
11: Assign Lock
199[1:0]
215[1:0]
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
40
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.2.10 Per Port Advanced Control register (119H,139H,159H,179H,199H,1B9H),
Bit
Name
ROM
Default
Description
15:9
RESERVED
--P0,R0
Reserved
PSE,R0
IGMP Snooping Fast Leave Enable
8
FAST_LEAV
136[8]
0: Disable
E
152[8]
1: Enable
168[8]
184[8]
200[8]
216[8]
7:6
5:4
3:2
1:0
RESERVED
RESERVED
RESERVED
STPS0
---------
PS00,RW
PS00,RW
PS00,RW
PS00,RW
Reserved
Reserved
Reserved
STP/RSTP Port State
There are 4 port states for STP supporting, and 3 port
states for RSTP supporting.
00: Forwarding State, The port transmits and receives
packets normally & learning is enabled.
01: Disabled State/Discarding, The port will only forward
the packets that are to and from uP port (span packets)
& learning is disabled.
10: Learning State, The port will only forward the packets
that are to and from uP port (span packets) & leaning
is enabled.
11: Blocking/Listening State, The port will only forward the
packets that are to and from uP port (span packets) &
learning is disabled.
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
41
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.2.11 Per Port Memory Control Register (11AH,13AH,15AH,17AH,19AH,1BAH),
Bit
Name
ROM
Default
Description
15:8
TDRQ_TH
137[15:8]
PSE19H, TDR output queue block threshold value, the block unit is
153[15:8]
RW
“128bytes”. It is used generally when Head-of-Line
169[15:8]
Blocking, per port register 1 bit 19H, is set.
185[15:8]
201[15:8]
217[15:8
7
RESERVED
--P0,RO
Reserved
PSE3AH, Per port receive buffer reserved block size, the block unit is
6:0
RV_BLKSIZ
137[6:0]
RW
“128bytes”.
153[6:0]
Use software to programming this field, the Maximum
169[6:0]
value is 3EH
185[6:0]
201[6:0]
217[6:0]
4.2.12 Per Port Discard Limitation Register (11BH,13BH,15BH,17BH,19BH,1BBH)
Bit
Name
ROM
Default
Description
15
RESERVED
--P0,R0
Reserved
PSE20H, Per port receive buffer reserved block high water
14:8
RV_HI_TH
138[14:8]
RW
threshold, the block unit is “128bytes”
154[14:8]
170[14:8]
186[14:8]
202[14:8]
218[14:8]
7
6:0
RESERVED
RV_LO_TH
--138[6:0]
154[6:0]
170[6:0]
186[6:0]
202[6:0]
218[6:0]
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
P0,R0
PSE0,RW
Reserved
Per port receive buffer reserved block Low water
threshold, the block unit is “128bytes”
42
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.3 Switch Engine Registers (200H~2FFH)
4.3.1 Switch Status Register (210H)
Bit
Name
ROM
15:4
RESERVED
--3
RV_BUF_ST
---
Default
RO
RO
2
1
RESERVED
BIST_1
-----
RO
RO
0
BIST_0
---
RO
4.3.2 Switch Reset Register (211H)
Bit
Name
ROM
15:3
RESERVED
--2
PD_ANLG
---
Default
P0,RO
P0,RW
1
RST_ANLG
---
P0,R/WC
0
RST_SW
---
P0,R/WC
4.3.3 Switch Control Register Register (212H)
Bit
Name
ROM
Default
15:12 RESERVED
18[15]
P0,RO
11:8
TRUNK_EN
18[11:8]
PSE0,
RW
7:5
4
RESERVED
NO_REG
--18[4]
P0,R0
PE0,RW
3
RESERVED
18[3]
PE0,RW
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
Description
Reserved
Receive Buffer Status
0: No packet in buffer
1: There are packets in buffer
Reserved
Memory 1 BIST Status for address table memory
0:Pass
1:Fail
Memory 0 BIST Status for receive packet memory
0:Pass
1:Fail
Description
Reserved
Power down all analog PHY
0: Power On
1: Power Down
Analog PHY Core Reset
Write 1 to reset, and auto-clear after 10us
Switch Core Reset
Write 1 to reset, and auto-clear after 10us
Description
Reserved
Trunk Enable {P3,P2,P1,P0}
[11] 1: Port3 trunk is enabled
0: Port3 trunk is disabled
[10] 1: Port2 trunk is enabled
0: Port2 trunk is disabled
[9] 1: Port1 trunk is enabled
0: Port1 trunk is disabled
[8] 1: Port0 trunk is enabled
0: Port0 trunk is disabled
Reserved
NO Initial of Register in Software Reset
0: initial of registers in software reset command
1: no initial of register in software reset command.
Reserved for testing only
Clear to 0 in application
43
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
3
AUTO_RST
18[3]
PE0,RW
2
DIS_CRCC
18[2]
PSE0,RW
1:0
RESERVED
---
P0,RO
4.3.4 CPU Port & Mirror Control Register (213H)
Bit
Name
ROM
Default
15:11 RESERVED
---P0,RO
10
MIRR_PAIR
19[10]
PSE0,RW
7
STAG_TXE
19[7]
PSE0,RW
6
STAG_RXE
19[6]
PSE0,RW
5:3
SNF_PORT
19[5:3]
PSE0,RW
2:0
CPU_PORT
19[2:0]
PE5,RW
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
Disable RV Buffer Count Checking
0: auto switch reset if per port’s RV buffer error
RV buffer count > 31 and not changed for 40ms.
1: disable checking (for testing only)
CRC Checking Disable
0: CRC checking is enabled
1: CRC checking is disabled
Reserved
Description
Reserved
Mirror RX/TX Pair Mode Enable
0: Disable
1: Enable
Special Tag Transmit Enable
0: Doesn't insert the Special Tag for outgoing packets
1: Identifies the Special Tag for outgoing packets
Special Tag Receive Enable
0: Doesn't identify the Special Tag for incoming packets
1: Identifies the Special Tag for incoming packets
Sniffer Port Number
000: Sniffer Port is Port 0
001: Sniffer Port is Port 1
010: Sniffer Port is Port 2
011: Sniffer Port is Port 3
100: Sniffer Port is Port 4
101: Sniffer Port is Port 5
110: Reserved
111: Reserved
Select CPU Port Number
000: Port 0
001: Port 1
010: Port 2
011: Port 3
100: Port 4
101: Port 5
110: Port 5
111: Port 5
44
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.3.5 Special Tag Ether-Type Register (214H)
Bit
Name
ROM
Default
15:0
STAG_ETH
20[15:0]
PSE,8606
H,RW
Description
Special Tag Ether-Type
4.3.6 Global Learning & Aging Control Register (215H)
Bit
Name
ROM
Default
Description
15:6
RESERVED
Reserved
--P0,RO
5
LRN_PAUS
21[3]
PSE0,RW Learn PAUSE Frame
E
0: Disable
1: Enable
4
LRN_VLAN
21[2]
PSE0,RW Address Learning Consider VLAN Member
0: Address learning despite VLAN member
1: Address learning is disable, if incoming port doesn’t
exist in its member set.
3
ATB_KEY
21[1]
PSE0,RW Address Table Hash Key
0: Use (DMAC) for searching and (SMAC) for learning
1: Use (DMAC+FID) for searching and (SMAC+FID) for
learning Note: Must clear address table after this bit is
changed.
2
ATB_MODE
21[0]
PSE0,RW Address Table Mode
0: Mixed mode, 2K address table for unicast or multicast
1: Separated mode, 1K for unicast and 1K for multicast
Note: Must clear address table after this bit is changed.
1:0
AGE_TIME
21[1:0]
PSE0,RW Aging Time Value
00: 512 sec ±256 sec
01: 256 sec ±128 sec
10: 128 sec ± 64 sec
11: 64 sec ± 32 sec
4.3.7 VLAN Priority Map Register (217H)
Bit
Name
ROM
Default
15:14
VLAN_PM7
28[15:14]
PSE3,RW
13:12
VLAN_PM6
28[13:12]
PSE3,RW
11:10
VLAN_PM5
28[11:10]
PSE2,RW
9:8
VLAN_PM4
28[9:8]
PSE2,RW
7:6
VLAN_PM3
28[7:6]
PSE1,RW
5:4
VLAN_PM2
28[5:4]
PSE1,RW
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
Description
When VLAN tag priority value = 07H,
the VLAN priority is mapping to these two bits.
When VLAN tag priority value = 06H,
the VLAN priority is mapping to these two bits.
When VLAN tag priority value = 05H,
the VLAN priority is mapping to these two bits.
When VLAN tag priority value = 04H,
the VLAN priority is mapping to these two bits.
When VLAN tag priority value = 03H,
the VLAN priority is mapping to these two bits.
When VLAN tag priority value = 02H,
the VLAN priority is mapping to these two bits.
45
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
3:2
VLAN_PM1
28[3:2]
PSE0,RW
1:0
VLAN_PM0
28[1:0]
PSE0,RW
When VLAN tag priority value = 01H,
the VLAN priority is mapping to these two bits.
When VLAN tag priority value = 00H,
the VLAN priority is mapping to these two bits.
4.3.8 TOS Priority Map 0 Register (218H)
If register 23EH bit 7 is set, for register 218H decode full TOS[5:0];
Otherwise decode TOS[2:0].
For registers 219H ~ 21FH full TOS[5:0] is decoded.
Bit
Name
ROM
Default
Description
15:14
TOS_PM07
29[15:14]
PSE0,RW TOS value = 07H
13:12
TOS_PM06
29[13:12]
PSE0,RW TOS value = 06H
11:10
TOS_PM05
29[11:10]
PSE0,RW TOS value = 05H
9:8
TOS_PM04
29[9:8]
PSE0,RW TOS value = 04H
7:6
TOS_PM03
29[7:6]
PSE0,RW TOS value = 03H
5:4
TOS_PM02
29[5:4]
PSE0,RW TOS value = 02H
3:2
TOS_PM01
29[3:2]
PSE0,RW TOS value = 01H
1:0
TOS_PM00
29[1:0]
PSE0,RW TOS value = 00H
4.3.9 TOS Priority Map 1 Register (219H)
Bit
Name
ROM
Default
15:14 TOS_PM0F
30[15:14]
PSE0,RW
13:12 TOS_PM0E
30[13:12]
PSE0,RW
11:10 TOS_PM0D
30[11:10]
PSE0,RW
9:8
TOS_PM0C
30[9:8]
PSE0,RW
7:6
TOS_PM0B
30[7:6]
PSE0,RW
5:4
TOS_PM0A
30[5:4]
PSE0,RW
3:2
TOS_PM09
30[3:2]
PSE0,RW
1:0
TOS_PM08
30[1:0]
PSE0,RW
Description
TOS value = 0FH
TOS value = 0EH
TOS value = 0DH
TOS value = 0CH
TOS value = 0BH
TOS value = 0AH
TOS value = 09H
TOS value = 08H
4.3.10 TOS Priority Map 2 Register (21AH)
Bit
Name
ROM
Default
15:14
TOS_PM17
31[15:14]
PSE1,RW
13:12
TOS_PM16
31[13:12]
PSE1,RW
11:10
TOS_PM15
31[11:10]
PSE1,RW
9:8
TOS_PM14
31[9:8]
PSE1,RW
7:6
TOS_PM13
31[7:6]
PSE1,RW
5:4
TOS_PM12
31[5:4]
PSE1,RW
3:2
TOS_PM11
31[3:2]
PSE1,RW
1:0
TOS_PM10
31[1:0]
PSE1,RW
Description
TOS value = 17H
TOS value = 16H
TOS value = 15H
TOS value = 14H
TOS value = 13H
TOS value = 12H
TOS value = 11H
TOS value = 10H
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
46
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.3.11 TOS Priority Map 3 Register (21BH)
Bit
Name
ROM
Default
15:14 TOS_PM1F
32[15:14]
PSE1,RW
13:12 TOS_PM1E
32[13:12]
PSE1,RW
11:10 TOS_PM1D
32[11:10]
PSE1,RW
9:8
TOS_PM1C
32[9:8]
PSE1,RW
7:6
TOS_PM1B
32[7:6]
PSE1,RW
5:4
TOS_PM1A
32[5:4]
PSE1,RW
3:2
TOS_PM19
32[3:2]
PSE1,RW
1:0
TOS_PM18
32[1:0]
PSE1,RW
Description
TOS value = 1FH
TOS value = 1EH
TOS value = 1DH
TOS value = 1CH
TOS value = 1BH
TOS value = 1AH
TOS value = 19H
TOS value = 18H
4.3.12 TOS Priority Map 4 Register (21CH)
Bit
Name
ROM
Default
15:14
TOS_PM27
33[15:14]
PSE2,RW
13:12
TOS_PM26
33[13:12]
PSE2,RW
11:10
TOS_PM25
33[11:10]
PSE2,RW
9:8
TOS_PM24
33[9:8]
PSE2,RW
7:6
TOS_PM23
33[7:6]
PSE2,RW
5:4
TOS_PM22
33[5:4]
PSE2,RW
3:2
TOS_PM21
33[3:2]
PSE2,RW
1:0
TOS_PM20
33[1:0]
PSE2,RW
Description
TOS value = 27H
TOS value = 26H
TOS value = 25H
TOS value = 24H
TOS value = 23H
TOS value = 22H
TOS value = 21H
TOS value = 20H
4.3.13 TOS Priority Map 5 Register (21DH)
Bit
Name
ROM
Default
15:14 TOS_PM2F
34[15:14]
PSE2,RW
13:12 TOS_PM2E
34[13:12]
PSE2,RW
11:10 TOS_PM2D
34[11:10]
PSE2,RW
9:8
TOS_PM2C
34[9:8]
PSE2,RW
7:6
TOS_PM2B
34[7:6]
PSE2,RW
5:4
TOS_PM2A
34[5:4]
PSE2,RW
3:2
TOS_PM29
34[3:2]
PSE2,RW
1:0
TOS_PM28
34[1:0]
PSE2,RW
Description
TOS value = 2FH
TOS value = 2EH
TOS value = 2DH
TOS value = 2CH
TOS value = 2BH
TOS value = 2AH
TOS value = 29H
TOS value = 28H
4.3.14 TOS Priority Map 6 Register (21EH)
Bit
Name
ROM
Default
15:14
TOS_PM37
35[15:14]
PSE3,RW
13:12
TOS_PM36
35[13:12]
PSE3,RW
11:10
TOS_PM35
35[11:10]
PSE3,RW
9:8
TOS_PM34
35[9:8]
PSE3,RW
7:6
TOS_PM33
35[7:6]
PSE3,RW
5:4
TOS_PM32
35[5:4]
PSE3,RW
3:2
TOS_PM31
35[3:2]
PSE3,RW
1:0
TOS_PM30
35[1:0]
PSE3,RW
Description
TOS value = 37H
TOS value = 36H
TOS value = 35H
TOS value = 34H
TOS value = 33H
TOS value = 32H
TOS value = 31H
TOS value = 30H
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
47
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.3.15 TOS Priority Map 7 Register (21FH)
Bit
Name
ROM
Default
15:14 TOS_PM3F
36[15:14]
PSE3,RW
13:12 TOS_PM3E
36[13:12]
PSE3,RW
11:10 TOS_PM3D
36[11:10]
PSE3,RW
9:8
TOS_PM3C
36[9:8]
PSE3,RW
7:6
TOS_PM3B
36[7:6]
PSE3,RW
5:4
TOS_PM3A
36[5:4]
PSE3,RW
3:2
TOS_PM39
36[3:2]
PSE3,RW
1:0
TOS_PM38
36[1:0]
PSE3,RW
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
Description
TOS value = 3FH
TOS value = 3EH
TOS value = 3DH
TOS value = 3CH
TOS value = 3BH
TOS value = 3AH
TOS value = 39H
TOS value = 38H
48
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.3.16 MIB Counter Disable Register (230H)
Bit
Name
ROM
Default
15:8
RESERVED
--P0,RO
7:6
RESERVED
--P0,RO
5:0
MIB_DIS
22[5:0]
PSE0,RW
4.3.17 MIB Counter Control Register (231H)
Bit
Name
ROM
Default
15
MIB_READY
--PS0,RO
14:10 RESERVED
--P0,RO
9:8
MIB_CMD
--PS0,RW
7:5
4:0
MIB_PORT
MIB_OFSET
-----
PS0,RW
PS0,RW
Description
Reserved
Reserved
Per-Port MIB Counter Disable
[5] 0: Port5 MIB counter is enabled
1: Port5 MIB counter is disabled
[4] 0: Port4 MIB counter is enabled
1: Port4 MIB counter is disabled
[3] 0: Port3 MIB counter is enabled
1: Port3 MIB counter is disabled
[2] 0: Port2 MIB counter is enabled
1: Port2 MIB counter is disabled
[1] 0: Port1 MIB counter is enabled
1: Port1 MIB counter is disabled
[0] 0: Port0 MIB counter is enabled
1: Port0 MIB counter is disabled
Description
Counter Data is Ready
Reserved
MIB Command
00: Read & Clear
01: Read only
10: Clear MIB counters of port
11: Clear MIB counters of all ports
Port Index (0~5)
Counter Offset (0~9)
MIB counter offset 00H: RX Byte Counter Register
MIB counter offset 01H: RX Uni-cast Packet Counter Register
MIB counter offset 02H: RX Multi-cast Packet Counter Register
MIB counter offset 03H: RX Discard Packet Counter Register
MIB counter offset 04H: RX Error Packet Counter Register
MIB counter offset 05H: TX Byte Counter Register
MIB counter offset 06H: TX Uni-cast Packet Counter Register
MIB counter offset 07H: TX Multi-cast Packet Counter Register
MIB counter offset 08H: TX Discard Packet Counter Register
MIB counter offset 09H: TX Error Packet Counter Register
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
49
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.3.18 MIB Counter Data Low Register (232H)
Bit
Name
ROM
Default
15:0
MIB_DL
--PS0,RW
Description
Counter Data Low (Bit 15:00)
4.3.19 MIB Counter Data High Register (233H)
Bit
Name
ROM
Default
15:0
MIB_DH
--PS0,RW
Description
Counter Data High (Bit 31:16)
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
50
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.3.20 QinQ TPID Register (23DH)
Bit
Name
ROM
15:0
QinQ_TPID
48[15:0]
Default
PSE88A8
H,RW
Description
QinQ Tag Protocol Identifier
For VLAN stacking function
4.3.21 VLAN Mode and Rule Control Register (23EH)
Bit
Name
ROM
Default
Description
15
FIR_VIDFFF
49[15]
PSE0,RW Enable to drop Pakcet with VID==FFFH
0: Disable
1: Enable
14
FIR_CFI
49[14]
PSE0,RW Enable to drop Pakcet with Nonzero CFI
Drop incoming packet, if the CFI field is not equal to zero.
0: Disable
1: Enable
11:9
RESERVED
--P0,RO
Reserved
8
QINQ_EN
49[8]
PSE0,RW VLAN Stacking Enable (QinQ)
0: Disable
1: Enable
7
TOS6
49[7]
PE0,RW
Full IP ToS Field for Priority Queue
1: check most significant 6-bit of TOS
0: check most significant 3-bit only of TOS
6
RESERVED
--P0,RO
Reserved
5
UNICAST
49[5]
PE0,RW
Unicast packet can across VLAN boundary
0: Disable
1: Enable
4
VLAN_RFFF
49[4]
PSE0,RW Replace VIDFFF with PVID Enable
Replace VID field of VLAN tag with PVID, if VID is FFFH
0: Disable
1: Enable
3
VLAN_RVD1
49[3]
PSE0,RW Replace VID1 with PVID Enable
Replace VID field of VLAN tag with PVID, if VID is 001H
0: Disable
1: Enable
2
VLAN_RVD0
49[2]
PSE0,RW Replace VID0 with PVID Enable
Replace VID field of VLAN tag with PVID, if VID is 000H
0: Disable
1: Enable
1
VLAN_RPRI
49[1]
PSE0,RW Replace Priority Enable
Replace priority field of VLAN tag with PPRI
0: Disable
1: Enable
0
VLAN_MOD
49[0]
PSE0,RW VLAN_MODE
0: Port-based VLAN
1: Tag-based VLAN
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
51
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.3.22 VLAN Table - Valid Control Register (23FH)
Bit
Name
ROM
Default
Description
15:0
VTAB_VALD
50[15:0]
PSE,01H, Entry Vailid Bits in VLAN Table
RW
There are 16 entries in VLAN Table,
VTAB_VALID indicate which entries are valid
0: Invalid
1: Valid
4.3.23 VLAN Table - ID_0H Register (250H)
Bit
Name
ROM
Default
15:12 VTAB_FID0
51[15:12]
PSE0,RW
11:00 VTAB_VID0
51[11:00]
PSE1,RW
Description
FID of Entry 0H in VLAN Table
VID of Entry 0H in VLAN Table
4.3.24 VLAN Table - ID_1H Register (251H)
Bit
Name
ROM
Default
15:12 VTAB_FID1
52[15:12]
PSE0,RW
11:00 VTAB_VID1
52[11:00]
PSE0,RW
Description
FID of Entry 1H in VLAN Table
VID of Entry 1H in VLAN Table
4.3.25 VLAN Table - ID_2H Register (252H)
Bit
Name
ROM
Default
15:12 VTAB_FID2
53[15:12]
PSE0,RW
11:00 VTAB_VID2
53[11:00]
PSE0,RW
Description
FID of Entry 2H in VLAN Table
VID of Entry 2H in VLAN Table
4.3.26 VLAN Table - ID_3H Register (253H)
Bit
Name
ROM
Default
15:12 VTAB_FID3
54[15:12]
PSE0,RW
11:00 VTAB_VID3
54[11:00]
PSE0,RW
Description
FID of Entry 3H in VLAN Table
VID of Entry 3H in VLAN Table
4.3.27 VLAN Table - ID_4H Register (254H)
Bit
Name
ROM
Default
15:12 VTAB_FID4
55[15:12]
PSE0,RW
11:00 VTAB_VID4
55[11:0]
PSE0,RW
Description
FID of Entry 4H in VLAN Table
VID of Entry 4H in VLAN Table
4.3.28 VLAN Table - ID_5H Register (255H)
Bit
Name
ROM
Default
15:12 VTAB_FID5
56[15:12]
PSE0,RW
11:00 VTAB_VID5
56[11:0]
PSE0,RW
Description
FID of Entry 5H in VLAN Table
VID of Entry 5H in VLAN Table
4.3.29 VLAN Table - ID_6H Register (256H)
Bit
Name
ROM
Default
15:12 VTAB_FID6
57[15:12]
PSE0,RW
11:00 VTAB_VID6
57[11:0]
PSE0,RW
Description
FID of Entry 6H in VLAN Table
VID of Entry 6H in VLAN Table
4.3.30 VLAN Table - ID_7H Register (257H)
Bit
Name
ROM
Default
15:12 VTAB_FID7
58[15:12]
PSE0,RW
11:00 VTAB_VID7
58[11:0]
PSE0,RW
Description
FID of Entry 7H in VLAN Table
VID of Entry 7H in VLAN Table
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
52
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.3.31 VLAN Table - ID_8H Register (258H)
Bit
Name
ROM
Default
15:12 VTAB_FID8
59[15:12]
PSE0,RW
11:00 VTAB_VID8
59[11:0]
PSE0,RW
Description
FID of Entry 8H in VLAN Table
VID of Entry 8H in VLAN Table
4.3.32 VLAN Table - ID_9H Register (259H)
Bit
Name
ROM
Default
15:12 VTAB_FID9
60[15:12]
PSE0,RW
11:00 VTAB_VID9
60[11:0]
PSE0,RW
Description
FID of Entry 9H in VLAN Table
VID of Entry 9H in VLAN Table
4.3.33 VLAN Table - ID_AH Register (25AH)
Bit
Name
ROM
Default
15:12 VTAB_FIDA
61[15:12]
PSE0,RW
11:00 VTAB_VIDA
61[11:0]
PSE0,RW
Description
FID of Entry AH in VLAN Table
VID of Entry AH in VLAN Table
4.3.34 VLAN Table - ID_BH Register (25BH)
Bit
Name
ROM
Default
15:12 VTAB_FIDB
62[15:12]
PSE0,RW
11:00 VTAB_VIDB
62[11:0]
PSE0,RW
Description
FID of Entry BH in VLAN Table
VID of Entry BH in VLAN Table
4.3.35 VLAN Table - ID_CH Register (25CH)
Bit
Name
ROM
Default
15:12 VTAB_FIDC
63[15:12]
PSE0,RW
11:00 VTAB_VIDC
63[11:0]
PSE0,RW
Description
FID of Entry CH in VLAN Table
VID of Entry CH in VLAN Table
4.3.36 VLAN Table - ID_DH Register (25DH)
Bit
Name
ROM
Default
15:12 VTAB_FIDD
64[15:12]
PSE0,RW
11:00 VTAB_VIDD
64[11:0]
PSE0,RW
Description
FID of Entry DH in VLAN Table
VID of Entry DH in VLAN Table
4.3.37 VLAN Table - ID_EH Register (25EH)
Bit
Name
ROM
Default
15:12 VTAB_FIDE
65[15:12]
PSE0,RW
11:00 VTAB_VIDE
65[11:0]
PSE0,RW
Description
FID of Entry EH in VLAN Table
VID of Entry EH in VLAN Table
4.3.38 VLAN Table - ID_FH Register (25FH)
Bit
Name
ROM
Default
15:12 VTAB_FIDF
66[15:12]
PSE0,RW
11:00 VTAB_VIDF
66[11:0]
PSE0,RW
Description
FID of Entry FH in VLAN Table
VID of Entry FH in VLAN Table
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
53
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.3.39 VLAN Table - MEMBER_0H Register (270H)
Bit
Name
ROM
Default
Description
15:14 RESERVED
--P0,RO
Reserved
13:8
VTAB_TM0
67[13:8]
PSE0,RW VLAN Entry 0H Tagged Member
The content of 250H.[11:0] equal to VID field of a tagged
frame which be received . The mapping ports of this field
is the direction of forwarding packets .
7:6
RESERVED
--P0,RO
Reserved
5:0
VTAB_VM0
67[5:0]
PSE,3FH, VLAN Entry 0H VLAN Member
RW
4.3.40 VLAN Table - MEMBER_1H Register (271H)
Bit
Name
ROM
Default
Description
15:14 RESERVED
--P0,RO
Reserved
13:8
VTAB_TM1
68[13:8]
PSE0,RW VLAN Entry 1H Tagged Member
The content of 251H.[11:0] equal to VID field of a tagged
frame which be received . The mapping ports of this field
is the direction of forwarding packets .
7:6
RESERVED
--P0,RO
Reserved
5:0
VTAB_VM1
68[5:0]
PSE0,RW VLAN Entry 1HVLAN Member
4.3.41 VLAN Table - MEMBER_2H Register (272H)
Bit
Name
ROM
Default
Description
15:14 RESERVED
--P0,RO
Reserved
13:8
VTAB_TM2
69[13:8]
PSE0,RW VLAN Entry 2H Tagged Member
The content of 252H.[11:0] equal to VID field of a tagged
frame which be received . The mapping ports of this field
is the direction of forwarding packets .
7:6
RESERVED
--P0,RO
Reserved
5:0
VTAB_VM2
69[5:0]
PSE0,RW VLAN Entry 2H VLAN Member
4.3.42 VLAN Table - MEMBER_3H Register (273H)
Bit
Name
ROM
Default
Description
15:14 RESERVED
--P0,RO
Reserved
13:8
VTAB_TM3
70[13:8]
PSE0,RW VLAN Entry 3H Tagged Member
The content of 253H.[11:0] equal to VID field of a tagged
frame which be received . The mapping ports of this field
is the direction of forwarding packets .
7:6
RESERVED
--P0,RO
Reserved
5:0
VTAB_VM3
70[5:0]
PSE0,RW VLAN Entry 3H VLAN Member
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
54
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.3.43 VLAN Table - MEMBER_4H Register (274H)
Bit
Name
ROM
Default
Description
15:14 RESERVED
--P0,RO
Reserved
13:8
VTAB_TM4
71[13:8]
PSE0,RW VLAN Entry 4H Tagged Member
The content of 254H.[11:0] equal to VID field of a tagged
frame which be received . The mapping ports of this field is
the direction of forwarding packets .
7:6
RESERVED
--P0,RO
Reserved
5:0
VTAB_VM4
71[5:0]
PSE0,RW VLAN Entry 4H VLAN Member
4.3.44 VLAN Table - MEMBER_5H Register (275H)
Bit
Name
ROM
Default
Description
15:14 RESERVED
--P0,RO
Reserved
13:8
VTAB_TM5
72[13:8]
PSE0,RW VLAN Entry 5H Tagged Member
The content of 255H.[11:0] equal to VID field of a tagged
frame which be received . The mapping ports of this field
is the direction of forwarding packets .
7:6
RESERVED
--P0,RO
Reserved
5:0
VTAB_VM5
72[5:0]
PSE0,RW VLAN Entry 5H VLAN Member
4.3.45 VLAN Table - MEMBER_6H Register (276H)
Bit
Name
ROM
Default
Description
15:14 RESERVED
--P0,RO
Reserved
13:8
VTAB_TM6
73[13:8]
PSE0,RW VLAN Entry 6H Tagged Member
The content of 256H.[11:0] equal to VID field of a tagged
frame which be received . The mapping ports of this field
is the direction of forwarding packets .
7:6
RESERVED
--P0,RO
Reserved
5:0
VTAB_VM6
73[5:0]
PSE0,RW VLAN Entry 6H VLAN Member
4.3.46 VLAN Table - MEMBER_7H Register (277H)
Bit
Name
ROM
Default
Description
15:14 RESERVED
--P0,RO
Reserved
13:8
VTAB_TM7
74[13:8]
PSE0,RW VLAN Entry 7H Tagged Member
The content of 257H.[11:0] equal to VID field of a tagged
frame which be received . The mapping ports of this field
is the direction of forwarding packets .
7:6
RESERVED
--P0,RO
Reserved
5:0
VTAB_VM7
74[5:0]
PSE0,RW VLAN Entry 7H VLAN Member
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
55
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.3.47 VLAN Table - MEMBER_8H Register (278H)
Bit
Name
ROM
Default
Description
15:14 RESERVED
--P0,RO
Reserved
13:8
VTAB_TM8
75[13:8]
PSE0,RW VLAN Entry 8H Tagged Member
The content of 258H.[11:0] equal to VID field of a tagged
frame which be received . The mapping ports of this field
is the direction of forwarding packets .
7:6
RESERVED
--P0,RO
Reserved
5:0
VTAB_VM8
75[5:0]
PSE0,RW VLAN Entry 8H VLAN Member
4.3.48 VLAN Table - MEMBER_9H Register (279H)
Bit
Name
ROM
Default
Description
15:14 RESERVED
--P0,RO
Reserved
13:8
VTAB_TM9
76[13:8]
PSE0,RW VLAN Entry 9H Tagged Member
The content of 259H.[11:0] equal to VID field of a tagged
frame which be received . The mapping ports of this field
is the direction of forwarding packets .
7:6
RESERVED
--P0,RO
Reserved
5:0
VTAB_VM9
76[5:0]
PSE0,RW VLAN Entry 9H VLAN Member
4.3.49 VLAN Table - MEMBER_AH Register (27AH)
Bit
Name
ROM
Default
Description
15:14 RESERVED
--P0,RO
Reserved
13:8
VTAB_TMA
77[13:8]
PSE0,RW VLAN Entry 0AH Tagged Member
The content of 25AH.[11:0] equal to VID field of a tagged
frame which be received . The mapping ports of this field
is the direction of forwarding packets .
7:6
RESERVED
--P0,RO
Reserved
5:0
VTAB_VMA
77[5:0]
PSE0,RW VLAN Entry 0AH VLAN Member
4.3.50 VLAN Table - MEMBER_BH Register (27BH)
Bit
Name
ROM
Default
Description
15:14 RESERVED
--P0,RO
Reserved
13:8
VTAB_TMB
78[13:8]
PSE0,RW VLAN Entry 0BH Tagged Member
The content of 25BH.[11:0] equal to VID field of a tagged
frame which be received . The mapping ports of this field
is the direction of forwarding packets .
7:6
RESERVED
--P0,RO
Reserved
5:0
VTAB_VMB
78[5:0]
PSE0,RW VLAN Entry 0BH VLAN Member
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
56
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.3.51 VLAN Table - MEMBER_CH Register (27CH)
Bit
Name
ROM
Default
Description
15:14 RESERVED
--P0,RO
Reserved
13:8
VTAB_TMC
79[13:8]
PSE0,RW VLAN Entry 0CH Tagged Member
The content of 25CH.[11:0] equal to VID field of a tagged
frame which be received . The mapping ports of this field
is the direction of forwarding packets .
7:6
RESERVED
--P0,RO
Reserved
5:0
VTAB_VMC
79[5:0]
PSE0,RW VLAN Entry 0CH VLAN Member
4.3.52 VLAN Table - MEMBER_DH Register (27DH)
Bit
Name
ROM
Default
Description
15:14 RESERVED
--P0,RO
Reserved
13:8
VTAB_TMD
80[13:8]
PSE0,RW VLAN Entry 0DH Tagged Member
The content of 25DH.[11:0] equal to VID field of a tagged
frame which be received . The mapping ports of this field
is the direction of forwarding packets .
7:6
RESERVED
--P0,RO
Reserved
5:0
VTAB_VMD
80[5:0]
PSE0,RW VLAN Entry 0DH VLAN Member
4.3.53 VLAN Table - MEMBER_EH Register (27EH)
Bit
Name
ROM
Default
Description
15:14 RESERVED
--P0,RO
Reserved
13:8
VTAB_TME
81[13:8]
PSE0,RW VLAN Entry 0EH Tagged Member
The content of 25EH.[11:0] equal to VID field of a tagged
frame which be received . The mapping ports of this field
is the direction of forwarding packets .
7:6
RESERVED
--P0,RO
Reserved
5:0
VTAB_VME
81[5:0]
PSE0,RW VLAN Entry 0EH VLAN Member
4.3.54 VLAN Table - MEMBER_FH Register (27FH)
Bit
Name
ROM
Default
Description
15:14 RESERVED
--P0,RO
Reserved
13:8
VTAB_TMF
82[13:8]
PSE0,RW VLAN Entry 0FH Tagged Member
The content of 25FH.[11:0] equal to VID field of a tagged
frame which be received . The mapping ports of this field
is the direction of forwarding packets .
7:6
RESERVED
--P0,RO
Reserved
5:0
VTAB_VMF
82[5:0]
PSE0,RW VLAN Entry 0FH VLAN Member
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
57
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.3.55 VLAN Table - Priority Enable Register (290H)
Bit
Name
ROM
Default
Description
15:0
VTAB_PEN
83[15:0]
PSE0,RW Priority Enable Bits in VLAN Table
Assign VLAN priority queue number from VLAN table
(293H~299H) field VTAB_QUE_0~F to be transmit queue
number.
0: Disable
1: Enable
4.3.56 VLAN Table - STP Index Enable Register (292H)
Bit
Name
ROM
Default
Description
15:0
VTAB_STPE
85[15:0]
PSE0,RW Spanning Tree Protocol I VLAN Table
To enable the STP function of the ports from VLAN table
0: Disable
1: Enable
4.3.57 VLAN Table - Misc_0 Register (293H)
Bit
Name
ROM
Default
15:10 RESERVED
86[15:10]
PSE0,RW
9:8
VTAB_QUE1
86[9:8]
PSE0,RW
7:2
RESERVED
86[6:2]
PSE0,RW
1:0
VTAB_QUE0
86[1:0]
PSE0,RW
Description
Reserved
VLAN Entry 1H, Priority Queue Number
Reserved
VLAN Entry 0H, Priority Queue Number
4.3.58 VLAN Table - Misc_1 Register (294H)
Bit
Name
ROM
Default
15:10 RESERVED
87[15:10]
PSE0,RW
9:8
VTAB_QUE3
87[9:8]
PSE0,RW
7:2
RESERVED
87[6:2]
PSE0,RW
1:0
VTAB_QUE2
87[1:0]
PSE0,RW
Description
Reserved
VLAN Entry 3H, Priority Queue Number
Reserved
VLAN Entry 2H, Priority Queue Number
4.3.59 VLAN Table - Misc_2 Register (295H)
Bit
Name
ROM
Default
15:10 RESERVED
88[15:10]
PSE0,RW
9:8
VTAB_QUE5
88[9:8]
PSE0,RW
7:2
RESERVED
88[6:2]
PSE0,RW
1:0
VTAB_QUE4
88[1:0]
PSE0,RW
Description
Reserved
VLAN Entry 5H, Priority Queue Number
Reserved
VLAN Entry 4H, Priority Queue Number
4.3.60 VLAN Table - Misc_3 Register (296H)
Bit
Name
ROM
Default
15:10 RESERVED
89[15:10]
PSE0,RW
9:8
VTAB_QUE7
89[9:8]
PSE0,RW
7:2
RESERVED
89[6:2]
PSE0,RW
1:0
VTAB_QUE6
89[1:0]
PSE0,RW
Description
Reserved
VLAN Entry 7H, Priority Queue Number
Reserved
VLAN Entry 6H, Priority Queue Number
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
58
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.3.61 VLAN Table - Misc_4 Register (297H)
Bit
Name
ROM
Default
15:10 RESERVED
90[15:10]
PSE0,RW
9:8
VTAB_QUE9
90[9:8]
PSE0,RW
7:2
RESERVED
90[6:2]
PSE0,RW
1:0
VTAB_QUE8
90[1:0]
PSE0,RW
Description
Reserved
VLAN Entry 9H, Priority Queue Number
Reserved
VLAN Entry 8H, Priority Queue Number
4.3.62 VLAN Table - Misc_5 Register (298H)
Bit
Name
ROM
Default
15:10 RESERVED
91[15:10]
PSE0,RW
9:8
VTAB_QUB
91[9:8]
PSE0,RW
7:2
RESERVED
91[6:2]
PSE0,RW
1:0
VTAB_QUA
91[1:0]
PSE0,RW
Description
Reserved
VLAN Entry 0BH, Priority Queue Number
Reserved
VLAN Entry 0AH, Priority Queue Number
4.3.63 VLAN Table - Misc_6 Register (299H)
Bit
Name
ROM
Default
15:10 RESERVED
92[15:10]
PSE0,RW
9:8
VTAB_QUD
92[9:8]
PSE0,RW
7:2
RESERVED
92[6:2]
PSE0,RW
1:0
VTAB_QUC
92[1:0]
PSE0,RW
Description
Reserved
VLAN Entry 0DH, Priority Queue Number
Reserved
VLAN Entry 0CH, Priority Queue Number
4.3.64 VLAN Table - Misc_7 Register (29AH)
Bit
Name
ROM
Default
15:10 RESERVED
93[15:10]
PSE0,RW
9:8
VTAB_QUF
93[9:8]
PSE0,RW
7:2
RESERVED
93[6:2]
PSE0,RW
1:0
VTAB_QUE
93[1:0]
PSE0,RW
Description
Reserved
VLAN Entry 0FH, Priority Queue Number
Reserved
VLAN Entry 0EH, Priority Queue Number
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
59
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.3.65 Snooping Control 0 Register (29BH)
Bit
Name
ROM
Default
15:14 RESERVED
--P0,RO
13:8
RPP
23[13:8]
PSE0,RW
7
6
5:4
UD_RP
RESERVED
MC_CTRL
23[7]
--23[5:4]
PSE0,RW
P0,RO
PSE0,RW
3:2
UMD_CTRL
23[3:2]
PSE0,RW
1
MLDS_EN
23[1]
PSE0,RW
0
HIGS_EN
23[0]
PSE0,RW
4.3.66 Snooping Control 1 Register (29CH)
Bit
Name
ROM
Default
15:14 RESERVED
--P0,RO
12
IGS_TODIS
24[12]
PSE0,RW
11:10
RP_TV
24[11:10]
PSE0,RW
9:8
IGS_RV
24[9:8]
PSE0,RW
7:0
IGS_QI
24[7:0]
PSE7DH,
RW
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
Description
Reserved
Router Port Portmap
Bit0: Port 0
Bit1: Port 1
Bit2: Port 2
Bit3: Port 3
Bit4: Port 4
Bit5: Port 5
User-defined Router Port Enable
Reserved
Multicast Control Packet Handle
00: Forward Membership Reports to router port. General
Query to all port.
01: Mirror to CPU (Forward to CPU also)
10: Trap to CPU (Forward to CPU only)
11: Flood
Unregistered Multicast Data Packet Handle
00: As normal multicast packets
01: Dropped.
10: Trap to CPU
11: Flood except CPU
MLD Snooping Enable
0: Disable
1: Enable
Hardware IGMP Snooping Enable
0: Disable
1: Enable
Description
Reserved
IGMP Snooping Timeout Scheme Disable
0: Timeout is enabled
1: Timeout is disabled
Router Port Timeout Value Selection
00: 1 times of Query Interval
01: 2 times of Query Interval
10: 3 times of Query Interval (default)
11: 4 times of Query Interval
Robustness Variable
00: 1 times
01: 2 times (default)
10: 3 times
11: 4 times
Query Interval
Default = 125 (sec)
60
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.3.67 Address Table Control & Status Register (2B0H)
Bit
Name
ROM
Default
Description
15
ATB_S
--PS0,RO
Address Table Access is Busy
0: Available (Access process is completed)
1: Busy (Access process is operating)
14:13
ATB_CR
--PS0,RO
Address Table Command Result
00: Command OK, entry doesn't exist
a. Create an new entry
(Write Command)
b. Do noting
(Delete Command)
c. not found
(Search Command)
d. Entry is invalid
(Read Command)
e. Process is successful
(Clear Command)
01: Command OK, entry is exist
a. Overwrite entry
(Write Command)
b. Delete entry
(Delete Command)
c. Entry found
(Search Command)
d. Entry is valid
(Read Command)
e. Process is successful
(Clear Command)
1X: Command Error
12:8
RESERVED
--P0,RO
Reserved
7
RESERVED
--P0,RO
Reserved
6
ATB_CLSE_
--PS0,RW
Enable to Clear Entries with Specified FID
FID
0: Disable
1: Enable
5
ATB_CLSE_
--PS0,RW
Enable to Clear Entries with Specified
PORT
Port Number or Port Map
(Port number for accessing unicast
address table, port map for multicast)
0: Disable
1: Enable
4:2
ATB_CMD
--PS0,RW
Command
000: Read a entry with sequence number of address table
001: Write a entry with MAC address
010: Delete a entry with MAC address
011: Search a entry with MAC address
100: Clear one or more than one entries
with Port or FID
101,110,111: Reserved
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
61
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
1:0
ATB_IDX
---
PS0,RW
Address Table Index
00: Unicast Address Table
01: Multicast Address Table
10: IGMP Table
11: Reserved
4.3.68 Address Table Data 0 Register (2B1H)
Bit
Name
ROM
Default
15:12 RESERVED
--P0,RO
11:8
ATB_FID
--PS0,RW
7:6
RESERVED
--P0,RO
5:0
ATB_PORT
--PS0,RW
Description
Reserved
FID Value
Reserved
Address Table Port Number or Port Map
4.3.69 Address Table Data 1 Register (2B2H)
Bit
Name
ROM
Default
15:0
ATB_DW1
--PSE0,RW
Description
Address Table Data Word 1
4.3.70 Address Table Data 2 Register (2B3H)
Bit
Name
ROM
Default
15:0
ATB_DW2
--PSE0,RW
Description
Address Table Data Word 2
4.3.71 Address Table Data 3 Register (2B4H)
Bit
Name
ROM
Default
15:0
ATB_DW3
--PSE0,RW
Description
Address Table Data Word 3
4.3.72 Address Table Data 4 Register (2B5H)
Bit
Name
ROM
Default
15:0
ATB_DW4
--PSE0,RW
Description
Address Table Data Word 4
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
62
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.4 Chip Control and Status Registers (300H~3FFH)
4.4.1 Vendor ID Register (310H)
Bit
Name
ROM
15:0
VID
4[15:0]
4.4.2 Product ID Register (311H)
Bit
Name
ROM
15:0
PID
5[15:0]
Default
PE,0A46H
,RO
Description
Vendor ID
Default
PE,8606H,
RO
Description
Product ID
4.4.3 Chip Revision ID Register (312H)
Bit
Name
ROM
Default
15:0
CHIPR
---P0,RO
4.4.4 Port 4 MAC Control Register (314H)
Bit
Name
ROM
Default
15:12 RESERVED
--P0,RO
11,10 P4_TB_SEL
12[11:10]
PET00,
RW
9:8
P4_DRIVE
12[9:8]
PET01,R
W
7
P4_SLEW
12[7]
PET0,RW
6
P4_50M_IN
12[6]
PE0,RW
5
P4_50MOUT
12[5]
PET0,RW
4
3
RESERVED
P4_MODE
--12[3]
P0,RO
PET0,RW
2
P4_LINK
12[2]
PET0,RW
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
Description
Chip Revision
Description
Reserved
Port4 turbo speed in RevMII
00: Default TXCLK 25MHz(100M)/2.5MHz(10M)
01: P4 RevMII TXCLK generate 50MHz clock
10: P4 RevMII TXCLK generate 100MHz clock
11: P4 RevMII TXCLK generate 125MHz clock
Port 4 output pin Current Driving/Sinking Capability
00: 2mA
01: 4mA (default)
10: 6mA
11: 8mA
Port 4 output pin slew rate
0: normal slew rate
1: low slew rate
When Port4 be configured as RMII/TP RMII
0: 50MHz clock source from pin
1: 50MHz clock source from internal chip
When Port4 be configured as RMII/TPRMII
0: Disable as High impedance
1: Output 50MHz clock
Reserved
Port4 in auto-negotiation mode for MII/RevMII/RMII
0: auto-negotiation mode
1: force mode
When Port4 in force mode for MII/RevMII/RMII
0: link ON
1: link OFF
63
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
1
P4_DPX
12[1]
PET0,RW
0
P4_SPEED
12[0]
PET0,RW
4.4.5 Port 5 MAC Control Register (315H)
Bit
Name
ROM
Default
15
Reserved
13[15]
PE1,RW
14
Reserved
13[14]
PET0,RW
13
Reserved
13[13]
PET0,RW
12
Reserved
13[12]
PET0,RW
11
Reserved
13[11]
PET0,RW
10
Reserved
--P0,RO
9,8
P5_DRIVE
13[9:8]
PET01,RW
7
P5_SLEW
13[7]
PET0,RW
6
P5_50M_IN
13[6]
PE0,RW
5
P5_50M_OU
T
13[5]
PET0,RW
4
3
Reserved
P5_MODE
--13[3]
P0,RO
PET0,RW
2
P5_LINK
13[2]
PET0,RW
1
P5_DPX
13[1]
PET0,RW
0
P5_SPEED
13[0]
PET0,RW
4.4.6 LED Control Register (317H)
Bit
Name
ROM
15
IRQ_PIN
6[9]
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
Default
PSE0,RW
When Port4 in force mode for MII/RevMII/RMII
0: Full-duplex mode
1: Half-duplex mode
When Port4 in force mode for MII/RevMII/RMII
0: 100M mode
1: 10M mode
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Port 5 output pin Current Driving/Sinking Capability
00: 2mA
01: 4mA (default)
10: 6mA
11: 8mA
Port 5 output pin slew rate
0: normal slew rate
1: low slew rate
When Port5 be configured as RMII
0: 50MHz clock source from pin
1: 50MHz clock source from internal chip
When Port5 be configured as RMII
0: Disable as High impedance
1: Output 50MHz clock
Reserved
When Port5 in MII/RevMII/RMII
0: auto-negotiation mode
1: force mode
When Port5 in force mode
0: link ON
1: link OFF
When Port5 in force mode
0: Full-duplex mode
1: Half-duplex mode
When Port5 in force mode
0: 100M mode
1: 10M mode
Description
Output Mode of INTR Pin
0: Direct output mode
1: Open-collected mode
64
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
14
IRQ_POL
6[8]
PSE,0,RW
13
12,11
RESERVED
CTL_DRIVE
--6[12:11]
P0,RO
PET01,R
W
10
CTL_SLEW
6[10]
PET0,RW
9,8
LED_DRIVE
6[9:8]
PET01,R
W
7
LED_SLEW
6[7]
PET1,RW
6:2
1:0
RESERVED
LED_CR
--6[1:0]
P0,RO
PE3,RW
4.4.7 Interrupt Status Register (318H)
Bit
Name
ROM
Default
15:4
RESERVED
--P0,RO
0
LNKCHG
--PS0,
RW/C1
4.4.8 Interrupt Mask & Control Register (319H)
Bit
Name
ROM
Default
15:4
RESERVED
--P0,RO
0
LNKCHG
--PS0,RW
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
Polarity Mode of INTR Pin
0: Active high
1: Active low
Reserved
Switch Control output pin Current Driving/Sinking
Capability
00: 2mA
01: 4mA (default)
10: 6mA
11: 8mA
Switch Control output pin slew rate
0: normal slew rate
1: low slew rate
LED pin Current Driving/Sinking Capability
00: 2mA
01: 4mA
10: 6mA (default)
11: 8mA
LED pin slew rate
0: normal slew rate
1: low slew rate
Reserved
LED mode select
00: LED mode 0
01: LED mode 1 ,dual color mode
10: LED mode 2 ,
11: LED mode 3 (default)
Description
Reserved
Link Status Change
Description
Reserved
Enable Link Status Change Interrupt
65
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.4.9 EEPROM Control & Address Register (31AH)
Bit
Name
ROM
Default
Description
15:8
EROA
--PS0,RW
EEPROM Word Address
7
RESERVED
--P0,RO
Reserved
6
EETYPE
--0,RO
EEPROM Type
0: 93C46
1: 93C66 / 93C56
5
REEP
--PS0,RW
Reload EEPROM. Write 1 and then write 0 to generate a
pulse to active EEPROM reload circuit
4
WEP
--PS0,RW
Write EEPROM Enable
3
EPOS
--PS0,RW
External PHY Operation Select
When set, Enable access external PHY .
2
ERPRR
--PS0,RW
EEPROM Read . Driver needs to clear it up after the
operation completes.
1
ERPRW
--PS0,RW
EEPROM Write . Driver needs to clear it up after the
operation completes.
0
ERRE
--PS0,RO
EEPROM Access Status
When set, it indicates that the EEPROM or PHY access is
in progress
When cleared, it indicates that the EEPROM or PHY
reload is completed or idle.
4.4.10 EEPROM Data Register (31BH)
Bit
Name
ROM
Default
15:0
EE_DATA
--PS0,RW
Description
EEPROM 16bit Data
4.4.11 Monitor Register 1 (31CH)
Bit
Name
ROM
15
STRP_DIS
--14
RESERVED
--13
TEST3
--12
TEST2
--11
TEST1
--10
RESERVED
--9
RESERVED
--8
P2_SPD
--7
P1_SPD
--6
P0_SPD
--5
RESERVED
--4
RESERVED
--3
RESERVED
--2
EECS
--1
EECK
--0
RESERVED
---
Description
Pin 93
Reserved
Pin 41
Pin 69
Pin 108
Reserved
Reserved
Pin 103
Pin 104
Pin 105
Pin 106
Pin 77
Pin 78
Pin 80
Pin 81
Pin 79
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
Default
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
66
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.4.12 Monitor Register 2 (31DH)
Bit
Name
ROM
15
P3_SPD
--14
P4_SPD
--13
RESERVED
--12
P4_FDX
--11
P3_FDX
--10
P2_FDX
--9
P1_FDX
--8
RESERVED
--7
RESERVED
--6
RESERVED
--5
P4_LNK
--4
RESERVED
--3
RESERVED
--2
RESERVED
--1
RESERVED
--0
RESERVED
---
Default
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Description
Reserved
Reserved
Reserved
Pin 107
Pin 110
Pin 111
Pin 112
Reserved
Reserved
Reserved
Pin 51
Reserved
Reserved
Reserved
Reserved
Reserved
4.4.13 Monitor Register 3 (31EH)
Bit
Name
ROM
15
P3_LNK
--14
P2_LNK
--13
P1_LNK
--12
P0_LNK
--11
P4_SET0
--10
CFG4
--9
P4_SET1
--8
RESERVED
--7
RESERVED
--6
RESERVED
--5
NC3
--4
NC4
--3
RESERVED
--2
RESERVED
--1
RESERVED
--0
PHY_MDC
---
Default
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Description
Pin 48
Pin 47
Pin 43
Pin 42
Pin 98
Pin 62
Pin 100
Reserved
Reserved
Reserved
Pin 115
Pin 117
Reserved
Reserved
Reserved
Pin 68
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
67
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.4.14 System Clock Select Register (338H)
Bit
Name
ROM
Default
15:8
RESERVED
--P0,RO
7
RESERVED
--PS0,RO
6:3
RESERVED
--P0,RO
2:0
CLK_TYPE
--PS0,RW
4.4.15 Serial Bus Error Check Register (339H)
Bit
Name
ROM
Default
15:9
RESERVED
--P0,RO
8
SMI_ERR
--PS0,RO
7:0
SMI_CSUM
---
PS0,RW
4.4.16 Serial Bus Control Register (33AH)
Bit
Name
ROM
Default
15:1
RESERVED
--P0,RO
0
SMI_ECE
--PS0,RW
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
Description
Reserved
Reserved
Reserved
Select system speed when internal system clock used
000: 50MHz
001: 66MHz
010: 83MHz
011: 100MHz
1XX: 25MHz
Description
Reserved
SMI Bus Error Status(Read only)
0: Checksum check correct
1: Checksum check error
SMI Bus Command Checksum for Error Check
Calculated Checksum value by HW
Description
Reserved
SMI Bus Error Check Enable(Default: 1’b0)
0: Disable
1: Enable
68
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
4.4.17 Virtual PHY Control Register (33DH)
Bit
Name
ROM
Default
15:13 RESERVED
--P0,RO
12
VPHY_LNK_
--PS0,RO
AND_RD
11
VPHY_LNK_
OR_RD
---
PS0,RO
10
9
RESERVED
VPHY_LNK_
AND_WR
-----
P0,RO
P0,WO
8
VPHY_LNK_
OR_WR
---
P0,WO
7:6
5:0
RESERVED
VPHY_MPP
-----
P0,RO
PS0,RW
4.4.18 PHY Control Test Register (33EH)
Bit
Name
ROM
Default
15
AT_MDIX0
7[15]
P0,RW
14
AT_MDIX1
7[14]
P0,RW
13
AT_MDIX2
7[13]
P0,RW
12
AT_MDIX3
7[12]
P0,RW
11
AT_MDIX4
7[11]
P0,RW
10:0
RESERVED
---
P3,RW
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
Description
Reserved
Read Value of Virtual PHY Link Operation Mode
0: Ignore, no operation
1: AND operation
Read Value of Virtual PHY Link Operation Mode
0: Ignore, no operation
1: OR operation
Reserved
Virtual PHY Link Operation Mode
0: Ignore, no operation
1: AND operation
Virtual PHY Link Operation Mode
0: Ignore, no operation
1: OR operation
Reserved
Port Map
[05]: Port 5
[04]: Port 4
[03]: Port 3
[02]: Port 2
[01]: Port 1
[00]: Port 0
Note: Valid if Reg33DH.[9] or Reg33DH.[8] is enabled
Description
Port 0 Auto-Mdix Control
0: ON
1: OFF
Port 1 Auto-Mdix Control
0: ON
1: OFF
Port 2 Auto-Mdix Control
0: ON
1: OFF
Port 3 Auto-Mdix Control
0: ON
1: OFF
Port 4 Auto-Mdix Control
0: ON
1: OFF
Reserved
69
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
5. EEPROM Format
5.1 EEPROM Words 4K (256 x 16)
Auto Load enable = 01, all other values will not enable auto load
Name
Signature
Word
0
RESERVED
1~2
Auto Load Control #1 3
Vendor ID
4
Product ID
5
Pin control
6
PHY control
7
Fiber Control
8
Preliminary
Doc No: DM8606C/DM8606CI -12-3-DS-P01
November 22, 2012
Description
EEPROM Signature = 1049H
This value must be pre-programmed into EEPROM in order for EEPROM auto
detection to work
Reserved, set to ZEROs
Bit [1:0] = 01: Load EEPROM’s Vendor ID and Product ID into switch’s Vendor
ID and Product ID registers
Bit [3:2] = 01: Load EEPROM word 6[9:0] into switch’s respective registers
Bit [5:4] = 01: Load EEPROM word 7 and 8 into switch’s respective registers
Bit [7:6] = 01: Load EEPROM’s PHY ID #1 and PHY ID #2 into switch’s
respective registers
Bit [9:8] = 01: Load EEPROM’s Port 4 MAC Control, word 12 and Port 5 MAC
Control, word 13, into switch register 314H and 315H, respectively
Bit [15:10] = Reserved, set to ZEROs
2 byte Vendor ID, default value in switch register, 310H, is 0A46H and it is
overwriten by this word when Auto Load is enabled.
This word can be customized to show different ID per application
2 byte Product ID, default value in switch register, 311H, is 8606H and it is
overwriten by this word when Auto Load is enabled.
This word can be customized to show different ID per application
Interrupt Pin Control, these bits controls pin 65, INTR mode
Bit [7:0] = Reserved, set to ZEROs
Bit [8] = INTR pin is active low when set to 1 (default = active high)
Bit [9] = INTR pin is open-collector when set to 1 (default = force output)
Bit [15:10] = Reserved, set to ZEROs
Bit [9:8] will be loaded to LED Control register, 317H, bit[15:14], respectively
Bit [10:0] : Reserved, set ZEROs
Bit [11] = Port 4 AUTO-MDIX, 1 = enable, 0 = disable (default = enable)
Bit [12] = Port 3 AUTO-MDIX, 1 = enable, 0 = disable (default = enable)
Bit [13] = Port 2 AUTO-MDIX, 1 = enable, 0 = disable (default = enable)
Bit [14] = Port 1 AUTO-MDIX, 1 = enable, 0 = disable (default = enable)
Bit [15] = Port 0 AUTO-MDIX, 1 = enable, 0 = disable (default = enable)
Bit [0] = Port 0 Media Mode, 1 = FIBER, 0 = Copper (default = Copper)
Bit [1] = Port 1 Media Mode, 1 = FIBER, 0 = Copper (default = Copper)
Bit [2] = Port 2 Media Mode, 1 = FIBER, 0 = Copper (default = Copper)
Bit [3] = Port 3 Media Mode, 1 = FIBER, 0 = Copper (default = Copper)
Bit [4] = Port 4 Media Mode, 1 = FIBER, 0 = Copper (default = Copper)
Bit [7:5] = Reserved, set ZEROs
Bit [8] = Port 0 Fiber SD source, 1 = external, 0 = internal (default = internal)
Bit [9] = Port 1 Fiber SD source, 1 = external, 0 = internal (default = internal)
Bit [10] = Port 2 Fiber SD source, 1 = external, 0 = internal (default = internal)
Bit [11] = Port 3 Fiber SD source, 1 = external, 0 = internal (default = internal)
Bit [12] = Port 4 Fiber SD source, 1 = external, 0 = internal (default = internal)
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6-Port 10/100Mb Fast Ethernet Smart Switch
PHY ID #1
9
PHY ID #2
10
RESERVED
Port 4 MAC Control
Port 5 MAC Control
Auto Load Control #2
Switch Chip Control
11
12
13
14
Auto Load Control #3 15
Per-Port Control
Bit [15:13] = Reserved, set ZEROs
This word will be load into Port 0 ~ 4’s PHY ID register #1 (042H, 062H, 082H,
0A2H and 0C2H).
This word will be load into Port 0 ~ 4’s PHY ID register #2 (043H, 063H, 083H,
0A3H and 0C3H)
Reserved, set ZEROs
This word will be loaded into Port 4 MAC Control register 314H in its entirety
This word will be loaded into Port 5 MAC Control register 315H in its entirety
Bit [1:0] = 01: Load EEPROM word 18 ~ 22 for switch status & control
Bit [3:2] = 01: Load EEPROM word 23 ~ 24 for IGMP Snooping Control
Bit [5:4] = 01: Load EEPROM word 28 ~ 36 for priority mapping
Bit [7:6] = Reserved, set ZEROs
Bit [9:8] = 01: Load EEPROM word 48 ~ 93 for VLAN setting
Bit [15:10] = Reserved, set ZEROs
Bit [1:0] = 01: Load EEPROM word 128 ~ 143 for port 0 setting
Bit [3:2] = 01: Load EEPROM word 144 ~ 159 for port 1 setting
Bit [5:4] = 01: Load EEPROM word 160 ~ 175 for port 2 setting
Bit [7:6] = 01: Load EEPROM word 176 ~ 191 for port 3 setting
Bit [9:8] = 01: Load EEPROM word 192 ~ 207 for port 4 setting
Bit [11:10] = 01: Load EEPROM word 208 ~ 223 for port 5 setting
Bit [15:12] = Reserved, set ZEROs
Reserved, set ZEROs
Bit [6:0] of this word will be loaded to Switch Control register 212H bit [6:0],
respectively
This word will be loaded into CPU Port & Mirror Control register 213H in its
entirety
This word will be loaded into Special Tag Ether-Typel register 214H in its entirety
RESERVED
Switch Control
16~17
18
CPU Port & Mirror
Control
Special Tag
Ether-Type
Global Learning &
Aging Control
MIB Counter Disable
19
22
Bit [5:0] of this word will be loaded to Global Learning & Aging Control register
215H bit [5:0], respectively
Bit [5:0] of this word will be loaded to register 230H bit [5:0], respectively
Snooping Control 0
Snooping Control 1
RESERVED
VLAN Priority Map
Register
TOS Priority Map 0
TOS Priority Map 1
TOS Priority Map 2
TOS Priority Map 3
TOS Priority Map 4
TOS Priority Map 5
TOS Priority Map 6
TOS Priority Map 7
RESERVED
QinQ TPID Register
VLAN Mode & Rule
Control
23
24
25~27
28
Bit [7:0] of this word will be loaded to register 29BH bit [7:0], respectively
Bit [13:1] of this word will be loaded to register 29CH bit [13:1], respectively
Reserved, set ZEROs
This word will be loaded into register 217H in its entirety
29
30
31
32
33
34
35
36
37~47
48
49
This word will be loaded into register 218H in its entirety
This word will be loaded into register 219H in its entirety
This word will be loaded into register 21AH in its entirety
This word will be loaded into register 21BH in its entirety
This word will be loaded into register 21CH in its entirety
This word will be loaded into register 21DH in its entirety
This word will be loaded into register 21EH in its entirety
This word will be loaded into register 21FH in its entirety
Reserved, set ZEROs
This word will be loaded into register 23DH in its entirety
This word will be loaded into register 23EH in its entirety
20
21
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DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
VLAN Table - Valid
Control
VLAN Table - ID_0H
VLAN Table - ID_1H
VLAN Table - ID_2H
VLAN Table - ID_3H
VLAN Table - ID_4H
VLAN Table - ID_5H
VLAN Table - ID_6H
VLAN Table - ID_7H
VLAN Table - ID_8H
VLAN Table - ID_9H
VLAN Table - ID_AH
VLAN Table - ID_BH
VLAN Table - ID_CH
VLAN Table - ID_DH
VLAN Table - ID_EH
VLAN Table - ID_FH
VLAN Table MEMBER_0H
VLAN Table MEMBER_1H
VLAN Table MEMBER_2H
VLAN Table MEMBER_3H
VLAN Table MEMBER_4H
VLAN Table MEMBER_5H
VLAN Table MEMBER_6H
VLAN Table MEMBER_7H
VLAN Table MEMBER_8H
VLAN Table MEMBER_9H
VLAN Table MEMBER_AH
VLAN Table MEMBER_BH
VLAN Table MEMBER_CH
VLAN Table MEMBER_DH
VLAN Table MEMBER_EH
VLAN Table -
50
This word will be loaded into register 23FH in its entirety
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
This word will be loaded into register 250H in its entirety
This word will be loaded into register 251H in its entirety
This word will be loaded into register 252H in its entirety
This word will be loaded into register 253H in its entirety
This word will be loaded into register 254H in its entirety
This word will be loaded into register 255H in its entirety
This word will be loaded into register 256H in its entirety
This word will be loaded into register 257H in its entirety
This word will be loaded into register 258H in its entirety
This word will be loaded into register 259H in its entirety
This word will be loaded into register 25AH in its entirety
This word will be loaded into register 25BH in its entirety
This word will be loaded into register 25CH in its entirety
This word will be loaded into register 25DH in its entirety
This word will be loaded into register 25EH in its entirety
This word will be loaded into register 25FH in its entirety
Bit [13:0] of this word will be loaded to register 270H bit [13:0], respectively
68
Bit [13:0] of this word will be loaded to register 271H bit [13:0], respectively
69
Bit [13:0] of this word will be loaded to register 272H bit [13:0], respectively
70
Bit [13:0] of this word will be loaded to register 273H bit [13:0], respectively
71
Bit [13:0] of this word will be loaded to register 274H bit [13:0], respectively
72
Bit [13:0] of this word will be loaded to register 275H bit [13:0], respectively
73
Bit [13:0] of this word will be loaded to register 276H bit [13:0], respectively
74
Bit [13:0] of this word will be loaded to register 277H bit [13:0], respectively
75
Bit [13:0] of this word will be loaded to register 278H bit [13:0], respectively
76
Bit [13:0] of this word will be loaded to register 279H bit [13:0], respectively
77
Bit [13:0] of this word will be loaded to register 27AH bit [13:0], respectively
78
Bit [13:0] of this word will be loaded to register 27BH bit [13:0], respectively
79
Bit [13:0] of this word will be loaded to register 27CH bit [13:0], respectively
80
Bit [13:0] of this word will be loaded to register 27DH bit [13:0], respectively
81
Bit [13:0] of this word will be loaded to register 27EH bit [13:0], respectively
82
Bit [13:0] of this word will be loaded to register 27FH bit [13:0], respectively
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DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
MEMBER_FH
VLAN Table - Priority
Enable
VLAN Table - Priority
Replace Enable
VLAN Table - STP
Index Enable
VLAN Table - Misc_0
VLAN Table - Misc_1
VLAN Table - Misc_2
VLAN Table - Misc_3
VLAN Table - Misc_4
VLAN Table - Misc_5
VLAN Table - Misc_6
VLAN Table - Misc_7
RESERVED
P0 Basic Control 0
P0 Basic Control 1
P0 Block Contrl 0
P0 Block Contrl 1
P0 Bandwidth Control
P0 VLAN Tag
Infomation
P0 Priority & VLAN
Control
P0 Security Control
P0 Advanced Control
P0 Memory
Configuration
P0 Discard packet
limitation
RESERVED
P1 Basic Control 0
P1 Basic Control 1
P1 Block Contrl 0
P1 Block Contrl 1
P1 Bandwidth Control
P1 VLAN Tag
Infomation
P1 Priority & VLAN
Control
P1 Security Control
P1 Advanced Control
P1 Memory
Configuration
P1 Discard packet
limitation
RESERVED
83
This word will be loaded into register 290H in its entirety
84
This word will be loaded into register 291H in its entirety
85
This word will be loaded into register 292H in its entirety
86
87
88
89
90
91
92
93
94~127
128
129
130
131
132
133
This word will be loaded into register 293H in its entirety
This word will be loaded into register 294H in its entirety
This word will be loaded into register 295H in its entirety
This word will be loaded into register 296H in its entirety
This word will be loaded into register 297H in its entirety
This word will be loaded into register 298H in its entirety
This word will be loaded into register 299H in its entirety
This word will be loaded into register 29AH in its entirety
Reserved, set ZEROs
Bit [14:0] of this word will be loaded to register 111H bit [14:0], respectively
Bit [15:0] of this word will be loaded to register 112H bit [15:0], respectively
Bit [13:0] of this word will be loaded to register 113H bit [13:0], respectively
Bit [13:0] of this word will be loaded to register 114H bit [13:0], respectively
Bit [15:0] of this word will be loaded to register 115H bit [15:0], respectively
Bit [15:0] of this word will be loaded to register 116H bit [15:0], respectively
134
Bit [15:0] of this word will be loaded to register 117H bit [15:0], respectively
135
136
137
Bit [14:0] of this word will be loaded to register 118H bit [14:0], respectively
Bit [15:0] of this word will be loaded to register 119H bit [15:0], respectively
Bit [15:0] of this word will be loaded to register 11AH bit [15:0], respectively
138
Bit [15:0] of this word will be loaded to register 11BH bit [15:0], respectively
139~143
144
145
146
147
148
149
Reserved, set ZEROs
Bit [14:0] of this word will be loaded to register 131H bit [14:0], respectively
Bit [15:0] of this word will be loaded to register 132H bit [15:0], respectively
Bit [13:0] of this word will be loaded to register 133H bit [13:0], respectively
Bit [13:0] of this word will be loaded to register 134H bit [13:0], respectively
Bit [15:0] of this word will be loaded to register 135H bit [15:0], respectively
Bit [15:0] of this word will be loaded to register 136H bit [15:0], respectively
150
Bit [15:0] of this word will be loaded to register 137H bit [15:0], respectively
151
152
153
Bit [14:0] of this word will be loaded to register 138H bit [14:0], respectively
Bit [15:0] of this word will be loaded to register 139H bit [15:0], respectively
Bit [15:0] of this word will be loaded to register 13AH bit [15:0], respectively
154
Bit [15:0] of this word will be loaded to register 13BH bit [15:0], respectively
155~159
Reserved, set ZEROs
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DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
P2 Basic Control 0
P2 Basic Control 1
P2 Block Contrl 0
P2 Block Contrl 1
P2 Bandwidth Control
P2 VLAN Tag
Infomation
P2 Priority & VLAN
Control
P2 Security Control
P2 Advanced Control
P2 Memory
Configuration
P2 Discard packet
limitation
RESERVED
P3 Basic Control 0
P3 Basic Control 1
P3 Block Contrl 0
P3 Block Contrl 1
P3 Bandwidth Control
P3 VLAN Tag
Infomation
P3 Priority & VLAN
Control
P3 Security Control
P3 Advanced Control
P3 Memory
Configuration
P3 Discard packet
limitation
RESERVED
P4 Basic Control 0
P4 Basic Control 1
P4 Block Contrl 0
P4 Block Contrl 1
P4 Bandwidth Control
P4 VLAN Tag
Infomation
P4 Priority & VLAN
Control
P4 Security Control
P4 Advanced Control
P4 Memory
Configuration
P4 Discard packet
limitation
RESERVED
160
161
162
163
164
165
Bit [14:0] of this word will be loaded to register 151H bit [14:0], respectively
Bit [15:0] of this word will be loaded to register 152H bit [15:0], respectively
Bit [13:0] of this word will be loaded to register 153H bit [13:0], respectively
Bit [13:0] of this word will be loaded to register 154H bit [13:0], respectively
Bit [15:0] of this word will be loaded to register 155H bit [15:0], respectively
Bit [15:0] of this word will be loaded to register 156H bit [15:0], respectively
166
Bit [15:0] of this word will be loaded to register 157H bit [15:0], respectively
167
168
169
Bit [14:0] of this word will be loaded to register 158H bit [14:0], respectively
Bit [15:0] of this word will be loaded to register 159H bit [15:0], respectively
Bit [15:0] of this word will be loaded to register 15AH bit [15:0], respectively
170
Bit [15:0] of this word will be loaded to register 15BH bit [15:0], respectively
171~175
176
177
178
179
180
181
Reserved, set ZEROs
Bit [14:0] of this word will be loaded to register 171H bit [14:0], respectively
Bit [15:0] of this word will be loaded to register 172H bit [15:0], respectively
Bit [13:0] of this word will be loaded to register 173H bit [13:0], respectively
Bit [13:0] of this word will be loaded to register 174H bit [13:0], respectively
Bit [15:0] of this word will be loaded to register 175H bit [15:0], respectively
Bit [15:0] of this word will be loaded to register 176H bit [15:0], respectively
182
Bit [15:0] of this word will be loaded to register 177H bit [15:0], respectively
183
184
185
Bit [14:0] of this word will be loaded to register 178H bit [14:0], respectively
Bit [15:0] of this word will be loaded to register 179H bit [15:0], respectively
Bit [15:0] of this word will be loaded to register 17AH bit [15:0], respectively
186
Bit [15:0] of this word will be loaded to register 17BH bit [15:0], respectively
187~191
192
193
194
195
196
197
Reserved, set ZEROs
Bit [14:0] of this word will be loaded to register 191H bit [14:0], respectively
Bit [15:0] of this word will be loaded to register 192H bit [15:0], respectively
Bit [13:0] of this word will be loaded to register 193H bit [13:0], respectively
Bit [13:0] of this word will be loaded to register 194H bit [13:0], respectively
Bit [15:0] of this word will be loaded to register 195H bit [15:0], respectively
Bit [15:0] of this word will be loaded to register 196H bit [15:0], respectively
198
Bit [15:0] of this word will be loaded to register 197H bit [15:0], respectively
199
200
201
Bit [14:0] of this word will be loaded to register 198H bit [14:0], respectively
Bit [15:0] of this word will be loaded to register 199H bit [15:0], respectively
Bit [15:0] of this word will be loaded to register 19AH bit [15:0], respectively
202
Bit [15:0] of this word will be loaded to register 19BH bit [15:0], respectively
203~207
Reserved, set ZEROs
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DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
P5 Basic Control 0
P5 Basic Control 1
P5 Block Contrl 0
P5 Block Contrl 1
P5 Bandwidth Control
P5 VLAN Tag
Infomation
P5 Priority & VLAN
Control
P5 Security Control
P5 Advanced Control
P5 Memory
Configuration
P5 Discard packet
limitation
RESERVED
208
209
210
211
212
213
Bit [14:0] of this word will be loaded to register 1B1H bit [14:0], respectively
Bit [15:0] of this word will be loaded to register 1B2H bit [15:0], respectively
Bit [13:0] of this word will be loaded to register 1B3H bit [13:0], respectively
Bit [13:0] of this word will be loaded to register 1B4H bit [13:0], respectively
Bit [15:0] of this word will be loaded to register 1B5H bit [15:0], respectively
Bit [15:0] of this word will be loaded to register 1B6H bit [15:0], respectively
214
Bit [15:0] of this word will be loaded to register 1B7H bit [15:0], respectively
215
216
217
Bit [14:0] of this word will be loaded to register 1B8H bit [14:0], respectively
Bit [15:0] of this word will be loaded to register 1B9H bit [15:0], respectively
Bit [15:0] of this word will be loaded to register 1BAH bit [15:0], respectively
218
Bit [15:0] of this word will be loaded to register 1BBH bit [15:0], respectively
219~255
Reserved, set ZEROs
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6-Port 10/100Mb Fast Ethernet Smart Switch
6. Function Description
6.1 Switch function
6.1.1 Address Learning
The DM8606C/DM8606CI stores MAC addresses, port number and time stamp information in the Hash-based
Address Table. The table can learn up to 2K unicast address entries. The DM8606C/DM8606CI provides two
methods to learn address in the table, self-learning and manual learning.
Self-learning
The self-learning mechanism means the DM8606C/DM8606CI learn the MAC addresses of incoming packets in
real time without CPU’s assistance.
The switch engine creates a new entry if incoming packet’s Source Address (SA) does not exist and the packet is
valid (error-free). If SA was found and incoming port mismatch with port number in table, update the entry with SA
and incoming port number. Those entries will be created, updated or aged dynamically.
Besides, the DM8606C/DM8606CI has an option to disable address learning for individual port. This feature can
be set by bit 12 of per port register 11h (i.e. 111h, 131h, 151h, 171h, 191h, and 1B1h).
Manual Learning
The DM8606C/DM8606CI also provides manual learning mechanism with CPU’s assistance. The CPU can
create, update or delete entry for flexible management. In addition to above, the entry can be set as static one
that will not be aged-out.
6.1.2 Address Aging
The time stamp information of address table is used in the aging process. The switch engine updates time
stamp whenever the corresponding SA receives. The switch engine would delete the entry if its time stamp is not
updated for a period of time. The period can be programmed or disabled through bit 0 & 1 of register 215h
6.1.3 Packet Forwarding
The DM8606C/DM8606CI forwards the incoming packet according to following decision:
(1). If Destination Address (DA) is multicast/broadcast, the packet is forwarded to all ports, except to the port
on which the packet was received.
(2). Switch engine would look up address table based on DA when incoming packets is uni-cast. If the DA was
not found in address table, the packet is treated as a multicast packet and forward to other ports. If the DA was
found and its destination port number is different to source port number, the packet is forward to destination port.
(3). Switch engine also look up VLAN, Port Monitor setting and other forwarding constraints for the forwarding
decision, more detail will discuss in later sections.
The DM8606C/DM8606CI will filter incoming packets under following conditions:
(1). Error packets, including CRC errors, alignment errors, illegal size errors.
(2). IEEE 802.3X PAUSE packets.
(3). If incoming packet is uni-cast and its destination port number is equal to source port number
.
6.1.4 Inter-Packet Gap (IPG)
IPG is the idle time between any two valid packets at the same port. The typical number is 96 bits time. In other
word, the value is 9.6u sec for 10Mbps and 960n sec for 100Mbps.
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6-Port 10/100Mb Fast Ethernet Smart Switch
6.1.5 Back-off Algorithm
The DM8606C/DM8606CI implements the binary exponential back-off algorithm in half-duplex mode compliant to
IEEE standard 802.3.
6.1.6 Late Collision
Late Collision is a type of collision. If a collision error occurs after the first 512 bit times of data are transmitted, the
packet is dropped.
6.1.7 Half Duplex Flow Control
The DM8606C/DM8606CI supports half-duplex backpressure. The inducement is the same as full duplex mode.
When flow control is required, the DM8606C/DM8606CI sends jam pattern and results in a collision.
6.1.8 Full Duplex Flow Control
The DM8606C/DM8606CI supports IEEE standard 802.3x flow control frames on both transmit and receive sides.
On the receive side, The DM8606C/DM8606CI will defer transmitting next normal frames, if it receives a pause
frame from link partner.
On the transmit side, The DM8606C/DM8606CI issues pause frame with maximum pause time when internal
resources such as received buffers, transmit queue and transmit descriptor ring are unavailable. Once resources
are available, The DM8606C/DM8606CI sends out a pause frame with zero pause time allows traffic to resume
immediately.
6.1.9 Partition Mode
The DM8606C/DM8606CI provides a partition mode for each port. The port enters partition mode when more
than 64 consecutive collisions are occurred. In partition mode the port continuous to transmit but it will not receive.
The port returned to normal operation mode when a good packet is seen on the wire. The detail description of
partition mode represent following:
(1). Entering Partition State
A port will enter the Partition State when either of the following conditions occurs:

The port detects a collision on every one of 64 consecutive re-transmit attempts to the same packet.

The port detects a single collision which occurs for more than 512 bit times.

Transmit defer timer time out, which indicates the transmitting packet is deferred to long.
(2). While in Partition state:
The port will continue to transmit its pending packet, regardless of the collision detection, and will not allow the
usual Back-off Algorithm. Additional packets pending for transmission will be transmitted, while ignoring the
internal collision indication. This frees up the ports transmit buffers which would otherwise be filled up at the
expense of other ports buffers. The assumption is that the partition is signifying a system failure situation (bad
connection/cable/station), thus dropping packets is a small price to pay vs. the cost of halting the switch due to a
buffer full condition.
(3). Exiting from Partition State
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6-Port 10/100Mb Fast Ethernet Smart Switch
The Port exits from Partition State, following the end of a successful packet transmission. A successful packet
transmission is defined as no collisions were detected on the first 512 bits of the transmission.
6.1.10 Broadcast Storm Filtering
The DM8606C/DM8606CI has an option to limit the traffic of broadcast or multicast packets, to protect the switch
from lower bandwidth availability.
There are two types of broadcast storm control, one is throttling broadcast packet only, the other includes
multicast. This feature can be set through bit 12 of per port register 12h.
The broadcast storm threshold can be programmed by EEPROM or per port register 5h, the default setting is no
broadcast storm protecting.
6.1.11 Bandwidth Control
The DM8606C/DM8606CI supports two types of bandwidth control for each port. One is the ingress and egress
bandwidth rate can be controlled separately, the other is combined together, this function can be set through bit
14 of per port register 12h. The bandwidth control is disabled by default.
To separate bandwidth control mode, the threshold rate is defined in per port register 5h. For combined mode, it
is defined in bit 3~0 of per port register 15h.
The behavior of bandwidth control as below:
(1).For the ingress control, if flow control function is enabled, Pause or Jam packet will be transmitted. The
ingress packets will be dropped if flow control is disabled.
(2).For the egress control, the egress port will not transmit any packets. On the other hand, the ingress
bandwidth of source port will be throttled that prevent packets from forwarding.
(3).In combined mode, if the sum of ingress and egress bandwidth over threshold, the bandwidth will be
throttled.
.
6.1.12 Port Monitoring Support
The DM8606C/DM8606CI supports “Port Monitoring” function on per port base, detail as below:
(1). Sniffer Port and Monitor Port
There is only one port can be selected as “sniffer port” by bit 5~3 of register 213h, multiple ports can be set as
“receive monitor port” or “transmit monitor port” in per-port register 11h.
(2).Receive monitor
All packets received on the “receive monitor port” are send a copy to “sniffer port”. For example, port 0 is set
as “receive monitor port” and port 2 is selected as a “sniffer port”. If a packet is received form port 0 and
predestined to port 1 after forwarding decision, the DM8606C/DM8606CI will forward it to port 1 and port 2 in the
end.
(3).Transmit monitor
All packets transmitted on the “transmit monitor port” are send a copy to “sniffer port”. For example, port 1 is
set as “transmit monitor port” and port 2 is selected as “sniffer port”. If a packet is received from port 0 and
predestined to port 1 after forwarding decision, the DM8606C/DM8606CI will forward it to port 1 and port 2 in the
end.
(4).Exception
The DM8606C/DM8606CI has an optional setting that broadcast/multicast packets are not monitored (see bit
11 of per port register 12h). It’s useful to avoid unnecessary bandwidth.
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6.1.13 VLAN Support
6.1.13.1 Port-Based VLAN
The DM8606C/DM8606CI supports port-based VLAN as default, up to 16 groups. Each port has a default VID
called PVID (Port VID, in bit 11~0 of per port register 16H). The DM8606C/DM8606CI used 12 bits PVID as index
and mapped with registers 250H~25FH to define the VLAN groups.
6.1.13.2 802.1q-Based VLAN
Regarding IEEE 802.1Q standard, Tag-based VLAN uses an extra tag to identify the VLAN membership of a
frame across VLAN-aware switch/router. A tagged frame is four bytes longer than an untagged frame and
contains two bytes of TPID (Tag Protocol Identifier) and two bytes of TCI (Tag Control Information).
Dest.
Src.
Dest.
Src.
Length/Type
TPID
TCI
Data
Length / Type
Standard frame
Data
Tagged frame
0x8100
2 bytes
Priority
3 bits
CFI
1 bits
VID
12 bits
The DM8606C/DM8606CI also supports 16 802.1Q-based VLAN groups, as specified in bit 0 of register 23Eh.
It’s obvious that the tagged packets can be assigned to several different VLANs which are determined according
to the VID inside the VLAN Tag. Therefore, the operation is similar to port-based VLAN. The
DM8606C/DM8606CI used full 12 bits VID of received packet with VLAN tag and VLAN table ID registers
(250h~25Fh) and then define members by VLAN Group Mapping Register (270h~27Fh) to configure the VLAN
partition. If the destination port of received packet is not same VLAN group with received port, it will be discarded.
6.1.13.3 Tag/Untag
User can define each port as Tag port or Un-tag port by bit 14 of per port register 17h in 802.1Q-based VLAN
mode. The operation of Tag and Un-tag can explain as below conditions:
(1). Receive untagged packet and forward to Un-tag port.
Received packet will forward to destination port without modification.
(2). Receive tagged packet and forward to Un-tag port.
The DM8606C/DM8606CI will remove the tag from the packet and recalculate CRC before sending it out.
(3). Receive untagged packet and forward to Tag port.
The DM8606C/DM8606CI will insert the PVID tag when an untagged packet enters the port, and
recalculate CRC before delivering it.
(4). Receive tagged packet and forward to Tag port.
Received packet will forward to destination port without modification.
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6.1.14 Special Tag
The Special Tag function provided by the DM8606C/DM8606CI is used to exchange control and status
information between Switch and CPU within frame. An extra 4-bytes tag is added into frame to carry different
content according to direction of special tag frame. Received special tag (CPU  Switch) specifies the desired
port mapping of packet sent by CPU and some configurations about frame handle rules. Transmitted special tag
(Switch  CPU) indicates the source port number of incoming frame.
The following figure shows special tag frame format. In left 2 bytes of special tag field, there is an identifier
called Special Tag Ether-Type that can use to recognize special tag frame. The value of this field can be set by
REG 23DH.
The detail information carried by received special tag is described as below. Through received special tag,
CPU can tell switch the handle rule per frame over the internal setting. This feature can be enabled through REG
213H bit 6.
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Received Special Tag(CPU  Switch) 4-byte Format:
Byte 0/1
[15:0]
Special Tag Ether-Type (Default: 0x8086)
Byte 2
[7]
Reserved
Byte 2
[6]
ST_PMAP_en, ST_PMAP Enable
Byte 2
[5:0]
ST_PMAP, Force to assign forwarding port map
Byte 3
[7]
Reserved
Byte 3
[6]
ST_CVLAN, Cross VLAN
0: This frame obeys VLAN boundary.
1: This frame can cross VLAN boundary.
Byte 3
[5]
ST_LRN_DIS, Disable learning
0: This frame will be learned
1: This frame will not be learned
Byte 3
[4]
ST_PRI_EN, ST_PRI Enable
Byte 3
[3:2]
ST_PRI, Priority Queue Number (0~3)
00: Queue 0
01: Queue 1
10: Queue 2
11: Queue 3
Byte 3
[1:0]
ST_TAG
00: Unmodified
01: Always Tagged
10: Always Untagged
11: Reserved
Beside, transmitted special tag is used to indicate source port number. CPU can use this message to judge
the incoming port number of the frame. REG 213H bit 7 can enable this feature by setting to 1.
Transmitted Special Tag (Switch  CPU) 4-byte Format:
Byte 0/1
[15:0]
Special Tag Ether-Type (Default: 0x8086)
Byte 2
[7:3]
Reserved
Byte 2
[2:0]
ST_SPORT, Source Port Number (0~5)
Byte 3
[7:0]
Reserved
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6.1.15 Priority Support
The DM8606C/DM8606CI supports Quality of Service (QoS) mechanism for multimedia communication such as
VoIP and video conferencing.
The DM8606C/DM8606CI provides three priority classifications: Port-based, 802.1p-based and DiffServ-based
priority. See next section for more detail. The DM8606C/DM8606CI offers four level queues for transmit on
per-port based.
The DM8606C/DM8606CI provides two packet scheduling algorithms: Weighted Fair Queuing and Strict Priority
Queuing. Weighted Fair Queuing (WFQ) based on their priority and queue weight. Queues with larger weights
get more service than smaller. This mechanism can get highly efficient bandwidth and smooth the traffic. Strict
Priority Queuing (SPQ) based on priority only. The Packet on the highest priority queue is transmitted first. The
next highest-priority queue is work until last queue empties, and so on. This feature can be set in bit 5 of per port
register 17H.
6.1.15.1 Port-Based Priority
Port based priority is the simplest scheme and as default. Each port has a 2-bit priority value as index for splitting
ingress packets to the corresponding transmit queue. This value can be set in bit 1~0 of per port register 17H.
6.1.15.2 802.1p-Based Priority
The DM8606C/DM8606CI extracts 3-bit priority field from received packet with 802.1p VLAN tag, and maps this
field against VLAN Priority Map Registers 217H to determine which transmit queue is designated. The VLAN
Priority Map is programmable.
6.1.15.3 DiffServ-Based Priority
DiffServ based priority uses the most significant 6-bit of the ToS field in standard IPv4 header, and maps this field
against ToS Priority Map Registers (218H~21FH) to determine which transmit queue is designated. The ToS
Priority Map is programmable too. In addition, User can only refer to most significant 3-bit of the ToS field
optionally, see bit 7 of register 23EH.
6.1.16 Address Table Accessing
6.1.16.1 Type of Address Table
There are three types of address table in the DM8606C/DM8606CI. The description is represented below:
(1). Unicast Address Table
This table is used for destination MAC address lookup and source MAC address learning. The table can have
up to 2048 entries. If the table is full, the latest one will kick out the eldest one. The programming method can
refer to next section.
(2). Multicast Address Table
The table that stores multicast addresses shares with unicast address table and can be maintained by host
CPU for custom filtering and forwarding multicast packets. If the table is full, the latest one will kick out the eldest
one. All of entries in multicast address table are static one. In addition to host CPU, multicast address table can
be manipulated by internal switch engine, if hardware-based IGMP Snooping function is enabled.
(3). IGMP Membership Table
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This table is used to establish IPv4 multicast forwarding rule under IGMP protocol if hardware-based IGMP
Snooping function is enabled. It is automatic maintained by internal engine according to snooping IGMP control
packets, and can only support to read out by the host CPU. The maximum of entries of table is 32. If the table is
full, never join anymore
.
6.1.16.2 Access Rules of Address Table
In DM8606C/DM8606CI, unicast and multicast address table support “Write”, “Delete”, ”Search”, “Read” and
“Clear” commands. However, for IGMP membership table, there are only three different type commands such as
“Write”, “Delete” and “Read”. The DM8606C/DM8606CI procedure and flow chart of Entry Access is described as
following:

Entry Write
(1). Check the busy bit of Address Table Control & Status Register (Reg2B0H.15) to seek the availability of
access engine. Waiting until engine is available and to keep on following.
(2). Write the MAC address to the Address Table Data 1~3 Registers (Reg2B2H~2B4H).
(3). Write the Port Number or Port Map to Address Table Data 0 Register (Reg2B1.[2:0]).
(4). If need, write the entry’s attribute such as static to Address Table Data 4 Register (Reg2B5H.0).
(5). Write the “WRITE” command and assign the target table to Address Table Control & Status Register
(Reg2B0H.[4:0]) to start the operation.
(6). Check the busy bit again, wait for available.
(7). Read the command status from Address Table Control & Status Register (Reg2B0H.[14:13])

Entry Delete
(1). Check the busy bit of Address Table Control & Status Register (Reg2B0H.15) to seek the availability of
access engine. Waiting until engine is available and to keep on following.
(2). Write the MAC address to the Address Table Data 1~3 Registers (Reg2B2H~2B4H).
(3). Write the “DELETE” command and assign the target table to Address Table Control & Status Register
(Reg2B0H.[4:0]) to start the operation
(4). Check the busy bit again, wait for available.
(5). Read the command status from Address Table Control & Status Register (Reg2B0H.[14:13]).

Entry Search
(1). Check the busy bit of Address Table Control & Status Register (Reg2B0H.15) to seek the availability of
access engine. Waiting until engine is available and to keep on following.
(2). Write the MAC address to the Address Table Data 1~3 Registers (Reg2B2H~2B4H).
(3). Write the “SEARCH” command and assign the target table to Address Table Control & Status Register
(Reg2B0H.[4:0]) to start the operation.
(4). Check the busy bit again, wait for available.
(5). Read the command status from Address Table Control & Status Register (Reg2B0H.[14:13]).
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(6). Read the Port Number or Port Map to Address Table Data 0 Register (Reg2B1.[2:0]).
(7). If need, read the entry sequence (the sequence number of entry in address table) from Address Table Data 1
Register (Reg2B2H).
(8). If need, read the entry’s attributes that include static (unicast address table only) and IGMP Entry (multicast
address table only) from Address Table Data 4 Register (Reg2B5H.0 for static and Reg2B5h.12 for IGMP
Entry).

Entry Read
(1). Check the busy bit of Address Table Control & Status Register (Reg2B0H.15) to seek the availability of
access engine. Waiting until engine is available and to keep on following.
(2). Write the entry sequence to the Address Table Data 1 Register (Reg2B2H).
(3). Write the “READ” command and assign the target table to Address Table Control & Status Register
(Reg2B0H.[4:0]) to start the operation.
(4). Check the busy bit again, wait for available.
(5). Read the command status from Address Table Control & Status Register (Reg2B0H.[14:13]).
(6). Read the Port Number or Port Map to Address Table Data 0 Register (Reg2B1.[2:0]).
(7). If target is unicast or multicast address table, read the entry’s MAC address from Address Table Data 1~3
Register (Reg2B2H~2B4H). If target is IGMP membership table, read the real memory address from
Address Table Data 1 Register (Reg2B2H.[10:0]).
(8). If target is unicast address table, read the entry’s attributes such as static from Address Table Data 4
Register (Reg2B5H.0). For multicast address table, IGMP Entry can be read from Address Table Data 4
Register (Reg2B5H.[12]). For IGMP membership table, IGMP valid signal and per-port aged timer can be
read from Address Table Data 2~3 Register (Reg2B3H.[2:0], Reg2B4H.[5:0]).

Entry Clear
(1). Check the busy bit of Address Table Control & Status Register (Reg2B0H.15) to seek the availability of
access engine. Waiting until engine is available and to keep on following.
(2). Write the “Clear” command and assign the target table to Address Table Control & Status Register
(Reg2B0H.[4:0]) to start the operation.
(3). Wait at least 4.5ms for clear procedure is done.
(4). Check the busy bit again, wait for available.
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6.1.17 IGMP Snooping
The Internet Group Management Protocol (IGMP) is a communications protocol used to manage the
membership of Internet Protocol multicast groups. IGMP is used by IP hosts and adjacent multicast routers to
establish multicast group memberships. There are three versions of IGMP, as defined by "Request for
Comments" (RFC) documents of the Internet Engineering Task Force (IETF). IGMP v1 is defined by RFC 1112,
IGMP v2 is defined by RFC 2236 and IGMP v3 is defined by RFC 3376.
IGMP snooping is a feature that allows the switch to "listen in" on the IGMP protocol conversation between
hosts and routers. The IGMP snooping switch hears an IGMP report from a host with a given multicast group
address. It adds the host's port number to the multicast list for that group, and when the switch hears an IGMP
Leave, it removes the host's port from the table entry. Finally, switch will only forward multicast traffic to the hosts
interested in that traffic. Therefore, this function can effectively reduce multicast traffic.
DM8606C/DM8606CI supports two types of IGMP Snooping, software-based and hardware-based.
6.1.17.1 Software-Based IGMP Snooping
If packet that is IGMP packet (the protocol field is 02H in the header of IPv4 packet) would be forward to CPU
port when IGMP Snooping is enabled and in software-based mode. In this mode, the supported version of IGMP
and the maximal entries depend on software implementation. CPU receives and parses the IGMP packets, and
then set the MAC address and port map in Multicast Address Table.
For example:
(1). If receiving V1REPORT or V2REPORT (i.e. Join), translate the Multicast IP address to MAC address first,
and then write the MAC address and source port number to Multicast Address Table.
(2). If receiving LEAVE and Fast Leave function is enabled, translate the Multicast IP and delete the entry directly.
(3). If the time (Query Interval * Robust Variable + Max Response Time, 260sec default) is expired which means
the entry never be updated, delete the entry in Multicast Address Table.
(4). Entry delete may mean to clear the owned port bit on the port map when there are other occupied. Otherwise,
delete the entry via delete command.
6.1.17.2 Hardware-Based IGMP Snooping
The DM8606C/DM8606CI supports IGMP v1/v2 snooping and the maximal group is 32 without any software
effort in this mode. The DM8606C/DM8606CI automatically manipulates and updates IGMP membership table
and Multicast table according to IGMP control packets, such as membership report and leave.
If IGMP membership table is full, the later incoming IGMP Membership Report (Join) packet will be ignored
and the group address won’t be registered into multicast address table. After that, the unregistered IP multicast
packets (the destination MAC address can not be found in the multicast address table) will be treated as normal
multicast packets by default. The additional forwarding control method can see the register Reg29BH.[3:2].
The DM8606C/DM8606CI supports router ports auto-detect and auto-aging mechanism. The port which
receives IGMP Query packets will be treated as router port by default. The router port also can be define as static
one by user (see Reg29BH.7) and the port map of the router port can be programmed at Reg29BH.[10:8]. Keep
in mind that the CPU port is never treated as router port. The DM8606C/DM8606CI leaves the router port if the
time (Router Present Timeout, 400sec by default) is expired that the port never receives IGMP Query during this
period.
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If receiving V1REPORT or V2REPORT (group join), DM8606C/DM8606CI creates new or updates the entry.
If receiving LEAVE, DM8606C/DM8606CI deletes the entry directly when Fast Leave is enabled, or waiting until
timeout.
DM8606C/DM8606CI removes the entry that was never updated after the timer of host timeout (Group
Membership Interval) is expired. This timer is programmable in DM8606C/DM8606CI and defined by RFC 2236
as ((the Robustness Variable) times (the Query Interval)) plus (one Query Response Interval). The setting of the
Robustness Variable and the Query Interval can see Reg29CH.
6.1.18 IPv6 MLD Snooping
The DM8606C/DM8606CI forwards the IPv6 Multicast Listener Discovery (MLD) packets to the processor port when MLD
Snooping is enabled and the MLD packets meet following scenario:

IPv6 Multicast packets.

The Hop Limit in IPv6 header is 1.

The Next Header in IPv6 header is 0x3A (ICMPv6) or 0x00 (and next header of hop-by-hop option header is 0x3A).

The Type in ICMP header is 0x82 (Multicast Listener Query), 0x83 (Multicast Listener Report) or 0x84 (Multicast Listener
Done).
6.1.19 STP / RSTP Support
DM8606C/DM8606CI supports both Spanning Tree Protocol(STP) and Rapid Spanning Tree Protocol(RSTP).
There are five types of STP Port State (Disabled, Blocking, Listening, Learning and Forwarding state) and three
types of RSTP Port State (Discarding, Learning and Forwarding) for these two protocols. The following figure is
the port state diagram of STP.
P ow er-on
Initialization
B locking
State
L istening
State
D isabled
State
L earning
State
Forw arding
State
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But in RSTP, there are only three port states. The port states comparison between STP and RSTP are listed
as below.
STP Port State
RSTP Port State
Disabled
Discarding
Blocking
Discarding
Listening
Discarding
Learning
Learning
Forwarding
Forwarding
For compatibility and design consideration, this function needs the cooperation with external CPU. Moreover,
the behavior of Disabled/Blocking/Listening states in STP must be equal to the behavior of Discarding state in
RSTP in DM8606C/DM8606CI. The difference between STP and RSTP should be implemented by CPU. The
following statement describes the STP/RSTP port state behavior and software action in DM8606C/DM8606CI.
(1). Disable State:

Drop all packets including BPDUs
 Implemented by transmitting BPDUs to CPU and CPU drops BPDUs.

Learning is disabled.

Does not transmit BPDUs received from CPU
 Implemented by CPU does not send BPDUs to this port
(2). Blocking State:

Drop all packets except BPDUs and transmit received BPDUs to CPU.

Learning is disabled.

Does not transmit BPDUs received from CPU
(3). Listening State:

Drop all packets except BPDUs and tranmit received BPDUs to CPU

Learning is disabled.

Forward BPDUs received from CPU
 Implemented by CPU uses special tag function to send BPDUs to decided port
(4). Learning State:

Drop all packets except BPDUs and transmit received BPDUs to CPU

Learning is enabled

Forward BPDUs received from CPU
(5). Forwarding State:
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
Forward all packets

Learning is enabled

Forward BPDUs received from CPU
Base on the behavior of different states described above, DM8606C/DM8606CI has a port states setting for
both STP and RSTP in per-port register 19h, . The register setting is：
i.
00： Forwarding
ii.
01： Disabled / Discarding
iii.
10： Learning
iv.
11： Blocking / Listening
The following flow diagram shows how to configure STP/RSTP function.
Start
Set Reg292h to enable STP/RSTP
Set Port States to Per-Port Register 0x19
[1:0] STPS0
00: Forwarding
01: Disabled/Discarding
10: Learning
11: Blocking / Listening
STP/RSTP Setting
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6.2
Host SMI Interface
Host SMI
SMI_CK
SMI_DIO
MDC
MDIO
Host / MAC
Only one host is allowed to acccess the SMI_CK, SMI_DIO
DM8606C/
DM8206
DM8606CI
Host SMI - Read Frame Structure
SMI_CK
SMI_DIO Read
32 "1"s
Idle
0
Preamble
1
SFD
1
0
R9
R8
R7
R6
R5
R0
Register Address
Op Code
//
//
Z
0
D15
D14
D1
Turn Around
D0
Idle
Data
Read
Write
Host SMI - Write Frame Structure
SMI_CK
SMI_DIO Write
32 "1"s
Idle
Preamble
0
1
SFD
0
1
Op Code
R9
R8
R7
R6
Register Address
Write
R5
R0
1
0
Turn Around
D15
D14
Data
D1
D0
Idle
The internal registers of DM8606C/DM8606CI can be accessed by Host Serial Management Interface (SMI). The
application of SMI illustrated as below.
1. The Host SMI consists of two pins, one is SMI_CK and another is SMI_DIO. User can access
DM8606C/DM8606CI’s EEPROM, PHY registers, MIB counters and Configuration registers through Host SMI.
The format is following. 32 bit “1” preamble field, “01” <SFD> field, <OpCode> field (“10” for read, “”01” for write),
the <Register Address> field of the frame is mapped to address of control and status register set of
DM8606C/DM8606CI, and the 16-bit <Data> field for read/writ data.
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6.2.2 Host SMI Bus Error Check Function
To prevent the host SMI bus to be interfered by noise on board-level. This function is used to check the
command validity to suppress the mistaken command. In write procedure, the written value in register will be
applied until the correct checksum is written (error proofing) and user can read status for validation (error
detecting). In read procedure, user can compare hardware calculated checksum with software calculated one to
validate the result.
For example:
Write Procedure

(1). Set register 33AH.[0] = 1 to enable SMI Bus Error Check function
(2). Write data to DM8606C/DM8606CI's register (general write command)
(3). CPU calculate checksum (CSUM[7:0]) and write it to register 339H.[7:0]
(4). Check function status in register 339H.[8]
Read Procedure

(1). Set register 33AH.[0] = 1 to enable SMI Bus Error Check function
(2). Read data from DM8606C/DM8606CI's register (general read command)
(3). Read hardware calculated checksum from register 339H.[7:0] and compare it with CPU calculated one
(CSUM[7:0])
Checksum calculate formula:
CSUM[0]
=
D[0]
^
D[8]
^
R[0]
^
R[8]
CSUM[1]
=
D[1]
^
D[9]
^
R[1]
^
R[9]
CSUM[2]
=
D[2]
^
D[10]
^
R[2]
^
OP[0]
CSUM[3]
=
D[3]
^
D[11]
^
R[3]
^
OP[1]
CSUM[4]
=
D[4]
^
D[12]
^
R[4]
CSUM[5]
=
D[5]
^
D[13]
^
R[5]
CSUM[6]
=
D[6]
^
D[14]
^
R[6]
CSUM[7]
=
D[7]
^
D[15]
^
R[7]
Note:
D[15:0]
=
<Data> field of SMI frame
R[9:0]
=
<Register Address> field of SMI frame
OP[1:0]
=
<Op Code> field of SMI frame
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6.3 LED Mode Control
LED mode
Bit [1:0] of register 317H
P0~4_LNK_LED
P0~4_SPD_LED
P0~4_FDX_LED
P0~4_LNK_LED
P0~4_SPD_LED
“00” : LED mode 0
“01” : LED mode 1, dual color mode
“10” : LED mode 2
“11” : LED mode 3 (default)
LED mode 0
100M link + Activity
OFF: 100M link fail
ON : 100M link ok and no TX/RX activity
BLINK: 100M link ok and TX/RX activity
Collision
OFF: no collision
BLINK: collision
10M link + Activity
OFF: 10M link fail
ON: 10M link ok and no TX/RX activity
BLINK: 10M link ok and TX/RX activity
LED mode 1 (Dual color mode)
Application circuit :
LNK_LED
100M link/act
10M link/act
SPD_LED
LNK_LED
SPD_LED
link off
HI
HI
100M link
HI
LO
BLINK
LO
10M link
LO
HI
10M link / activity
LO
BLINK
100M link / activity
P0~4_FDX_LED
Full / half duplex mode
OFF: half-duplex
ON: full-duplex
BLINK: half-duplex and collision
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6-Port 10/100Mb Fast Ethernet Smart Switch
P0~4_LNK_LED
P0~4_SPD_LED
P0~4_FDX_LED
LED mode 2
100M link + Activity
OFF: 100M link fail
ON: 100M link ok and no TX/RX activity
BLINK: 100M link ok and TX/RX activity
Full / half duplex mode
OFF: half-duplex
ON: full-duplex
BLINK: half-duplex and collision
10M link + Activity
OFF: 10M link fail
ON: 10M link ok and no TX/RX activity
BLINK: 10M link ok and TX/RX activity
LED mode 3 (Default)
link + Activity
OFF: link fail
ON,: link ok and no TX/RX activity
BLINK: link ok and TX/RX activity
P0~4_SPD_LED
Speed
OFF: 10M mode or link OFF
ON: 100M mode link
P0~4_FDX_LED
Full / half duplex mode
OFF: half-duplex
ON: full-duplex
BLINK: half-duplex and collision
Where OFF means in floating state
ON means in ground state if LED is low active, or in high voltage state if LED is high active
BLINK means in toggle state with ON 20ms and OFF 80ms
HI means in high voltage state
LO means in ground state
P0~4_LNK_LED
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6-Port 10/100Mb Fast Ethernet Smart Switch
Preliminary
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6-Port 10/100Mb Fast Ethernet Smart Switch
6.4 Internal PHY functions
6.4.1 100Base-TX Operation
The transmitter section contains the following functional blocks:
- 4B5B Encoder
- Scrambler
- Parallel to Serial Converter
- NRZ to NRZI Converter
- NRZI to MLT-3
- MLT-3 Driver
6.4.1.1 4B5B Encoder
The 4B5B encoder converts 4-bit (4B) nibble data generated by the MAC Reconciliation Layer into a 5-bit (5B)
code group for transmission, see reference Table 1. This conversion is required for control and packet data to be
combined in code groups. The 4B5B encoder substitutes the first 8 bits of the MAC preamble with a J/K
code-group pair (11000 10001) upon transmit. The 4B5B encoder continues to replace subsequent 4B preamble
and data nibbles with corresponding 5B code-groups. At the end of the transmit packet, upon the deassertion of
the Transmit Enable signal from the MAC Reconciliation layer, the 4B5B encoder injects the T/R code-group pair
(01101 00111) indicating the end of frame. After the T/R code-group pair, the 4B5B encoder continuously injects
IDLEs into the transmit data stream until Transmit Enable is asserted and the next transmit packet is detected.
6.4.1.2 Scrambler
The scrambler is required to control the radiated emissions (EMI) by spreading the transmit energy across the
frequency spectrum at the media connector and on the twisted pair cable in 100Base-TX operation.
By scrambling the data, the total energy presented to the cable is randomly distributed over a wide frequency
range. Without the scrambler, energy levels on the cable could peak beyond FCC limitations at frequencies
related to the repeated 5B sequences, like the continuous transmission of IDLE symbols. The scrambler output is
combined with the NRZ 5B data from the code-group encoder via an XOR logic function. The result is a
scrambled data stream with sufficient randomization to decrease radiated emissions at critical frequencies.
6.4.1.3 Parallel to Serial Converter
The Parallel to Serial Converter receives parallel 5B scrambled data from the scrambler, and serializes it
(converts it from a parallel to a serial data stream). The serialized data stream is then presented to the
NRZ to NRZI encoder block
6.4.1.4 NRZ to NRZI Encoder
After the transmit data stream has been scrambled and serialized, the data must be NRZI encoded for
compatibility with the TP-PMD standard, for 100Base -TX transmission over Category-5 unshielded twisted pair
cable.
6.4.1.5 MLT-3 Converter
The MLT-3 conversion is accomplished by converting the data stream output, from the NRZI encoder into two
binary data streams, with alternately phased logic
one event.
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DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
6.4.1.6 MLT-3 Driver
The two binary data streams created at the MLT-3 converter are fed to the twisted pair output driver, which
converts these streams to current sources and alternately drives either side of the transmit transformer’s primary
winding, resulting in a minimal current MLT-3 signal.
6.4.1.7 4B5B Code Group
Symbol
Meaning
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data A
Data B
Data C
Data D
Data E
Data F
4B code
3210
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
5B Code
43210
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
I
J
K
T
R
H
Idle
SFD (1)
SFD (2)
ESD (1)
ESD (2)
Error
undefined
0101
0101
undefined
undefined
undefined
11111
11000
10001
01101
00111
00100
V
V
V
V
V
V
V
V
V
V
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
00000
00001
00010
00011
00101
00110
01000
01100
10000
11001
Table 1
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6-Port 10/100Mb Fast Ethernet Smart Switch
6.4.2 100Base-TX Receiver
The 100Base-TX receiver contains several function blocks that convert the scrambled 125Mb/s serial data to
synchronous 4-bit nibble data.
The receive section contains the following functional blocks:
- Signal Detect
- Digital Adaptive Equalization
- MLT-3 to Binary Decoder
- Clock Recovery Module
- NRZI to NRZ Decoder
- Serial to Parallel
- Descrambler
- Code Group Alignment
- 4B5B Decoder
6.4.2.1 Signal Detect
The signal detect function meets the specifications mandated by the ANSI XT12 TP-PMD 100Base-TX standards
for both voltage thresholds and timing parameters.
6.4.2.2 Adaptive Equalization
When transmitting data over copper twisted pair cable at high speed, attenuation based on frequency becomes a
concern. In high speed twisted pair signaling, the frequency content of the transmitted signal can vary greatly
during normal operation based on the randomness of the scrambled data stream. This variation in signal
attenuation, caused by frequency variations, must be compensated for to ensure the integrity of the received data.
In order to ensure quality transmission when employing MLT-3 encoding, the compensation must be able to
adapt to various cable lengths and cable types depending on the installed environment. The selection of long
cable lengths for a given implementation requires significant compensation, which will be over-killed in a situation
that includes shorter, less attenuating cable lengths. Conversely, the selection of short or intermediate cable
lengths requiring less compensation will cause serious under-compensation for longer length cables. Therefore,
the compensation or equalization must be adaptive to ensure proper conditioning of the received signal
independent of the cable length.
6.4.2.3 MLT-3 to NRZI Decoder
The DM8606C/DM8606CI decodes the MLT-3 information from the Digital Adaptive Equalizer into NRZI data.
6.4.2.4 Clock Recovery Module
The Clock Recovery Module accepts NRZI data from the MLT-3 to NRZI decoder. The Clock Recovery Module
locks onto the data stream and extracts the 125MHz reference clock. The extracted and synchronized clock and
data are presented to the NRZI to NRZ decoder.
6.4.2.5 NRZI to NRZ
The transmit data stream is required to be NRZI encoded for compatibility with the TP-PMD standard for
100Base-TX transmission over Category-5 unshielded twisted pair cable. This conversion process must be
reversed on the receive end. The NRZI to NRZ decoder, receives the NRZI data stream from the Clock Recovery
Module and converts it to a NRZ data stream to be presented to the Serial to Parallel conversion block.
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6-Port 10/100Mb Fast Ethernet Smart Switch
6.4.2.6 Serial to Parallel
The Serial to Parallel Converter receives a serial data stream from the NRZI to NRZ converter. It converts the
data stream to parallel data to be presented to the descrambler.
6.4.2.7 Descrambler
Because of the scrambling process requires to control the radiated emissions of transmit data streams, the
receiver must descramble the receive data streams. The descrambler receives scrambled parallel data streams
from the Serial to Parallel converter, and it descrambles the data streams, and presents the data streams to the
Code Group alignment block.
6.4.2.8 Code Group Alignment
The Code Group Alignment block receives un-aligned 5B data from the descrambler and converts it into 5B code
group data. Code Group Alignment occurs after the J/K is detected, and subsequent data is aligned on a fixed
boundary.
6.4.2.9 4B5B Decoder
The 4B5B Decoder functions as a look-up table that translates incoming 5B code groups into 4B (Nibble) data.
When receiving a frame, the first 2 5-bit code groups receive the start-of-frame delimiter (J/K symbols). The J/K
symbol pair is stripped and two nibbles of preamble pattern are substituted. The last two code groups are the
end-of-frame delimiter (T/R
Symbols).
The T/R symbol pair is also stripped from the nibble, presented to the Reconciliation layer.
6.4.3 10Base-T Operation
The 10Base-T transceiver is IEEE 802.3u compliant. When the DM8606C/DM8606CI is operating in 10Base-T
mode, the coding scheme is Manchester. Data processed for transmit is presented in nibble format, converted to
a serial bit stream, then the Manchester encoded. When receiving, the bit stream, encoded by the Manchester, is
decoded and converted into nibble format.
6.4.4 Collision Detection
For half-duplex operation, a collision is detected when the transmit and receive channels are active
simultaneously. Collision detection is disabled in full duplex operation.
6.4.5 Carrier Sense
Carrier Sense (CRS) is asserted in half-duplex operation during transmission or reception of data. During
full-duplex mode, CRS is asserted only when receiving operations.
6.4.6 Auto-Negotiation
The objective of Auto-negotiation is to provide a means to exchange information between linked devices and to
automatically configure both devices to take maximum advantage of their abilities. It is important to note that
Auto-negotiation does not test the characteristics of the linked segment. The Auto-Negotiation function provides a
means for a device to advertise supported modes of operation to a remote link partner, acknowledge the receipt
and understanding of common modes of operation, and to reject un-shared modes of operation. This allows
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DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
devices on both ends of a segment to establish a link at the best common mode of operation. If more than one
common mode exists between the two devices, a mechanism is provided to allow the devices to resolve to a
single mode of operation using a predetermined priority resolution function.
Auto-negotiation also provides a parallel detection function for devices that do not support the Auto-negotiation
feature. During Parallel detection there is no exchange of information of configuration. Instead, the receive signal
is examined. If it is discovered that the signal matches a technology, which the receiving device supports, a
connection will be automatically established using that technology. This allows devices not to support
Auto-negotiation but support a common mode of operation to establish a link.
6.4.7 Auto-MDIX Functional Description
The DM8606C/DM8606CI supports the automatic detect cable connection type, MDI/MDIX (straight
through/cross over) for internal port 0 ~ 4 PHY. A manual configuration by register bit for MDI or MDIX is still
accepted.
When set to automatic, the polarity of MDI/MDIX controlled timing is generated by a 16-bits LFSR. The switching
cycle time is located from 200ms to 420ms. The polarity control is always switch until detect received signal. After
selected MDI or MDIX,
This feature is able to detect the required cable connection type.( straight through or crossed over ) and make
correction automatically
RX + /- from DM8606C/DM8606CI
RX+/- to RJ45
TX + /- from DM8606C/DM8606CI
TX+/- to RJ45
* MDI : __________
* MDIX : - - - - - - - - -
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DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
7. DC and AC Electrical Characteristics
7.1
Absolute Maximum Ratings(DM8606CI support -40C~+85C)
Symbol
VDD33
VDD18
AVDD33
AVDD18
VIN
TSTG
TA
TA
LT
LT
7.2
Parameter
3.3V Supply Voltage
1.8V core power supply
Analog power supply 3.3V
Analog power supply 1.8V
DC Input Voltage (VIN)
Storage Temperature range
Ambient Temperature
Ambient Temperature
Lead Temperature
(TL, soldering, 10 sec.).
Lead Temperature
(TL, soldering, 10 sec.).
Min.
3.135
1.71
3.135
1.71
3.135
-65
0
-40
-
Max.
3.6
1.95
3.6
1.95
3.6
+150
+70
+85
+245
Unit
V
V
V
V
V
C
C
C
C
-
+260
C
Conditions
DM8606CI
DM8606CI
Operating Conditions
Symbol
DVDD33
DVDD18
AVDD33
AVDD18
PD
(Power
Dissipation)
Parameter
3.3V Supply Voltage
1.8V core power supply
Analog power supply 3.3V
Analog power supply 1.8V
5 ports 100BASE-TX
5 ports10BASE-TX
5 ports Auto-negotiation or cable
off
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Doc No: DM8606C/DM8606CI-12-3-DS-P01
November 22, 2012
Min.
3.135
1.71
3.135
1.71
-
Typ.
3.30
1.80
3.30
1.80
380
180
440
530
70
210
180
Max.
3.465
1.89
3.465
1.89
-
Unit
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
Conditions
1.8V only
3.3V only
TX idle, 1.8V only
100% utilization,
1.8V only
3.3V only
1.8V only
3.3V only
101
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
7.3
DC Electrical Characteristics
Symbol
Inputs
VIL
VIH
IIL
IIH
Outputs
VOL
VOH
Receiver
VICM
Parameter
Min.
Typ.
Max.
Input Low Voltage
Input High Voltage
Input Low Leakage Current
Input High Leakage Current
2.0
-1
-
-
0.8
1
V
V
uA
uA
Vcond1
Vcond1
VIN = 0.0V, Vcond1
VIN = 3.3V, Vcond1
Output Low Voltage
Output High Voltage
2.4
-
0.4
-
V
V
IOL = 4mA
IOH = -4mA
-
1.8
-
V
100  Termination
Across
1.9
4.4
│19│
│44│
2.0
5
│20│
│50│
2.1
5.6
│21│
│56│
V
V
mA
mA
RX+/RX- Common Mode Input
Voltage
Transmitter
VTD100 100TX+/- Differential Output Voltage
VTD10 10TX+/- Differential Output Voltage
ITD100 100TX+/- Differential Output Current
ITD10
10TX+/- Differential Output Current
Unit
Conditions
Peak to Peak
Peak to Peak
Absolute Value
Absolute Value
Note: Vcond1 = DVDD3 = 3.3V, DVDD18 = 1.8V, AVDD3 = 3.3V, AVDD18 = 1.8V.
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6-Port 10/100Mb Fast Ethernet Smart Switch
7.4 AC Characteristics
7.4.1 Power On Reset Timing
Symbol
T1
T2
Parameter
PWRST# Low Period
Strap pin hold time with PWRST#
Min.
1
40
Typ.
-
Max.
-
Unit
ms
ns
T3
T4
PWRST# high to EECS high
PWRST# high to EECS burst end
-
5
--
4
us
ms
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Conditions
-
103
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
7.4.2 Port 4,5 MII Interface Transmit Timing
TXC
TXE
T1
TXD_3~0
Symbol
Parameter
Min.
Typ.
T1
TXE,TXD to TXC Rising Output Delay
8
Note: TXC stand for pin P4_TXC in port 4 and pin P5_TXC in port 5
TXE stand for pin P4_TXE in port 4 and pin P5_TXE in port 5
TXD_3~0 stand for pin P4_TXD[3:0] in port 4 and pin P5_TXD[3:0] in port 5
Max.
Unit
ns
Max.
-
Unit
ns
ns
7.4.3 Port 4,5 MII Interface Receive Timing
RXC
RXER,RXDV
T1
T2
RXD_3~0
Symbol
Parameter
Min.
Typ.
T1
RXER, RXDV and RXD to RXC Setup Time
5
T2
RXER, RXDV and RXD to RXC Hold Time
5
Note: RXC stand for pin P4_RXC in port 4 and pin P5_RXC in port 5
RXDV stand for pin P4_RXDV in port 4 and pin P5_RXDV in port 5
RXD_3~0 stand for pin P4_RXD[3:0] in port 4 and pin P5_RXD[3:0] in port 5
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6-Port 10/100Mb Fast Ethernet Smart Switch
7.4.4 Port 4,5 RevMII Interface Transmit Timing
TXC
TXE
T1
TXD_3~0
Symbol
Parameter
Min.
Typ.
T0
100M MII Transmit Clock Period
40
T0
10M MII Transmit Clock Period
400
T1
TXE,TXD to TXC Rising Output Delay
8
Note: TXC stand for pin P4_TXC in port 4 and pin P5_TXC in port 5
TXE stand for pin P4_TXE in port 4 and pin P5_TXE in port 5
TXD_3~0 stand for pin P4_TXD[3:0] in port 4 and pin P5_TXD[3:0] in port 5
Max.
-
Unit
ns
ns
ns
Max.
-
Unit
ns
ns
7.4.5 Port 4,5 RevMII Interface Receive Timing
RXC
RXER,RXDV
T1
T2
RXD_3~0
Symbol
Parameter
Min.
Typ.
T1
RXER, RXDV and RXD to RXC Setup Time
5
T2
RXER, RXDV and RXD to RXC Hold Time
5
Note: RXC stand for pin P4_RXC in port 4 and pin P5_RXC in port 5
RXDV stand for pin P4_RXDV in port 4 and pin P5_RXDV in port 5
RXD_3~0 stand for pin P4_RXD[3:0] in port 4 and pin P5_RXD[3:0] in port 5
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DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
7.4.6 Port 4,5 RMII Interface Transmit Timing
50MCLK
TXE
T1
TXD_1~0
Symbol
Parameter
Min.
Typ.
T1
TXE,TXD to 50MCLK Rising Output Delay
8
Note: 50MCLK stand for pin 50MCLK4 in port 4 and pin 50MCLK5 in port 5
TXE stand for pin P4_TXE in port 4 and pin P5_TXE in port 5
TXD_1~0 stand for pin P4_TXD[1:0] in port 4 and pin P5_TXD[1:0] in port 5
Max.
Unit
ns
Max.
-
Unit
ns
ns
7.4.7 Port 4,5 RMII Interface Receive Timing
50MCLK
CRSDV
T1
T2
RXD_1~0
Symbol
Parameter
Min.
Typ.
T1
CRSDV, RXD to 50MCLK Setup Time
4
T2
CRSDV, RXD to 50MCLK Hold Time
2
Note: 50MCLK stand for pin 50MCLK4 in port 4 and pin 50MCLK5 in port 5
CRSDV stand for pin P4_CRSDV in port 4 and pin P5_CRSDV in port 5
RXD_1~0 stand for pin P4_RXD[1:0] in port 4 and pin P5_RXD[1:0] in port 5
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DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
7.4.8 Port 4 PHY MII Interface Receive Timing
P4_RXC
P4_RXDV
T1
P4_RXD[3:0]
Symbol
T1
Parameter
P4_RXDV,P4_RXD[3:0] to P4_RXC Rising Output Delay
Min.
Typ.
8
Max.
Unit
ns
Max.
-
Unit
ns
ns
7.4.9 Port 4 PHY MII Interface Transmit Timing
P4_TXC
P4_TXE
T1
T2
P4_TXD[3:0]
Symbol
T1
T2
Parameter
P4_TXE and P4_TXD[3:0] to P4_TXC Setup Time
P4_TXE and P4_TXD[3:0] to P4_TXC Hold Time
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Min.
5
5
Typ.
-
107
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
7.4.10 Host SMI Interface Timing
T1
SMI_CK
T2
SMI_DIO (drived by processor)
T4
T3
SMI_DIO (drived by DM8606C)
T5
Symbol
T1
T2
T3
T4
T5
Parameter
SMI_CK Period
SMI_DIO by processor Setup Time
SMI_DIO by processor Hold Time
SMI_DIO by DM8606C/DM8606CI Setup Time
SMI_DIO by DM8606C/DM8606CI Hold Time
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Min.
80
40
40
70
Typ.
5
Max.
-
Unit
ns
ns
ns
ns
ns
108
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
7.4.11 PHY SMI Interface Timing
T1
PHY_MDC
T2
PHY_MDIO (drived by DM8606C)
T4
T3
PHY_MDIO (drived by PHY)
T5
Symbol
T1
T2
T3
T4
T5
Parameter
PHY_MDC Period
PHY_MDIO drived by DM8606C/DM8606CI Setup
Time
PHY_MDIO drived by DM8606C/DM8606CI Hold
Time
PHY_MDIO drived by PHY Setup Time
PHY_MDIO drived by PHY Hold Time
Preliminary
Doc No: DM8606C/DM8606CI-12-3-DS-P01
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Min.
5
5
Typ.
1920
960
Max.
-
Unit
ns
ns
960
-
ns
920
920
ns
ns
109
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
7.4.12 EEPROM Timing
T1
T2
EECS
T3
EECK
T4
EEDIO
T6
T5
EEDIO
T7
Symbol
T1
T2
T3
T4
T5
T6
T7
Parameter
EECS Setup Time
EECS Hold Time
EECK Frequency
EEDIO Setup Time drive by DM8606C/DM8606CI
EEDIO Hold Time drive by DM8606C/DM8606CI
EEDIO Setup Time drive by EEPROM
EEDIO Hold Time drive by EEPROM
Preliminary
Doc No: DM8606C/DM8606CI-12-3-DS-P01
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Min.
8
8
Typ.
480
2080
0.39
460
2100
Max.
Unit
ns
ns
MHz
ns
ns
ns
ns
110
DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
8. Package Information
128 Pins QFP Package Outline Information:
Symbol
A
A1
A2
B
C
D
D1
E
E1
e
L
L1
y
θ
Dimension in mm
Min
Nom
Max
－
－
3.40
0.25
－
－
2.73
2.85
2.97
0.17
0.22
0.27
0.09
－
0.20
23.00
23.20
23.40
19.90
20.00
20.10
17.00
17.20
17.40
13.90
14.00
14.10
0.50 BSC
0.73
0.88
1.03
1.60 BSC
－
－
0.10
o
o
0
－
7
Dimension in inch
Min
Nom
Max
－
－
0.134
0.010
－
－
0.107
0.112 0.117
0.007
0.009 0.011
0.004
－
0.008
0.906
0.913 0.921
0.783
0.787 0.791
0.669
0.677 0.685
0.547
0.551 0.555
0.020 BSC
0.029
0.035 0.041
0.063 BSC
－
－
0.004
o
o
0
－
7
1. Dimension D1 and E1 do not include resin fin.
2. All dimensions are base on metric system.
3. General appearance spec should base on its final visual inspection spec.
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DM8606C/DM8606CI
6-Port 10/100Mb Fast Ethernet Smart Switch
DAVICOM for such applications. Please note that
application circuits illustrated in this document are for
reference purposes only.
9. Ordering Information
Part Number
Pin Count
DM8606CFP
128
DM8606CIFP
128
Package
QFP
(Pb-Free)
QFP
(Pb-Free)
Disclaimer
The information appearing in this publication is
believed to be accurate. Integrated circuits sold by
DAVICOM Semiconductor are covered by the
warranty and patent indemnification provisions
stipulated in the terms of sale only. DAVICOM makes
no warranty, express, statutory, implied or by
description regarding the information in this
publication or regarding the information in this
publication or regarding the freedom of the described
chip(s) from patent infringement.
FURTHER,
DAVICOM
MAKES
NO
WARRANTY
OF
MERCHANTABILITY OR FITNESS FOR ANY
PURPOSE. DAVICOM reserves the right to halt
production or alter the specifications and prices at any
time without notice. Accordingly, the reader is
cautioned to verify that the data sheets and other
information in this publication are current before
placing orders. Products described herein are
intended for use in normal commercial applications.
Applications involving unusual environmental or
reliability requirements, e.g. military equipment or
medical life support equipment, are specifically not
recommended without additional processing by
DAVICOM’s terms and conditions printed on the order
acknowledgment govern all sales by DAVICOM.
DAVICOM will not be bound by any terms inconsistent
with these unless DAVICOM agrees otherwise in
writing. Acceptance of the buyer’s orders shall be
based on these terms.
Company Overview
DAVICOM Semiconductor Inc. develops and
manufactures integrated circuits for integration into
data communication products. Our mission is to
design and produce IC products that are the industry’s
best value for Data, Audio, Video, and
Internet/Intranet applications. To achieve this goal, we
have built an organization that is able to develop
chipsets in response to the evolving technology
requirements of our customers while still delivering
products that meet their cost requirements.
Products
We offer only products that satisfy high performance
requirements and which are compatible with major
hardware and software standards. Our currently
available and soon to be released products are based
on our proprietary designs and deliver high quality,
high performance chipsets that comply with modem
communication standards and Ethernet networking
standards.
Contact Windows
For additional information about DAVICOM products, contact the Sales department at:
Headquarters
Hsin-chu Office:
No.6 Li-Hsin Rd. VI,
Science-based Industrial Park,
Hsin-chu City, Taiwan, R.O.C.
TEL: +886-3-5798797
FAX: +886-3-5646929
MAIL: [email protected]
HTTP: http://www.davicom.com.tw
WARNING
Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near
the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and function.
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