CoreSGMII v2.0 Handbook Revision History Date June 2015 Revision Change 1 First Release Confidentiality Status This is a non-confidential document. CoreSGMII v2.0 Handbook 2 Table of Contents Table of Contents Preface ...........................................................................................................................................5 About this Document .................................................................................................................................................. 5 Intended Audience ...................................................................................................................................................... 5 References................................................................................................................................................................... 5 Introduction ..................................................................................................................................6 Overview ...................................................................................................................................................................... 6 Key Features ............................................................................................................................................................... 6 Core Version ................................................................................................................................................................ 7 Supported Families ..................................................................................................................................................... 7 Utilization and Performance .................................................................................................................................... 7 Functional Block Description ..................................................................................................8 G/MII Interface............................................................................................................................................................. 8 MDIO Interface ............................................................................................................................................................ 8 Serial G/MII Ten Bit Interface.................................................................................................................................... 8 Clocking and Reset .................................................................................................................................................... 8 Transmit Conversion .................................................................................................................................................. 8 Receive Conversion ................................................................................................................................................... 9 Ten Bit Interface .......................................................................................................................................................... 9 Auto Negotiation (ANX).............................................................................................................................................. 9 PCS Error Detection ................................................................................................................................................. 10 Register Map ............................................................................................................................................................. 10 Interface Description ................................................................................................................18 Ports............................................................................................................................................................................ 18 Configuration Parameters........................................................................................................................................ 20 Timing Diagrams .......................................................................................................................21 G/MII Timing Diagrams ............................................................................................................................................ 21 TBI Interface Timing Diagrams ............................................................................................................................... 21 MDIO Timing Diagrams ........................................................................................................................................... 21 Tool Flows...................................................................................................................................22 License ....................................................................................................................................................................... 22 SmartDesign .............................................................................................................................................................. 22 Simulation Flows ....................................................................................................................................................... 23 Synthesis in Libero ................................................................................................................................................... 23 Place-and-Route in Libero ....................................................................................................................................... 23 Testbench Operation and Modification...............................................................................24 User Test-bench ....................................................................................................................................................... 24 CoreSGMII v2.0 Handbook 3 Table of Contents System Integration....................................................................................................................26 Ordering Information................................................................................................................28 Ordering Codes ......................................................................................................................................................... 28 List of Changes..........................................................................................................................29 Product Support ........................................................................................................................30 Customer Service ..................................................................................................................................................... 30 Customer Technical Support Center...................................................................................................................... 30 Technical Support ..................................................................................................................................................... 30 Website ...................................................................................................................................................................... 30 Contacting the Customer Technical Support Center ........................................................................................... 30 ITAR Technical Support ........................................................................................................................................... 31 CoreSGMII v2.0 Handbook 4 Preface About this Document This handbook provides details about the CoreSGMII DirectCore module, and how to use it. Intended Audience ® FPGA designers using Libero System-on-Chip (SoC). References Microsemi Publications • SmartFusion2 Microcontroller Subsystem User Guide Third Party Publications • http://standards.ieee.org/getieee802/download/802.3-2012_section2.pdf • http://standards.ieee.org/getieee802/download/802.3-2012_section3.pdf CoreSGMII v2.0 Handbook 5 Overview Introduction Overview The CoreSGMII provides a solution for ten bit interface (TBI) on gigabit media independent interface (G/MII) based designs. The CoreSGMII takes the G/MII data stream and encodes it into 10-bit symbols. In the Receive direction, the 10-bit symbols are decoded and converted into the receive G/MII signal set. The CoreSGMII is managed and monitored through the management data input/output (MDIO) interface. The CoreSGMII supports Auto-Negotiation, which allows two link partners to exchange details of capabilities and determine the appropriate link operation. Figure 1 Top-Functional Block Diagram Key Features CoreSGMII supports the following features: • Full-duplex support for 1000 Mbps operation • Full and half-duplex support for 10/100 Mbps operation • Internal or external G/MII for interfacing to a MAC • MDIO interface to configure and monitor • Implements 8b/10b encoding and decoding • Clause 37 Auto-Negotiation • Ten Bit Interface • Comma alignment CoreSGMII v2.0 Handbook 6 Core Version Core Version This handbook is for CoreSGMII version 2.0. Supported Families • SmartFusion 2 • IGLOO 2 ® ® Utilization and Performance A summary of the utilization data of CoreSGMII is listed in Table 1. Speed Grade – STD, Core Voltage – 1.2V and Operating Condition- IND Table 1 ·CoreSGMII Device Utilization and Performance FPGA Family IGLOO2 Device M2GL050T FPGA Resources Utilization Combinatorial Sequential Total 2,236 1,294 3,530 ~ 6% Clock Rate (MHz) GTXCLK > 125 RXCLK > 125 TXCLK > 125 SmartFusion2 M2S050T 2,171 1,294 3,465 ~ 6% GTXCLK > 125 RXCLK > 125 TXCLK > 125 Note: Data in this table are achieved using synthesis and layout settings optimized for speed along with interfacing to SerDeS. CoreSGMII v2.0 Handbook 7 Functional Block Description The CoreSGMII IP has the following interfaces: G/MII Interface Gigabit media-independent Interface (G/MII) is an interface between the media access control (MAC) device and physical layer (PHY). It defines speeds up to 1000 Mbps, implemented using an 8-bit data interface clocked at 125MHz, and is backwards compatible with the media-independent interface (MII) specification. It can also operate at fall-back speeds of 10 or 100 Mbps as per the MII specification. Data on the interface is framed using the IEEE Ethernet standard. It consists of the following: • Preamble • Start frame delimiter • Ethernet headers • Protocol specific data • Cyclic redundancy check (CRC) In case of G/MII transmission, there are two clocks, depending on whether the PHY is operating at 1000 Mbps or 10/100 Mbps speeds. GTXCLK is supplied to the PHY for 1000 Mbps speed, and the transmit data and control signals are synchronized to this. Otherwise, for 10/100 Mbps, the TXCLK supplied by the PHY is used for synchronizing those signals. This operates at either 25 MHz for 100 Mbps, or 2.5 MHz for 10 Mbps connections. The RXCLK is 2.5/25/125 MHz for 10/100/1000 respectively, is supplied from PHY/SerDes. MDIO Interface The CoreSGMII registers are accessed through the MDIO interface. The MDIO controller in the MAC can read and write the control and status registers of the CoreSGMII. Serial G/MII Ten Bit Interface The TBI provides independent Ten bit interface functionality contained in 802.3z Clauses 36 and 37. TBI can interface directly to the encoded physical coding sub layer (EPCS) interface of the Serializer/Deserializer (SerDeS). Clocking and Reset • Master Reset (RESET) is external reset used for the complete core. • PHY Reset (0x00 Control) is a bit from the MII Management Control register. This reset is synchronized to the native clocks of the TEX, REX and ANX sub modules and reset these modules. • TXCLK is used for converting G/MII data into GTXCLK domain. • RXCLK is used for driving 8b data on to G/MII interface (8b data is received from TBI’s PMA_RX_CLK0/1 domain). • GTXCLK is used for Ten bit interface module. • PMA_RX_CLK0 and PMA_RX_CLK1 are used in TBI and RX conversion. Transmit Conversion This module synchronizes G/MII transmit path data to the GTXCLK clock domain. This module repeats each data byte 10/100 times for 10/100 Mbps respectively. CoreSGMII v2.0 Handbook 8 Receive Conversion Receive Conversion This module stores the G/MII transmit data from the Ten bit interface module to drive out to the G/MII RXCLK clock domain. This module only stores data every 10/100 clocks for 10/100 Mbps respectively, and artificially creates preamble and SFD. Ten Bit Interface TEX (Transmit Exchange functionality) • This module performs clause 36 transmit related functionality of 802.3z. TEX operation is governed by auto negotiation, which provides CFG/IDL/DAT information. • In CFG mode, TEX sends /C/ ordered sets with data from ANX. • In IDL mode, TEX sends /I/ order sets. • In DAT mode, TEX send 8b10b encoded packets. REX (Receive Exchange functionality) • Performs comma alignment and passes aligned two-code-group wide data clocked at 62.5 MHz into the PCS. • Performs clause 36 receive related functionality of 802.3z. • The code-groups from PCS are decoded for 10b8b and inspected by the receive logic. • The PCS module looks for Configuration ordered sets and passes the Receive Configuration Register contents to the ANX module. • After Auto-Negotiation completes, removes the encapsulation codes and passes the received packet. TBM (Ten-bit interface management) • This module provides the control and status path to an external processor. • All the outputs from TBM module to ANX module are synchronous to MDC, which runs at a lower frequency and then, they are double registered synchronous to the GTXCLK, which runs at 125 MHz. Auto Negotiation (ANX) • The ANX module is responsible for the Auto-Negotiation function specified in Clause 37 of IEEE 802.3z. It provides implementation for link partners to exchange ability information and link operation characteristics. These characteristics include duplex mode and remote fault conditions. • Auto-Negotiation function is managed via the MDIO interface. Software programs the ability information via the AN Advertisement register and status information about the Auto-Negotiation process can be gathered by reading several registers. • For instance, software can detect that ability information has been received from bit 1 of the AN Expansion register – Page Received. • The Auto negotiation has four key functions, ability_match, acknowledge_match, consistency_match, and Idle_match. • The Auto-Negotiation function has a mechanism to acknowledge reception of ability information and to send additional information via Next Pages. After both link partners properly exchange ability information and acknowledge reception, normal packet transmission may occur. Either end of the link may choose to renegotiate at will and do so by sending a ‘Break Link’, which comprises of Configuration ordered_sets with a zeroed ability field. • Currently AN Status information about the Auto-Negotiation process can be gathered by reading several registers. For instance, software can detect that ability information has been received from bit 1 of the AN Expansion register – Page Received. Status register (0x01) has one bit filed, which indicates the successful completion auto negotiation. CoreSGMII v2.0 Handbook 9 PCS Error Detection PCS Error Detection The CoreSGMII reports the running disparity error (RDERR) and code error (BCERR) of the RCG data stream. The RCG consists of a 6-bit block and 4-bit block. The running disparity rules are applicable to the sub-block boundaries. The running disparity at the end of the sub-block must be -1 or +1. Failure to meet these criteria is also flagged as a disparity error. Code error indicates that the RCG is not a valid member of the code group. Register Map The following registers are accessed through the MDIO interface clause 22 of the IEEE 802.3 specification. The PHY address for the MDIO registers can be configured. The CoreSGMII contains the management registers specified in IEEE 802.3, Clause 37 – Control, Status, Auto Negotiation Advertisement, Link Partner Ability, Auto Negotiation Expansion and Extended Status. The register set is read/write through MDIO interface. Table 2 CoreSGMII Register Map ADR Register 00h Control 01h Status 04h AN Advertisement 05h AN Link Partner Base Page Ability 06h AN Expansion 07h AN Next Page Transmit 08h AN Link Partner Ability Next Page 0Fh Extended Status 10h Jitter Diagnostics 11h TBI Control CoreSGMII v2.0 Handbook 10 Register Map Table 3 Register descriptions Address 0x00 Function Control [15] (R/W, SC) PHY RESET: Default 0 Setting this bit causes the TEX, REX, and ANX sub-modules in the CoreSGMII core to be reset. This bit is self-clearing. [14] (R/W) LOOP BACK: Default 0 Setting this bit causes the transmit outputs of the CoreSGMII to be connected to the receive inputs. Clearing this bit results in normal operation. [13] Reserved. [12] (R/W) AUTO-NEGOTIATION ENABLE Default 0 Setting this bit enables the Auto-negotiation process. [11:10] Reserved. [9] (R/W, SC) RESTART AUTO-NEGOTIATION: Default 0 Setting this bit causes the Auto-negotiation process to restart. This action is only available when Auto-Negotiation has been enabled [8:0] Reserved. 0x01 Status - Default Value 0x149 [15:9] Reserved. [8] (RO) EXTENDED STATUS: Default 1 This bit indicates that PHY status information [7] Reserved. [6] (RO) MF PREMABLE SUPPRESSION ENABLE: Default 1 This bit indicates whether the PHY is capable of handling MII Management Frames without the 32-bit preamble field. Returns 1 indicating support for suppressed preamble MII Management Frames. [5] (RO) AUTO-NEGOTIATION COMPLETE: When 1, this bit indicates that the Auto-negotiation process has completed. This bit returns ‘0’ when either the Auto-negotiation process is underway or the Auto-negotiation function is disabled. [4] (RO) REMOTE FAULT: Default 0 When 1, a remote fault condition has been detected between the CoreSGMII and the PHY. [3] (RO) AUTO-NEGOTIATION ABILITY: Default 1 When 1, this bit indicates that the CoreSGMII has the ability to perform Auto-negotiation. [2] (RO) LINK STATUS: Default 0 When 1, this bit indicates that a valid link has been established between the CoreSGMII and PHY. When 0, no valid link has been established. [1] Reserved. [0] (RO) EXTENDED CAPABILITY: Default 1 This bit indicates that the CoreSGMII contains the extended set of registers. 0x02 Reserved 0x03 Reserved CoreSGMII v2.0 Handbook 11 Register Map Address 0x04 Function AN Advertisement (SGMII) Bit Tx_config from PHY to MAC Tx_config from MAC to PHY 15 Link: 1=link up, 0=link down 0:Reserved 14 Reserved for AN ACK 1 13 0:Reserved 0:Reserved 12 Duplex mode: 1=full, 0=half 0:Reserved 11:10 Speed: 11 = Reserved 10 = 1000 Mbps 01 =100 Mbps 00 = 10 Mbps 9:1 0:Reserved 0:Reserved 0 1 1 [15] (R/W) LINK UP: Assertion of this bit indicates that the link is up. When the CoreSGMII integrated with in MAC this bit must be written ‘0’. [14] (RO) ACK (Reserved). Ignore on read. [13] (R/W) RESERVED: This bit must be written ‘0’ for correct CoreSGMII operation. [12] (R/W) FULL-DUPLEX: Assertion of this bit indicates that the link is transferring data in full duplex mode. When the CoreSGMII is integrated within MAC this bit must be written ‘0’. [11:10] (R/W) LINK SPEED: Link speed set by the application for the Auto negotiation. These bits have no relation with SPEEDO port signal. [9:0] (R/W): These bits must always be written ‘0000000001’ for correct CoreSGMII operation CoreSGMII v2.0 Handbook 12 Register Map Address 0x04 Function AN Advertisement (1000BASE-X) [15] (R/W) NEXT PAGE: Default 0 The local device asserts this bit to either request Next Page transmission or advertise Next Page exchange capability. This bit can thus be set when the local has no Next Pages but wishes to allow reception of Next Pages. If the local device has no Next Pages, and the Link Partner wishes to send Next Pages, the local device must send Null Message Codes and have the MESSAGE PAGE set to 0b000_0000_0001. This bit must be cleared where the local device wishes not to engage in Next Page exchange. [14] Reserved. [13:12] (R/W) REMOTE FAULT: Default 0 Encodes the local device’s remote fault condition. A fault may be indicated by setting a non-zero Remote Fault encoding and re-negotiating. RF1 (4.12) RF2 (4.13) Description 0 0 No error, link Ok. 0 1 Offline. 1 0 Link_Failure 1 1 Auto-Negotiation_Error. [11:9] Reserved [8:7] (R/W) PAUSE: Encodes the local device’s PAUSE capability. Pause Encoding: PAUSE1 (4.7) ASM_DIR (4.8) Capability 0 0 No PAUSE. 0 1 Asymmetric PAUSE toward link partner. 1 0 Symmetric PAUSE. 1 1 Asymmetric PAUSE toward local device. [6] (R/W) HALF-DUPLEX: Setting this bit means local device is capable of half-duplex operation. [5] (R/W) FULL-DUPLEX: Setting this bit means local device is capable of full-duplex operation. [4:0] Reserved 0x5 AN Link Partner Base Page Ability (SGMII) [15] (RO) LINK UP: This bit indicates that the link is up. [14:13] Reserved [12] (RO) FULL DUPLEX: Link partner full duplex ability received. [11:10] (RO) LINK SPEED: Link partner speed ability received. [9:0] (R/W): These bits must always be written 0000000001 for correct CoreSGMII operation. CoreSGMII v2.0 Handbook 13 Register Map Address 0x5 Function AN Link Partner Base Page Ability (1000BASE-X) [15] (RO) NEXT PAGE: The Link Partner asserts this bit either to request Next Page transmission or to indicate the capability to receive Next Pages. When 0, the Link Partner has no subsequent Next Pages or is not capable of receiving Next Pages. [14] (RO) ACK (Reserved): Ignore on read. [13:12] (RO) REMOTE FAULT: Encodes the Link Partner’s remote fault condition. RF1 (4.12) RF2 (4.13) Description 0 0 No error, link Ok. 0 1 Offline. 1 0 Link_Failure 1 1 Auto-Negotiation_Error. [11:9] Reserved [8:7] (RO) PAUSE: Encodes of the Link Partner’s PAUSE capability Pause Encoding: PAUSE1 (4.7) ASM_DIR (4.8) Capability 0 0 No PAUSE. 0 1 Asymmetric PAUSE toward link partner. 1 0 Symmetric PAUSE. 1 1 Asymmetric PAUSE toward local device. [6] (RO) HALF-DUPLEX: When 1, Link Partner is capable of half-duplex operation. When 0, Link Partner is incapable of half-duplex mode. [5] (RO) FULL-DUPLEX: When 1, Link Partner is capable of full-duplex operation. When 0, Link Partner is incapable of full-duplex mode. [4:0] Reserved 0x06 AN Expansion (SGMII) [15:3] Reserved [2] (RO) NEXT PAGE ABLE: Default 1 When 1, indicates that the local device supports the Next Page function. [1] (RO) PAGE RECEIVED: When 1, indicates that a new page has been received and stored in the applicable AN LINK PARTNER ABILITY or AN NEXT PAGE [0] Reserved AN Expansion (1000BASE-X) [15:3] Reserved [2] (RO) NEXT PAGE ABLE: 1 indicates local device supports Next Page function. Returns 1 on read. [1] (RO,LH) PAGE RECEIVED: 1 indicates that a new page has been received and stored in the applicable AN LINK PARTNER ABILITY or AN NEXT PAGE register. This bit latches high in order for software to detect when polling. The bit is cleared on a read to the register. CoreSGMII v2.0 Handbook 14 Register Map Address 0x07 Function AN Next Page Transmit (SGMII) Use of this register is user dependent. User can define functionality of bits of this register as per system requirement [15:0] User defined Register AN Next Page Transmit (1000BASE-X) [15] (R/W) NEXT PAGE: Assert this bit to indicate additional Next Pages to follow. Bit is cleared to indicate last page. [14] (RO) ACK (Reserved): Write ‘0’, ignore on read. [13] (R/W) MESSAGE PAGE: Assert bit to indicate Message Page. Clear bit to indicate Unformatted Page. [12] (R/W) ACKNOWLEDGE 2: Used by Next Page function to indicate device has ability to comply with the message. Assert bit if local device complies with message. Clear bit if local device cannot comply with message. [11] (RO) TOGGLE: Used to ensure synchronization with the Link Partner during Next Page exchange. This bit always takes opposite value of the Toggle bit of the previously exchanged Link Code Word. The initial value in the first Next Page transmitted is the inverse of bit 11 in the base Link Code Word. [10:0] (R/W) MESSAGE / UNFORMATTED CODE FIELD: Message pages are formatted pages that carry a predefined Message Code, which is enumerated in IEEE 802.3u/Annex 28C. Unformatted Code Fields take on an arbitrary value. 0x08 AN Link Partner Ability Next Page (SGMII) Use of this register is user dependent. User can define functionality of bits of this register as per system requirement [15:0] User defined Register AN Link Partner Ability Next Page (1000BASE-X) [15] (RO) NEXT PAGE: The Link Partner asserts this bit to indicate additional Next Pages to follow. When 0, indicates last Next Page from link partner. [14] (RO) ACK (Reserved): Ignore on read. [13] (RO) MESSAGE PAGE: When 1, indicates Message Page. When ‘0’, indicates Unformatted Page. [12] (RO) ACKNOWLEDGE 2: Indicates Link Partner’s ability to comply with the message. When 1, Link Partner complies with message. When 0, Link Partner cannot comply with message. [11] (RO) TOGGLE: Used to ensure synchronization with the Link Partner during Next Page exchange. This bit always takes opposite value of the Toggle bit of the previously exchanged Link Code Word. The initial value in the first Next Page transmitted is the inverse of bit 11 in the base Link Code Word. [10:0] (RO) MESSAGE / UNFORMATTED CODE FIELD: Message pages are formatted pages that carry a predefined Message Code, which is enumerated in IEEE 802.3u/Annex 28C. Unformatted Code Fields take on an arbitrary value. CoreSGMII v2.0 Handbook 15 Register Map Address 0x0F Function Extended Status [15] (RO) 1000BASE-X FULL-DUPLEX: Default 1 When 1, indicates PHY can operate in 1000BASE-X full-duplex mode. When ‘0’, indicates PHY cannot operate in this mode. [14] (RO) 1000BASE-X HALF-DUPLEX: Default 0 When 1, indicates PHY can operate in 1000BASE-X half-duplex mode. When 0, indicates PHY cannot operate in this mode. [13] (RO) 1000BASE-T FULL-DUPLEX: Default 1 When 1, indicates PHY can operate in 1000BASE-T full-duplex mode. When 0, indicates PHY cannot operate in this mode. [12] (RO) 1000BASE-T HALF-DUPLEX: Default 0 When 1, indicates PHY can operate in 1000BASE-T half-duplex mode. When 0, indicates PHY cannot operate in this mode. [11:0] Reserved 0x10 Jitter Diagnostics [15] (R/W) JITTER DIAGNOSTIC ENABLE: Default 0 Set this bit to enable the CoreSGMII to transmit the jitter test patterns defined in IEEE 802.3z 36A. Clear this bit to enable normal transmit-operation. [14:12] (R/W) JITTER PATTERN SELECT: Default is 0 Selects the jitter pattern to be transmitted in diagnostics mode. Jitter Pattern Select Encodings Bit 14 Bit 13 Bit 12 Jitter Pattern Select 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 User Defined Custom Pattern 802.3z 36A Defined High Frequency 1010101010101010101010… 802.3z 36A Defined Mixed Frequency 11111010110000010100… Custom Defined Low Frequency 11111000001111100000… Random Jitter Pattern 1 0 1 802.3z 36A Defined Low Frequency 11111000001111100000… 1 1 0 Reserved 1 Reserved 1 1 [11:10] Reserved [9:0] (R/W) CUSTOM JITTER PATTERN: Default 0 Used in conjunction with JITTER PATTERN SELECT and JITTER DIAGNOSTIC ENABLE. Set this field to the desired custom pattern. 0x11 Ten Bit Interface Control [15] (R/W) SOFT RESET: Default 0 This bit resets the functional modules in the CoreSGMII. Clear it for normal operation. [14] (R/W) SHORTCUT LINK TIMER: Default 0 Set this bit 1 to reduce the value of Go Link Timer and Sync. Status Fail Timer to 64 clock pulse. This reduces the simulation time needed to time the 1.6ms Link Timer. Clear it for normal operation. In normal operation, the value of Go Link Timer is 200000 clock pulses and the value of the Sync. Status Fail Timer is 1250000 clock pulses. [13] (R/W) DISABLE RECEIVE RUNNING DISPARITY: Default 0 CoreSGMII v2.0 Handbook 16 Register Map Address Function Set this bit to disable the running disparity calculation and checking in the receive direction. This bit must be 0 for correct CoreSGMII operation. [12] (R/W) DISABLE TRANSMIT RUNNING DISPARITY: Default 0 Set this bit to disable the running disparity calculation and checking in the transmit direction. This bit must be 0 for correct CoreSGMII operation. [11] (R/W) GO LINK TIMER VALUE CONTROL: Default 0 When 0 the Go Link Timer Value=1.6ms When set to 1 the Go Link Timer Value=10ms [10:9] Reserved [8] (R/W) AUTO-NEGOTIATION SENSE: Default 0 Set this bit to allow the Auto-Negotiation function to sense either a MAC in Auto-Negotiation bypass mode or an older MAC without Auto-Negotiation capability. When sensed, Auto-Negotiation Complete becomes true; however, Page Received will be low, indicating no page is exchanged. Management can then act accordingly. Clear this bit when IEEE 802.3z Clause 37 behaviour is desired, which results in the link not coming up. [7:4] Reserved [3:2] (R/W) SPEEDO: Default '10' Bit 3 Bit 2 Description 1 1 Reserved 1 0 1000 Mbps 0 1 100 Mbps 0 0 10 Mbps [1:0] Reserved CoreSGMII v2.0 Handbook 17 Ports Interface Description Ports The port signals for CoreSGMII are described in Table 4 and shown in Figure 2. Figure 2 CoreSGMII I/O Signals CoreSGMII v2.0 Handbook 18 Ports Table 4 I/O Signal Description Signal Direction Description Reset RESET Input Active high reset Clocks 125 MHz clock generated from SerDes/EPCS transmit clock Transmit clock. Based on the SPEEDO value, 2.5/25/125 MHz for 10/100/1000 Mbps respectively are generated from SerDes/EPCS transmit clock. Receive clock. Based on the SPEEDO value, 2.5/25/125 MHz for 10/100/1000 Mbps respectively are generated from SerDes/EPCS receive/transmit clock. 62.5 MHz PMA Receive Clock generated from SerDes/EPCS receive clock GTXCLK Input TXCLK Input RXCLK Input PMA_RX_CLK0 Input PMA_RX_CLK1 Input 62.5 MHz PMA Receive Clock with 180° phase shift with PMA_RX_CLK0 G/MII Interface TXD[7:0] Input G/MII transmit data TXEN Input G/MII transmit enable TXER Input G/MII transmit error RXD[7:0] Output G/MII Receive data RXDV Output G/MII Receive data valid RXER Output G/MII Receive Error COL Output MII collision CRS Output MII carrier sense TBI Interface RCG[9:0] Input TBI Receive code group TCG[9:0] Output TBI Transmit code group SGMII_READY Input SGMII_TXVAL Output RCG valid, recommended to connect with SerDes/EPCS Ready TCG valid, recommended to connect with SerDes/EPCS Valid MDIO Interface MDC Input Management data clock, recommended to drive 2.5 MHz MDO Input Management data output MDOEN Input Management data output enable MDI_EXT Input Management data input from external PCS/PHY MDI Output MII Management data Input Other Interface Signals INTLB Output Loop back enabled status SPEEDO[1:0] Output SPEEDO refers to '00'/'01'/'10' for 10/100/1000 Mbps respectively. SPEEDO signal is used for 2.5/25/125 MHz TXCLK and RXCLK clocks generation. PHY speed read by the driver/application must be updated to Ten Bit Interface Control (0x11). Auto negotiation status information ANX_STATE[9:0] CoreSGMII v2.0 Handbook Output 0th bit - DISABLE_LINK_OK state 1st bit - AN_ENABLE state 2nd bit - AN_RESTART state 3rd bit - ABILITY_DETECT state 4th bit - ACKNOWLEDGE_DETECT state 5th bit - NEXT_PAGE_WAIT state 6th bit - COMPLETE_ACKNOWLEDGE state 19 Configuration Parameters 7th bit - IDLE_DETECT state 8th bit - LINK_OK state 9th bit - Received configuration frame data BCERR[1:0] Output BCERR [1] indicates RCG code error in PCSRXD[15:8] and BCERR [0] indicates RCG code error in PCSRXD[7:0], BCERR[1:0] is active high signal RDERR[1:0] Output RDERR[1] indicates RCG disparity error in PCSRXD[15:8] and RDERR[0] indicates RCG disparity error in PCSRXD[7:0], RDERR[1:0] is active high signal PCSRXD[15:0] Output This port is intended to be used to monitor the decoded receive data. PCSRXK[1:0] Output PCSRXK[1] indicates K character indicator associated with the PCSRXD[15:8] and PCSRXK[0] indicates K character indicator associated with the PCSRXD[7:0], PCSRXK[1:0] is active high signal ANX_CDATA[15:0] Output This port provides the received C1 and C2 data from the auto-negotiation process. The auto-negotiation state machine inside the CoreSGMII terminates the C1 and C2 data. This port is intended to be used to monitor the received data. ANX_CVALID Output C1 and C2 ordered set valid indicator Configuration Parameters The register transfer level (RTL) code for CoreSGMII has parameters for configuring the core. While working with the core in the SmartDesign tool, a configuration GUI is used to set the values of these parameters. Table 5 CoreSGMII Configuration Parameters Name MDIO_PHYID Valid Range Default 0 or 31 12 Description MDIO PHY address Note : MSS Hard MAC user to avoid the address 30 CoreSGMII v2.0 Handbook 20 G/MII Timing Diagrams Timing Diagrams G/MII Timing Diagrams Refer to http://standards.ieee.org/getieee802/download/802.3-2012_section2.pdf • Figure 22–4: Transmission with no collision • Figure 22–5: Propagating an error • Figure 22–6: LPI transition • Figure 22–7: Reception with no errors • Figure 22–9: Reception with errors • Figure 22–10: False Carrier indication • Figure 22–11: Transmission with collision TBI Interface Timing Diagrams Refer to http://standards.ieee.org/getieee802/download/802.3-2012_section3.pdf • Figure 36–14: TBI transmit interface timing diagram • Figure 36–15: TBI receive interface timing diagram MDIO Timing Diagrams Refer to http://standards.ieee.org/getieee802/download/802.3-2012_section2.pdf • Figure 22–15: Behavior of MDIO during TA field of a read transaction • Figure 22–18: MDIO sourced by STA • Figure 22–19: MDIO sourced by PHY CoreSGMII v2.0 Handbook 21 License Tool Flows License CoreSGMII is available as obfuscated RTL only. SmartDesign CoreSGMII is available for download in the Libero IP catalog through the web repository. Once it is listed in the catalog, the core can be instantiated using the SmartDesign flow. For information on using SmartDesign to configure, connect, and generate cores, refer to the Libero online help. An example instantiated view is shown in Figure 3. After configuring and generating the core instance, basic functionality can be simulated using the test-bench supplied with the CoreSGMII. The testbench parameters automatically adjust to the CoreSGMII configuration. The CoreSGMII can be instantiated as a component of a larger design. CoreSGMII is compatible with Libero SoC Figure 3 SmartDesign CoreSGMII Instance View CoreSGMII v2.0 Handbook 22 Simulation Flows Configuring CoreSGMII in SmartDesign Figure 4 Configuring CoreSGMII in SmartDesign Simulation Flows To run simulations, select the user testbench in the core configuration window. After generating the CoreSGMII, the pre-synthesis test-bench hardware description language (HDL) files are installed in Libero. Synthesis in Libero To run synthesis on the CoreSGMII, set the design root to the IP component instance and run the synthesis tool from the Libero design flow pane. Place-and-Route in Libero After the design is synthesized, run the compilation and then place-and-route the tools. CoreSGMII requires no special place-and-route settings. CoreSGMII v2.0 Handbook 23 User Test-bench Testbench Operation and Modification A unified test-bench is used to verify and test CoreSGMII called a user test-bench. User Test-bench The user test-bench is included with the releases of CoreSGMII that verifies the operations of the CoreSGMII. A simplified block diagram of the user test-bench is shown in Figure 5. The user test-bench instantiates the CoreSGMII, behavioral code, which generates test vectors and necessary clock, reset and other signals. Test bench has tasks to generate and monitor transactional activity on G/MII and TBI interfaces. Test Bench has minimal glue logic to verify the auto negotiation functionality related status pins. Figure 5 CoreSGMII User Test-bench The following all the Test bench tasks: • Write, read access to registers using MDIO interface. • Generate packets in G/MII and TBI interfaces. • Monitor and data integrity check on G/MII and TBI interfaces. • Minimal Auto negotiation logic, which can mimic the end partner’s auto negotiation behavior. CoreSGMII v2.0 Handbook 24 User Test-bench The following are Test Cases and Sequences: 1. Auto negotiation Enable test case • Configure MDIO registers for restarting and enable Auto negotiation. • Input /I/ codes such that the DUT enters the ABILITY_DETECT state. • Input /C/ codes with a Configure_Reg of zero. • Input /C/ codes with Base Page information of a Link Partner. • Verify that Auto negation status is successful & and ANX_STATE port status is correct. 2. Auto negotiation Disable test case • Configure MDIO registers for restarting and disable Auto negotiation. • Input /I/ codes to DUT. • Input /C/ codes with a Configure_Reg of zero. • Input /C/ codes with Base Page information of a Link Partner. • Verify that Auto negation status is un-successful and ANX_STATE port status is correct. 3. 100 Mbps loop back test • Configure MDIO registers for 100 Mbps mode of operation. • Input G/MII packets with data byte incrementing from ‘h00 to ‘h12 at G/MII TX interface. • Verify the Output packets received at G/MII RX interface with expected data. 4. 10 Mbps loop back test • Configure MDIO registers for 10 Mbps mode of operation. • Input G/MII packets with data byte incrementing from ‘h00 to ‘h12 at G/MII TX interface. • Verify the Output packets received at G/MII RX interface with expected data. 5. TXD to TCG Test case • Configure MDIO registers for full duplex and 1000 Mbps mode of operation. • Input G/MII packets with data byte incrementing from ‘h00 to ‘h10. • Verify the data received at TBI interface with expected data. 6. RCG to RXD Test case • Configure MDIO registers for full duplex and 1000 Mbps mode of operation. • Input TBI packets with data byte incrementing from ‘h00 to ‘h7. • Verify the data received at G/MII interface with expected data. • RCG to RXD translation takes 20 Clock cycles until then RDERR and BCERR are not valid. 7. Disparity and 8b10b error detection Test case • Configure MDIO registers for full duplex and 1000 Mbps mode of operation. • Input TBI packets with data byte incrementing from ‘h00 to ‘h10 with disparity error. • Verify the RDERR port getting asserted for the disparity error encoded code groups. • Input TBI packets with data byte incrementing from ‘h00 to ‘h10 with 8b10B error. • Verify the BCERR port getting asserted for the disparity error encoded code groups. • RCG to RXD translation takes 20 Clock cycles until then Disparity and 8b10b error are not valid. CoreSGMII v2.0 Handbook 25 User Test-bench System Integration The example design explains the CoreSGMII features and implements the Webserver application on the SmartFusion2 Security Evaluation Kit. • Use of SmartFusion2 Ethernet MAC connected to an independent interface (SGMII) PHY through CORESGMII and COREMACFILTER. • Integration of the SmartFusion2 MAC driver with the lwIP TCP/IP stack and the FreeRTOS operating system. The microcontroller subsystem (MSS) of the SmartFusion2 device has an instance of the MAC peripheral that can be configured between the host PC and the Ethernet network at the 10/100/1000 Mbps data transfer rates. For more information on the MAC interface for the SmartFusion2 devices, refer to the SmartFusion2 Microcontroller Subsystem User Guide Figure 6 CoreSGMII Example Design • FABRIC RESET (SYSRESET_0) is used for all resets. • The CORESGMII has TXCLK, RXCLK, GTXCLK, PMA_RX_CLK0, PMA_RX_CLK1 and MDC clocks. CoreSGMII v2.0 Handbook 26 User Test-bench • 125 MHz GTXCLK clock is generated from FCCC_2. The clock source for the FCCC_2 is EPCS_3_TX_CLK. • TXCLK and RXCLK are 2.5, 25, and 125 MHz are generated from FCCC_3 depending on 10/100/1000 Mbps respectively based on SPEEDO. The clock source for the FCCC_3 is FCCC_2/GL0. • 62.5 MHz PMA_RX_CLK0 and PMA_RX_CLK1 are generated from FCCC_1. The clock source for the FCCC_1 is EPCS_3_RX_CLK. PMA_RX_CLK1 is 180° phase shift with PMA_RX_CLK0. • 2.5 MHz MDC is generated from SmartFusion2 Ethernet MAC. Run the Libero flow with enabling the Timing Driven and High Effort Place & Route options enabled. The example design clock constraints are included in the core package, generated under smart design path /component/Actel/DirectCore/CoreSGMII/ <Core version number>/constraints/ CoreSGMII v2.0 Handbook 27 Ordering Information Ordering Information Ordering Codes CoreSGMII can be ordered through your local sales representatives. It must be ordered using the following number scheme: CoreSGMII-XX, where XX is listed in Table 6. Table 6 ·Ordering Codes XX OM CoreSGMII v2.0 Handbook Description Available as obfuscated RTL only 28 List of Changes List of Changes The following table shows important changes made in this document for each revision. Date and Revision Revision 1 (June 2015) Change Initial release. CoreSGMII v2.0 Handbook Page NA 29 Product Support Product Support Microsemi SoC Products Group backs its products with various support services, including Customer Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices. This appendix contains information about contacting Microsemi SoC Products Group and using these support services. Customer Service Contact Customer Service for non-technical product support, such as product pricing, product upgrades, update information, order status, and authorization. From North America, call 800.262.1060 From the rest of the world, call 650.318.4460 Fax, from anywhere in the world 650. 318.8044 Customer Technical Support Center Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled engineers who can help answer your hardware, software, and design questions about Microsemi SoC Products. The Customer Technical Support Center spends a great deal of time creating application notes, answers to common design cycle questions, documentation of known issues and various FAQs. So, before you contact us, please visit our online resources. It is very likely we have already answered your questions. Technical Support For Microsemi SoC Products support/fpga-soc-support. Support, visit http://www.microsemi.com/products/fpga-soc/design- Website You can browse a variety of technical and non-technical information on the Microsemi SoC Products Group home page, at http://www.microsemi.com/soc/. Contacting the Customer Technical Support Center Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be contacted by email or through the Microsemi SoC Products Group website. Email You can communicate your technical questions to our email address and receive answers back by email, fax, or phone. Also, if you have design problems, you can email your design files to receive assistance. We constantly monitor the email account throughout the day. When sending your request to us, please be sure to include your full name, company name, and your contact information for efficient processing of your request. The technical support email address is [email protected]. My Cases Microsemi SoC Products Group customers may submit and track technical cases online by going to My Cases. CoreSGMII v2.0 Handbook 30 Product Support Outside the U.S. Customers needing assistance outside the US time zones can either contact technical support via email ([email protected]) or contact a local sales office. Sales office listings can be found at www.microsemi.com/soc/company/contact/default.aspx. ITAR Technical Support For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms Regulations (ITAR), contact us via [email protected]. Alternatively, within My Cases, select Yes in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR web page. CoreSGMII v2.0 Handbook 31 Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense & security, aerospace and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world’s standard for time; voice processing devices; RF solutions; discrete components; security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has approximately 3,600 employees globally. Learn more at www.microsemi.com. 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