iniUART data sheet Features: • Configurable Transfer Rate: 1200bps to 115.2kbps with Accuracy Better than 0.1% from 8MHz Clock! • Data Format: 7, 8 Bits • Parity Enable, Odd/Even, Error Detection • Stop Bit: 1, 2 Bits • Format Check • 3-Point Input Sampling, Glitch Rejection • Parallel Interface with Event Control • Structured, Synchronous VHDL Design • Flexible Interfaces Structure of iniUART: The iniUART is an innovative, flexible implementation of an Universal Asynchronous Receiver Transmitter (UART) device. iniUART, which uses the RS- Tx Unit D_in TX Config Format Analyzer Interrupts Status D_out Rx Unit Clk Baudrate Generator RX iniUART INICORE - the reliable Core and System Provider. We provide high quality IP, design expertise and leading edge silicon to the industry. INICORE INC. 5600 Mowry School Road, Suite 180, Newark, CA 94560 Tel: 510 445 1529 Fax: 510 656 0995 E-mail: [email protected] Web: www.inicore.com Ref.Nr.: 391-DS-14 / 07/99 232 serial protocol, provides the interface between a microprocessor and a serial port or between the system and a standard serial port. The core contains a highly accurate programmable baud rate generator, serial receiver and transmitter communications channels, and interrupt control signals. The iniUART core may be used as a data link layer with parallel interfaces and event communication. Application-specific blocks (e.g., interrupt controller, special interfaces, status reporting circuits) can then be built around the iniUART and will not affect the main functionality. INICORE’s in-depth know how in serial communication and frequency synthesizers gives you the best benefit for the UART of your needs. INICORE offers the structural VHDL UART simulation/synthesis model for the target technology of your choice. INICORE AG iniUART data sheet reset_n tx_data(7:0) tx_we tx_busy clock outputs clk physical layer config(21:0) system control The iniUART core may be used as a data link layer with parallel interfaces and event communication. Microprocessor specific interfaces must be built around the iniUART, as well queues, interrupt controllers and status reporting circuits. The following picture shows all inputs and outputs: transmitter 1 Overview rx_ready par_error form_error 1.1 Event communication bit_clk_ebl 16x_clk 16x_clk_ebl rx_pin tx_pin receiver rx_data(7:0) bit_clk iniUART For communicating events, the iniUART core uses or produces always active ‘1’ pulses, which are activated for only one clk cycle. In the inactive state, they remain low with respect to the rising clk edge, so glitches may occur. For communicating over clock domains, these events must be synchronized first! event clk event input event output tsetup tpd thold tpd The parameters tsetup, thold and tpd are technology dependent and must be determined according to the chosen technology. Ref.Nr.: 391-DS-14 Page 2 of 7 INICORE AG iniUART data sheet 2 IO description The following part lists the input and output ports of the iniUART core and gives a short overview of their functionality. 2.1 General inputs These pins are used to clock and initialize the whole iniUART core. There are no other clocks in this core. pin name 2.2 Configuration clk in system clock for the whole iniUART reset_n in asynchronous system reset, active low The configuration pins are used to set the bitrate, bit timing and output format. They’re static inputs. and used for both receiver and transmitter in common. pin name 2.3 Serial interface type description baudrate[15:0] in Defines the baudrate. For formulas, resolution etc. see ‘Serial bit clocks’ data_78 in ‘0’: use 7 bit data ‘1’: use 8 bit data par_ebl in ‘0’: no parity check, no parity bit transmitted and received ‘1’: use parity check, parity bit inserted and checked par_pol in ‘0’: use even parity (number of ones in a byte, including parity bit is even) ‘1’: use odd parity (number of ones in a byte, including parity bit is odd) ignored when par_ebl is inactive! stop_12 in ‘0’: use and check 1 stop bit ‘1’: use and check 2 stop bits tx_run in ‘0’: inactive transmitter, ignores all inputs, outputs are inactive ‘1’: transmitter is working rx_run in ‘0’: inactive receiver, ignores all inputs, outputs are inactive ‘1’: receiver is working The serial interface includes the receive and transmit path separately. It is full a duplex solution, receive and transmit is possible at the same time. pin name Ref.Nr.: 391-DS-14 type description type description rx_pin in Pin for the incoming bit stream. The inactive state is logic 1 tx_pin out Pin for the outgoing bit stream. The inactive state is logic 1 Page 3 of 7 INICORE AG 2.4 Serial bit clocks iniUART data sheet The baudrate generator produces for diagnostics and other purposes a bit clock, which is used for transmitting and receiving. Also, for a synchronous use in the same clock domain, there is a bit clock event pulse with the same frequency as the bit clock, but its high time is only one clk cycle (125ns @ 8MHz). See also the diagram. pin name type description bit_clk out Baudrate, generated from the baudrate generator, nearly symmetrical. bit_clk_ebl out Baudrate, same frequency as bit_clk, but is logic 1 for 1 clk cycle when bit_clk has its rising edge. 16x_clk out 16x Baudrate, generated from the baudrate generator, nearly symmetrical. (16 x clock signal as in 16550 devices) 16x_clk_ebl out 16x Baudrate, same frequency as 16x_clk, but is logic 1 for 1 clk cycle when 16x_clk has its rising edge. bit_clk 1 bit time bit_clk_ebl 16x_clk 16x_clk_ebl The baudrate generator is not a simple prescaler, but an innovative DCO (digitally controlled oscillator) which allows generating all baudrates from the system clock. There is no special quartz needed for that purpose and you’re free in choosing the system clock frequency. For configurating the baudrate, the 16bit value is calculated according the following formula: fclk n Baudrate = ---------- -------16 2 18 resp. 2 18 n = ----------16 Baudrate fclk where Baudrate is the transmitting speed in bits per second fclk is the system clock speed in Hz n is the 16bit value to be programmed Example: For 8Mhz clock and 64kbps, n is 33554(dec), accuracy better than 13ppm, For 10Mhz clock and 1200bps, n is 503(dec), accuracy better than 600ppm. Remark: The faster the baudrate, the better the accuracy, but more jitter is added. Maximum absolute jitter is always equal 1/fclk. Ref.Nr.: 391-DS-14 Page 4 of 7 INICORE AG 2.5 Transmitter interface iniUART data sheet For transmitting data, a parallel event controlled interface is used. It is an efficient way to embed the iniUART in systems as well as connecting simple or complex specific interfaces, including queues etc., to it. pin name type description tx_data[7:0] in 8bit data to be transmitted. For 7bit configuration, bit[7] is ignored (use only tx_data[6:0]). The data must be valid when tx_we is active. tx_we in Event for storing the tx_data in the transmit shift register. It’s up to the system to not activate this input when the iniUART is busy. tx_busy out When the transmitter is sending a byte, this status output remains active (logic 1) until it is ready to send a new byte. While tx_busy is 1, tx_we mustn’t be activated. The following diagram shows a typical case: clk tx_we start sending ready for next byte tx_busy tx_pin tx_data valid transmitting byte data may change The transmitter path stores the incoming byte in the shift register by means of the tx_we signal and starts the transmitting activity. tx_busy goes high also and remains high until the data is sent. Ref.Nr.: 391-DS-14 Page 5 of 7 INICORE AG 2.6 Receiver interface iniUART data sheet For receiving data, the same type of interface is used as in the transmitter path. pin name Ref.Nr.: 391-DS-14 type description rx_data[7:0] out 8bit data that has been received. For 7bit configuration, bit[7] is ignored (use only rx_data[6:0]). The data will be stable when rx_ready is active, but it will change when the iniUART is actually receiving a byte. For making the received byte available permanently, it has to be buffered. rx_ready out Event (active 1) for signalling, that a new byte is arrived and the rx_data is valid now. par_error out Event (active 1) for signalling, that a byte with wrong parity has been received and aborted (it’s not visible at rx_ready) This signal is always inactive when par_ebl is deactivated. form_error out Event (active 1) for signalling, that a byte with wrong format has been received and aborted (it’s not visible at rx_ready) Page 6 of 7 INICORE AG iniUART data sheet This is a normal case, where a correct byte arrives... clk rx_ready byte received rx_pin receiving byte par_error rx_data data is changing data valid ... and when a parity error occurs clk rx_ready no byte received rx_pin receiving byte with parity error parity error event par_error rx_data data is changing ... and discarded The receiver path contains several checks and special features. First, the level at the rx_pin is watched. When a falling edge is detected, the receiver is started. Glitches are successfully rejected since the level of the start bit is fully checked. Now, data is shifted in the receive register and after the check of the stop bit(s) and the parity bit (when configured so) the byte is marked as valid. The following list show the cases where an incoming byte is aborted: Ref.Nr.: 391-DS-14 Glitch on rx_pin not reported Stop bit(s) not equal logic 1 not reported Parity bit doesn’t match internally calculated parity reported by par_error Page 7 of 7