Optimized for VME A24D32 Slave Controller Description Features The VMEbus was first standardized in 1981 and is still in wide use. With the advances in integration technologies, custom integrated VME controllers open the door for smaller and cheaper systems. Inicore offers a wide range of different VME slave controllers. Each one optimized for a certain application. The difference lies mainly in the address and data bus width and the supported data modes. The VME slave controller shields all the complexity of the asynchronous VMEbus and provides an easy-to-use, synchronous parallel user side interface towards custom logic. A built-in interrupter handles all local interrupt requests and acknowledgments. on-chip bus TIM ERmod VM E Slave Controller • VME slave controller • Data modes: D8, D16, D32 • Address modes: A16, A24 • Supports read, write, readmodify-write cycles • Configurable D8, D16 or D32 interrupter INTCmod VMEbus • ANSI/VITA 1-1994 compliant GPIOmod • Fully synchronous user side interface UARTmod • User selectable wait-states Bus Bridge • Synchronous design User Decode VMEchip Applications Figure 1: Sample application The figure above illustrates a typical application where several peripheral functions together with the VME slave core as well as a bus bridge are integrated in one FPGA. Supported modes • Industrial control • Military • Aerospace • Telecom • Data modes: D8, D16, D32 • Address modes: A16, A24 • Access modes: Read, write, read-modify-write • Interrupter: D8, D16, D32, RORA, ROAK • Medical Sample Utilization and Performance Table Optimized for Actel Devices Family ProASIC Axcelerator SXA RTSX PLUS Device - (speed grade) APA150 AX500-3 SX72A-3 RTSX72S-1 MIL s-mod 177 177 177 Utilization c-mod Tiles 453 159 163 162 RAM Total 6% 4% 6% 6% Performance [MHz] 67 110 71 43 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 Tel: 510 445 1529 Fax: 510 656 0995 www.inicore.com Page 1/2 Us er Sid e Bu s VM E Slav e In terru p ts VM E Bu s v m e_ addr[2 3 :1 ] v m e_ am [5 :0 ] v m e_ da t a _ in [3 1 :0 ] v m e_ da t a _ o ut [3 1 :0 ] v m e_ da t a _ in t _ drv _ n v m e_ da t a _ drv _ n v m e_ da t a _ dir v m e_ ds0 _ n v m e_ ds1 _ n v m e_ lwo rd_ n v m e_ as_ n v m e_ writ e_ n v m e_ dt ac k _ n v m e_ be rr_ n v m e_ ia c k _ n v m e_ ia c k _ in _ n v m e_ ia c k _ o ut _ n v m e_ ir q_ n [6 :0 ] user_ addr[2 3 :2 ] user_ am [5 :0 ] user_ acc _ req user_ acc _ rdy user_ dat a _ rd[3 1 :0 ] user_ dat a _ wr[3 1 :0 ] user_ rwn user_ by t e_ v alid[3 :0 ] user_ ia ck user_ ir eq user_ ile v [2 :0 ] user_ iv ec [3 1 :0 ] Decod e About Inicore reset _ n clk _ sy s in t _ user_ am [5 :0 ] in t _ user_ addr[2 3 :1 ] user_ acc ess_ ebl Interfaces Typ e Description Global Signals clk in System clock reset_n in Asynchronous system reset, active low VME Bus Pin Name Typ e Description vme_iack_out_n out Interrupt acknowledge chain out vme_irq_n[6:0] out Interrupt request User Side Bus user_addr[23:2] out Address bus vme_addr[23:1] in Address bus user_am[5:0] out Address modifier code vme_am[5:0] in Address modifier code user_acc_req out Data access request vme_data_in[31:0] in Data bus input user_acc_rdy in vme_data_out[31:0] out Data bus output Data access request ready vme_data_int_drv_n out Internal i/o driver enable user_data_rd[31:0] in Data read bus vme_data_drv_n out External data bus driver enable user_data_wr[31:0] out Data write bus user_rwn out vme_data_dir out External data bus driver direction Data read or write access user_byte_valid [3:0] out Data byte valid in Data strobe 0 User Decode vme_ds1_n in Data strobe 1 int_user_addr[23:1] out Address bus vme_lword_n in Long word indicator int_user_am[5:0] out Address modifier code vme_as_n in Address strobe user_access_ebl in Valid user access vme_write_n in Read write not indicator Interrupt vme_dtack_n out Data acknowledge user_iack out Interrupt acknowledge vme_berr_n in Bus error user_ireq in Interrupt request vme_iack_n in Interrupt acknowledge user_ivec[31:0] in Interrupt vector vme_iack_in_n in Interrupt acknowledge chain in user_ilevel[2:0] in Interrupt request level vme_ds0_n Easy-to-use IP Cores System-on-Chip Solutions Consulting Services ASIC to FPGA Migration Figure 2: Symbol Pin Name FPGA and ASIC Design Obsolete ASIC Replacements Inicore is an experienced system design house providing FPGA / ASIC and SoC design services. The company's expertise in architecture, intellectual property, methodology and tool handling provides a complete design environment that helps customers shorten their design cycle and speed time to market. Our offering covers feasibility study, concept analysis, architecture definition, code generation and implementation. When ready, we deliver you a FPGA or take your design to an ASIC provider, whatever is more suitable for your unique solution. Deliverables The core is available as Actel optimized netlist or as RTL version. Actel Optimized Netlist: • Netlist for target FPGA, EDIF, Verilog and VHDL format • User Guide RTL Source Code: • VHDL or Verilog source code • Funtional verification testbench • Synthesis script • Timing constraints • User guide © 2003, Inicore Inc, All rights reserved. All brands or product names mentioned are the property of their respective holders. 51405.71.02 Sept/2003 INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 Tel: 510 445 1529 Fax: 510 656 0995 www.inicore.com Page 2/2