Reed-Solomon Encoder and Decoder Core Datasheet For Actel

4i2i Communications Ltd.,
Doig Scott Building, Craibstone, Aberdeen AB21 9YA, UK.
Tel. +44 1224 712844, Fax +44 1224 714413,
email: [email protected], web: http://www.4i2i.com
Reed-Solomon Encoder and
Decoder Core Datasheet
For Actel FPGAs
Overview
provided which allow this to meet the
requirements of nearly all the various
modern standards using RS error correc4i2i’s Verilog or VHDL Reed-Solomon
tion. The core has been demonstrated
core is a leading edge soft IP core which
compatible with a wide range of Inhas been sold widely and is well tested in
ternational Standards including CCSDS,
silicon. It is suitable for just about any
DECT and xDSL.
application requiring block error correctWith s-bit symbols the core can suping codes. The core can support fulllength and shortened systematic Reed- port RS codewords with any length less
Solomon codes with s-bit symbols (s > than 2s . (The RS code is shortened
2). A number of customer options are by conceptually setting a number of the
1
data symbols to zero and replacing them
at the decoder). The core can operate
with any chosen number of parity symbols (2t) in which case up to t symbol
errors can be corrected. Optionally, the
decoder can be provided with an erasure
decoding capability that allows up to 2t
erasures to be corrected. Status indicators are provided to indicate decoding
success/failure, and to give counts of corrected errors and, optionally, erasures.
The core is available in a range of
options ranging from a small and area
efficient core to an extremely fast and
flexible pipelined core which is capable
of 1 clock cycle per symbol processing
for a wide range of RS codes. Cores are
available which allow the codeword parameters to be changed on the fly.
• Demonstrated compatibility with
a wide range of standards including CCSDS, ADSL(ANSI T1.413)
and DECT.
• Options for internal or external
decoder RAM buffer.
• Easy to use encoder/decoder interface.
• Compatible ANSI C source code
available.
Deliverables
The core can be supplied either as synthesizable Verilog or VHDL source code.
The RS generator polynomial and
primitive polynomial for the field are parameters which may be specified by the
customer. Alternatively, 4i2i will agree
to conform to a specified standard.
The synthesizable source code is supplied for internal use along with a license
to allow redistribution of the synthesized
design within one specified product or
product line without payment of per unit
royalties.
A comprehensive testbench is supplied which creates random data, encodes the data, inserts random errors
and checks the decoders error-correcting
operation and status indicators. The
testbench provides a good illustration of
writing code to interface to the core. Optionally the complete encoder, decoder
and testbench can be additionally provided in ANSI C.
Features
• Parameterized RS(n,k) code with
options for fixed or on the fly variable n, k and symbol size s.
• Full-duplex encoding and decoding operation.
• Optional erasure decoding in the
sequential (non-pipelined) version
of the core.
• Single clock cycle encoder latency
in the sequential core; 1 clock cycle per symbol decoding in the
pipelined core, with latency just
over 3 codewords.
• Status signals for success flag, and
error and erasure counts.
Encoder overview
• User-specified RS generator polynomial and finite field primitive
polynomial. DVB (x8 + x4 + x3 +
x2 +1) and Intelsat (x8 +x7 +x2 +
x + 1) polynomials as standard.
Encoding is performed using 2t parallel
linear feedback shift registers. All data
paths are s−bits wide, and multiplications and additions are performed within
the specified galois field.
2
Figure 1: Decoder architecture
Decoder overview
codewords with ρ erasures and σ errors
where
The decoder uses the Berlekamp-Massey
2ρ + σ 6 2t
and Forney algorithms to calculate the
where 2t is the number of parity symposition and magnitude of symbol erbols.
rors. The symbol errors are corrected
and the recovered codeword (with or
without parity symbols) is output from Encoding and decoding speed
the decoder.
The RS encoder requires k active clock
Where a codeword has errors up cycles to output the data symbols folto the error-correcting capability of the lowed by 2t active clock cycles to output
code, the decoder will correct the errors the parity symbols. There is a latency of
and provide an error count. If more er- one active clock cycle.
rors occur than can be corrected then
The number of clock cycles required
the decoder will usually detect this sit- to perform decoding depends on the paruation, leave the codeword and flag de- ticular code (n, k and s values) being
coder failure.
used, and on the number of errors and
An option is provided to allow the erasures being corrected. Generally ladecoder to perform erasure decoding. In tency improvements are available at the
this case an additional 1-bit flag is asso- expense of gate count, and vice-versa.
ciated with each symbol that is input to The sequential decoder processes only
the decoder. This flag is used to pass one codeword at a time. On the other
soft decision information from the de- hand, with the pipelined decoder it is
coder to indicate whether the symbol is possible in most cases to decode words
erased. The decoder will always correct at a rate of one symbol per clock cycle.
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should be chosen to be greater than
In this situation the latency through the
decoder is fixed and is equivalent to just
over three codewords. Variable latency
decoding is also an option, for codes involving variable n, k values; this requires
an increased number of RAM buffers.
A selection of decoding clock cycle
requirements is provided in Table 1 below, for a symbol size of 8 bits. In the
case of the sequential (non-pipelined) decoder, figures refer to the absolute worstcase codeword.
The decoding rate depends on the
core options. For the high performance
pipelined core, in order to maintain
one symbol per clock cycle decoding, n
(t2 + 12t + 7) ∗ data rate(bps)/clock(Hz).
Implementation
Example implementations of the s =8bit RS(255,239) encoder, sequential decoder, and encoder/decoder cores in Actel devices are given in Table 2 - Table 4.
(It should be noted that the decoder
in the RTSX-S and SX/SX-A devices
would require an external RAM buffer to
store the input codeword.) Further examples can be generated on request for
any customer specification.
RS(n, k)
Latency
(clock cycles)
Speed
(clocks per symbol)
Sequential (255,239)
755
755/255 = 2.96
Sequential (236,220)
717
717/236 = 3.04
Sequential (32,28)
111
111/32 = 3.47
Pipelined (255,239)
843
1
Pipelined (236,220)
786
1
Pipelined (32,28)
117
35/32 = 1.09
Table 1: Example decoder timing requirements
4
Family
Device
(-speed grade)
Seq.
(R-cells)
ProASICPlus
APA075-STD
Axcelerator
AX125-3
154
RTSX-S
RT54SX32S-1
SX/SX-A
54SX08A-1
Comb.
(C-Cells)
Total
util.
RAM
(blocks)
Performance
Throughput
26%
0
42 MHz
314 Mbps
337
25%
0
67 MHz
502 Mbps
154
337
18%
n/a
42 MHz
314 Mbps
154
337
64%
n/a
53 MHz
397 Mbps
Table 2: Example implementations of 8-bit RS(255,239) Encoder in Actel
FPGAs
Family
Device
(-speed grade)
Seq.
(R-cells)
ProASICPlus
APA450-STD
Axcelerator
AX500-3
1168
RTSX-S
RT54SX72S-1
SX/SX-A
54SX72A-1
Comb.
(C-Cells)
Total
util.
RAM
(blocks)
Performance
Throughput
70%
1
27 MHz
68 Mbps
3591
60%
1
40 MHz
101 Mbps
1169
3534
78%
n/a
29 MHz
73 Mbps
1175
3465
77%
n/a
32 Mhz
80 Mbps
Table 3: Example implementations of 8-bit sequential RS(255,239) Decoder
in Actel FPGAs
Family
Device
(-speed grade)
Seq.
(R-cells)
ProASICPlus
APA450-STD
Axcelerator
AX500-3
1322
RTSX-S
RT54SX72S-1
SX/SX-A
54SX72A-1
Comb.
(C-Cells)
Total
util.
RAM
(blocks)
Performance
Throughput
77%
1
26 MHz
65 Mbps
3925
66%
1
40 MHz
101 Mbps
1323
3871
87%
n/a
29 MHz
73 Mbps
1331
3830
87%
n/a
31 Mhz
78 Mbps
Table 4: Example implementations of 8-bit RS(255,239) Encoder and Sequential Decoder core in Actel FPGAs
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