7:1 Video SERDES Core Serializer/Deserializer Product Features RSTN A1_IN(6:0) A2_IN(6:0) A3_IN(6:0) CLK1_IN text + TX_A0 + TX_A1 + TX_A2 + TX_A3 + TX_CLK1 - + + RX_A1 + RX_A2 + RX_A3 + RX_CLK1 RX_A0 CLK 7:1 SERDES (28-bit Data Shown) SERDES Features General Channel Link interface Supports 6-bit video data via three LVDS channels Supports 8-bit video data via four LVDS channels Supports 10-bit video data via five LVDS channels Transmitter LVDS transmit clock automatically aligned to data 7:1 data serialization Transmits data on 3, 4, or 5 LVDS channels Receiver PLL generation of system clocks Auto-alignment of receiver data to clock Up to five input LVDS data channels 1:7 data deserialization Supported Standards VGA – 640x480 – Yes SVGA – 800x600 - Yes XGA – 1024x768 - Yes HDTV 720p – 24 Hz and 30 Hz Only HDTV 1080p - No A0_OUT(6:0) Deserializer A0_IN(6:0) Serializer General Features 7:1 SERDES Design Designed specifically for the Actel ProASIC3 and derivatives Supports Digital Display Interfaces via OpenLDI specification (Channel Link) Can be used for 6-, 8-, and 10bit video data (supports HD video) Supports 21-bit parallel data on three LVDS channels Supports 28-bit parallel data on four LVDS channels Supports 35-bit parallel data on five LVDS channels Supports flat-panel LVDS rates to 200 MHz Verilog testbench available text A1_OUT(6:0) A2_OUT(6:0) A3_OUT(6:0) RX_CLK1_OUT