Overview iW-SDIO Slave controller acts as a bridge core of SDIO to UART. It also facilitates the design of SDIO cards and reduces the development time. By using this IP core, customers no longer need to spend time on handling the SD bus protocol since such function is provided by the core. Features X X X X X X X X X X Compliant with SD Physical Specification Version 2.00 and SDIO Specification Version 2.00 SPI, 1-bit and 4bit SD modes Supports SDIO Interrupt feature Supports all mandatory SDIO Commands/Response types SPI Mode : CMD0, CMD5, CMD52, CMD53, CMD59 SD Mode : CMD0, CMD3, CMD5, CMD7, CMD52, CMD53 CRC7 checking/generation for Command/Response CRC16 checking/generation for Data transfer Supports High Speed Mode(upto 50MHz) of operation Data Transfer in Multi Byte and Multi Block mode using CMD53 8 GPIO lines supported through Function0 UART 16550 function features: Programmable baud generator divides any input clock by 1 to (216 -1) and generates the 16x clock Hardware Handshaking signals (CTS, RTS) 5, 6, 7, or 8-bit characters Even, odd, or no-parity bit generation and detection 1, 1/2, or 2-stop bit generation Baud generation (DC to 1.5M baud) Line break generation and detection Independently controlled transmit, receive, line status, and data set interrupts Core Benefits X Helps in designing in SDIO cards X Can be used as a bridge core of SDIO to UART Core Applications X Portable devices: Cell phone, PDA, GPS, GPRS and etc. X Consumer electronic and security devices Resource Utilization Summary Family Device ProASIC3 A3P250 Cores RAM IO 4355 (71%) 4 (50%) 16 (11%) PLL Fmax (MHz) 0 48 Block Diagram SDIO Slave Controller SDIO Interface CRC7 CIA Registers CMD Shifter CMD FSM Wishbone Master CRC16 Data FSM Data Shifter Deliverables X X X X Technical Specification RTL Verilog Synthesizable Code Comprehensive Test Environment Technical Support and Maintenance Wishbone Bus UART Function UART Interface