Generates color and control data for standard displays in the following resolutions: DISPLAY-CTRL High-Resolution Display Controller Core Implements a controller that accepts video data and works with a digital/analog converter (DAC) to drive standard QVGA (320x240) to WUXGA (1920x1200) displays. The core accepts two different standard input formats — 15-bit (5:5:5) and 24-bit (8:8:8) RGB — and produces 24-bit RGB pixel data. It also generates all of the required horizontal and vertical timing periods: horizontal and vertical front porch, back porch and sync intervals. Video aspect ratios and monitor frequencies are configurable, and various display functions are provided. The core passes 24-bit RGB to standard analog/digital video converters such as Analog Devices’ ADV7120 CMOS, 80MHz, Triple 8-Bit Video DAC (ADV®). The DAC then generates output signals compatible with RS-343A/RS-170 standards. Test and power save modes are built into the core. The design is strictly synchronous with positive-edge clocking, no internal tri-states and asynchronous reset; therefore scan insertion is straightforward. Actel FPGA implement requires 5,324 cells in Fusion or ProASIC3 devices. Applications The core is designed to work with a video data processor in a variety of video display systems, including • Portable video systems • Digital cameras with video output • Advanced mobile phones with video capabilities Block Diagram − QVGA 320 x 240 85Hz − VGA 640 x 480 85Hz − SVGA 800 x 600 85Hz − XGA 1024 x 768 85Hz − SXGA 1280 x 1024 85Hz − HD 720 1280 x 720 60Hz − UXGA 1600 x 1200 60Hz − HD 1080 1920 x 1080 60Hz − WUXGA 1920 x 1200 60Hz Works in conjunction with external video DAC such as Analog Devices’ ADV7120 Accepts two standard video data formats: − 24-bit RBG (8:8:8) − 15-bit RBG (5:5:5) Output interface − 8:8:8 24-bit RGB video − HSYNC and VSYNC signals or one composite − Blanking (Data Enable) signal Display functions with hardware support: − Scroll (in horizontal and ver- tical directions) − Sub-screen display (any posi- tion) − Horizontal flip screen Fully configurable monitor frequencies and aspect ratios Progressive scanning mode 32-bit data path Configurable internal FIFO Integrated Test mode: core generates color bar without any AHB bus transactions Internal, event-stimulated, interrupt request generation with masking capability Dedicated unidirectional DMA controller with burst transaction support Built-in Power Save mode Integrated with AMBA™ bus: − AMBA™ AHB slave unit inter- faces with host controller − AMBA™ AHB master unit in- terfaces with host memory February 2009 Functional Description The core combines a flexible data generation module with additional elements necessary to communicate with its host system, accept and convert different forms of video data, and store that data for processing and output. DMA AHB Unidirectional DMA controller with an AHB Master Interface. It is implemented to take image data from the AHB data bus. The AHB Master Interface is compatible with the ARM® AMBA™ Advanced High-speed Bus (AHB) interface standard specification version 2.0. It operates as a master device for data transfers, and only read transfers can be initiated. It supports a 32-bit width data bus and a 32-bit width address bus. The AHB Master can initiate only one of the following transfer types: SINGLE, INCR, or INCR16. AHB Slave Bidirectional AHB Slave Interface for the CONTROL block. The AHB Slave Interface is compatible with the ARM® AMBA™ Advanced High-speed Bus (AHB) interface standard specification version 2.0. It supports a 32-bit width data bus and a 32-bit width address bus. The AHB Slave supports only SINGLE transfers. Conv RGB format converter. Converts input RGB15 format to output RGB24 format and stores into the FIFO. RGB Pixel data output and synchronization module. The RGB module takes data from the FIFO and outputs this data with horizontal and vertical synchronization signals (HSYNC and VSYNC), as well as the video blanking signal (Data Enable). Additionally it generates data in test-mode without any AHB bus activity. SFR Sync Software reset generation and synchronization module. Write FIFO CTRL & Read FIFO CTRL FIFO component implemented in a Dual Port RAM. It is designed to buffer pixel data between the CONV and RGB units and works in two clock domains. The size of the FIFO buffer is parameterized. There are two controllers: WRITE FIFO CTRL for writing data from CONV to FIFO and READ FIFO CTRL for reading data from FIFO to RGB. The core was designed to make the integration of a highresolution display controller into an application-specific integrated circuit (ASIC) or a system-on-a-chip (SoC) design easy to accomplish Implementation Results DISPLAY-CTRL reference designs have been evaluated in a variety of technologies. The following are sample Actel results optimized for area with a FIFO size of 512x48 bits implemented. Actel Device Fusion AFS1500-2 ProASIC3 A3P1000-2 Cells Sequ (R) Comb (C) RAM Blocks I/Os Fmax (MHz) 1184 4140 6 196 63 1184 4140 6 196 64 Support The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available. Performance VESA Monitor Timing Specification contains pixel clock frequencies for standard graphic resolutions; however, the VESA Coordinated Video Timing Generator can be used to calculate reduced timing parameters for LCD panels and monitors. Pixel clock frequency versus on-screen resolution according to VESA CVT is shown in the following table. Resolution Refresh Rate Pixel Clock 320 x 240 85 Hz 8.50 MHz 640 x 480 85 Hz 35.00 MHz 800 x 600 85 Hz 56.75 MHz 1024 x 768 85 Hz 94.50 MHz 1280 x 1024 85 Hz 91.00 MHz 1280 x 720 60 Hz 64.00 MHz 1600 x 1200 60 Hz 130.25 MHz 1920 x 1080 60 Hz 138.50 MHz 1920 x 1200 60 Hz 154.00 MHz Verification The core’s functionality was verified by processing bitmap pictures. These were converted by a C program into stimuli and reference files. The stimuli files were applied to core inputs, and the reference files compared with the core simulation outputs. The DISPLAY-CTRL has also been verified through extensive functional simulation and it has achieved high Code Coverage results. A demo system has been implemented. Configurability The DISPLAY-CTRL core has a set of synthesizable parameters that allow adjustment of the core for a particular application: DEPTH – defines the depth of the FIFO memory LEVEL_AFULL – defines the almost full level of the FIFO Default endianness type is Little-endian. Big-endian is selected by using `define BIG_ENDIAN directive. CAST, Inc. Page 2 Deliverables The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation. The Actel version includes: • Post-synthesis EDIF netlist • Sophisticated self-checking HDL Testbench including: • An example system design • External Dual Port TAM • Behavioral model of an external Video DAC • Example AMBA™ bus systems • Clock generator • Simulation scripts, vectors, and expected results • Place and route script • Comprehensive user documentation, including a detailed specification, system integration guide and a verification specification Related Products TVOUT-CTRL – is a synthesizable core which implements a video display controller compatible with the ITU-R BT.601/BT.656 recommendation (formally CCIR-601 and CCIR-656). The Video DAC interface of the controller is compatible with Analog Devices’ ADV7174/79 encoder video chip. The TVOUT-CTRL accepts three different input formats and produces 4:2:2 YCbCr pixel data format. It can also generate all of the required horizontal and vertical timing periods: horizontal and vertical front porch, back porch and sync intervals. Application Example This application enables transmission of data from the host memory to an LCD monitor, or a CRT monitor, or a TFT panel. The CPU controls the configuration of the core and process interrupt requests using an AMBA™ AHB Slave bus. Data from the host memory are sent to the DISPLAYCTRL through an AMBA™ AHB Master interface. The DISPLAY-CTRL outputs data in RGB24 format. Examples of supported Video DAC devices are: • ADV7120 – Analog Devices, 80MHz Triple 8-Bit Video DAC • CH7301C – Chrontel, DVI Transmitter up to 165M pixels/second • AD9889B – Analog Devices, 165MHz HDMI/DVI Transmitter ST7787 – Sitronix, 262K Color Single-Chip TFT Controller/Driver CAST, Inc. 11 Stonewall Court Woodcliff Lake, NJ 07677 USA tel 201-391-8300 fax 201-391-8694 Copyright © CAST, Inc. 2009, All Rights Reserved. Contents subject to change without notice. Trademarks are the property of their respective owners.