High and Low Side N-Channel Gate Driver Product Datasheet IDTP9090 Features Description Input Voltage Range: 4.5 to 5.5 Output Voltage Range: Control Range 0-30V Peak MOSFET Drive current into 3nF LGDRV Sink 3A LGDRV Source 1A UGDRV Sink 1A UGDRV Source 0.8A Static Current (inputs at 0V) 175 A No-load, 250kHz current 1.3mA On-chip boost Schottky diode Dual Independent Schmitt trigger inputs with ~2V hysteresis and 28 A pull downs The IDTP9090 is available in an 8-lead 3mm x 3mm QFN package. Typical Application Circuit +5V VIN 1 UGIN 3.4V UVLO with 0.4V of hysteresis for sequencing with controller 2 UG LOGIC 8 7 BOOST 47nF UGDRV UGRTN UVLO 24ns nominal propagation delays Tx The IDTP9090 is a high-performance dual-PWM-input MOSFET driver for wireless power and general-purpose applications. It is designed to interface directly with a power controller IC and provide a 5V gate drive to two separately-controlled power MOSFETs. The IDTP9090 contains one ground-referred MOSFET driver and one floating MOSFET driver capable of floating up to 30V. 5 LGIN 6 LG LOGIC Not All Blocks and Connections Are Shown For General Reference Purposes Only Not To Scale VCC LGDRV 4 3 0.1uF GND Applications Wireless Power Gate Driver General Purpose MOSFET driver Custom ASIC Power Logic Buffer Motor Driver Package: NLG8 – QFN-8 3x3-8 QFN (See page 9) Ordering Information PART NUMBER MARKING PACKAGE AMBIENT TEMP. RANGE SHIPPING CARRIER QUANTITY P9090-0NLGI P9090-0NLGI8 P9090I P9090I NLG8 - QFN-8 3x3x1mm NLG8 - QFN-8 3x3x1mm -40°C to +125°C -40°C to +125°C Tube Tape and Reel 25 2,500 Revision 1.1.1 1 © 2013 Integrated Device Technology, Inc. IDTP9090 0 Product Datasheet Absolute Maximum Ratings These absolute maximum ratings are stress ratings only. Stresses greater than those listed below (Table 1 and Table 2) may cause permanent damage to the device. Functional operation of the IDTP9090 at maximum ratings is not implied. Continuous application of the absolute maximum rating conditions affects device reliability. Table 1. Absolute Maximum Ratings. All voltages are referred to ground, unless otherwise noted. PINS RATING UNITS VCC, UGIN, LGDRV, LGIN, -0.3 to 6 V UGRTN -0.3 to 30 V BOOST, UGDRV -0.3 to 35 V BOOST to UGRTN -0.3 to 6 V UGDRV to UGRTN -0.3 to 6 V Table 2. Package Thermal Information SYMBOL DESCRIPTION RATING UNITS JA Thermal Resistance Junction to Ambient (NLG8 - QFN) 119.6 C/W JC Thermal Resistance Junction to Case (NLG8 - QFN) 131.84 C/W JB2 Thermal Resistance Junction to Board (NLG8 - QFN) 13.4 C/W TJ Junction Temperature -40 to +150 C TA Ambient Operating Temperature -40 to +125 C TSTG Storage Temperature -55 to +150 C TLEAD Lead Temperature (soldering, 10s) +300 C Note 1: The maximum power dissipation is PD(MAX) = (TJ(MAX) - TA) / θJA where TJ(MAX) is 150°C. Exceeding the maximum allowable power dissipation will result in excessive die temperature, and the device will enter thermal shutdown. Note 2: This thermal rating was calculated on the JEDEC 51 standard 4-layer board with dimensions 3” x 4.5” in still air conditions. Note 3: Actual thermal resistance is affected by PCB size, solder joint quality, layer count, copper thickness, air flow, altitude, and other unlisted variables. Note 4: For the NTG8 package, connecting the 1.1 mm X 1.1 mm EP to internal/external ground planes with a 2x2 matrix of PCB plated-throughhole (PTH) vias, from top to bottom sides of the PCB, is recommended for improving the overall thermal performance. Table 3. ESD Information TEST MODEL PINS HBM All ±1500 V CDM All ±500 V Revision 1.1.1 RATINGS 2 UNITS © 2013 Integrated Device Technology, Inc. IDTP9090 0 Product Datasheet Electrical Specifications VVCC = 5V, TA = -40°C to +125°C, typical values are at TA =+25°C, unless otherwise noted. All voltages are referred to ground, unless otherwise noted. Table 4. Device Characteristics SYMBOL BIAS VVCC UGDRVMCM IQDC DESCRIPTION MIN TYP MAX UNITS 4.5 - - 5.5 35 V V - 150 200 µA - 300 500 µA 3.2 - 3.4 400 3.7 - V mV 15 1 1 - 28 50 3.5 1.3 2.4 2.8 1.2 1.6 50 100 3.8 3.3 - µA mV V V V V V V Source = 100 mA Sink = 100 mA 1.0 nF Load 10 % to 90 % 1.0 nF Load 90 % to 10 % - 1.4 1.3 6 5 2 1.8 - Ω Ω ns ns Source = 100 mA Sink = 100 mA 3.0 nF Load 10 % to 90 % 3.0 nF Load 90 % to 10 % - 1.2 0.6 10 8 1.9 1.1 - Ω Ω ns ns - 24 - ns - 24 - ns - 10 - ns - 10 - ns - 600 0.1 800 - mV µA VCC Input Voltage Range UGDRV Max Common Mode Operating Supply Current, Not Switching Operating Supply Current, Switching IQSW CONDITIONS UVLO VCCTHR VCC Rising VCCHYST VCC Hysteresis UGIN and LGIN Inputs INISINK Input Current VFLP Pull Down Voltage VUGINON Input Threshold UGDRV Rising VUGINOFF Input Threshold UGDRV Falling VUGINHYST Input Hysteresis UGDRV VLGINON Input Threshold LGDRV Rising VLGINOFF Input Threshold LGDRV Falling VLGINHYST Input Hysteresis LGDRV UGDRV UGDRVRSRC Source Impedance UGDRVRSINK Sink Impedance UGDRVTR Rise Time UGDRVTF Fall Time LGDRV LGDRVRSRC Source Impedance LGDRVRSINK Sink Impedance LGDRVTR Rise Time LGDRVTF Fall Time Propagation Delays UGDLYON UGIN Rising to UGDRV Rising UGDLYOFF UGIN Falling to UGDRV Falling LGDLYON LGIN Rising to LGDRV Rising LGDLYOFF LGIN Falling to LGDRV Falling Boost Diode BDFV BDRL Forward Voltage Reverse Leakage Revision 1.1.1 UGDRV & LGDRV = Open, FS = 250 kHz UGIN = LGIN = VVCC UGIN = LGIN = Open VUGINON - VUGINOFF VLGINON - VLGINOFF 3.0 nF load LGIN = 50 % to LGDRV at 90 %, Vin = 5 V 3.0 nF load LGIN = 50 % to LGDRV at 10 %, Vin = 5 V 3.0 nF load LGIN = 50 % to LGDRV at 90 % 3.0 nF load LGIN = 50 % to LGDRV at 10 % I = 10 mA VBOOST =5V, VVCC=0 3 © 2013 Integrated Device Technology, Inc. IDTP9090 0 Product Datasheet Pin Configuration BOOST UGDRV UGRTN IDTP9090 is packaged in an 8-lead 3mm x 3mm QFN package. 8 7 6 LGIN 1 UGIN 2 5 VCC 4 3 LGDRV GND Figure 1. IDTP9090 Pin Configuration Pin Descriptions Table 5. IDTP9090 Package Pin Functions by Pin Number PIN # PIN 1 BOOST 2 3 4 5 6 UGIN GND LGDRV VCC LGIN 7 UGRTN 8 UGDRV EP Revision 1.1.1 DESCRIPTION BOOST pin for Upper Gate N Chanel Drive. An internal Schottky diode is connected between this pin and VCC. A minimum 16V X7R ceramic capacitor must be connected from the BOOST pin to the UGRTN pin Control input signal for the UGDRV output. The pin has a 28μA pull-down. Digital & signal ground, as well as the Power Ground for LG driver. Lower-side MOSFET gate driver output controlled by the LGDRV pin (no logic inversion). Power for the LGDRV and BOOST pins, and for the bias current for the IDTP9090. Control input signal for the LGDRV output. The pin has a 28μA pull-down. Return for UGDRV drive. Connect this pin to the source of the high-side FET/drain of the lowside FET. Upper-side MOSFET gate driver output controlled by the UGDRV pin (no logic inversion). Exposed pad, must be connected to ground. Do not use as the IC ground connection. 4 © 2013 Integrated Device Technology, Inc. IDTP9090 0 Product Datasheet Block Diagram UVLO VCC BOOST UGIN UGDRV UG LOGIC 28µA LGIN UGRTN LG LOGIC LGDRV 28µA GND Figure 2. IDTP9090 Functional Block Diagram Revision 1.1.1 5 © 2013 Integrated Device Technology, Inc. IDTP9090 0 Product Datasheet TYPICAL PERFORMANCE CHARACTERISTICS Figure 3. Quiescent Current vs Vin IDTP9090 Quiescent Current vs Vin IDTP9035 DEMO PCB V4.0 w/ 4.1 mods; (Vin: 4.5V~5.5V) 180 160 Quiescnet Current (µA) 140 120 100 IQDC 80 60 40 20 0 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5 Input Voltage (V) Figure 4. Quiescent Current vs Frequency IDTP9090 Quiescent Current vs Frequency IDTP9035 DEMO PCB V4.0 w/ 4.1 mods; (Vin: 4.75V~5.25V) 600 Quiescnet Current (µA) 500 400 IQSW No… 300 200 100 0 10 Revision 1.1.1 100 Frequency (kHz) 6 1000 © 2013 Integrated Device Technology, Inc. IDTP9090 0 Product Datasheet Figure 5. Input Current vs Frequency IDTP9090 Input Current vs Frequency IDTP9035 DEMO PCB V4.0 w/ 4.1 mods; (Vin: 4.75V~5.25V) 300 Quiescnet Current (mA) 250 200 Iin With FETs 150 100 50 0 10 Revision 1.1.1 100 Frequency (kHz) 1000 7 © 2013 Integrated Device Technology, Inc. IDTP9090 0 Product Datasheet Application Schematics Half-Bridge Wireless Power Inverter Driver The following diagram shows an IDTP9090 being used to drive a Wireless Power Solution Transmitter Coil. +5V VIN 1 UGIN UG LOGIC 2 8 7 BOOST 47nF UGDRV UGRTN Tx UVLO 5 LGIN LG LOGIC 6 Not All Blocks and Connections Are Shown For General Reference Purposes Only VCC 0.1uF LGDRV 4 3 GND Figure 6. Application Diagram – Half Bridge Wireless Power Driver Full Bridge Wireless Power Inverter Driver The following diagram shows two IDTP9090s driving a Wireless Power Solution Transmitter Coil. 5V Bias VIN 1 UGIN 2 UG LOGIC 8 BOOST BOOST 47nF 47nF UGDRV UGDRV 1 8 UG LOGIC 2 UGIN Tx 7 UGRTN UGRTN VCC VCC 7 UVLO UVLO 5 LGIN 6 LG LOGIC Not All Blocks and Connections Are Shown For General Reference Purposes Only LGDRV 4 3 0.1uF 0.1uF GND 5 LGDRV 4 GND 3 LG LOGIC 6 LGIN Not All Blocks and Connections Are Shown For General Reference Purposes Only Figure 7. Application Diagram – Full Bridge Wireless Power Driver Revision 1.1.1 8 © 2013 Integrated Device Technology, Inc. IDTP9090 0 Product Datasheet Functional Description The IDTP9090 is a high-performance dual-PWM-input MOSFET driver for wireless power and general purpose applications. It is designed to interface directly with a power controller IC and provide a 5V gate drive to two separately-controlled N-channel power MOSFETs. The IDTP9090 contains one ground-referred MOSFET driver and one floating MOSFET driver capable of floating up to 30V. Active Input Pull Down Each drive signal input has a Schmitt trigger and a 28μA (nominal) pull down. This prevents a high impedance input from causing an indeterminate state on the output DRV signals. VCC UVLO The IDTP9090 will be kept disabled until the voltage on the VCC pin exceeds VCCTHR, as specified in Table 4. Revision 1.1.1 Independent UGIN and LGIN signals The IDTP9090 utilizes two independent non-inverting gate drive signal paths for controlling the respective output drive pins. This provides the customer maximum flexibility in choosing a control architecture. 30V Floating Drive with Integral Boost Diode The IDTP9090 UGDRV provides a 5V signal referred to UGRTN for driving a high efficiency N-Channel MOSFET with up to 30V on the UGRTN pin. An internal Boost Diode is connected between the VCC pin and the BOOST pin to recharge the boost capacitor when the UGDRV pin is at or near 0V. 9 © 2013 Integrated Device Technology, Inc. Package Outline Drawing Figure 8. Package Outline Drawing (NLG8 QFN-8 3.0mmx3.0mmx1mm 8-ld, 0.65mm pitch) Ordering Information Revision 1.1.1 10 © 2013 Integrated Device Technology, Inc. IDTP9090 0 Product Datasheet PART NUMBER MARKING PACKAGE AMBIENT TEMP. RANGE SHIPPING CARRIER QUANTITY P9090-0NLGI P9090-0NLGI8 P9090I P9090I NLG8 - QFN-8 3x3x1mm NLG8 - QFN-8 3x3x1mm -40°C to +125°C -40°C to +125°C Tube Tape and Reel 25 2,500 www.IDT.com 6024 Silver Creek Valley Road San Jose, California 95138 Tel: 800-345-7015 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. © Copyright 2013. All rights reserved. Revision 1.1.1 11 © 2013 Integrated Device Technology, Inc.