Recommended Land Pattern 0.01 4 (4x ) 0.35 Sold e ope rmask ning s #3 0.033±0.001 0.84±0.02 #4 #1 #4 #3 #1 #2 0.039 1.00 #2 Polymer coating ) 4x 0( 1 0.0 s 5 pad 2 . 0 MD NS 0.016 0.41 0.061±0.001 1.54±0.02 (soldermask openings shown with heavy dashed line) 0.024 0.60 MAX 0.002 0.04 Recommend 4-mill (0.1mm) stencil thickness 1,4 GND 2 CLK Out 3 #2 Name Vdd I/O Functionality Connect to ground. All GND pins must be connected power supply ground. The GND pins can be Power Supply Ground to connected together, as long as both GND pins are connected to ground. OUT Oscillator clock output. Power Supply Connect to power supply 1.5V≤Vdd≤3.63V. Under normal operating conditions, Vdd doesn’t require external bypass/decoupling capacitor(s). Internal power supply filtering will reject more than ±150mVpp with frequency components through 10MHz. 0.016 0.41 BSC #1 0. 0. 0 31 12 5 ± ±0 0.0 .0 01 15 Pin DO NOT SCALE DRAWING #4 0.039 1.00 BSC REVISION - #3 Apracon LLC. 2 Faraday, Suite#B Irvine, Ca. 92618 TITLE: TOP PACKAGE MARKING IS FOR ILLUSTRATION PURPOSES ONLY DWG NO. SCALE:30:1 ASTMTXK SHEET 1 OF 1 A3