DATA SHEET SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column Display Data Memory To improve design and/or performance, Avant Electronics may make changes to its products. Please contact Avant Electronics for the latest versions of its products data sheet (v4) 2005 Oct 25 Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 1 GENERAL 1.1 Description The SBN1661G_X is a series of STN LCD SEGMENT/COMMON drivers. The series has four members: • the SBN1661G_M18, • the SBN1661G_M02, • the SBN0080G_S18, and • the SBN0080G_S02. Both the SBN1661G_M18 and the SBN1661G_M02 can drive 16 COMMONs and 61 SEGMENTs and can be used as master in a master-slave connection. They both have 32-row x 80-column Display Data Memory. Functionally, their only difference is that the SBN1661G_M18 has an on-chip RC-type oscillator and can provide clock to slave, while the SBN1661G_M02 does not have an on-chip oscillator and needs external clock source. Both the SBN0080G_S18 and the SBN0080G_S02 are purely SEGMENT drivers. They do not have COMMON outputs and are used for segment expansion in a master-slave connection. Both devices need either a master or an external clock source to provide clock. The only difference between these two chips is their operating frequency. The SBN0080G_S18’s operating frequency is 18 KHz, while the SBN0080G_S02’s operating frequency is 2KHz. All four devices have on-chip Display Data Memory of 32-rows x 80-columns, for storing display data. Dot-matrix mapping method is used to drive the LCD panel. Therefore, a bit of the Display Data Memory corresponds to a pixel on the LCD panel. SEGMENT drivers provide display data to the LCD panel and COMMON drivers provide row-scanning signal. All four devices have a set of internal registers. These internal registers must be properly programmed to ensure proper operation of the devices. Display on the LCD panel is controlled by a host microcontroller. All four devices communicate with the host microcontroller via data bus and control bus. The data bus is 8-bit wide. The control bus are READ, WRITE, and Chip Select. The host microcontroller can perform READ/WRITE operations to the internal registers and Display Data RAM of all four devices. A wide variety of microcontrollers can easily interface with the devices, as the devices can accept both 80-type interface timing and 68-type interface timing. The selection of interface timing is via the dual-function RESET/IF pin. 2005 Oct 25 2 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 1.2 Features • Four members of the SBN1661G_X series: – the SBN1661G_M18, – the SBN1661G_M02, – the SBN0080G_S18, and – the SBN0080G_S02 • 16 COMMON, 61 SEGMENT STN LCD driver (the SBN1661G_M18 and the SBN1661G_M02). • 80 SEGMENT STN LCD driver for expanding segment number (the SBN0080G_S18 and the SBN0080G_S02). • On-chip Display Data Memory: 32-row x 80-column (totally 2560 bits). • Dot Matrix Mapping between the Display Data Memory bit and LCD pixel. • A “0” stored in the Display Data Memory bit corresponds to an OFF-pixel on the LCD panel; a “1” stored in the Display Data Memory bit corresponds to an ON-pixel on the LCD panel. • 5-level external LCD bias. • Display duty cycle: 1/16, 1/32 for all four devices. • Two types of interface timing with a host microcontroller: the 80-type microcontroller and the 68-type microcontroller. • Dual function RESET/IF input for chip reset and selection of microcontroller interface timing. • 8-bit parrallel data bus; READ, WRITE, CHIP SELECT control bus. • A set of internal registers: Display ON/OFF, Display Start Line, Static Drive ON/OFF, Memory Page Address, Memory Column Address, Duty Selection, Memory Column/Segment mapping, and Status. • Display Data Read/Write commands and Software Reset command. • Read-Modify-Write command for block data transfer from the host microcontroller to the Display Data Memory. • Power-saving mode. • On-chip RC-type oscillator, requiring only an external resistor (the SBN1661G_M18). • Operating voltage range (VDD): 2.7 ~ 5.5 volts. • LCD bias voltage (VLCD=V5-VDD): -13 volts (max.). • Operating frequency range: 2 KHz, 18 KHz. • Operating temperature range: -20 to +75 °C. • Storage temperature range: -55 to +125 °C. 2005 Oct 25 3 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 1.3 Ordering information Table 1 Product types Product Name SBN1661G_M18 Clock frequency on-chip External 18 KHz 18 KHz SBN1661G_M02 2 KHz SBN0080G_S18 18 KHz SBN0080G_S02 2 KHz Table 2 Number of segment driver Number of common driver 61 16 duty cycle 1/16, 1/32 80 0 Ordering information PRODUCT TYPE DESCRIPTION SBN1661G_M18-LQFPG LQFP100 Pb-free package. SBN1661G_M18-QFPG QFP100 Pb-free package. SBN1661G_M18-LQFP LQFP100 general package. SBN1661G_M18-QFP QFP100 general package. SBN1661G_M18-D tested die. SBN1661G_M02-LQFPG LQFP100 Pb-free package. SBN1661G_M02-QFPG QFP100 Pb-free package. SBN1661G_M02-LQFP LQFP100 general package. SBN1661G_M02-QFP QFP100 general package. SBN1661G_M02-D tested die. SBN0080G_S18-LQFPG LQFP100 Pb-free package. SBN0080G_S18-QFPG QFP100 Pb-free package. SBN0080G_S18-LQFP LQFP100 general package. SBN0080G_S18-QFP QFP100 general package. SBN0080G_S18-D tested die. SBN0080G_S02-LQFPG LQFP100 Pb-free package. SBN0080G_S02-QFPG QFP100 Pb-free package. SBN0080G_S02-LQFP LQFP100 general package. SBN0080G_S02-QFP QFP100 general package. SBN0080G_S02-D tested die. 2005 Oct 25 4 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column FUNCTIONAL BLOCK DIAGRAM AND DESCRIPTION V5 V4 V3 Output Driver V2 Level Shifter V1 SEG0 SEG1 SEG59 COM1 SEG60 Funtional block diagram (SBN1661G_M18, SBN1661G_M02) COM15 2.1 COM0 2 High Voltage Circuit MUX Display Control Time Gen. Mapping Circuit COMMON Counter C/S Mappig Register Display Data RAM Buffer Display ON/OFF Register Display Start Line Register 32 row x 80 column (2560 bits) Display Data RAM Line Address Decoder Page Address Register Column Address Register Status Register Duty Select Register Column Address Decoder Static Drive ON/OFF Register Display Data RAM Access Control Command Decoder Display Data Read/Write Control Display Control OSC2(CL) OSC1(CS) FR M/S OSC and Timing Gen. RESET/IF R/W(WR) C/D E/RD DB0~DB7 Microcontroller Interface Fig.1 Functional Block Diagram 2005 Oct 25 5 of 52 data sheet (v4) SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Avant Electronics Dot-matrix STN LCD Driver with 32-row x 80-column 3 PIN(PAD) ASSIGNMENT, PAD COORDINATES, SIGNAL DESCRIPTION The SBN1661G_M18 and SBN1661G_M02 pinning diagram (LQFP100) DB1 DB0 VSS R/W(WR) E/RD OSC2(CL) OSC1(CS) C/D SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 3.1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DB2 DB3 DB4 DB5 DB6 DB7 VDD RESET/IF FR V5 V3 V2 M/S V4 V1 COM0 COM1 COM2 COM3 COM4 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 SBN1661G_M18 SBN1661G_M02 (Master/Slave Driver) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Note: (1) For the SBN1661G_M18, pin 74 is OSC1 and pin 75 is OSC2. (2) For the SBN1661G_M02, pin 74 is CS and pin 75 is CL. (3) All other pins of both devices have the same pin(pad) assignment. (4) Both devices can be used as master or slave, by setting their M/S pin. Fig.2 The SBN1661G_M18 , the SBN1661G_M02 pin assignment of LQFP100 package. 2005 Oct 25 6 of 52 data sheet (v4) SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Avant Electronics Dot-matrix STN LCD Driver with 32-row x 80-column The SBN0080G_S18, the SBN0080G_S02 pinning diagram (LQFP100) DB1 DB0 VSS R/W(WR) E/RD CL CS C/D SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 3.2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DB2 DB3 DB4 DB5 DB6 DB7 VDD RESET/IF FR V5 V3 V2 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 SBN0080G_S18 SBN0080G_S02 (Slave Segment Driver) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Note: (1) Both devices have the same pin(pad) assignment. (2) Both devices can be used only as Slave Segment Driver. Fig.3 The SBN0080G_S18, the SBN0080G_S02 pin assignment of LQFP100 package. 2005 Oct 25 7 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 81 DB2 80 DB1 82 DB3 83 DB4 84 DB5 85 DB6 86 DB7 87 VDD 88 RESET/IF 89 FR 90 V5 91 V3 93 M/S 92 V2 95 V1 94 V4 97 COM1 96 COM0 98 COM2 99 COM3 The SBN1661G_M18 , SBN1661G_M02 pad placement 100 COM4 3.3 79 DB0 1 COM6 2 COM7 3 COM8 4 76 E/RD COM9 5 75 OSC2(CL) COM10 6 74 OSC1(CS) COM11 7 73 C/D COM12 8 COM13 9 72 SEG0 71 SEG1 chip ID COM5 78 VSS 77 R/W(WR) COM14 10 70 SEG2 69 SEG3 COM15 11 SEG60 12 68 SEG4 Y 67 SEG5 66 SEG6 SEG59 13 SEG58 14 (0,0) SEG57 15 65 SEG7 X SEG56 16 64 SEG8 SEG55 17 63 SEG9 SEG54 18 62 SEG10 SEG53 19 61 SEG11 SEG52 20 60 SEG12 SEG51 21 59 SEG13 SEG50 22 58 SEG14 SEG49 23 57 SEG15 SEG48 24 56 SEG16 SEG47 25 55 SEG17 chip size : 4162 µm x 3000 µm. SEG46 26 54 SEG18 Pad size: 90 µm x 90 µm. SEG45 27 53 SEG19 SEG44 28 52 SEG20 SEG43 29 51 SEG21 SEG42 30 50 SEG22 49 SEG23 48 SEG24 47 SEG25 46 SEG26 45 SEG27 44 SEG28 43 SEG29 42 SEG30 41 SEG31 40 SEG32 39 SEG33 2005 Oct 25 38 SEG34 37 SEG35 36 SEG36 35 SEG37 34 SEG38 33 SEG39 32 SEG40 31 SEG41 Note: (1) The SBN1661G_M18 and the SBN1661G_M02 have the same pad placement. (2) The chip ID of the SBN1661G_M18 is AT18001-01. (3) The chip ID of the SBN1661G_M02 is AT18001-02. (4) The die origin is at the center of the chip. (5) For chip_on_board_bonding, chip carrier should be connected to VDD or left open. Chip carrier is the metal pad to which the die is attached. Fig.4 The SBN1661G_M18, SBN1661G_M02 pad placement 8 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 81 DB2 80 DB1 82 DB3 83 DB4 84 DB5 85 DB6 86 DB7 87 VDD 88 RESET/IF 89 FR 90 V5 91 V3 93 SEG79 92 V2 95 SEG77 94 SEG78 97 SEG75 96 SEG76 98 SEG74 99 SEG73 The SBN0080G_S18 , SBN0080G_S02 pad placement 100 SEG72 3.4 79 DB0 1 SEG70 2 SEG69 3 SEG68 4 76 E/RD SEG67 5 75 CL SEG66 6 74 CS SEG65 7 73 C/D SEG64 8 SEG63 9 72 SEG0 71 SEG1 chip ID SEG71 78 VSS 77 R/W(WR) SEG62 10 70 SEG2 69 SEG3 SEG61 11 SEG60 12 68 SEG4 Y 67 SEG5 66 SEG6 SEG59 13 SEG58 14 (0,0) SEG57 15 65 SEG7 X SEG56 16 64 SEG8 SEG55 17 63 SEG9 SEG54 18 62 SEG10 SEG53 19 61 SEG11 SEG52 20 60 SEG12 SEG51 21 59 SEG13 SEG50 22 58 SEG14 SEG49 23 57 SEG15 SEG48 24 56 SEG16 SEG47 25 55 SEG17 chip size : 4162 µm x 3000 µm. SEG46 26 54 SEG18 Pad size: 90 µm x 90 µm. SEG45 27 53 SEG19 SEG44 28 52 SEG20 SEG43 29 51 SEG21 SEG42 30 50 SEG22 49 SEG23 48 SEG24 47 SEG25 46 SEG26 45 SEG27 44 SEG28 43 SEG29 42 SEG30 41 SEG31 40 SEG32 39 SEG33 38 SEG34 37 SEG35 2005 Oct 25 36 SEG36 35 SEG37 34 SEG38 33 SEG39 32 SEG40 31 SEG41 Note: (1) The SBN0080G_S18 and the SBN0080G_S02 have the same pad placement. (2) The chip ID of the SBN0080G_S18 is AT18001-03 (3) The chip ID of the SBN0080G_S02 is AT18001-04. (4) The die origin is at the center of the chip. (5) For chip_on_board_bonding, chip carrier should be connected to VDD or left open. Chip carrier is the metal pad to which the die is attached. Fig.5 The SBN0080G_S18, SBN0080G_S02 pad placement 9 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 3.5 The SBN1661G_M18, SBN1661G_M02 pad coordinates Table 3 The SBN1661G_M18, SBN1661G_M02 pad coordinates (unit: µm) PAD NO. PAD NAME X Y PAD NO. PAD NAME X Y PAD PAD NO. NAME X Y 1 COM5 -1824 -1430 35 SEG37 2011 -732 69 SEG3 -498 1430 2 COM6 -1694 -1430 36 SEG36 2011 -597 70 SEG2 -628 1430 3 COM7 -1569 -1430 37 SEG35 2011 -462 71 SEG1 -758 1430 1430 4 COM8 -1444 -1430 38 SEG34 2011 -327 72 SEG0 -888 5 COM9 -1319 -1430 39 SEG33 2011 -192 73 C/D -1062 1430 6 COM10 -1186 -1430 40 SEG32 2011 -57 74 OSC1 -1194 1430 7 COM11 -1053 -1430 41 SEG31 2011 78 75 OSC2 -1326 1430 8 COM12 -920 -1430 42 SEG30 2011 213 76 E/RD -1458 1430 9 COM13 -787 -1430 43 SEG29 2011 348 77 R/W(WR) -1590 1430 10 COM14 -654 -1430 44 SEG28 2011 483 78 VSS -1722 1430 11 COM15 -521 -1430 45 SEG27 2011 618 79 DB0 -1854 1430 12 SEG60 -388 -1430 46 SEG26 2011 753 80 DB1 -2011 1358 13 SEG59 -255 -1430 47 SEG25 2011 883 81 DB2 -2011 1176 14 SEG58 -122 -1430 48 SEG24 2011 1013 82 DB3 -2011 1044 15 SEG57 11 -1430 49 SEG23 2011 1143 83 DB4 -2011 909 16 SEG56 144 -1430 50 SEG22 2011 1273 84 DB5 -2011 771 17 SEG55 277 -1430 51 SEG21 1842 1430 85 DB6 -2011 635 18 SEG54 410 -1430 52 SEG20 1712 1430 86 DB7 -2011 497 19 SEG53 543 -1430 53 SEG19 1582 1430 87 VDD -2011 358 20 SEG52 676 -1430 54 SEG18 1452 1430 88 RESET/IF -2011 212 21 SEG51 809 -1430 55 SEG17 1322 1430 89 FR 81 -2011 22 SEG50 942 -1430 56 SEG16 1192 1430 90 V5 -2011 -50 23 SEG49 1075 -1430 57 SEG15 1062 1430 91 V3 -2011 -180 -326 24 SEG48 1208 -1430 58 SEG14 932 1430 92 V2 -2011 25 SEG47 1341 -1430 59 SEG13 802 1430 93 M/S -2011 -456 26 SEG46 1474 -1430 60 SEG12 672 1430 94 V4 -2011 -586 27 SEG45 1607 -1430 61 SEG11 542 1430 95 V1 -2011 -716 28 SEG44 1740 -1430 62 SEG10 412 1430 96 COM0 -2011 -846 29 SEG43 1873 -1430 63 SEG9 282 1430 97 COM1 -2011 -976 30 SEG42 2006 -1430 64 SEG8 152 1430 98 COM2 -2011 -1106 31 SEG41 2011 -1272 65 SEG7 22 1430 99 COM3 -2011 -1236 32 SEG40 2011 -1137 66 SEG6 -108 1430 100 COM4 -2011 -1388 33 SEG39 2011 -1002 67 SEG5 -238 1430 34 SEG38 2011 -867 68 SEG4 -368 1430 2005 Oct 25 10 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 3.6 The SBN0080G_S18, SBN0080G_S02 pad coordinates Table 4 The SBN0080G_S18, SBN0080G_S02 pad coordinates ( unit: µm ) Pad No. Pad Name X Y Pad No. Pad Name X Y Pad No. Pad Name X Y 1 SEG71 -1824 -1430 35 SEG37 2011 -732 69 SEG3 -498 1430 2 SEG70 -1694 -1430 36 SEG36 2011 -597 70 SEG2 -628 1430 3 SEG69 -1569 -1430 37 SEG35 2011 -462 71 SEG1 -758 1430 4 SEG68 -1444 -1430 38 SEG34 2011 -327 72 SEG0 -888 1430 5 SEG67 -1319 -1430 39 SEG33 2011 -192 73 C/D -1062 1430 6 SEG66 -1186 -1430 40 SEG32 2011 -57 74 CS -1194 1430 7 SEG65 -1053 -1430 41 SEG31 2011 78 75 CL -1326 1430 8 SEG64 -920 -1430 42 SEG30 2011 213 76 E/RD -1458 1430 9 SEG63 -787 -1430 43 SEG29 2011 348 77 R/W(WR) -1590 1430 10 SEG62 -654 -1430 44 SEG28 2011 483 78 VSS -1722 1430 11 SEG61 -521 -1430 45 SEG27 2011 618 79 DB0 -1854 1430 12 SEG60 -388 -1430 46 SEG26 2011 753 80 DB1 -2011 1358 13 SEG59 -255 -1430 47 SEG25 2011 883 81 DB2 -2011 1176 14 SEG58 -122 -1430 48 SEG24 2011 1013 82 DB3 -2011 1044 15 SEG57 11 -1430 49 SEG23 2011 1143 83 DB4 -2011 909 16 SEG56 144 -1430 50 SEG22 2011 1273 84 DB5 -2011 771 17 SEG55 277 -1430 51 SEG21 1842 1430 85 DB6 -2011 635 18 SEG54 410 -1430 52 SEG20 1712 1430 86 DB7 -2011 497 19 SEG53 543 -1430 53 SEG19 1582 1430 87 VDD -2011 358 20 SEG52 676 -1430 54 SEG18 1452 1430 88 RESET/IF -2011 212 21 SEG51 809 -1430 55 SEG17 1322 1430 89 FR -2011 81 22 SEG50 942 -1430 56 SEG16 1192 1430 90 V5 -2011 -50 23 SEG49 1075 -1430 57 SEG15 1062 1430 91 V3 -2011 -180 24 SEG48 1208 -1430 58 SEG14 932 1430 92 V2 -2011 -326 25 SEG47 1341 -1430 59 SEG13 802 1430 93 SEG79 -2011 -456 26 SEG46 1474 -1430 60 SEG12 672 1430 94 SEG78 -2011 -586 27 SEG45 1607 -1430 61 SEG11 542 1430 95 SEG77 -2011 -716 28 SEG44 1740 -1430 62 SEG10 412 1430 96 SEG76 -2011 -846 29 SEG43 1873 -1430 63 SEG9 282 1430 97 SEG75 -2011 -976 30 SEG42 2006 -1430 64 SEG8 152 1430 98 SEG74 -2011 -1106 31 SEG41 2011 -1272 65 SEG7 22 1430 99 SEG73 -2011 -1236 32 SEG40 2011 -1137 66 SEG6 -108 1430 100 SEG72 -2011 -1388 33 SEG39 2011 -1002 67 SEG5 -238 1430 34 SEG38 2011 -867 68 SEG4 -368 1430 2005 Oct 25 11 of 52 data sheet (v4) SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Avant Electronics Dot-matrix STN LCD Driver with 32-row x 80-column 3.7 Pin(pad) signal difference among the four members of the SBN1661G_X All four members of the SBN1661G_X series have the same pad sequence and placement. However, some pins(pads) have different signals for different types. A comparison is given in Table 5. Table 5 Comparison of pin(pad) signals Type Pin(pad) 1~11 Pin(pad) 74 Pin(pad) 75 Pin(pad) 93 Pin(pad) 94 Pin(pad) 95 Pin(pad) 96~100 SBN1661G_M18 COM5~15 OSC1 OSC2 M/S V4 V1 COM0~4 SBN1661G_M02 COM5~15 CS CL M/S V4 V1 COM0~4 SEG71~61 CS CL SEG79 SEG78 SEG77 SEG76~72 SBN0080G_S18 SBN0080G_S02 3.8 Pin (pad) states after hardware RESET Table 6 Pin(pad) states after RESET SBN1661G_M18, SBN1661G_M02 SBN0080G_S18, SBN0080G_S02 signal states after RESET signal states after RESET DB0~DB7 tri-state DB0~DB7 tri-state COM0~COM15 VDD SEG0~SEG61 VDD SEG0~SEG79 VDD FR(SBN1661G_M18) tri-state OSC2 (SBN1661G_M18) tri-state 2005 Oct 25 12 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 3.9 The SBN1661G_M18 and the SBN1661G_M02 signal description Table 7 Pin (pad) signal description To avoid a latch-up effect at power-on: VSS − 0.5 V < voltage at any pin at any time < VDD + 0.5 V . Pin number SYMBOL I/O DESCRIPTION COMMON driver outputs. The output voltage level of COMMON outputs are decided by the combination of the alternating frame signal (FR) and the internal COMMON COUNTER, which generates raster-scanning COMMON signals. Depending on the value of the frame signal and the COMMON counter output, a single voltage level is selected from VDD, V1, V4, or V5 for COMMON driver , as shown in Fig. 6. 1~11, 96~100 COM5~15, COM0~4 Output FR Common Counter output COMMON output 0 0 1 0 1 0 1 0 1 0 1 0 1 V4 V5 V1 VDD V4 V5 V1 VDD Fig.6 COMMON driver utput voltage level SEGNENT driver outputs. The output voltage level of SEGMENT outputs are decided by the combination of the alternating frame signal (FR) and display data. Depending on the value of the frame signal and the display data, a sinlge voltage level is selected from VDD, V2, V3, or V5 for SEGMENT driver, as shown in Fig. 7. 12~72 SEG60~0 Output 0 1 FR 0 Display Data bit 0 1 0 1 0 1 0 1 V3 VDD V2 V5 V3 VDD V2 V5 SEG output 0 1 Fig.7 SEGMENT driver output voltage level Selection of command or data. 73 C/D Input When C/D=0, the data on the 8-bit data bus (DB0~DB7) are either COMMAMD, data to be written to an internal register, or data read from the internal Status Register. When C/D=1, the data on the 8-bit data bus (DB0~DB7) are related to the Display Data Memory. They are the data to be written to or read from the Display Data Memory. 2005 Oct 25 13 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column Pin number SYMBOL OSC1 I/O Input 74 DESCRIPTION For the SBN1661G_M18, pin 74 is the OSC1 pin of the on-chip RC oscillator. It is the input pin to the oscillator. An external resistor should be connected across the OSC1 and the OSC2. For the SBN1661G_M02, pin 74 is the CS pin. Usually, a signal decoded from the host microcontroller address lines or a port line (C51) is connected to this pin. CS OSC2 Output For the SBN1661G_M18, pin 75 is the OSC2 pin. It is the output pin of the on-chip RC oscillator. CL Input For the SBN1661G_M02, pin 75 is the CL pin. Clock from master or an external clock source should be added to this pin. 75 Enable signal (E) for the 68-type microcontroller, or READ (RD) signal for the 80-type microcontroller. 76 E/(RD) Input If a 68-type microcotroller is selected as the host microcontroller, this pin should be connected to the ENABLE output of the microcontroller. A HIGH level on this pin indicates that the microcontroller intends to select the SBN1661G_X series. If a 80-type microcontroller is selected as the host microcontroller, this pin should be connected to the RD output of the microcontroller. A LOW level on this pin indicates that the microcontroller intends to read from the SBN1661G_X series.. Read/Write (R/W) signal for the 68-type microcontroller, or WRITE(WR) signal for the 80-type microcontroller. 77 R/W(WR) Input If a 68-type microcotroller is selected as the host microcontroller, this pin should be connected to the R/W output of the microcontroller. A HIGH level on this pin indicates that the microcontroller intends to read from the SBN1661G_X series. A LOW level on this pin indicates that the microcontroller intends to write to the SBN1661G_X series. If a 80-type microcontroller is selected as the host microcontroller, this pin should be connected to the WR output of the microcontroller. A LOW level on this pin indicates that the microcontroller intends to write to the SBN1661G_X series. 78 VSS Ground pin. Bi-direction, tri-state 8-bit parallel data bus for interface with a host microcontroller. 79~86 DB0~DB7 I/O 87 VDD Input 2005 Oct 25 This data bus is for data transfer between the host microcontroller and the SBN1661G_X. Power supply for logic part of the chip. The VDD should be in the range from 2.7 volts to 5.5 volts. 14 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column Pin number SYMBOL I/O DESCRIPTION Hardware RESET and interface type selection. This pin is a dual function pin. It can be used to reset the SBN1661G_X and select the type of interface timing. The hardware RESET is edge-sensitive. It is not level-sensitive. That is, either a falling edge or a rising edge on this pin can reset the chip. The voltage level after the reset pulse selects the type of interface timing. If the voltage level after the reset pulse stays at HIGH, interface timing for the 68-type microcontroller is selected. If the voltage level after the reset pulse stays at LOW, then interface timing for the 80-type microcontroller is selected. 88 RESET/IF Input Therefore, a positive RESET pulse selects the 80-type microcontroller for interface and a negative RESET pulse selects the 68-type microcontroller for interface. The following diagram illustrates the reset pulse and the selected type of microcontroller. Interface timing for the 80-type microcontroller is selected. Positive RESET pulse Interface timing for the 68-type microcontroller is selected. Negative RESET pulse Fig.8 RESET pulse interface timing selection Frame output or input. 89 FR I/O 90, 91, 92, 94, 95 V5, V3, V2, V4, V1 Input 93 M/S Input The frame signal is the AC siganl for generating alternating bias voltage of reverse polarities for LCD cell. When the chip is used as Master in a Master-Slave connection, this pin is an output pin and sends frame signal to the slave. When the chip is used as Slave, this pin is an input pin and accepts frame signal from the master. External LCD Bias voltage. The condition VDD≥V1≥V2≥V3≥V4≥V5 must always be met. In addition, VLCD (V5-VDD) should not exceed -13 volts. Selection for Master or Slave in a master-slave conneciton. 2005 Oct 25 When this pin is connected to VDD (hardwired-connection), the chip is used as Master. When this pin is connected to VSS, the chip is used as Slave. 15 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 4 A SBN1661G_X-BASED DISPLAY SYSTEM A SBN1661G_X-based display system is shown in Fig. 9. The SBN1661G_X , on the one side, interfaces with a host microcontroller via address bus , data bus, and control bus. The address bus from the microcontroller needs to be further decoded to generate Chip Select signal. The host microcontroller can perform READ/WRITE operation to the on-chip Display Data Memory, can send commands to the SBN1661G_X, and can program the internal registers to congifure the SBN1661G_X. How data is to be displayed on the LCD panel is completely controlled by the host microcontroller. On the other side, the SBN1661G_X provides 15 COMMON drivers and 61 SEGMENT drivers to drive the LCD panel. To expand the COMMON number and SEGMENT number, both the SBN1661G_M18 and SBN1661G_M02 can be used either as a master or as a slave in a master-slave connection. The synchronization between the master and the slave is via the FR (frame) signal and the CL (clock) signal supplied from the master to the slave. If only segment number needs to be expanded, then the SBN0080G_S18 or the SBN0080G_S02 can be used as slave. Address bus Data bus Host microcontroller Control bus Decoder SBN1661G_X COM0 (master) COM15 Display Data Memory 68-series 80-seris Registers SEG1 SEG61 C51-series LCD Panel SBN1661G_X (slave) Display Data Memory Registers RESET COM0 COM15 SEG1 SEG16 LCD Bias Power Supply Fig.9 A SBN1661G_X series-based display system 2005 Oct 25 16 of 52 data sheet (v4) SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Avant Electronics Dot-matrix STN LCD Driver with 32-row x 80-column 5 INTERFACE WITH A HOST MICROCONTROLLER 5.1 Selection of interface type by use of the RESET/IF pin(pad) The SBN1661G_X series can accept two types of interface timing for two types of microconftroller: the 68-type micrcontrollers and the 80-type microcontrollers. Selection of interface type is by use of the dual-function RESET/IF pin(pad). If the voltage at the RESET/IF pin(pad) stays at HIGH after RESET pulse, then the 68-type interface timing is selected. If the voltage at the RESET/IF pin(pad) stays at LOW after RESET pulse, then the 80-type interface timing is selected. The RESET of the SBN1661G_X is edge-sensitive, instead of level-sensitive. That is, a pulse on the RESET/IF input triggers reset only on the rising edge and falling edge of the pulse. The voltage level after the RESET pulse is used to select interface type. 5.2 Interface signal and operation The interface signal between the host microcontroller and the SBN1661G_X are data bus and control bus. The data bus is an 8-bit (DB0~DB7) bi-directional bus. The control bus is composed of the following siganls: C/D, E/(RD), and R/W(WR). By means of data bus and control bus, the host microcontroller can write data to the on-chip Display Data Memory, can read data from the Display Data Memory, can program the internal registers, can send commands, and can read status of the chip. It is the host microcontroller’s responsibility to put proper data and timing on the data bus and control bus to ensure proper communication. Table 8 lists the setting for control bus and the types of interface operation. Table 8 Interface signal and microcontroller operation COMMAN /DATA 68-type interface C/D R/W RD WR 1 1 0 1 The host microcontroller reads data from the Display Data Memory. 1 0 1 0 The host microcontroller writes data to the Display Data Memory 0 1 0 1 The host microcontroller reads the Status Register. 0 0 1 0 The host microcontroller issues a command or writes data to an internal register. 5.3 80-type interface Operation Interface Timing Please refer to Fig. 22 and Fig. 24 for interface timing diagram and Table 42 , Table 43, Table 44, and Table 45 for AC characteristics of interface timing. 5.4 Interface Circuit Please refer to Fig. 24, Fig. 25, and Fig. 26 for interface circuit examples. 2005 Oct 25 17 of 52 data sheet (v4) SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Avant Electronics Dot-matrix STN LCD Driver with 32-row x 80-column 6 DISPLAY DATA MEMORY AND LCD DISPLAY The Display Data Memory is a static memory bit(cell) array of 32-row x 80-column. So, the total bit number of the Display Data Memory is 32 x 80 = 2560 bits. Each bit of the memory is mapped to a single pixel (dot) on the LCD panel. A “1” stored in the Display Data Memory bit corresponds to an ON pixel (black dot in normal display) of the LCD panel. A “0” stored in the Display Data Memory bit corresponds to an OFF pixel (background dot in normal display) of the LCD panel. Column outputs(Column 0~79) of the Display Data Memory is mapped to SEG 0~79 outputs of the SBN1661G_X. The mapping can be normal mapping or inverse mapping. Normal mapping means that Column0 is mapped to SEG0, Column1 to SEG1, Column2 to SEG2, and so on. Inverse mapping means that Column0 is mapped to SEG79, Column1 to SEG78, Column2 to SEG77, and so on. The mapping relation is decided by the Column/Segment Mapping Register. Row 0 COM 0 Row 1 COM 1 Row 2 COM 2 Row 3 COM 3 Row 28 COM 15 Row 29 SEG 79 SEG 78 SEG 77 SEG 2 SEG 1 SEG 0 Column 79 Column 78 Column 77 Column 2 Column 1 Column 0 Any row (80 bits) of the Display Data Memory can be selected as the first row (COM0) to be displayed on the LCD panel. This is decided by the Display Start Line Register. The Display Start Line Register points at the first row of a block of the Display Data Memory, which will be mapped to COM0 of the LCD display. The length of the block of the memory can be 32 rows or 16 rows, which is decided by the Duty Select Register. LCD panel pixel array Row 30 Row 31 Display Data Memory Cell Array Fig.10 Memory cell array and LCD pixel array 2005 Oct 25 18 of 52 data sheet (v4) SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Avant Electronics Dot-matrix STN LCD Driver with 32-row x 80-column 7 DISPLAY CONTROL INSTRUCTIONS AND REGISTERS 7.1 Registers and their states after hardware RESET The SBN1661G_X has a set of registers. To ensure proper operation of the devices, these registers must be programmed with proper values after hardware reset. The registers and their states after RESET is given in Table 9. Table 9 Registers and their states after RESET Register Name Description Display ON/OFF Register The Display ON/OFF Register is a 1-bit register. After RESET, its value is LOW and, therefore, the LCD display is turned OFF. 0 Display Start Line Register The Display Start Line Register is a 6-bit register. After RESET, its value is 0 0000 and Row0 of the Display Data Memory is mapped to COM0. 00 0000 Page Addres Register The Page Address Register is a 3-bit register. After RESET, its value is 11 and, therefore, it points to Page 7 of the Display Data Memory. 111 Column Address Register The Column Address Register is a 7-bit register. After RESET, its value is 000 0000 and, therefore, it points to column 0 of the Display Data Memory. 000 0000 The Static Drive ON/OFF Register is a 1-bit register. After RESET, its value is LOW and static display is turned OFF. 0 The Duty Select Register is a 1-bit register. After RESET, its value is HIGH and 1/32 display duty is selected. 1 The Column/Segment Mapping Register is a 1-bit register. After RESET, its value is LOW and normal mapping is selected. 0 The Status Register shows the current state of the SBN1661G_X. It is a 4-bit register, with each bit showing the status of a programmed function. 0000 0000 Static Drive ON/OFF Register Duty Select Register Column/Segment Mapping Register Status Register 7.2 States after RESET Display ON/OFF and the Display ON/OFF Register The Display ON/OFF Register is a 1-bit Register. When this bit is progammed to HIGH, the display is turned ON. When this bit is programmed to LOW, the display is turned OFF. When display is turned OFF, SEG0~SEG60 will stay at either V2 or V3, and COM0~COM15 will stay at their previous value before the Display OFF command is issued. To program this register, the setting of control bus is given in Table 10 and the setting of the data bus is given in Table 11. Table 10 Setting of the control bus for programming the Display ON/OFF Register C/D E/(RD) R/W(WR) 0 1 0 Table 11 Setting of the data bus for programming the Display ON/OFF Register D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) 1 0 1 0 1 1 1 D0 When D0=1, the code is AF(Hex) and the display is turned ON. When D0=0, the code is AE(Hex) and the display is turned OFF. 2005 Oct 25 19 of 52 data sheet (v4) SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Avant Electronics Dot-matrix STN LCD Driver with 32-row x 80-column 7.3 Display Start Line and the Display Start Line Register SEG 79 SEG 78 SEG 77 SEG 2 SEG 1 COM 0 Column 79 Column 78 Column 77 Column 2 Column 1 Column 0 SEG 0 The Display Start Line Register is a 5-bit Register. It points at the first row of a block of the Display Data Memory, which will be mapped to COM0. The length of the block of the memory can be 32 rows or 16 rows, which is decided by the Duty Select Register. For example, if the Display Start Line Register is programmed with 00010 ( decimal 2) and display duty is 1/32, then Row2 of the Display Data Memory will be mapped to COM0 of LCD panel, Row3 to COM1, Row4 to COM2, Row30 to COM28, Row31 to COM29, Row0 to COM30, and finally Row1 to COM31, as illustrated in Fig. 11. However, in this case, only Row2~Row17 can be displayed on COM0~COM15, as COM16~COM31 are not availabe from the chip. COM 1 COM 2 COM 3 Row 0 Row 1 Row 2 Row 3 COM 28 0 0 0 1 COM 29 0 A4 A3 A2 A1 A0 COM 30 Display Start Line Register COM 31 Row 28 Row 29 LCD panel Row 30 Row 31 Display Data Memory Fig.11 Display Start Line Register To program this register, the setting of the control bus is given in Table 12 and the setting of the data bus is given in Table 13. Table 12 The setting of the control bus for programming the Display Start Line Register C/D E/(RD) R/W(WR) 0 1 0 Table 13 The setting of the data bus for programming the Display Start Line Register D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) 1 1 0 A4 A3 A2 A1 A0 A4, A3, A2, A1, and A0 are Start Line address bits and they can be programmed with a value in the range from 0 to 31. Therefore, the code can be from 1100 0000 (C0 Hex) to 1101 1111 (DF Hex). 2005 Oct 25 20 of 52 data sheet (v4) SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Avant Electronics Dot-matrix STN LCD Driver with 32-row x 80-column 7.4 Display Data Memory Page and the Page Address Register Page 1 Page 2 Page 3 Column 79(Byte79) Column 78(Byte78) Column 77(Byte77) Row0 Row1 Row2 Row3 Row4 Row5 Row6 Row7 Row8 Row9 Row10 Row11 Row12 Row13 Row14 Row15 Row16 Row17 Row18 Row19 Row20 Row21 Row22 Row23 Row24 Row25 Row26 Row27 Row28 Row29 Row30 Row31 Column 3(Byte3) Column 2(Byte2) Column 1(Byte1) Page 0 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Column 0(Byte0) The on-chip Display Data Memory is divided into 4 pages: Page 0, Page 1, Page 2, and Page 3, with each page having 80 bytes in horizontal direction. Page 0 is from Row 0 to Row 7, Page 1 from Row 8 to Row 15, Page 2 from Row 16 to Row 23, and Page 3 from Row 24 to Row 31, as shown in Fig 12. When the host microtroller intends to perform a READ/WRITE operation to the Display Data Memory, it has to program the Page Adrress Register to indicate which page it intends to access. Fig.12 Page/Column allocation of the Display Data Memory To program this register, the setting of the control bus is given in Table 14 and the setting of the data bus is given in Table 15. Table 14 The setting of the control bus for programming the Page Address Register C/D E/(RD) R/W(WR) 0 1 0 Table 15 The setting of the data bus for programming the Page Address Register D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) 1 0 1 1 1 0 A1 A0 A1and A0 are page address bits and can be programmed with a value in the range from 0 to 3. A1A0=00 selects Page 0, A1A0=01 selects Page 1, A1A0=10 selects Page 2, and A1A0=11 selects Page 3. Therefore, the code can be from 1011 1000 (B8 Hex) to 1011 1011 (BB Hex). 2005 Oct 25 21 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 7.5 Column address and the Column Address Register The Column Address Register points at a column of the Display Data Memory which the host microcontroller intends to perform a READ/WRITE operation. The Column Address Register automatically increments by 1 after a READ or WRITE operation is finished. When the Column Address Register reaches 79, it overflows to 0. Please refer to Fig.12 for the column sequence in a page of the Display Data Memory. To program this register, the setting of the control bus is given in Table 16 and the setting of the data bus is given in Table 17. Table 16 The setting of the control bus for programming the Column Address Register C/D E/(RD) R/W(WR) 0 1 0 Table 17 The setting of the data bus for programming the Column Address Register D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) 0 A6 A5 A4 A3 A2 A1 A0 A6~A0 are column address bits and can be programmed with a value in the range from 0 to 79. Therefore, the code can be from 0000 0000 (00 Hex) to 0100 1111 (4F Hex). 2005 Oct 25 22 of 52 data sheet (v4) SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Avant Electronics Dot-matrix STN LCD Driver with 32-row x 80-column 7.6 Mapping between Memory Cloumns and Segments and the Column/Segment Mapping Register The Column/Segment Mapping Register is a 1-bit register and selects the mapping relation between the column outputs of the Display Data Memory and the Segment outputs SEG0~SEG79. If this register is programmed with HIGH, then the data from column 79 of the Display Data Memory will be output from SEG0. This type of mapping is called inverted mapping. If this register is programmed with LOW, then data from column 0 of the Display Data Memory will be output from SEG0. This type of mapping is called normal mapping. By use of this register, the flexibility of component placement and routing on a PCB can be increased. SEG 77 SEG 78 SEG 79 Column 78 Column 79 SEG 2 Column 77 Row 2 Row 3 Row 3 Row 28 Row 28 Row 29 Row 29 Row 30 Row 30 Row 31 Column 2 Row 1 Column 1 Row 0 Column 79 Column 78 Column 77 Column 2 Column 1 Row 2 Column 0 Row 1 Column 0 Inverted mapping (D=1) Normal Mapping (D=0) Row 0 SEG 1 SEG 0 SEG 79 SEG 78 SEG 77 Segment Driver SEG 2 SEG 1 SEG 0 Segment Driver Row 31 Display Data Memory Display Data Memory Fig.13 Column/Segment Mapping Register. To program this register, the setting of the control bus is given in Table 18 and the setting of the data bus is given in Table 19. Table 18 The setting of the control bus for programming the Column/Segment Mapping Register C/D E/(RD) R/W(WR) 0 1 0 Table 19 The setting of the data bus for programming the Memory/Segment Mapping Register D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) 1 0 1 0 0 0 0 D The least significant bit D can be programmed with either 0 or 1. Therefore, the codes are A0 Hex or A1 Hex. 2005 Oct 25 23 of 52 data sheet (v4) SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Avant Electronics Dot-matrix STN LCD Driver with 32-row x 80-column 7.7 Static Drive ON/OFF and the Static Drive ON/OFF register The Static Drive ON/OFF Register is a 1-bit register. It is used to turn ON or OFF the Static Drive Mode of the SBN1661G_X. When this register is programmed with HIGH, Static Drive Mode is turned ON and the device enters into Static Drive Mode, in which the internal clock circuitry is disabled and the switching of the internal logic is suspended. When this register is programmed with LOW, Static Drive Mode is turned OFF and the chip returns to normal operation. This register is used in combination with the Display ON/OFF register to make the current consumption of the LCD module reduced to almost static level. By turning OFF the display and turning ON the static drive mode,the chip is configured into the following state: • all COMMON and SEGMENT outputs are set to VDD, • on-chip oscillator or external clock is inhibited and internal logic circuit stays idle, • OSC2 is in floating state (please refer to Section 11 , On-chip RC Oscillator), and • the state of registers and the data of the Display Data Memory are kept unchanged. In addition to turning ON the static drive mode and turning OFF the display, to really reduce the power consumption of the LCD module, the host microcontroller should also send out a power-save signal to turn off the PNP transistor in the bias circuit, such that the current flow from VDD to VEE can be cut off, as shown in Fig. 14. VDD VDD V0 Microcontroller C V1 C V2 C V3 C V4 C V5 V0 VDD V1 SEG0~SEG60 V2 V3 COM0~COM15 V4 V5 VSS Power Save Signal VEE Fig.14 Power Save Mode To program this register, the setting of the control bus is given in Table 20 and the setting of the data bus is given in Table 21. Table 20 The setting of the control bus for programming the Static Drive ON/OFF Register C/D E/(RD) R/W(WR) 0 1 0 Table 21 The setting of the data bus for programming the Static Drive ON/OFF Register D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) 1 0 1 0 0 1 0 D The least significant bit D0 can be programmed with either 0 or 1. Therefore, the code is A4 Hex or A5 Hex. 2005 Oct 25 24 of 52 data sheet (v4) SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Avant Electronics Dot-matrix STN LCD Driver with 32-row x 80-column 7.8 Select Duty and the Select Duty Register The Select Duty Register is a 1-bit register. If it is programmed with HIGH, 1/32 display duty is selected. If it is programmed with LOW, 1/16 display duty is selected. To program this register, the setting of the control bus is given in Table 22 and the setting of the data bus is given in Table 23. Table 22 The setting of the control bus for programming the Select Duty Register C/D E/(RD) R/W(WR) 0 1 0 Table 23 The setting of the data bus for programming the Select Duty Register D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) 1 0 1 0 1 0 0 D The least significant bit D can be programmed with either 0 or 1. Therefore, the code is A8 Hex or A9 Hex. In a Master-Slave connection using the SBN1661G_M18 or the SBN1661G_M02 as the master, COM0~COM15 will be from the master and COM16~COM31 will be from the slave. The Select Duty Register of both the Master and the Slave should be programmed with HIGH to select 1/32 duty. Fig.15 shows the COMMON sequence of this connection. Frame Signal (From Master) COM0~COM15 (From Master) COM16~COM31 (From Slave) 0 1 2 13 14 15 0 16 17 18 29 30 31 1 2 13 14 15 16 17 18 29 30 31 Fig.15 COMMON sequence of Master-Slave connection This register is not available in the SBN0080G_S18 and the SBN0080G_S02, because both the devices are purely Segment Drivers and their duty cycle is decided by the FR and the CL from the master. 2005 Oct 25 25 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 7.9 Status Read and Status Register The Status Register shows the current state of the SBN1661G_X. It can be read by the host microcontroller. Bit 7~4 shows the status and Bit 3~0 are always fixed at 0. To read the Status Register, the setting of the control bus is given in Table 24, the bit allocation is given in Table 25 and the description for each bit is given in Table 26. Table 24 The setting of the control bus for reading the Status Register C/D E/(RD) R/W(WR) 0 0 1 Table 25 The Status Register bit allocation D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) BUSY MAPPING ON/OFF RESET 0 0 0 0 Table 26 The Status Register bit description Bit Description BUSY BUSY=1 indicates that the SBN1661G_X is currently busy and can not accept new command or data. The SBN1661G_X is executing a command or is in the process of reset. MAPPING MAPPING=1 indicates that the Column/Segment Mapping Register has been programmed with a value of “1” and the SEG0 is mapped to Column 79 of the Display Data Memory (inverted mapping). BUSY=0 indicates that the SBN1661G_X is not busy and is ready to accept new command or data. MAPPING=0 indicates that the Column/Segment Mapping Register has been programmed with a value of “0” and the SEG0 is mapped to Column 0 of the Display Data Memory (normal mapping). ON/OFF The ON/OFF bit indicates the current of status of display. If ON/OFF=0, then the display has been turned ON. If ON/OFF=1, then the display has been turned OFF. Note that the polarity of this bit is inverse to that of the Display ON/OFF Register. RESET RESET=1 indicates that the SBN1661G_X is currently in the process of being reset. RESET=0 indicates that the SBN1661G_X is currently in normal operation. 2005 Oct 25 26 of 52 data sheet (v4) SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Avant Electronics Dot-matrix STN LCD Driver with 32-row x 80-column 8 COMMANDS The host microcontroller can issue commands to the SBN1661G_X. Table 27 lists all the commands. When issuing a command, the host microcontroller should put the command code on the data bus. The host microcontroller should also give the control bus C/D, E(RD), and R/W(WR) proper value and timing. Table 27 Commands COMMAND COMMAND CODE D7 D6 D5 D4 D3 D2 D1 FUNCTION D0 Write Display Data Data to be written into the Display Data Memory. Write a byte of data to the Display Data Memory. Read Display Data Data read from the Display Data Memory. Read a byte of data from the Display Data Memory. Read-Modify-Write 1 1 1 0 0 0 0 0 Start Read-Modify-Write operation. END 1 1 1 0 1 1 1 0 Stop Read-Modify-Write operation. Software Reset 1 1 1 0 0 0 1 0 Software Reset. 8.1 Write Display Data The Write Display Data command writes a byte (8 bits) of data to the Display Data Memory. Data is put on the data bus by the host microcontroller. The location which accepts this byte of data is pointed to by the Page Address Register and the Column Address Register. At the end of the command operation, the content of the Column Address Register is automatically incremented by 1. For page address and column address of the Display Data Memory, please refer to Fig. 12. Table 28 gives the control bus setting for this command. Table 28 The setting of the control bus for issuing Write Display Data command C/D E/(RD) R/W(WR) 1 1 0 2005 Oct 25 27 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 8.2 Read Display Data The Read Display Data command starts a 3-step operation. 1. First, the current data of the internal 8-bit output latch of the Display Data Memory is read by the microcontroller, via the 8-bit data bus DB0~DB7. 2. Then, a byte of data of the Display Data Memory is transferred to the 8-bit output latch from a location specified by the Page Address Register and the Column Address Register, 3. Finally, the content of the Column Address Register is automatically incremented by one. Fig. 16 shows the internal 8-bit ouptut latch located between the 8-bit I/O data bus and the Display Data Memory cell array. Because of this internal 8-bit output latch, a dummy read is needed to obtain correct data from the Display Data Memory. For Display Data Write operation, a dummy write is not needed, because data can be directly written from the data bus to internal memory cells. DB7 DB6 DB4 DB5 DB2 DB3 DB1 DB0 (8-bit bi-directional data bus) Write Display Data Row Address Decoder Read Display Data 8-bit output latch Display Data Memory cell array ( 32 row x 80 column ) Column Address Decoder Fig.16 Read Display Data Memory Table 29 gives the control bus setting for this command. Table 29 The setting of the control bus for issuing Read Display Data command C/D E/(RD) R/W(WR) 1 0 1 2005 Oct 25 28 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 8.3 Read-Modify-Write When the Read-Modify-Write command is issued, the SBN1661G_X enters into Read-Modify-Write mode. In normal operation, when a Read Display Data command or a Write Display Data command is issued, the content of the Column Address Register is automatically incremented by one after the command operation is finished. However, during Read-Modify-Write mode, the content of the Column Address Register is not incremented by one after a Read Display Data command is finished; only the Write Display Data command can make the content of the Column Address Register automatically incremented by one after the command operation is finished. During Read-Modify-Write mode, any other registers, except the Column Address Register, can be modified. This command is useful when a block of the Display Data Memory needs to be repeatedly read and updated. Fig. 17 gives the change sequence of the Column Address Register during Read-Modify-Write mode. Figure 18 gives the flow chart for Read-Modify-Write command. END command issued. Read-Modify-Write command issued. Read-Modify-Write duration Column Address N N+1 N+2 Internal Buffer Register N+3 N+m N Re-load column address by issuing the END command Fig.17 Column address change during Read-Modify-Write 2005 Oct 25 29 of 52 data sheet (v4) SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Avant Electronics Dot-matrix STN LCD Driver with 32-row x 80-column Set Page Address Register Set Column Address Register Read-Modify-Write command Dummy Read Read Display Data Memory Write Display Data Memory No Finish Modifying ? Yes END Fig.18 The flowchart for Read-Modify-Write Table 30 gives the setting for the control bus and the setting of the data bus is given in Table 31. Table 30 The setting of the control bus for the Read-Modify-Write command C/D E/(RD) R/W(WR) 0 1 0 Table 31 The setting of the data bus for the Read-Modify-Write command D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) 1 1 1 0 0 0 0 0 The command code is E0 Hex. 8.4 The END command The END command releases the Read-Modify-Write mode and re-loads the Column Address Register with the value previously stored in the internal buffer (refer to Fig. 17) when the Read-Modify-Write command was issued. Table 32 gives the setting for the control bus and the setting of the data bus is given in Table 33. 2005 Oct 25 30 of 52 data sheet (v4) SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Avant Electronics Dot-matrix STN LCD Driver with 32-row x 80-column Table 32 The setting of the control bus for the END command C/D E/(RD) R/W(WR) 0 1 0 Table 33 The setting of the data bus for the END command D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) 1 1 1 0 1 1 1 0 The command code is EE Hex. 8.5 Software RESET command The Software Reset command is different from the hardware reset and can not be used to replace hardware reset. When Software Reset is issued by the host microcontroller, • the content of the Display Start Line Register is cleared to zero(A4~A0=00000), • the Page Address Register is set to 3 (A1 A0 = 11), • the content of the Display Data Memory remains unchanged, and • the content of all other registers remains unchanged. Table 34 gives the setting for the control bus and the setting of the data bus is given in Table 35. Table 34 The setting of the control bus for Software RESET C/D E/(RD) R/W(WR) 0 1 0 Table 35 The setting of the data bus for Software RESET D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB) 1 1 1 0 0 0 1 0 The command code is E2 Hex. 2005 Oct 25 31 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 9 LCD BIAS CIRCUIT A typical LCD bias circuit is shownin Fig. 19. The condition VDD≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 must always be met. The maximum allowed voltage for LCD bias (VLCD=VDD-V5) should not exceed 13 volts. COMPONENT RECOMMENDED VALUE C 0.1 µF, electrolytic R1 2.2K R2 7.5K R3 10K TR1 PNP VDD VDD R1 C R1 C R2 C R1 C Microcontroller R1 C V0 V0 V1 V1 V2 V2 V3 V3 V4 V4 V5 V5 VDD SEG0~SEG60 COM0~COM15 VSS R3 Power Save Signal TR1 VEE Fig.19 LCD Bias circuit 2005 Oct 25 32 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 10 COMMON, SEGMENT OUTPUT VOLTAGE The output voltage level of COMMON driver and SEGMENT driver is given in Table 36. The output voltage level of COMMON driver is decided by the combination of Frame signal, internal COMMON COUNTER output, and the Display ON/OFF register. The output voltage level of SEGMENT driver is decided by the combination of Frame signal, Display Data, and the Display ON/OFF register. Table 36 COMMON/SEGMENT ouptut voltage level FR Data DISPLAY ON/OFF SEG0~SEG60 (SEG0~SEG79) COM0~COM15 L L ON V3 V4 L H ON V5 VDD H L ON V2 V1 H H ON VDD V5 x(don’t care) x(don’t care) OFF V2 or V3 previous voltage Note that, in the above table, “Data” for the COM0~COM15 is actually the output of the internal COMMON COUNTER, which generates horizontal raster scanning signal. During RESET, both SEGMENT and COMMON outputs are at VDD. 2005 Oct 25 33 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 11 ON-CHIP RC OSCILLATOR The SBN1661G_M18 has an on-chip RC-type oscillator. All other three members of the family do not have on-chip oscillator and need external clock source. The output CLK of the oscillator is the basic timing clock of the internal control logic, display pixel rate, and is also used to generate frame signal. The capacitor of the RC-oscillator is fabricated on-chip. Only an external resistor Rf needs to be connected across OSC1 and OSC2. The recommended value of Rf is in the range from 1000K ohm to 1200K ohm. During PCB layout, this resistor should be placed as close to the SBN1661G_M18 as possible, such that stray capacitance, inductance, and resistance can be minimized. VDD CLK VDD OSC1 OSC2 Disable Disable Disable VSS VSS Rf 1.0 MΩ(typical) Fig.20 On-chip RC oscillator The characteristics of the oscillator is given is Table. 37. Table 37 On-chip RC oscillator characteristics, Tamb = −20 to +75 °C Oscillation min. typ. max. unit Oscillation frequency at VDD=5V, Rf= 1.0 MΩ ±20% 17.6 21.5 25.9 KHz Oscillation frequency at VDD=3V, Rf= 1.0 MΩ ±20% 15.7 19.1 22.8 KHz 2005 Oct 25 34 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 12 ELECTRICAL CHARACTERISTICS 12.1 Absolute maximum rating Table 38 Absolute maximum rating SYMBOL PARAMETER MIN. −0.3 VDD voltage on the VDD pin(pad) VLCD (note 2) LCD bias voltage, VLCD=VDD-V5 VI input voltage on any pin with respect to VSS PD power dissipation −0.3 MAX. UNIT +7.0 Volts 13 Volts VDD + 0.3 Volts 250 mW Tstg storage temperature range −55 +125 °C Tamb operating ambient temperature range -40 + 85 °C Tsol (note 3) soldering temperature/time at pin 260 °C, 10 Second Notes 1. The following applies to the Absolute Maximum Rating: a) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. b) The SBN1661G_X series includes circuitry specifically designed for the protection of its internal devices from the damaging effect of excessive static charge (ESD). However, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. c) Parameters are valid over operating temperature range unless otherwise specified. d) All voltages are with respect to VSS, unless otherwise noted. 2. The condition VDD≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 must always be met. 3. QFP-type packages are sensitive to moisture of the enviroment, please check the drypack indicator on the tray package before soldering. Exposure to moisture longer than the rated drypack level may lead to cracking of the plastic package or broken bonding wiring inside the chip. 2005 Oct 25 35 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 13 DC CHARACTERISTICS Table 39 DC Characteristics VDD = 5 V ±10%; VSS = 0 V; all voltages with respect to VSS, unless otherwise specified; Tamb = −20 to +75 °C. SYMBOL PARAMETER VDD Supply voltage for logic VLCD LCD bias voltage VLCD= VDD-V5 CONDITIONS MIN. TYP. MAX. UNIT 2.7 5.0 5.5 V 13 V V VIL LOW level input voltage For all inputs 0 0.8 VIH HIGH level input voltage For all inputs VDD-2.2 VDD V VOL LOW level output voltage For all outputs 0.0 0.3 V VOH HIGH level output voltage For all outputs VDD − 0.3 VDD V ISTBY Standby current at VDD=5 volts Note 1 3.0 µA IDD(1) Operating current at VDD=5 volts and fCL=2KHz, VLCD=10 volts 2.0 5.0 µA IDD(2) Operating current at VDD=5 volts and Rf=1 MΩ, VLCD=10 volts 9.5 15.0 µA IDD(3) Operating current at VDD=5 volts and fCL=18 KHz, VLCD=10 volts 5.0 10.0 µA 1.5 4.5 µA Note 2 & Note 3 IDD(4) Operating current at VDD=3 volts and fCL=2KHz, VLCD=6 volts IDD(5) Operating current at VDD=3 volts and Rf=1 MΩ, VLCD=6 volts 6.0 12.0 µA IDD(6) Operating current at VDD=3 volts and fCL=18 KHz, VLCD=6 volts 4.2 8.8 µA IDD(7) Operating current at VDD=5 volts and tCYC=200 KHz, VLCD=10 volts 300 500 µA 150 300 µA 5.0 8.0 pF 5.0 7.5 ΚΩ Note 4 IDD(8) Operating current at VDD=3 volts and tCYC=200 KHz, VLCD=6 volts fosc(VDD=5V), fosc(VDD=3V) Please refer to Table 37, On-chip RC oscillator characteristics. Cin Input capacitance of all input pins RON LCD driver ON resistance Note 5 tR Reset time Note 6 1.0 µS Notes: 1. Conditions for the measurement: OSC1=OSC2=VDD, measured at the VDD pin. 2. These values are measured when the microcontroller does not perform any READ/WRITE operation to the chip. 3. These meaurements are for different members of the series: a) IDD(1) and IDD(4) are measured for the SBN1661G_M02 and the SBN0080G_S02, b) IDD(2) and IDD(5) are measured for the SBN1661G_M18, and c) IDD(3) and IDD(6) are measured for the SBN0080G_S18. 4. These values are measured when the microcontroller continuously performs READ/WRITE operation to the chip. 5. This measurement is for the transmission high-voltage PMOS or NMOS of COM0~15 and SEG0~60(79). Please refer to Section 18 for these driver circuit. The meaurement is for the case when the voltage differential between the source and the drain of the high voltage PMOS or NMOS is 0.1 volts. 6. The value is relative to the RESET pulse edge. That is, 1.0 µS after the last RESET edge, the device is completely reset. 2005 Oct 25 36 of 52 data sheet (v4) SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Avant Electronics Dot-matrix STN LCD Driver with 32-row x 80-column 14 AC TIMING CHARACTERISTICS 14.1 CL and FR timing TF TR TWHCL CL TWLCL 0.1 x VDD 0.9 x VDD 0.9 x VDD 0.1 x VDD 0.9 x VDD 0.1 x VDD 0.1 x VDD TDFR FR 0.1 x VDD Fig.21 Display Control Signal Timing Table 40 CL and FR timing characteristics at VDD=5 volts VDD = 5 V ±10%; VSS = 0 V; all voltages with respect to VSS unless otherwise specified; Tamb = −20 to +75 °C. SYMBOL PARAMETER CONDITIONS MIN. TWHCL CL clock high pulse width 33 TWLCL CL cock low pulse width 33 TR CL clock rise time TF CL clock fall time TDFR(input) FR delay time (input) When used as input in Slave Mode application TDFR(output) FR delay time (output) When used as output in Master Mode application, with CL= 100 pF. -2.0 TYP. MAX. UNIT µs µs 28 120 ns 28 120 ns 0.2 1.6 µS 0.2 0.36 µS Table 41 CL and FR timing characteristics at VDD=3 volts VDD = 3 V ±10%; VSS = 0 V; all voltages with respect to VSS unless otherwise specified; Tamb = −20 to +75 °C. SYMBOL PARAMETER CONDITIONS MIN. TWHCL CL clock high pulse width 65 TWLCL CL cock low pulse width 65 TR CL clock rise time TF CL clock fall time TDFR(input) FR delay time (input) When used as input in Slave Mode application TDFR(output) FR delay time (output) When used as output in Master Mode application, with CL= 100 pF. 2005 Oct 25 37 of 52 -3.6 TYP. MAX. UNIT µs µs 50 220 ns 50 220 ns 0.36 3.6 µS 0.32 0.6 µS data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 14.2 AC timing for interface with an 80-type microcontroller C/D, CS 0.9 x VDD 0.9 x VDD 0.1 x VDD 0.1 x VDD tAS tAH tF tR tRWPW RD, WR 0.9 x VDD 0.9 x VDD 0.1 x VDD 0.1 x VDD D0 to D7 (WRITE) Hi-Z D0 to D7 (READ) Hi-Z tCYC tDH tDS 0.9 x VDD 0.9 x VDD 0.1 x VDD 0.1 x VDD Hi-Z 0.9 x VDD 0.9 x VDD 0.1 x VDD 0.1 x VDD tACC tOH Hi-Z Fig.22 AC timing for interface with a 80-type microcontroller Table 42 AC timing for interface with a 80-type microcontorller at VDD=5 volts VDD = 5 V ±10%; VSS = 0 V; Tamb = -20 °C to +75°C. symbol parameter min. tAS Address set-up time 20 max. test conditons tAH Address hold time 10 tF, tR Read/Write pulse falling/rising time tRWPW Read/Write pulse width 200 ns tCYC System cycle time 1000 ns ns ns ns 15 tDS Data setup time 80 tDH Data hold time 10 tACC Data READ access time tOH Data READ output hold time 10 unit ns ns 90 CL= 100 pF. ns 60 Refer to Fig. 23. ns test conditons unit Table 43 AC timing for interface with an 80-type microcontorller at VDD=3 volts VDD = 3 V ±10%; VSS = 0 V; Tamb = -20 °C to +75°C. symbol parameter min. max. tAS Address set-up time 40 tAH Address hold time 20 tF, tR Read/Write pulse falling/rising time tRWPW Read/Write pulse width 400 ns tCYC System cycle time 2000 ns tDS Data setup time 160 ns 2005 Oct 25 ns ns 15 38 of 52 ns data sheet (v4) SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Avant Electronics Dot-matrix STN LCD Driver with 32-row x 80-column symbol parameter min. 20 tDH Data hold time tACC Data READ access time tOH Data READ output hold time 20 max. test conditons unit 180 CL= 100 pF, ns 120 Refer to 23. ns ns Note: The measurement is with the load circuit connected. The load circuit is shown in Fig. 23. Pin CL CL= 100 pF (including wiring and probe capacitance). VSS 2005 Oct 25 Fig.23 Load circuit. 39 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 14.3 AC timing for interface with a 68-type microcontroller tCYC tF tR E 0.9 x VDD tEW 0.1 x VDD 0.1 x VDD 0.9 x VDD 0.1 x VDD tAS1 R/W tAH1 0.9 x VDD 0.9 x VDD 0.1 x VDD 0.1 x VDD tAS2 C/D, CS tAH2 0.9 x VDD 0.9 x VDD 0.1 x VDD 0.1 x VDD tDH tDS D0 to D7 (WRITE) Hi-Z 0.9 x VDD 0.9 x VDD 0.1 x VDD 0.1 x VDD tACC D0 to D7 (READ) Hi-Z Hi-Z tOH 0.9 x VDD 0.9 x VDD 0.1 x VDD 0.1 x VDD Hi-Z Fig.24 AC timing for interface with a 68-type microcontroller Table 44 AC timing for interface with a 68-type microcontroller at VDD=5 volts VDD = 5 V ±10%; VSS = 0 V; Tamb = -20 °C to +75°C. symbol parameter min. tAS1 Address set-up time with respect to R/W 20 tAS2 Address set-up time with respect to C/D, CS 20 ns tAH1 Address hold time with respect to R/W 10 ns tAH2 Address hold time respect with to C/D, CS 10 ns tF, tR Enable (E) pulse falling/rising time tCYC System cycle time tEWR Enable pulse width for READ 100 ns tEWW Enable pulse width for WRITE 80 ns test conditons ns 15 tDS Data setup time 80 Data hold time 10 tACC Data access time tOH Data output hold time 10 40 of 52 unit ns 1000 tDH 2005 Oct 25 max. ns Note 1 ns ns 90 CL= 100 pF. ns 60 Refer to Fig. 23. ns data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column Table 45 AC timing for interface with a 68-type microcontroller at VDD=3 volts VDD = 3 V ±10%; VSS = 0 V; Tamb = -20 °C to +75°C. symbol parameter min. max. test conditons unit tAS1 Address set-up time with respect to R/W 40 tAS2 Address set-up time with respect to C/D, CS 40 ns tAH1 Address hold time with respect to R/W 20 ns tAH2 Address hold time respect with to C/D, CS 20 tF, tR Enable (E) pulse falling/rising time tCYC System cycle time tEWR Enable pulse width for READ 200 ns tEWW Enable pulse width for WRITE 160 ns ns ns ns 15 2000 tDS Data setup time 160 tDH Data hold time 20 tACC Data access time tOH Data output hold time 20 ns Note 1 ns ns 180 CL= 100 pF. ns 120 Refer to Fig. 23. ns Note: 1. The system cycle time(tCYC) is the time duration from the time when Chip Enable is enabled to the time when Chip Select is released. 2005 Oct 25 41 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 15 MICROCONTROLLER INTERFACE CIRCUIT 15.1 Example for interface with a 80-family microcontroller VDD VDD VDD A0 Note: This example is applicable to the SBN1661G_M02. A1~A7 IORQ 80-family Microcontroller C/D DECODER CS SBN1661G_M02 D0~D7 DB0~DB7 RD RD WR WR RES RESET/IF VSS GND V5 RESET Negative LCD bias voltage Fig.25 Interface example with an 80-family microcontroller 15.2 Example for interface with a 68-family microcontroller VDD VDD VDD A0 Note: This example is applicable to the SBN1661G_M02. The CS selection for the SBN0080G_S18 and the SBN0080G_S02 can be decoded from the address lines in the same way. For application with the SBN1661G_M18, which does not have a CS input, the CS output from the decoder must be ORed with C/D, E, and R/W. A1~A15 VMA 68-family Microcontroller C/D DECODER CS SBN1661G_M02 D0~D7 DB0~DB7 E E R/W R/W RES RESET/IF VSS GND V5 RESET Negative LCD bias voltage Fig.26 Interface example with a 68-family microcontroller 2005 Oct 25 42 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 15.3 Example for interface with other types of 8-bit microcontroller VDD VDD Note: This example is applicable only to the SBN1661G_M18, which does not have a CS input and the CS output from the address or I/O space decoding circut must be ORed with C/D, RD(E), and (WR)R/W. C/D Address 8-bit Microcontroller VDD (indicating commad/data) C/D Address or I/O space decoding D0~D7 SBN1661G_M18 DB0~DB7 RD(E) E WR(R/W) R/W RESET/IF VSS RES GND V5 RESET Negative LCD bias voltage Fig.27 Interface example with an 8-bit microcontroller 2005 Oct 25 43 of 52 data sheet (v4) SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Avant Electronics Dot-matrix STN LCD Driver with 32-row x 80-column 16 SYNCHRONIZATION OF CLOCK AND FRAME IN MASTER/SLAVE CONNECTIONS To expand COMMON/SEGMENT number, both the SBN1661G_M18 and the SBN1661G_M02 can be used Master. They can also be used as Slave. However, if the SBN1661G_M02 is used as Master, external clock source is needed, as it has no on-chip oscillator. In master/slave connections, clock and frame between the master and its slaves must be in synchronization. The SBN0080G_S18 and the SBN0080G_S02 can be used only as Slave for SEGMENT expansion. 16.1 SBN1661G_M18 connected with a SBN1661G_M18 To LCD SEGMENT To LCD SEGMENT SBN1661G_M18 SBN1661G_M18 To LCD COMMON To LCD COMMON VDD Master M/S OSC1 OSC2 Slave M/S FR OSC1 OSC2 VSS FR Rf Fig.28 SBN1661G_M18 connected with a SBN1661G_M18. 16.2 SBN1661G_M18 connected with more than two SBN0080G_S18 To LCD SEGMENT VDD To LCD SEGMENT SBN1661G_M18 SBN0080G_S18 To LCD SEGMENT SBN0080G_S18 To LCD COMMON M/S Master OSC1 OSC2 Rf Slave FR CL Slave FR CL FR CMOS buffer Note: when more than two slaves are connected, a CMOS clock buffer is needed to drive all the slaves. The duty and phase of the clock to all the slaves must be the same as that for the master. Fig.29 SBN1661G_M18 connected with more than two SBN0080G_S18 2005 Oct 25 44 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 16.3 SBN1661G_M02 connected with a SBN1661G_M02 To LCD SEGMENT To LCD SEGMENT SBN1661G_M02 SBN1661G_M02 M/S Master CL M/S FR External clock source 16.4 To LCD COMMON To LCD COMMON VDD VSS Slave CL FR Fig.30 SBN1661G_M02 connected with a SBN1661G_M02. SBN1661G_M02 connected with a SBN0080G_S02 To LCD SEGMENT To LCD SEGMENT SBN1661G_M02 SBN0080G_S02 To LCD COMMON VDD M/S Master CL Slave FR External clock source 2005 Oct 25 CL FR Fig.31 SBN1661G_M02 connected with a SBN0080G_S02. 45 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 17 TYPICAL APPLICATIONS 17.1 1/16 duty, 10 characters x 2 lines COM0 In this application, 10-characters x 2-lines can be displayed, if the format of character font is 6 x 8 pixels. 16 x 61 LCD Panel COM15 SEG0 SEG60 SEG0 SEG60 COM15 SBN1661G_M18 COM0 Fig.32 1/16 duty, 10 characters x 2 lines 17.2 1/16 duty, 23 characters x 2 rows COM0 16 x 141 LCD Panel COM15 In this application, 23-characters x 2-lines can be displayed, if the format of character font is 6 x 8 pixels. SEG0 SEG60 SEG0 SEG60 SEG61 SBN1661G_M18 SEG79 SBN1661G_S18 (slave) CL (master) COM0 SEG0 FR COM15 SEG140 Fig.33 1/16 duty, 23 characters x 2 lines 17.3 1/32 duty, 33 characters x 4 lines COM0 32 x 202 LCD Panel COM15 COM16 COM31 SEG0 SEG0 SEG60 SEG60 SEG61 COM15 FR COM0 CL SBN1661G_M18 (master) SEG0 SEG79 SEG141 SEG201 FR SBN1661G_S18 (slave) In this application, 33-characters x 4-lines can be displayed, if the format of character font is 6 x 8 pixels. 2005 Oct 25 SEG140 46 of 52 CL SEG0 SEG60 COM15 SBN1661G_M18 (slave) COM0 Fig.34 1/32 duty, 33 characters x 4 lines data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 18 PIN CIRCUITS Table 46 MOS-level schematics of all input, output, and I/O pins. SYMBOL Input/ output CIRCUIT NOTES VDD C/D, R/W(WR), E/RD, RESET/IF Inputs VSS VDD M/S Input VSS VDD CLK VDD OSC1 OSC2 OSC1, OSC2 Disable Disable Disable The circuit encircled inside the red dashed frame is the oscillator circut. VSS VSS VDD Enable VDD Output Enable D0~D7, FR I/O Data out VSS VSS Data in 2005 Oct 25 47 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column SYMBOL Input/ output CIRCUIT VDD EN1 NOTES VDD SEG0~79 VDD V5 VDD EN2 V5 V2 SEG0~79 V5 VDD EN3 VDD EN4 V3 V5 V5 V5 VDD EN1 VDD COM0~15 VDD V5 VDD EN2 V5 V1 COM0~15 V5 VDD EN3 VDD EN4 V4 V5 V5 V5 2005 Oct 25 48 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 19 APPLICATION NOTES 1. It is recommended that the following power-up sequence be followed to ensure reliable operation of your display system. As the ICs are fabricated in CMOS and there is intrinsic latch-up problem associated with any CMOS devices, proper power-up sequence can reduce the danger of triggering latch-up. When powering up the system, control logic power must be powered on first. When powering down the system, control logic must be shut off later than or at the same time with the LCD bias (VEE). 1 second (minimum) 1 second (minimum) 5V VDD 0V 0~50 ms 0~50 ms Signal VEE 0 second (minimum) 0 second (minimum) -30V Fig.35 Recommended power up/down sequence 2. The metal frame of the LCD panel should be grounded. 3. A 0.1 µF ceramic capacitor should be connected between VDD and VSS. 4. A 0.1 mF ceramic capacitor should be connected between VDD (or VSS) and each of V1, V2, V3, V4, and V5. 5. If the length of the cable connecting the host microcontroller and the LCD module is longer than 45 cm, a ceramic capacitor of 20P~150P should be connected between VDD (or VSS) and each of the R/WR(WR), the E/RD, and the CS. 2005 Oct 25 49 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 20 PACKAGE INFORMATION Pakage information is provided in another document. Please contact Avant Electronics for package information. 2005 Oct 25 50 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 21 SOLDERING 21.1 Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. For more in-depth account of soldering ICs, please refer to dedicated reference materials. 21.2 Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, please contact Avant for drypack information. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. 21.3 Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 21.4 Repairing soldered joints Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 2005 Oct 25 51 of 52 data sheet (v4) Avant Electronics SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G_S02 Dot-matrix STN LCD Driver with 32-row x 80-column 22 LIFE SUPPORT APPLICATIONS Avant’s products, unless specifically specified, are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Avant customers using or selling Avant’s products for use in such applications do so at their own risk and agree to fully indemnify Avant for any damages resulting from such improper use or sale. 2005 Oct 25 52 of 52 data sheet (v4)