=
Low Cost, Low Power
Stereo Audio Analog Front End
AD74322
Preliminary Technical Data
FEATURES
2.5V Stereo Audio Codec with 3.3 V Tolerant Digital
Interface
Supports 96 kHz Sample Rates
Supports 16/18 /20/24-Bit Word Lengths
Multibit Sigma Delta Modulators with
“Perfect Differential Linearity Restoration” for
Reduced Idle Tones and Noise Floor
Data Directed Scrambling DACs - Least Sensitive to Jitter
Performance (20 Hz to 20 kHz)
90 dB ADC and DAC SNR
Digitally Programmable Input/Output Gain
On-chip Volume Controls Per Output Channel
Hardware and Software Controllable Clickless Mute
Supports 256xFs, 512xFs and 768xFs Master Mode Clocks
Master Clock Pre-Scaler for use with DSP master clocks
Flexible Serial Data Port with Right-Justified, LeftJustified, I2S-Compatible and DSP Serial Port Modes
Supports Packed Data Mode (“TDM”) for cascading
devices.
On-Chip Reference
16, 20 and 24-Lead SOIC, SSOP and TSSOP Package
options.
FUNCTIONALBLOCKDIAGRAM
DVDD1(EXT) DVDD2(INT)
CDOUT
CCLK
SPI
Control
Port
Block
CHANNEL 1
VIN1N
VIN2P
CHANNEL 2
VIN2N
ASDATA/SDO
LRCLK/SDIFS
CHANNEL 1
I2S
Port
SDOFS
Reference
BCLK/SCLK
DGND
VOUT2P
DAC
VOUT2N
REFCAP
CLKIN
AGND
AVDD
ADC
CDIN
CCLK
VOUT1N
CHANNEL 2
DVDD1(EXT) DVDD2(INT)
CDOUT
VOUT1P
DAC
DSDATA/SDI
SPI
Control
Port
Block
CHANNEL 1
VIN1
ADC
CLATCH
CHANNEL 2
VIN2
ASDATA
DAC
DSDATA
LRCLK
CHANNEL 1
I2S
Port
Reference
BCLK
GENERAL DESCRIPTION
DGND
REFCAP
DVDD1(EXT) DVDD2(INT)
CLKIN
VOUT1
DAC
CHANNEL 2
VOUT2
AGND
AVDD
ADC
CHANNEL 1
Control
VIN1
Block
ADC
CHANNEL 2
VIN2
SDO
DAC
SDI
SDIFS
CHANNEL 1
Data
Port
SDOFS
Reference
SCLK
REFCAP
VOUT1
DAC
CHANNEL 2
DGND
REV. Pr D
VIN1P
ADC
CLATCH
The AD74322 is a front-end processor for general purpose
audio and voice applications. It features two multi-bit Σ∆
A/D conversion channels and two multi-bit Σ∆ D/A
conversion channels. Each ADC channel provides >85 dB
signal-to-noise ratio while each DAC channel provides
>90 dB, both over an audio signal bandwidth.
The AD74322 is particularly suitable for a variety of applications where stereo input and output channels are
required, including audio sections of Digital Video
Camcorder, portable personal audio devices and the
analog front ends of conference phones . Its high quality
performance also make it suitable for speech and telephony
applications such as speech recognition and synthesis and
modern feature phones.
AVDD
ADC
CDIN
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APPLICATIONS
Digital Video Camcorders (DVC)
Portable Audio Devices (Walkman etc)
Audio Processing
Voice Processing
Conference Phones
General Purpose Analog I/O
CLKIN
VOUT2
AGND
03/00
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1998
PRELIMINARY TECHNICAL DATA
AD74322
An on-chip reference voltage is included but can be
bypassed if required for use with an external reference
source.
The AD74322 offers sampling rates which, depending on
MCLK selection and MCLK divider ratio, range from 8
kHz in the voiceband range to 96 kHz in the audio range.
The digital interface to the AD74322 is configured as two
separate ports which allow separation of device control
and data streams. Control and status are monitored using
an SPI® compatible serial port while the input and output
data streams are controlled using an I2S® port. The two
I2S streams are controlled by a common Bit-Clock and
Left/Right Clock pins. There is also a DSP mode
available on the audio data port which will also allow both
control and data to be streamed through the same interface
where controller resources are limited.
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The AD74322 is available in various lead count package
options. These range from a 16-pin variant with singleended inputs/outputs and no SPI port through a 20-pin
variant with single-ended inputs/outputs and an SPI port
to a 24-pin variant with differential inputs/outputs and an
SPI port. These devices will be available in SOIC, SSOP
and TSSOP package options and are specified for the
industrial temperature range of -40°C to +85°C.
–2–
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03/00
AD74322
PRELIMINARY TECHNICAL DATA
PARAMETER
Min
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution (all ADCs)
Dynamic Range (20 Hz to 20 kHz, -60 dB Input)
No Filter
With A-Weighted Filter
Total Harmonic Distortion + Noise
Interchannel Isolation
InterchannelGainMismatch
Programmable Input Gain
Gain Step Size
Offset Error
Full Scale Input Voltage At Each Pin
Automatic Level Control
Attack Time Resolution
Attack Time
Decay Time Resolution
Decay Time
Gain Drift
InputResistance
InputCapacitance
Common Mode Input Volts
AD74322A
Typ
Max
24
90
92
-85(0.0056)
TBD
TBD
12
3
0.5 (1.414)
Units
Test Conditions
Bits
dB
dB
dB(%)
dB
dB
dB
dB
0
LSB
Vrms (Vpp)
Single Ended
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TBD
TBD
TBD
TBD
TBD
dB
dB
dB(%)
dB
dB(%)
15
TBD
TBD
TBD
TBD
TBD
0.098
60
-100
0.5 (1.414)
??
2.25
REFERENCE(Internal)
Absolute Voltage, VREF
VREF TC
DACINTERPOLATIONFILTER
Pass Band
Pass Band Ripple
TransitionBand
Stop Band
Stop Band Attenuation
GroupDelay
PR D 03/00
90
92
-85(0.0056)
TBD
TBD
10
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range (20 Hz to 20 kHz, -60 dB Input)
No Filter
With A-Weighted Filter
Total Harmonic Distortion + Noise
Interchannel Isolation
InterchannelGainMismatch
DCAccuracy
Gain Error
Interchannel Gain Mismatch
Gain Drift
Interchannel Crosstalk (EIAJ method)
Interchannel Phase Deviation
Volume Control Step Size (1023 Linear Steps)
Volume Control Range (Max Attenuation)
MuteAttenuation
De-emphasis Gain Error
Full Scale Output Voltage At Each Pin
Output Resistance At Each Pin
Common Mode Output Volts
ADCDECIMATIONFILTER
Pass Band
Pass Band Ripple
TransitionBand
Stop Band
Stop Band Attenuation
GroupDelay
1.1V
Bits
µs/Bit
Bits
µs/Bit
ppm/°C
kΩ
pF
V
%
ppm/°C
dB
dB
Degrees
%
dB
dB
+/- 0.1
dB
Vrms(Vpp)
??
Ω
V
1.1
TBD
0.xxFs
0.xxFs
70
lll/Fs
0.xxFs
0.xxFs
70
lll/Fs
V
ppm/°C
0.xxxFs
±0.00xx
0.xxFs
nnn/Fs
mmm/Fs
0.xxxFs
±0.00xx
0.xxFs
nnn/Fs
–3–
mmm/Fs
Hz
dB
Hz
Hz
dB
ms
Hz
dB
Hz
Hz
dB
ms
Single Ended
AD74322–SPECIFICATIONS
PARAMETER
LOGICINPUT
VINH, Input High Voltage
VINL, Input Low Voltage
Input Current
InputCapacitance
LOGICOUTPUT
VOH, Output High Voltage
VOL, Output Low Voltage
Three-State Leakage Current
POWERSUPPLIES
AVDD,DVDD2
DVDD1
POWERCONSUMPTION
All Sections On
ADCsOnOnly
DACsOnOnly
Reference On Only
PowerdownMode
(AVDD = DVDD2 = +2.5V ±10%, DVDD1 = 3.0V ±10%, fCLKIN = 12.288 MHz,
fSAMP = 48 kHz, TA = TMIN to TMAX, unless otherwise noted)
Min
AD74322A
Typ
Max
Units
DVDD1 - 0.8
0
-10
DVDD1
0.8
+10
10
V
V
µA
pF
DVDD1 - 0.4
0
-10
DVDD1
0.4
+10
V
V
µA
2.75
3.3
V
V
2.25
2.7
2.5
3.0
Test Conditions
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TBD
TBD
TBD
TBD
TBD
–4–
mA
mA
mA
mA
µA
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PRELIMINARY TECHNICAL DATA
AD74322
ORDERING GUIDE
Model
Range
AD74322DAR
AD74322DARU
AD74322AAR
AD74322AARU
AD74322AAR
AD74322AARU
-40
-40
-40
-40
-40
-40
C
C
C
C
C
C
to
to
to
to
to
to
Package
+85
+85
+85
+85
+85
+85
C
C
C
C
C
C
R-16
RU-16
R-20
RU-20
R-24
RU-24
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CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the XX0000 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
VINN1 1
24 VOUTN1
VINN2 2
23 VOUTN2
VINN1 3
22 VOUTN1
VINP1 4
21 VOUTP1
REFCAP 5
20 AVDD
AGND 6
19 RESET
DGND 7
18 SDO
DVDD2 8
17 SDFS
TOP VIEW
DVDD1 9 (Not
to Scale)
MCLK 10
16 SDI
CIN 12
VINP2 1
20 VOUTP2
VINP1 2
19 VOUTP1
REFCAP 3
13 CLATCH
18 AVDD
AGND 4
17 RESET
DGND 5
16 SDO
DVDD2 6
15 SDFS
15 SCLK
14 COUT
CCLK 11
VINP2 1
16 VOUTP2
VINP1 2
15 VOUTP1
REFCAP 3
TOP VIEW
DVDD1 7 (Not
to Scale)
MCLK 8
CCLK 9
CIN 10
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03/00
14 SDI
13 SCLK
12 COUT
11 CLATCH
–5–
14 AVDD
AGND 4
13 RESET
DGND 5
12 SDO
DVDD2 6
11 SDFS
TOP VIEW
DVDD1 7 (Not
to Scale)
MCLK 8
10 SDI
9 SCLK
PRELIMINARY TECHNICAL DATA
AD74322
PIN FUNCTION DESCRIPTION (SINGLE-ENDED I/O ; NO SPI PORT)
Mnemonic
I/O
Function
VIN1
VIN2
VOUT1
VOUT2
REFCAP
AVDD
AGND
DVDD1
DVDD2
DGND
MCLK
SDO
SDI
SDFS
4-5-6
SCLK
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I/O
Analog Input - Channel 1
Analog Input - Channel 2
Analog Output - Channel 1
Analog Output - Channel 2
Internal Reference - Can also be used for connection of an external reference
Analog Power Supply Connection
AnalogGround/SubstrateConnection
Digital Power Supply Connection (Interface)
Digital Power Supply Connection (Core)
DigitalGround/SubstrateConnection
ExternalClockConnection
ADC Serial Data Out - DSP Mode
DAC Serial Data In - DSP Mode
Serial Data Input Frame Sync - DSP Mode
Powerdown/Reset Input
Serial Clock - DSP Mode
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PIN FUNCTION DESCRIPTION (SINGLE-ENDED I/O WITH SPI PORT)
Mnemonic
I/O
Function
VIN1
VIN2
VOUT1
VOUT2
REFCAP
AVDD
AGND
DVDD1
DVDD2
DGND
MCLK
CDIN
CDOUT
CCLK
CLATCH
ASDATA
DSDATA
LRCLK/
BCLK
RESET
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O
I/O
Analog Input - Channel 1
Analog Input - Channel 2
Analog Output - Channel 1
Analog Output - Channel 2
Internal Reference - Can also be used for connection of an external reference
Analog Power Supply Connection
Analog Ground/Substrate Connection
Digital Power Supply Connection (Interface)
Digital Power Supply Connection (Core)
Digital Ground/Substrate Connection
External Clock Connection
Serial Data In on SPI Control Port
Serial Data Out on SPI Control Port
Serial Clock on SPI Control Port
Serial Data Latch on SPI Control Port
ADC Serial Data Out - I2S
DAC Serial Data In - I2S
Left/Right Channel Select - I2 S
Bit Clock - I2S
Powerdown/Reset Input
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I/O
I/O
I
–6–
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PRELIMINARY TECHNICAL DATA
AD74322
PIN FUNCTION DESCRIPTION (DIFFERENTIAL I/O WITH SPI PORT)
Mnemonic
I/O
Function
VINP1
VINN1
VINP2
VINN2
VOUTP1
VOUTN1
VOUTP2
VOUTN2
REFCAP
AVDD
AGND
DVDD1
DVDD2
DGND
MCLK
CDIN
CDOUT
CCLK
CLATCH
ASDATA
DSDATA
LRCLK/
BCLK
RESET
I
I
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O
O
O
O
I/O
Analog Input - Channel 1 Positive
Analog Input - Channel 1 Negative
Analog Input - Channel 2 Positive
Analog Input - Channel 2 Negative
Analog Output - Channel 1 Positive
Analog Output - Channel 1 Negative
Analog Output - Channel 2 Positive
Analog Output - Channel 2 Negative
Internal Reference - Can also be used for connection of an external reference
Analog Power Supply Connection
Analog Ground/Substrate Connection
Digital Power Supply Connection (Interface)
Digital Power Supply Connection (Core)
Digital Ground/Substrate Connection
External Clock Connection
Serial Data In on SPI Control Port
Serial Data Out on SPI Control Port
Serial Clock on SPI Control Port
Serial Data Latch on SPI Control Port
ADC Serial Data Out - I2S
DAC Serial Data In - I2S
Left/Right Channel Select - I2 S
Bit Clock - I2S
Powerdown/Reset Input
Pr D
03/00
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I/O
I/O
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–7–
PRELIMINARY TECHNICAL DATA
AD74322
FUNCTIONAL DESCRIPTION
Reference
ADCSection
The AD74322 features an on-chip reference whose
nominal value is 1.125 V.A __ nF capacitor applied at the
REFCAP pin is necessary to stabilise the referrence. (See
Figure <REFCAP_Int>)
There are two ADC channels in the AD74322, configured as a stereo
pair. Each ADC channel can be independently muted. The input pins
are switched between differential inputs or four single ended inputs
accordingly. The gain block can be programmed for independent left and
right gains, in steps of +3dB, from 0dB to +12dB. The ADC operates at
an oversampling ratio of 128 and the decimation filter reduces the output
to the standard sample rates. The output maximum
sample rate is 96 kHz at ASDATA.
AD743xx
REFCAP
AutomaticLevelControl
AnalogSigmaDeltaModulator
DecimatorSection
The digital decimation filter has a passband ripple of ±0.01dB and a
stopband attenuation of 70dB. The filter is an FIR type with a linear
phase response. The group delay at 48kHz is ??us. Output sample rates
up to 96 kHz are supported.
Input Signal swing
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Each ADC input has an input range of 0.5 VRMS / 1.414 VP-P (SingleEnded) about a bias point equal to VREFCAP (See Figure
<Input_Swing>)
Figure <REFCAP_Int>
If it is required to use an external reference, because of its value or its
reference tempco, the internal reference can be disabled via Control
Register __ and the external reference applied at the REFCAP pin (See
Figure<REFCAP_Ext>).
AD743xx
1.414 V P-P
VREFCAP
VINPx
1.0 V
1.414 V P-P
VREFCAP
AD743xx
REFCAP
EXTERNAL
REFERENCE
VINNx
Figure <Input_Swing>
DACSection
The AD74322 has two DAC channels arranged as a stereo pair, with two,
fully differential voltage, analog outputs for improved noise and distortion
performance. Each channel has it’s own independently programmable
attenuator with a maximum attenuation of 63dB, adjustable in 1dB steps.
Digital inputs are via a serial data input pin and a common frame
(DLRCLK) and bit (DBLCK) clock or using a ‘packed data’ mode, both
channels can be input using a single data pin.
InterpolatorSection
Digital Sigma Delta Modulator
DAC
Analog Output Filter
OutputSignalswing
Each ADC input has an output range of 0.5 VRMS / 1.414 VP-P (SingleEnded) about a bias point equal to VREFCAP (See Figure
<Output_Swing>)
Figure <REFCAP_Ext>
MasterClockingScheme
The update rate of the AD74322’s ADC and DAC channels require an
internal master clock (IMCLK) which is 256 times that sample update
rate (IMCLK = 256 * FS). In order to provide some flexibility in
selecting sample rates, the device has a series of three
master clock pre-scalers which are programmable and
allow the user to choose a range of convenient sample
rates from a single external master clock. The master
clock signal to the AD74322 is applied at the MCLK pin.
The MCLK signal is passed through a series of two
programmable MCLK pre-scalers (divider) circuits which
can be selected to reduce the resulting Internal MCLK
(IMCLK) frequency if required. The first MCLK prescaler provides divider ratios of /1 (pass through), /2, /3
while the second pre-scaler provides divider ratios of ./1
(pass through), /2, /4 and the third pre-scaler provides
ratios of /1 (pass through), /2 and /5..
AD743xx
1.414 V P-P
VREFCAP
Programmable
MCLK
Divider
Pre-Scaler 1
Pre-Scaler 2
VOUTPx
MCLK
1.414 V P-P
VREFCAP
VOUTNx
/1
/1
/2
/2
/3
/4
IMCLK
Control Reg
Figure <Output_Swing>
–8–
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PRELIMINARY TECHNICAL DATA
AD74322
2.4 V
FILTER
AVDD
VDD2
3.3 V
DUAL
REGULATOR
5.0 V
DVDD
VDD1
4
AD743xx
DSP
4
AGND
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DGND
DGND
Figure <PSU_Connection>
Figure <MCLK_Divider>
The divider ratios will allow more convenient sample rate
selection from a common MCLK which may be required
in many voice related applications.
a known state following the power-up of the device. There
is also a software reset capability available by setting the
RESET bit in Control Register _. This control register is
accessed through the Control Port.
Example 1: fSAMP = 48 kHz and 8 kHz required
Power Supplies and Grounds
MCLK = 48*10 * 256 = 12.288 MHz to cater for 48
kHz fSAMP
The AD74322 features three separate supplies: AVDD,
DVDD1 and DVDD2.
For fSAMP = 8 kHz, it is necessary to use the /3 setting in
Pre-Scaler 1, the /2 setting in Pre-Scaler 2 and pass
through in Pre-Scaler 3. This results in an IMCLK =
8*103 * 256 = 2.048 MHz (= 12.288 MHz/6).
AVDD is the supply to the analog section of the device
and must therefore be of sufficient quality to preserve the
AD74322’s performance characteristics. It is nominally a
2.4 V supply.
Example 2: fSAMP = 48 kHz and 32 kHz required
DVDD1 is the supply for the digital interface section of
the device. It is fed from the digital supply voltage of the
DSP or controller to which the device is interfaced and
allows the AD74322 to interface with devices operating at
supplies of between 2.4 V -5% to 3.3 V + 10%.
3
MCLK =
24.576 MHz
For fSAMP = 48 kHz, it is necessary to use the /2 setting in
Pre-Scaler 1 and the /1 (pass-through) setting in PreScaler 2 and pass through in Pre-Scaler 3. This results in
an IMCLK = 48*103 * 256 = 12.288 MHz.
DVDD2 is the supply for the digital core of the
AD74322. It is nominally a 2.4 V supply.
For fSAMP = 32 kHz, it is necessary to use the /3 setting in
Pre-Scaler 1 and the /1 (pass-through) setting in PreScaler 2 and pass through in Pre-Scaler 3. This results in
an IMCLK = 32*103 * 256 = 8.192 MHz.
Example 3: fSAMP = 44.1 kHz and 11.025 kHz required
MCLK = 44.1*103 * 256 = 11.2896 MHz to cater for
44.1 kHz fSAMP
For fSAMP = 11.025 kHz, it is necessary to use the /1 setting in PreScaler 1 and the /4 setting in Pre-Scaler 2 and pass
through in Pre-Scaler 3. This results in an IMCLK =
11.025*103 * 256 = 2.8224 MHz (= 11.2896 MHz/4).
SampleRates
For all applications the sampling rate is defined by the internal master
clock frequency (IMCLK) where IMCLK = 256 * fSAMP.
Power-On Reset
The AD74322 features a power-on reset circuit which
Pr D 03/00
ensures
that all internal circuitry is reset and initialised to –9–
PRELIMINARY TECHNICAL DATA
AD74322
Sampling Rate s (kHz) us ing Scalar (Divide r) Ratios (as s ume s 256fs )
M CLK
(M Hz)
1
2
3
4
5
6
8
9
10
12
15
2.048
8
4
-
2
-
-
1
-
-
-
-
12 . 2 8 8
48
24
-
12
-
-
6
-
-
-
-
16.384
64
32
-
16
-
-
8
-
-
-
-
24.576
96
48
36.864
-
-
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-
24
-
-
12
-
-
-
-
48
-
-
24
-
-
-
12
-
Table <MCLK_Divider>
MCLK (MHz)
Sampling Rate
fS (kHz)
Interpolator
Mode
8
16
256fS
512fS
768fS
8x (Normal)
4x (Double)
2.048
4.096
6.144
11.1
22.2
8x (Normal)
4x (Double)
2.8224
5.6448
8.4672
32
64
8x (Normal)
4x (Double)
8.192
16.384
24.576
44.1
88.2
8x (Normal)
4x (Double)
11.2896
22.5792
33.8688
48
96
8x (Normal)
4x (Double)
12.288
24.576
36.864
Table <MCLK_Select>
–10–
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PRELIMINARY TECHNICAL DATA
AD74322
Data in and out of the Control Port go through a 16-bit
shift register whose contents are mapped to the internal
registers using the mapping scheme of Figure
<ContPortMap>. A 16-bit word received by the Control
Port is decoded as a read or write to a register address set
by bits 15 - 12. This 4-bit register address selects 1 of 16
registers as shown in Table <ContRegMap>. Bit 11
selects whether a register read or write is requested Write = 0, Read = 1. Bit-10 is reserved. Bits 9 through 0
contain register data. Each Control register’s contents are
detailed below.
INTERFACING
The AD74322 features two separate interfaces, Control and Data, which
are used to program control settings and send/receive sample data
respectively. The Control interface is implemented using an SPI type
protocol but transfers 16-bits per frame. The Data interface uses either a
DSP or I2S protocol to transfer stereo data samples between controller
and codec. The DSP compatible interface mode allows data samples to be
transferred in a protocol that is supported by the serial interfaces of most
fixed- and floating-point DSPs.
In order to reduce peripheral requirements when interfacing the AD74322
with the host DSP, the DSP mode allows the DSP to send both data and
control information to the device via the data interface. This is the default
mode and requires users to only use a single DSP SPORT to both control
the device and service it with data samples.
DataInterface
There are two modes of operation of the data interface: DSP mode and
I2S mode. The default mode of the data interface is a DSP mode which
combines control and data functions in a single protocol. This is to reduce
the peripheral overhead required on the DSP when interfacing to the
AD74322. This mode operates in a standard DSP serial format. In I2S
mode the data interface streams audio data samples being sent to or
received from the DACs and ADCs respectively, using the I2S serial
protocol.
ControlInterface
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Control of the AD74322 operation is via a set of 16 Control Registers
which are programmed through the Control Port. The Control Port
protocol is similar to the SPIÒ protocol with the exception that 16-bits of
data are transferred per frame. The Control Port consists of the following
pins: CCLK - Control Port Serial Clock, CLATCH - Control Port Latch
or Frame signal, CDIN - Control Port Serial Data In and CDOUT Control Port Data Out. CLATCH is a framing signal that is active low.
When asserted, it gates the other interface lines as being active. CCLK is
used to clock input data on CDIN and clock output (readback) data on
CDOUT. Figure <Control_Interface> details the connectivity of the
Control Port to a controller and Figure <Control_Timing> details the
interface timing.
In either mode it can be configured as either a master or slave device
ensuring connectivity to the largest number of host processors.
DSPMode
The DSP mode allows interfacing to most fixed- and floating-point DSPs
as well as other processors such as RISCs etc that having serial ports that
support synchronous communications. The key feature of synchronous
DSP communications is that the serial data is framed by a separate Frame
Sync signal. Figures <Data_DSP_Slave> and <Data_DSP_Master> detail
connectivity in Master Mode (codec is master) and Slave Mode (codec is
slave) respectively.
AD743xx
CDIN CLATCH CCLK CDOUT
AD743xx
(MASTER)
LRCLK/SDIFS
TFS
DSDATA/SDI
DT
DSP
BCLK/SCLK
SCLK
(SLAVE)
ASDATA/SDO
DR
CONTROLLER
RFS
SDOFS
Figure <Data_DSP_Slave>
Figure <Control_Interface>
CCLK
CDIN
MSB
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
MSB
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
CDOUT
CLATCH
Figure <Control_Timing>
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–11–
PRELIMINARY TECHNICAL DATA
AD74322
BCLK/
SCLK
LRCLK/
FS
DSDATA/
SDI
CONTROL
LEFT DAC
RIGHT DAC
ASDATA/
SDO
STATUS
LEFT ADC
RIGHT ADC
Figure <DSP_Protocol>
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AD743xx
(SLAVE)
DSP
(MASTER)
TFS
LRCLK/SDIFS
TFS
DSDATA/SDI
DT
BCLK/SCLK
SCLK
TCLK
(MASTER)
ASDATA/SDO
DR
RFS
DT
ADSP21065L
DR
RFS
SDOFS
RCLK
Figure <Data_DSP_Master>
DSDATA/SDI
BCLK/SCLK
ASDATA/SDO
AD743xx
(SLAVE)
Figure <Data_I2S_DSP_Master>
The serial protocol uses a fixed position for data being sent to or received
from the Left and Right DACs and ADCs respectively and the control
words being sent to and the status words being received from the device
respectively. Figure <DSP_Protocol> details the arrangement of both
audio and control/status information in the serial transfer.
TFS
The I2S bus is a three line serial bus which features a serial data line
carrying both left and right (stereo) channels. The Left and Right channel
information are selected by the status of the Left/Right Clock (Word
Select) line. Serial data is clocked by the Bit Clock line. Figures
<Data_I2S_DSP_Master> and <Data_I2S_DSP_Slave> detail the
interface configuration between controller and codec in I2S mode with
controller as master and slave respectively. Figure <> details I2S timing.
The interface allows easy transfer of arbitrary length serial data samples
sent MSB first. Toggling of the Left/Right Clock line indicates that the
end of the current word will occur after the following Bit Clock cycle and
the start of the alternate channel word will occur on the subsequent Bit
Clock cycle
DT
ADSP21065L
TCLK
(MASTER)
DR
I2S (Inter IC Sound Bus) Mode
RFS
RCLK
LRCLK/SDIFS
DSDATA/SDI
BCLK/SCLK
ASDATA/SDO
AD743xx
(SLAVE)
Figure <Data_I2S_DSP_Slave>
LEFT CHANNEL
LRCLK
LRCLK/SDIFS
RIGHT CHANNEL
BCLK
SDATA
MSB
LSB
MSB
LSB
I2S MODE - 16 TO 24-BITS PER CHANNEL
Figure <I2S_Timing>
–12–
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PRELIMINARY TECHNICAL DATA
AD74322
AD743xx
CDIN CLATCH
AD743xx
CCLK
CDOUT
CDIN CLATCH
CCLK
CDOUT
CONTROL DATA IN
CONTROL DATA OUT
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CONTROL DATA LATCH
CONTROL DATA CLOCK
Figure <Control_Cascade_Daisy_Chain>
CCLK
CDIN
MSB
14
13
DEV N
CDOUT
MSB
DEV N
14
13
12
12
11
11
10
10
9
9
8
8
DEV N
DEV 1
8
8
DEV N
DEV 1
7
7
6
6
5
5
CLATCH
Figure <Control_Cascade_Timing_Daisy_Chain>
INTERFACING MULTIPLE DEVICES
Many applications require multiple channels of input and output. The
AD743xx series of devices are designed to cater for extending the number
of I/O channels by cascading devices together while interfacing to a single
control or data port. This reduces the overhead requirement on the
controller in terms of serial ports.
ControlPortCascading
There are two methods of cascading the Control Ports of
multiple AD743xx devices together so that all devices can
be controlled from a single controller serial port. One
method is to configure the multiple devices as a daisy
chain of Control Ports each 16-bits wide with common
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–13–
4
3
2
1
LSB
DEV 1
4
3
2
1
LSB
DEV 1
PRELIMINARY TECHNICAL DATA
AD74322
AD743xx
CDIN CLATCH
AD743xx
CCLK
CDOUT
CDIN CLATCH
CCLK
CDOUT
CONTROL DATA IN
CONTROL DATA OUT
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CONTROL DATA CLOCK
CONTROL DATA LATCH 1
CONTROL DATA LATCH N
Figure <Control_Cascade_TDM>
CCLK
CDIN
MSB
14
5
4
3
2
1
DEV N
0
MSB
14
13
3
2
1
DEV N DEV 1
LSB
DEV 1
CDOUT
MSB
DEV N
14
5
4
3
2
1
0
MSB
14
13
DEV N DEV 1
3
2
1
LSB
DEV 1
CLATCH N
CLATCH 1
Figure <Control_Cascade_Timing_TDM>
–14–
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PRELIMINARY TECHNICAL DATA
AD74322
AD743xx
AD743xx
(SLAVE)
(SLAVE)
LRCLK/ DSDATA/
SDIFS
SDI
BCLK/
SCLK
ASDATA/
SDO
SDOFS
LRCLK/ DSDATA/
SDIFS
SDI
BCLK/
SCLK
ASDATA/
SDO
SDOFS
TFS
DSP
(MASTER)
DT
SCLK
DR
RFS
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Clock and Latch signals. The other method involves
creating a common Data In and Data Out buses where
each device has a common Clock but has separate Latch
signals which enable the devices on the bus at different
times - either as a Time Division Multiplex (TDM) or
software control.
DACs (with I2S interfaces) to be interfaced to a cascade
of AD743xx devices. This allows extra flexibility in
choosing the number of input and out channels in the
cascade. The various (potential) modes for interfacing the
data ports of multiple devices are listed below:
DaisyChainMode
In this mode, sample data is passed along a daisychain of
I/O registers in a similar manner that used in the present
AD733xx devices. At the sample event each ADC result is
placed in the I/O register and is subsequently shifted
towards the DSP’s Rx register. This achieved by a
common SDIFS pulse which samples each device (enables
each device’s sample). {Drawback: as the device is stereo,
we would need to send 32 bits (or perhaps more) to the I/
O register at each sample event.}
DSP Mode - Daisy Chaining
In Daisy Chain Mode, the serial registers (16-bit) of each device are
cascaded together by connecting the controller’s Data Out to CDIN of
the first device and the CDOUT of the first device to
CDIN of the next device (see Figure
<Control_Cascade_Daisy_Chain>). The CDOUT of the
final device is connected to the controller’s Data In. The
effective cascade length becomes 16 * N (where N is the
number of devices in cascade) and each control word write
to each device requires 16 * N CCLK cycles. Please note
that the CLATCH pin of each device is driven from a
common controller output signal which must be active
during the entire 16 * N CCLK cycles as shown in Figure
<Control_Cascade_Timing_Daisy_Chain>.
TDMMode
In multiplexed mode, each device is programmed with its cascade
position. This allows devices to be enabled to the data buses only in their
appropriate time-slot as defined by the initial frame-sync
signal.
TDMMode
In TDM Mode, each device’s CDIN and CDOUT are commoned to the
controller’s Data Out and Data In respectively (see Figure
<Control_Cascade_TDM>). Each device’s CLATCH pin is separately
controlled. When CLATCH is disasserted activity on CDIN and CCLK
is not recognised and the CDOUT pin is tri-stated. Figure
<Control_Cascade_Timing_TDM>showsTDMModeControltiming.
Data Port Cascading
The Data Port of the AD74322 is designed to allow
multiple single or dual channel devices to be cascaded
from a single DSP or controller serial port (SPORT).
There is also a mode which allows stereo ADCs and
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–15–
PRELIMINARY TECHNICAL DATA
AD74322
REGISTER ADDRESS
15
14
13
12
R/W RES
11
10
DATA FIELD
9
8
7
6
5
4
3
2
1
0
3
2
1
0
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Note: Bit 15 = MSB
Figure <ContPortMap>
REGISTER ADDRESS
R/W
RES
11
10
DATA FIELD
15
14
13
12
9
8
7
6
5
4
0
0
0
0
Power Settings
0
0
0
1
Clock Dividers
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
ADC0 Gain Setting
0
1
0
1
1
ADC0 Peak Level
0
1
1
0
0
ADC1 Gain Setting
0
1
1
0
1
ADC1 Peak Level
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
DAC0 Gain Setting
1
0
1
1
DAC1 Gain Setting
1
1
0
0
Reserved
1
1
0
1
Reserved
1
1
1
0
REF Trim Control
1
1
1
1
Test Mode Control
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Serial Port Control
Mute Control
Input/O utput Configuration
Reserved
Reserved
I/O Filter Select
Figure <ContRegMap>
–16–
PRELIMINARY TECHNICAL DATA
REG
ADDRESS
15 - 12
AD74322
Power Control
R/W RES
11
10
0000
RESET
PURA
PUR
PUD1
PUD0
PUA3
PUA2
PUA1
PUA0
PU
9
8
7
6
5
4
3
2
1
0
Software
Reset
Power
Up
Reference
Amplifier
Power
Up
Reference
Power
Up
DAC1
Power
Up
DAC0
Power
Up
ADC3
Power
Up
ADC2
Power
Up
ADC1
Power
Up
ADC0
Global
Power
Up
Table <MCLK_Divider>
REG
ADDRESS
15 - 12
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Clock Dividers
R/W RES
Reserved
11
10
0000
9
8
7
BCD2-0
6
5
4
MCD2-0
3
2
Bit Clock Divider
1
0
Master Clock Divider
Serial Interface Control
REG
ADDRESS
15 - 12
R/W RES
11
10
0000
DSTDME
TPOS2
TPOS1
TPOS0
DDF1
DDF0
ADF1
ADF0
DSMM
DSMS
9
8
7
6
5
4
3
2
1
0
TDM
Mode
Enable
TDM
Mode
Position
2
TDM
Mode
Position
1
TDM
Mode
Position
0
DAC
Data
Format 2
DAC
Data
Format 2
ADC
Data
Format 2
ADC
Data
Format 1
Mixed-Mode
Enable
Master/
Slave
Mode
Mute Control
REG
ADDRESS
15 - 12
0000
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R/W RES
DWW1 DWW0
11
10
AWW1
AWW0
DMUTE1
DMUTE0
-
-
AMUTE1
AMUTE0
9
8
7
6
5
4
3
2
1
0
DAC
Word
Width 1
DAC
Word
Width 0
ADC
Word
Width 1
ADC
Word
Width 0
Mute
DAC 1
Mute
DAC 0
Reserved
Reserved
Mute
ADC 1
Mute
ADC 0
–17–
PRELIMINARY TECHNICAL DATA
AD74322
ADC Configuration
REG
ADDRESS
R/W
15 - 12
11
RES
10
0111
R/W
15 - 12
11
0001
0
DSLB
ALB1
ALB0
INV1
INV0
SEE1
SEE0
9
8
7
6
5
4
3
2
1
0
ADC
Peak
Level
Reading
Reserved
Digital
Loopback
Data
SPORT
Loopback
Analog
Loopback
Ch1
Analog
Loopback
Ch0
Invert
ADC1
Inputs
Invert
ADC0
Inputs
ADC1 in
Single
Ended
Mode
ADC0 in
Single
Ended
Mode
1
0
A0G1
A0G0
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A0G9- 0
10
9
8
7
6
5
4
3
2
Reserved
A0P9
ADC0 Peak Readback
A0P0
ADC1 Gain Setting/Peak Readback
REG
ADDRESS
R/W
15 - 12
11
0001
0
RES
A1G9- 0
10
9
8
7
6
5
4
3
2
Reserved
1
0101
DLB
RES
1
15 - 12
RES
ADC0 Gain Setting/Peak Readback
REG
ADDRESS
REG
ADDRESS
PEAKE
A1P9
1
0
A1G1
A1G0
ADC1 Peak Readback
A0P0
DAC0 Gain Setting
R/W RES
D0G9-0
11
10
9
8
7
6
D0G9
5
4
DAC0 Gain Setting
–18–
3
2
1
0
D0G0
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PRELIMINARY TECHNICAL DATA
REG
ADDRESS
15 - 12
DAC1 Gain Setting
R/W RES
D1G9-0
11
10
0110
REG
ADDRESS
15 - 12
15 - 12
0000
Pr D
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9
8
7
6
5
D1G9
4
3
2
1
DAC1 Gain Setting
0
D1G0
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Trim Control
R/W RES
11
10
0000
REG
ADDRESS
AD74322
BMF
LTE
9
8
Blow
Master
Fuse
Link
Trim
Enable
LT3-0
7
6
5
4
3
Link Trim
ST3-0
2
1
0
Software Trim
Test Mode Control
R/W RES
TME1-0
11
10
9
DI3-0
8
Test Mode Control
7
6
AI3-0
5
DAC Current Settings
–19–
4
3
2
1
ADC Current Settings
0
AD74322
PRELIMINARY TECHNICAL DATA
OUTLINE DIMENSIONS (STYLE: outline hd)
00000000
Dimensions shown in inches and (mm). (STYLE: outline sub)
PRINTED IN U.S.A.
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–20–
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