ANALOG DEVICES HighResolution l+Bit andHoldAmplifier Sample FEATURES t10V min lnput/Output Range 50ns Aperture Delay 0.5nsApertureJitter 6ps SettlingTime t0.001% Max Gain LinearityError Completewith Input Buffer APPLICATIONS Trackand Hold PeakMeasurementSystems Data Acquisition Systems Simultaneous Sample-and-Hold GENERAL DESCRIPTION The SHA1144 is a fast sample-holdamplifier module with ac curacy and dynamic performance appropriatefor applications "sample" with fast 14-bit A/D converters.In the mode, it acrs as a fast amplifier, tracking the input signal. When switched to "hold" mode, the output is held at a level corresponding the to the input signal voltage at t}le instant of switching. The "hold" droop rate in is appropriate to allow accurate conversion by 14-bit A/D converters having conversion times of up to 150trrs. DYNAMIC PERFORMANCE The SHA1144wasdesignedto be compatiblewith fast 14-bit A/D converters suchasthe AnalogDevices'ADC1130and ADC1131series,which convert14 bits in 25gsand 129s,respectively.Maximum acquisitiontime of 8trrsfor the SHA1144 permits high samplingrates for 14-bit conversions.The SHA1144is guaranteed to havea maximumgainnonlinearity of 10.0017o of full scaleto insure1/2LSBaccuracyin 14-bit systems. Whenin the "hold" mode,the droop rate is LpVltrrs, so the SHA1144will hold an input signalto 10.003%of full scale(20V p-p) for over60oprs. PRINCIPLEOF OPERATION The SHA1144consistsbasicallyof two high speedoperational amplifiers,a storagecapacitor,and a digitally controlled modulesin one switch. It differs from typical sample-and-hold important respectiapplicationversatility.The user completes the SHA1144feedbackcircuit externalto the module.Therefore, the module may be usedin invertingor noninvertingconfigurationsand can easilybe arrangedto providecircuit gain of more than uniry to simplifysignalconditioningin a subsystem. Information furnished by Anatog Devices is believed to be accurate a n d r e l i a b l e . H o h r e v e r .n o r e s p o n s i b i l i t y i s a s s u m e db y A n a l o g D e v i c e s f o r i t s u s e ; n o r f o r a n y i n f r i n g e m e n t so f p a t e n t s o r o t h e r r i g h t s o f t h i r d p a r t i e s w h i c h m a y r e s u l t f r o m i t s u s e . N o l i c e r t s ei s g r a n r e d b y i m p l i c a tion or otherwise under anv or riohts Analoo Devices. FEEDBACK CONNECTIONS A block diagramof the SHA1144 is shownin Figure 1. The input sectionactsas a voltage-to-current converter,providingthe current neededto chargethe "hold" capacitor.The output amplifier isolatesthe "hold" capacitorand provideslow output impedancefor driving the load. Sincefeedbackis not hardwired in the module,both invertingand noninvertinginput terminalsare available,and the SHAl144 can be connectedas a follower with unity gain or potentiometricgain,as well as inverteror evena differentialamplifier. Sincethe unity gain follower mode will be the most frequent application,performancedata listed in the specificationtable is basedon this operating mode. .15V ANALOG GROUND +l5v +INPUT -INPUT MODE CONTROL DIGITAL GROUND Figure l. Block Diagram- SHAI144 =+1v/v SPFCIFICATI0NS ,*o,rr,r.ru'rl and nominatsuppty vottases unress ealn .therwise noted) MODEL SHA1144 ACCURACY Gain Gain Error Gain Nonlinearity Gain TemperatureCoefficient(0 to +7OoC) +IY/Y 10.0057o 10.0005 7o(10.001 %omax) +1ppm/oC (+2ppm/oC max) INPUT CHARACTERISTICS Input Voltage Range Impedance Bias Current Initial Offset Voltage Offset vs. Temperature (0 to +7ooC) 0,5nA max Adjustableto Zero t3opV/oC max OUTPUT CHARACTERISTICS Voltage Current Resistance Capacitive load Noise @ 100kHz Bandwidth @ lMHz Bandwidth + 1 0 Vm i n t20mA min <1Q 35 o p F 70pV p-p 1 7 5 9 Vp a +10v 1011 o ll lopF SAMPLEMODE DYNAMICS FrequencyResponse Small Signal(-3dB) Full Power Slew Rate SAMPLE.TO-HOLDSWITCHING Aperture Delay Time Aperture Uncertainty Offset Step Offset Nonlinearity SwitchingTransient Amplitude SettlingTime to 1O.OO3% HOLD MODE DYNAMICS Droop Rate Variation with Temperature Feedthrough(for 20V p-p Input @ lkHz) HOLD-TO-SAMPLESWITCHING AcquisitionTime to t0.0037o (20V Step) (10V Step) !O.017o (20V Srep) (10V Step) DIGITAL INPUT SampleMode (Logic "1") Hold Mode (Logic "0") POWERREQUIREDI lMHz 50kHz 3Y/1ts 5Ons 0.5ns 1mV 16OpV subject to change without L pV/ tts(2 ttY/ ttsmax) doubleevery+1OoC -80dB 6ps (8psmax) 5ps 5ps 4tts +2V(Logic "1" (+5.5V @ 15nA max 0V(Logic "0" (+0.8V @ 5pA (20pA max) 0 to +70oC -55oc to +85oc norice. sHA1144 I I _@ Lo.z | I,l#1" u," rs-ot) BOTTOM V|EW +i 1. 2. 3. 4. 5. 6. TRIM TRIM +INPUT -INPUT TRIM +15V | | FGR|D0.l (2.5) 7. ANALOG GROUND 8. -15V 9. ANALOG OUTPUT 10. MODE CONTROL 11. DIGITALGROUND OFFSETZERO ADJUST (oPTroNAL) 5OmV 1ps I Recommended Power Supply ADI Model 902-2, !15V @ rlOOmA output. Specifications F-2.o1sMAx(sr.rs)--*| PIN DESIGNATIONS +lsV !3o/o@ 6OmA -L5Y !3o1o@ 45mA TEMPERATURERANGE Operating Storage OUTLINE DIMENSIONS Dimensionsshownin inchesand (mm). rOFFSET ZERO f ADJUST r -->t i ' r i I 10ka Figure2 showsfeedbackconnectionsto the SHA1144 for the unity gain follower mode. Output (pin 9) is connectedto input (pin 4). Input signalis appliedto pin 3. ANALOG INPUT/OUTPUT SIGNALS P I N9 SHA11tl4 MODE MODE -15V CONTROL SHAI'|'|4 MODECONTROL INPUT 1 ^ Figure 2. Unity Gain Follower o.rl*ro '"lllflyo Figure 3 showsfeedbackconnectionsfor noninvertingoperationwith potentiomeuic gain.Whenthe indicatedvalues areinstalled,gain will be +5. As in all operationalamplifiers, gain-bandwidthproduct is a constanrfor a givensample-andhold. Effective 3dB bandwidthwill be inverselyproportional to gain. Figure 4. Aperture Uncertainty The maximum allowableslewrate will thus equalthe quotient of the maximum allowablevolrageuncertainty and the 0.5ns apertureuncertainty. For sinewaveinputs, the corresponding maximum frequencyis expressedby: Rl lk ^ - f-o= n F 1 C#;) ( T^r) - n F = 3 . 1 8 x 1 0 6, r r - ; , where: AE = the allowablevoltageuncertainty ErS = the sinewavemagnitude Figure 3. Noninverting For a systemcontaininga SHA1144 and a 14-bit A/D with +10V input signalsand an allowableinput uncertainryof tll?LSB (!62OpY), the maximum allowablesignalfrequency will be 19.7kH2. Operation By using conventional operational amplifier feedback connections, the SHA1144 can be connected for use as an inverter, with various gains (as determined by the Rp/R1 ratio), or as a differential amplifier. DATA ACQUISITION APPLICATION Successive-approximation A/D converters can generate zubstantid linearity errors if the analog input varies during the period of conversion; even the fast 14-bit models available cannot tolerate input signal frequencies ofgreater than a few Hz. For this reason, sample-and-hold amplifiers like the SHA1l44 are connected berween the A/D and its signal source to hold the analog input constant during conversion. When the SHAl144 is connected to an A/D, its aperture time uncertainty, rather than the A/D's conversion time, is the factor which limits the allowable input signal frequency. The SHAl144, with a typical aperture delay time of 50ns and an uncertainty of O.Sns,will change from the sample mode to the hold mode 50 to 50.5ns after the "1" to "0" transition of the mode control input. If the system timing is so arranged as to initiate the mode conuol signal 50ns early, then switching will actually occur within 0.5ns of the desired time as shown below. POWERSUPPLYAND GROUNDING CONNECTIONS The proper power supply and groundingconnectionsare shown shown below in Figure 5. TO DIGITAL LOGIC Figure 5. Power Supply and Grounding Connections The t15V power suppliesmusr be externally bypassedas shown. The capacitorsshould be tantalum types and should be installed as closeto the module pins aspossible.The analogand digital ground lines should be run separatelyto their respectivepower supply commonsto prevenrcouplingof digital switching noise to the sensitiveanalogcircuit section. -3- OPERATIONWITH AN A/D AND MULTIPLEXER The subsystemof Figure9 may alsobe connectedto a multiplexer like the Harris HI508A asshown below. OPERATION WITH AN A/D CONVERTER Figure 6 below shows the appropriate connections between the SHA1144 and a successiveapproximation A/D converrer in block diagram form. 'l CHANNEL 1 INPUT sHAl 144 INPUT o,o,,o. OUTPUT MODE CONTROL OUTPUT -J CHANNEL 6 CONVERT COMMAND CONVEFT Figure 6. SHAI144 and A/D Connections INPUT The resultingtiming sequenceat the start of conversionis illustrated in Figure 7. sHAl 144 MOOE STFTUSOUTPUT/ MOOE CONTROL INPUT MPX Connections The leading edge of the convert command pulse sets the "0" STATUS output to Logic thereby switching the SHAl144 "1" "hold"; to the correspondingchange to Logic of the STATUS output increments the binary counter and changes the multiplexer address.Since the SHA1144's aperture time is small with respect to the multiplexer switching time, it will have switched to the hold mode before the multiplexer actually changes channels. The multiplexer switching transients "sample" will settle out long before the SHA returns to at the end of conversion. The timing sequence described above is illustrated in Figure 10. sHA1144 INPUT OUTPUT SIGNALS CONVERT CoMMAND Figure 9. A/D, SHA,and 'I o 1 n SWITCHING TRANSIENT SETTLING - lai Figure 7. A/D and SHA Timing at Start of Conversion Note that the leading edge of the convert command pulse causes the converter's STATUS output to go to Logic "0" which in turn switches the SHAl144 from sample to hold. As discussed previously, the typical SHA1144 actually changesmodes 50 "1." to "O" to 50.5ns after the transition of the mode control input. This mode switching causesa transient on the output terminal which decays to within 0.0037o of the final value in approximately ltrts. Once the transient has settled, the convert command input is returned to Logic "0" and the conversion proceeds. As shown in Figure 8, the STATUS signal returns "l" to Logic and the SHAl144 returns to the sample mode at the end of conversion. Within 6gs, it will have acquired the input signal to O.0O37o accuracy and a new conversion cycle may be started. 33ill'^lt ffiooJ,'#I1".u, r,YlJlll,:*" +10v MULTIPLEXER OUTPUT/ SHA INPUT OV _10v SH41144MODE +10v SHA OUTPUT/ ilD TNPUT -l 0v MNEL gEtTG Figure 10. A/D, SHA, and MPX Timing sHAl 144 INPUT/ OUTPUT SIGNALS This method of sequencing the multiplexer may be altered to permit random addressing or addressing in a preset pattern. The timing of the multiplexer address changes may also be altered but corisideration should be given to the effects of feedthrough in the SHA1144. Feedthrough is the coupling of analog input signals to the output terminal while the SHA is "hold". in Large multiplexer switching transients occuring during A/D conversion may introduce an error. MODE SHA114/t SfFfu-S ourPUT/ l MODECONTROL U INPUT Figure 8. A/D and SHA Timing at End of Conversion -L- may be removed and the SHA MODE CONTROL may be driven in accordance with the option chart. GENERAL DESCRIPTION High resolution,high speeddata acquisitiondemandsthat considerablethought be givento wiring connections,evenwhen simply evaluatingthe unit in a temporarylaboratory bench set-up.To assistwith suchevaluations,an AC1580 is available. This'4 ll2" X 6" printed circuit card hassocketsthat allow a SHA1144and ADCL130or ADC1131to be pluggeddirectly onto it. It alsohasprovisionsfor two optional Harris HI508A multiplexers.This card includesgain and offset adjustment potentiometersand power supply bypasscapacitors.It mates with a Cinch25L-22-3o-t6o(or equivalent)edgeconnector (P1) and Cinch25146-30-160(or equivalent)edgeconnector (P2) which are suppliedwith every card. Offset C,alibration For the 0 to +10V unipolar range set the input voltage precisely to +0.0003V. Adjust the zero potentiometer until the converter isjust on the verge of switching from 00. . . . . O to00.....1. For the +5V bipolar range, set the input voltage precisely to 4.9997Y; for t10V units set it to -9.9994V. Adjust the zero potentiometer until offset binary coded units are just on the v e r g eo f s w i t c h i n g f r o m 0 0 . . . . . 0 t o 0 0 . . . . . L a n d t w o ' s complement coded units are just on the verge of switching f r o m1 0 0 . . . . 0 t o 1 0 0 . . . . . 1 . To usethe AC158O,programas shown in the wiring chart of Table 1, by installingthe appropriatejumpers.An outline drawingand schematicare providedfor reference. Gain C-alibration Set the input voltage preciselyto +9.9991Y for 0 to +10V units. +4.999lV for 15V units or +9.9982Y for ilOV units. Note that these values are 1 1/2LSB's less than the nominal full scale. Adjust the gain potentiometer until binary and offset binary coded units are just on the verge of switching from 11 . . . . 0to 11 ... . 1 andtwo'scomplementcodedunits a r ej u s t o n t h e v e r g e o f s w i t c h i n gf r o m 0 1 1 . . . 1 0 t o 0 1 1 . . . 1 1 . C-alibration Procedure Setup the SHAl144 for the desiredgainper the wiring chart of Table 1. Short W9 which drivesthe SHA MODE CONTROL with the STATUS of the ADC. Calibrateoffset and gain in the mannerdescribedbelow. When calibrationis completedW9 P,I sHoRT ,, CYCLE " R CLOCKOUIPUT Y P CIOCK INPUT stT 14 (Lsa) 3 V CONVERTCOMMAND SrAntg stT 13 2 Z STATUS BIT T2 N S SERIALOUTPUT B I T1 1 M 15 OIGITALGND +5V atT 10 L T A I T 9 K 17 +15V BITS J 16 -15V 20 GNDSENSE B I T T H Rvv3 B I T 6 F B I T S E m w3 B I T 4 D -o I I nwo! s t T 3 c rE .* I w DIGITAL GND MOOE CONTROL 16 -15V 17 +15V MSE t BIT2 B stT | (Mss, A R1 a). tk I R2 100k GAIN R3 1ook OFFSET P2 6 ANALOG INPUT -15V il;.r___r r-f Pl w13^----l-J Ht8 wtlHlg A INCH 1 B INCH 2 c tNcH 3 D INCH 4 E INCH 5 F INCH 6 H INCH 7 J INCH 8 MUX ADONESS MUX AODFESS MUX AOORESS MUX ADORESS ( L M N I 10 ll 12 tNcH I INCHlO INCHll INCH12 rNCH13 t Nc H 1 4 tNcH t5 tN cH 16 +15V Figure | 1. Schematicand Pin Designations -5- 5 ANALoGGND ANALOGINPUT ANALoGGND A to D Converter Options OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 2'02151'31--+l Range Jumpers J u m p e rW 1 1 Jumper Wl1 and Jumper G to F on Board JumperW10 and Jumper G to F on Board 0V to 10V 15V t10v SHA Options o o SHA Unity Gain (+1) SHA with Gainl'3 Jumper W1 and Jumper W7 Jumper WL and Install RW4 and RW7 in W4 and W7 Locations3 Jumper W2 and Jumper W5 and Install RW3 and RW7 in W3 and W7 Locations3 SHA as an Inverter2'3 o o SHA Mode Control o o Internal (Driven from Status of the ADC) JumperW9 External (Apply External Signal to Pin 9 of ConnectorP1) JumPerW8 lw9 Multiplexer Option When UsingMultiplexers Jumper W16 INPUT OPTIONS Inputs Analog Input Analog Ground From Connector P1 From Connector P2 JumPerW12 Jumper Wl5 Jumper W13 Jumper W14 NOTES t c = 1 + fRW7 f+ ^' c = - f RW7 fit 3SeeFigure11 for appropriategainsettingresistorlocations (RW3,RW4,Rw7) NOTES 1. pl rs crNcH coNN€cToR TYPE251.22.30.rm. TYP€251'6.30-1il. 2. p2 rs crNcHcoNNECTOB Table 1. Option Chart Figure 12. AC158O Mounting Board "ON"ChannelI I 2 a + 5 6 1 8 9 10 11 L2 13 I4 15 r6 2 3 4 "0" L= TTL Logic L L L L (oV<"0"(+0.8V) H L L L L H L L H=TTLLogic"l" H H L L H L L l ( + 2 V = < " 1 " ( + 5 . 5 V ) H L H L H H L L H H H L L L L H L L H H L H L H L H H H H L L H H L H H H H L H H H H H Table 2. Multiplexer -6- Address