HD74LS83A 4-bit Binary Full Adder (with Fast Carry) REJ03D0420–0200 Rev.2.00 Feb.18.2005 This improved full adder performs the addition of two 4-bit binary numbers. The sum (Σ) outputs are provided for each bit and the resultant carry (C4) is obtained from the fourth bit. This adder features full internal look ahead across all four bit generating the carry term in ten nanoseconds typically. This provides the system designer with partial lookahead performance at the economy and reduced package count of a ripple-carry implementation. Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LS83AP DILP-16 pin PRDP0016AE-B (DP-16FV) P — Note: Please consult the sales office for the above package availability. Pin Arrangement A4 1 16 B4 Σ3 2 Σ3 Σ4 15 Σ4 A3 3 A3 C4 14 C4 B3 4 B3 C0 13 C0 VCC 5 12 GND Σ2 6 Σ2 B1 11 B1 B2 7 B2 A1 10 A1 A2 8 9 Σ1 A4 B4 A2 Σ1 (Top view) Rev.2.00, Feb.18.2005, page 1 of 7 HD74LS83A Function Table Input A1 B1 When C0 = L A2 A3 Σ1 B2 B3 A4 Σ2 Σ3 B4 L H L H L H L H L H L H L L H H L L H H L L H H L L L L H H H H L L L L L L L L L L L L H H H H L H H L L H H L L H H L L L L H H H H L H H H L L H L L H H H H L H L L Output When C0 = H When C2 = L C2 Σ1 Σ2 Σ4 C4 Σ3 L H L L L L L H L H L L L L H H L H L L L L H H H H H L L H H H H L L L H L L L L H When C2 = H C2 Σ4 C4 L L L L L H H H L H H H H H L H H H H L H L H H H H H H L H H H H H H; high level, L; low level, X; irrelevant Note: Input conditions at A1, B1, A2, B2, and C0 are used to determine outputs Σ1 and Σ2 and the value of the internal carry C2. The value at C2, A3, B3, A4, and B4 are than used to determine outputs Σ3, Σ4 and C4. Rev.2.00, Feb.18.2005, page 2 of 7 HD74LS83A Block Diagram C4 B4 A4 Σ4 B3 A3 Σ3 B2 Σ2 A2 B1 Σ1 A1 C0 Absolute Maximum Ratings Item Supply voltage Input voltage Power dissipation Storage temperature Symbol VCC VIN PT Tstg Ratings 7 7 400 –65 to +150 Unit V V mW °C Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Recommended Operating Conditions Item Supply voltage Output current Operating temperature Rev.2.00, Feb.18.2005, page 3 of 7 Symbol VCC IOH IOL Topr Min 4.75 — — Typ 5.00 — — Max 5.25 –400 8 Unit V µA mA –20 25 75 °C HD74LS83A Electrical Characteristics (Ta = –20 to +75 °C) Item Input voltage Symbol VIH VIL VOH Output voltage VOL Input current except C0 C0 except C0 C0 except C0 C0 Short-circuit output current Supply current IIH IIL II IOS ICC Input clamp voltage VIR Note: * VCC = 5 V, Ta = 25°C min. 2.0 — 2.7 typ.* — — — max. — 0.8 — — — — — — — — — — — — — — — — — 0.4 0.5 40 20 –0.8 –0.4 0.2 0.1 –20 — –100 — 22 39 Unit V V V V Condition VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 µA IOL = 4 mA VCC = 4.75 V, VIH = 2 V, V IL = 0.8 V IOL = 8 mA µA VCC = 5.25 V, VI = 2.7 V mA VCC = 5.25 V, VI = 0.4 V mA VCC = 5.25 V, VI = 7 V mA VCC = 5.25 V All inputs = 0 V mA — 19 34 — 19 34 — — –1.5 Inputs Outputs CO Σ1 Ai, Bi Σ1 V B input = 0.8 V, Other inputs 4.5 V All inputs = 4.5 V VCC = 5.25 V VCC = 4.75 V, IIN = –18 mA Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Propagation delay time Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Rev.2.00, Feb.18.2005, page 4 of 7 CO C4 Ai, Bi C4 min. — — typ. 16 15 max. 24 24 — — 15 15 24 24 — — — — 11 15 11 12 17 22 17 17 Unit Condition ns CL = 15 pF, RL = 2 kΩ HD74LS83A Testing Method Test Circuit VCC Output 4.5V RL Load circuit 1 C4 CL A4 B4 Input See Testing Table P.G. Zout = 50Ω Output A3 Σ4 B3 A2 Σ3 B2 Same as Load Circuit 1. Output A1 Σ1 B2 Same as Load Circuit 1. Output C0 Notes: Same as Load Circuit 1. Output Σ1 Same as Load Circuit 1. 1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H). Waveform tTHL tTLH 90% 1.3 V Input 3V 90% 1.3 V 10% 10% 0V tPHL tPLH VOH In phase output 1.3 V 1.3 V VOL tPHL tPLH VOH Out of phase output 1.3 V 1.3 V VOL Note: Input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle = 50% Rev.2.00, Feb.18.2005, page 5 of 7 HD74LS83A Testing Table Item From input to output CO → Σi or C4 tPLH tPHL Ai or Bi → Σi or C4 B4 GND GND A4 GND GND B3 GND GND A3 GND 4.5 v Input B2 GND GND A2 GND 4.5 v GND GND GND GND GND GND GND GND GND GND GND IN GND GND GND IN IN GND GND IN IN GND GND GND GND GND C4 — OUT Σ4 — OUT GND — — — — OUT GND GND — — — OUT — GND GND GND — — OUT — — GND GND GND GND — OUT — — — GND GND 4.5 v IN IN 4.5 v GND — — — OUT OUT GND 4.5 v IN IN 4.5 v GND GND GND — — OUT OUT — 4.5 v IN IN 4.5 v GND GND GND GND GND — OUT OUT — — GND GND GND GND GND GND GND OUT OUT — — — A1 GND 4.5 v IN GND IN GND GND GND GND GND GND GND GND GND GND GND GND 4.5 v IN IN 4.5 v Rev.2.00, Feb.18.2005, page 6 of 7 Output Σ3 Σ2 — — OUT OUT C0 IN IN B1 GND GND GND IN Σ1 OUT OUT HD74LS83A Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B MASS[Typ.] 1.05g Previous Code DP-16FV D 9 E 16 1 8 b3 0.89 Z A1 A Reference Symbol L e e bp Dimension in Millimeters Min D 19.2 E 6.3 A θ c e1 A1 0.51 b p 0.40 b 3 20.32 7.4 0.48 0.56 1.30 c 0.19 θ 0° e 2.29 L Max 5.06 Z ( Ni/Pd/Au plating ) Rev.2.00, Feb.18.2005, page 7 of 7 Nom 7.62 1 0.25 0.31 2.54 2.79 15° 1.12 2.54 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 © 2005. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .2.0