HD74LS375 Quadruple Bistable Latches REJ03D0484–0200 Rev.2.00 Feb.18.2005 The HD74LS375 bistable latch is electrically and functionally identical to the HD74LS75, respectively. Only the arrangement of the terminals has been changed in the HD74LS375. This latch is ideally suited for use as temporary storage for binary information between processing units and input / output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable (G) is high and the Q output will follow the data input as long as the enable remains high. When the enable goes low, the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the enable goes high. Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LS375P DILP-16 pin PRDP0016AE-B (DP-16FV) P — PRSP0016DH-B FP (FP-16DAV) Note: Please consult the sales office for the above package availability. HD74LS375FPEL SOP-16 pin (JEITA) EL (2,000 pcs/reel) Pin Arrangement 1D 1 1Q 2 Q D 1Q 3 Q G Enable 1-2 4 2Q 5 Q G 2Q 6 Q D 2D 7 GND 8 16 VCC 15 4D D Q 14 4Q G Q 13 4Q 12 Enable 3-4 G Q 11 3Q D Q 10 3Q 9 3D (Top view) Rev.2.00, Feb.18.2005, page 1 of 5 HD74LS375 Function Table Inputs Outputs D L H X G H H L Q H L Q0 Q L H Q0 Notes: H; high level, L; low level, X; irrelevant Q0; level of Q before the indicated steady state input conditions were established Q0; complement of Q0 or level of Q before the indicated steady state input conditions were established Block Diagram (1/4) Q Data Q To Other Latch Enable Absolute Maximum Ratings Symbol Ratings Unit Supply voltage Item VCC 7 V Input voltage VIN 7 V Power dissipation PT 400 mW Tstg –65 to +150 °C Storage temperature Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Recommended Operating Conditions Item Supply voltage Output current Symbol Min Typ Max Unit VCC 4.75 5.00 5.25 V IOH — — –400 µA IOL — — 8 mA Topr –20 25 75 °C Enable input pulse width tw 20 — — ns Setup time tsu 20 — — ns Hold time th 5 — — ns Operating temperature Rev.2.00, Feb.18.2005, page 2 of 5 HD74LS375 Electrical Characteristics (Ta = –20 to +75 °C) Item Input voltage Symbol VIH VIL min. 2.0 — typ.* — — max. — 0.8 Unit V V VOH 2.7 — — V — — — — — — — — — — — — — — — — 0.4 0.5 20 80 –0.4 –1.6 0.1 0.4 Output voltage VOL IIH Input current IIL II V µA mA mA Short-circuit output current IOS –20 — –100 Supply current** ICC — 6.3 12 Input clamp voltage VIK — — –1.5 Notes: * VCC = 5 V, Ta = 25°C ** ICC is measured with all outputs open and all inputs grounded. mA mA V Condition VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 µA IOL = 4 mA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V IOL = 8 mA D G D G D G VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V VCC = 5.25 V VCC = 5.25 V VCC = 4.75 V, IIN = –18 mA Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Propagation delay time Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Rev.2.00, Feb.18.2005, page 3 of 5 Inputs Output D Q D Q G Q G Q min. — — — — — — — — typ. 15 9 12 7 15 14 16 7 max. 27 17 20 15 27 25 30 15 Unit Condition ns CL = 15 pF, RL = 2 kΩ HD74LS375 Testing Method Test Circuit VCC D G Q Q RL P.G. Zout = 50Ω D Q G Q P.G. Zout = 50Ω Notes: CL RL CL 1. Test is put into the each latch. 2. CL includes prove and jig capacitance. 3. All diodes are 1S2074(H). Waveform 1µs tTLH D 90% 1.3 V 1µs tTHL 3V 90% 1.3 V 10% 1.3 V 10% tsu th tTLH tTHL 500ns tPLH tPLH th 3V 90% 90% 1.3 V 1.3 V 10% 10% G 0V tsu 1.3 V 1.3 V 0V 500ns tPHL tPHL VOH Q 1.3 V 1.3 V VOL tPLH VOH tPLH Q 1.3 V tPHL 1.3 V VOL tPHL Notes: 1. Input pulse; D input: PRR = 500 kHz, G input: PRR = 1 MHz, tTHL ≤ 10 ns, tTLH ≤ 10 ns. 2. When measuring propagation delay times from the D input, the corresponding G input must be held high. Rev.2.00, Feb.18.2005, page 4 of 5 HD74LS375 Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B MASS[Typ.] 1.05g Previous Code DP-16FV D 9 E 16 1 8 b3 0.89 Z A1 A Reference Symbol L e Nom θ c e1 D 19.2 E 6.3 JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV 7.4 A1 0.51 b p 0.40 b 3 0.48 0.56 1.30 c 0.19 θ 0° e 2.29 0.25 0.31 2.54 2.79 15° 1.12 L 2.54 MASS[Typ.] 0.24g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D F 16 20.32 5.06 Z ( Ni/Pd/Au plating ) Max 7.62 1 A bp e Dimension in Millimeters Min 9 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) 1 Z *3 bp Nom D 10.06 E 5.50 Max 10.5 A2 8 e Dimension in Millimeters Min x A1 M 0.00 0.10 0.20 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 A L1 2.20 bp b1 c A c A1 θ y L Detail F 1 θ 0° HE 7.50 e 1.27 x 0.12 y 0.15 0.80 Z L L Rev.2.00, Feb.18.2005, page 5 of 5 8° 0.50 1 0.70 1.15 0.90 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 © 2005. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .2.0