RENESAS HD74LS77FPEL

HD74LS77
4-bit Bistable Latches
REJ03D0418–0300
Rev.3.00
Jul.22.2005
The HD74LS77 is ideally suited for use as temporary storage for binary information between processing units and
input / output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable
(G) is high and the Q output will follow the data input as long as the enable remains high. When the enable goes low,
the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the
enable is permitted to go high.
Features
• Ordering Information
Part Name
Package Type
HD74LS77FPEL
SOP-14 pin (JEITA)
Package Code
(Previous Code)
PRSP0014DF-B
(FP-14DAV)
Package
Abbreviation
Taping Abbreviation
(Quantity)
FP
EL (2,000 pcs/reel)
Pin Arrangement
1D
1
14
1Q
2
Q
D G
2D
13
2Q
Enable 3-4
3
D
12
Enable 1-2
VCC
4
11
GND
10
NC
9
3Q
8
4Q
3D
5
4D
6
NC
7
G
Q
Q
D G
D
G
Q
(Top view)
Function Table
D
Inputs
G
Outputs
Q
L
H
H
H
L
H
X
H; high level, L; low level, X; irrelevant
L
Q0
Rev.3.00, Jul.22.2005, page 1 of 4
HD74LS77
Block Diagram (1/4)
Data
Q
To Other
Latch
Enable
Absolute Maximum Ratings
Symbol
Ratings
Unit
Supply voltage
Input voltage
Item
VCC
VIN
7
7
V
V
Power dissipation
Storage temperature
PT
Tstg
400
–65 to +150
mW
°C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item
Symbol
Min
Typ
Max
Unit
VCC
IOH
4.75
—
5.00
—
5.25
–400
V
µA
IOL
Topr
—
–20
—
25
8
75
mA
°C
Pulse width
Setup time
tw
tsu
20
20
—
—
—
—
ns
ns
Hold time
th
5
—
—
ns
Supply voltage
Output current
Operating temperature
Electrical Characteristics
(Ta = –20 to +75 °C)
Item
Input voltage
Symbol
min.
typ.*
max.
Unit
VIH
VIL
2.0
—
—
—
—
0.8
V
V
VOH
2.7
—
—
V
—
—
0.4
—
—
—
—
0.5
20
—
—
—
—
80
–0.4
—
—
—
—
–1.6
0.1
—
—
0.4
IOS
–20
—
ICC
VIK
—
—
6.9
—
Output voltage
VOL
D
Input current
G
D
G
D
G
Short-circuit output
current
Supply current**
Input clamp voltage
IIH
IIL
II
V
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V,
IOH = –400 µA
IOL = 4 mA
VCC = 4.75 V, VIH = 2 V,
VIL = 0.8 V
IOL = 8 mA
µA
VCC = 5.25 V, VI = 2.7 V
mA
VCC = 5.25 V, VI = 0.4 V
mA
VCC = 5.25 V, VI = 7 V
–100
mA
VCC = 5.25 V
13
–1.5
mA
V
VCC = 5.25 V
VCC = 4.75 V, IIN = –18 mA
Notes: * VCC = 5 V, Ta = 25°C
** ICC is measured with all outputs open and all inputs grounded.
Rev.3.00, Jul.22.2005, page 2 of 4
Condition
HD74LS77
Switching Characteristics
(VCC = 5 V, Ta = 25°C)
Item
Symbol
tPLH
Inputs
Outputs
D
Q
tPHL
tPLH
Propagation delay
time
G
tPHL
min.
—
typ.
11
max.
19
—
—
9
10
17
18
—
10
18
Q
Unit
ns
Condition
CL = 15 pF,
RL = 2 kΩ
Testing Method
Test Circuit
VCC
Output
Input
RL
P.G.
Zout = 50Ω
D
Q
Input
CL
P.G.
Zout = 50Ω
Notes:
G
1. Test is put into the each latch.
2. CL includes probe and jig capacitance.
3. All diodes are 1S2074(H).
Waveform
1µs
tTLH
D
90%
1.3 V
1µs
tTHL
3V
90%
1.3 V
1.3 V
10%
10%
tsu
tTLH
th
tTHL
3V
90% 90%
1.3 V 1.3 V
10%
10%
G
0V
tsu
th
tw
1.3 V 1.3 V
0V
tw
tPLH
VOH
Q
1.3 V
tPLH
Notes:
tPHL
1.3 V
VOL
tPHL
1. Input pulse; tTLH ≤ 10 ns, tTHL ≤ 10 ns.
2. When measuring propagation delay times from the D input, the corresponding G input must be
held high.
Rev.3.00, Jul.22.2005, page 3 of 4
HD74LS77
Package Dimensions
JEITA Package Code
P-SOP14-5.5x10.06-1.27
RENESAS Code
PRSP0014DF-B
*1
Previous Code
FP-14DAV
D
MASS[Typ.]
0.23g
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
F
14
8
c
HE
*2
E
bp
Index mark
Reference
Symbol
Terminal cross section
( Ni/Pd/Au plating )
1
Z
*3
Nom
Max
D
10.06
10.5
E
5.50
A2
7
e
A1
bp
Dimension in Millimeters
Min
x
M
0.00
0.10
0.20
0.34
0.40
0.46
0.15
0.20
0.25
7.80
8.00
2.20
A
L1
bp
b1
c
A
c
A1
θ
y
L
Detail F
1
θ
0°
HE
7.50
1.27
e
x
0.12
y
0.15
Z
1.42
0.50
L
L
Rev.3.00, Jul.22.2005, page 4 of 4
8°
1
0.70
1.15
0.90
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