RENESAS HD74LVC125ATELL

HD74LVC125A
Quad. Bus Buffer Gates with 3-state Outputs
REJ03D0348–0400Z
(Previous ADE-205-108C (Z))
Rev.4.00
Jul. 23, 2004
Description
The HD74LVC125A has four bus buffer gates in a 14 pin package. The device require the three state control input C to
be taken high to put the output into the high impedance condition, whereas the device requires the control input to be
low to put the output into high impedance. Low voltage and high-speed operation is suitable at the battery drive
product (note type personal computer) and low power consumption extends the life of a battery for long time operation.
Features
•
•
•
•
•
•
•
VCC = 2.0 V to 5.5 V
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VOUT (Max.) = 5.5 V (@VCC = 0 V or output off state)
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
High output current ±24 mA (@VCC = 3.0 V to 5.5 V)
Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LVC125AFPEL
SOP–14 pin (JEITA)
FP–14DAV
FP
EL (2,000 pcs/reel)
HD74LVC125ATELL
TSSOP–14 pin
TTP–14DV
T
ELL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
C
A
Outputs Y
H
L
L
X
L
H
Z
L
H
H:
L:
X:
Z:
High level
Low level
Immaterial
High impedance
Rev.4.00 Jul. 23, 2004 page 1 of 6
HD74LVC125A
Pin Arrangement
1C 1
14 VCC
1A 2
13 4C
1Y 3
12 4A
2C 4
11 4Y
2A 5
10 3C
2Y 6
9 3A
GND 7
8 3Y
(Top view)
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage
Input diode current
Input voltage
Output diode current
VCC
IIK
VI
IOK
V
mA
V
mA
Output voltage
VO
Output current
VCC, GND current / pin
Storage temperature
IO
ICC or IGND
Tstg
–0.5 to 6.0
–50
–0.5 to 6.0
–50
50
–0.5 to VCC +0.5
–0.5 to 6.0
±50
±100
–65 to +150
V
Conditions
VI = –0.5 V
VO = –0.5 V
VO = VCC +0.5 V
Output "H" or "L"
Output "Z" or VCC:OFF
mA
mA
°C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Rev.4.00 Jul. 23, 2004 page 2 of 6
HD74LVC125A
Recommended Operating Conditions
Item
Symbol
Ratings
Unit
Conditions
Supply voltage
VCC
1.5 to 5.5
V
Data hold
V
V
At operation
C, A
Output "H" or "L"
Output "Z" or VCC:OFF
Input / output voltage
VI
VO
Operating temperature
Output current
Ta
IOH
IOL
Input rise / fall time *1
tr, tf
2.0 to 5.5
0 to 5.5
0 to VCC
0 to 5.5
–40 to 85
–12
–24*2
12
24*2
10
°C
mA
mA
VCC = 2.7 V
VCC = 3.0 V to 5.5 V
VCC = 2.7 V
VCC = 3.0 V to 5.5 V
ns/V
Notes: 1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
2. Duty cycle ≤ 50%
Electrical Characteristics
Ta = –40 to 85°C
Item
Symbol
VCC (V)
Min
Max
Unit
Input voltage
VIH
2.7 to 3.6
4.5 to 5.5
2.7 to 3.6
4.5 to 5.5
2.7 to 5.5
2.7
3.0
3.0
4.5
2.7 to 5.5
2.7
3.0
4.5
0 to 5.5
2.7 to 5.5
2.0
VCC×0.7
—
—
VCC –0.2
2.2
2.4
2.2
3.8
—
—
—
—
—
—
—
—
0.8
VCC×0.3
—
—
—
—
—
0.2
0.4
0.55
0.55
±5.0
±5.0
V
0
2.7 to 3.6
2.7 to 5.5
3.0 to 3.6
—
—
—
—
20
±10
10
500
VIL
Output voltage
VOH
VOL
Input current
Off state output current
IIN
IIOZ
Output leak current
Quiescent supply current
IOFF
ICC
∆ICC
Rev.4.00 Jul. 23, 2004 page 3 of 6
Test Conditions
V
V
IOH = –100 µA
IOH = –12 mA
IOH = –24 mA
V
IOL = 100 µA
IOL = 12 mA
IOL = 24 mA
µA
µA
VIN = 5.5 VCC GND
VIN = VCC, GND,
VOUT = 5.5 V or GND
µA
µA
VIN / VOUT = 5.5 V
VIN / VOUT = 3.6 to 5.5 V
VIN = VCC or GND
VIN = one input at (VCC –0.6) V,
other inputs at VCC or GND
µA
HD74LVC125A
Switching Characteristics
Item
Symbol
VCC (V)
Min
Ta = –40 to 85°C
Typ
Max
Unit
From
(Input)
To
(Output)
Propagation delay time
tPLH
tPHL
ns
C
Y
tHZ
tLZ
6.5
6.0
5.0
8.0
7.0
6.0
6.5
5.5
4.5
—
1.0
1.0
—
—
Y
Output disable time
—
—
—
—
—
—
—
—
—
—
—
—
3.0
15.0
A
tZH
tZL
—
1.5
—
—
1.5
—
—
1.5
—
—
—
—
—
—
ns
Output enable time
2.7
3.3±0.3
5.0±0.5
2.7
3.3±0.3
5.0±0.5
2.7
3.3±0.3
5.0±0.5
2.7
3.3±0.3
5.0±0.5
2.7
2.7
ns
C
Y
Between output pins skew *1 tOSLH
tOSHL
Input capacitance
Output capacitance
Note:
CIN
CO
ns
pF
pF
1. This parameter is characterized but not tested.
tosLH = | tPLHm - tPLHn|, tosHL = | tPHLm - tPHLn|
Test Circuit
VCC
Input
Pulse Generator
Zout = 50 Ω
See Function Table
VCC
Output
500 Ω S1
CL =
50 pF
450 Ω
50 Ω Scope
Symbol
t PLH / t PHL
t ZH/ t HZ
t ZL / t LZ
Note:
1. CL includes probe and jig capacitance.
Rev.4.00 Jul. 23, 2004 page 4 of 6
OPEN
See under table
GND
*1
S1
Vcc=2.7V,
3.3±0.3V
Vcc=5.0±0.5V
OPEN
GND
OPEN
GND
6V
2×Vcc
HD74LVC125A
Waveforms – 1
tr
tf
90 %
Vref
Input A
VIH
90 %
Vref
10 %
10 %
GND
t PHL
t PLH
VOH
Vref
Output Y
Vref
VOL
Notes:
1. tr = 2.5 ns, tf = 2.5 ns
2. Input waveform : PRR = 10 MHz, duty cycle 50%
Waveforms – 2
tf
Input C
tr
90 %
Vref
10 %
VIH
90 %
Vref
10 %
t LZ
t ZL
GND
≈V OH1
Vref
Waveform - A
t ZH
Waveform - B
VOL + 0.3 V
t HZ
VOH – 0.3 V
Vref
VOL
VOH
≈V OL1
TEST
VIH
Vref
VOH1
VOL1
Notes:
Vcc=2.7V,
3.3±0.3V
Vcc=5.0±0.5V
2.7 V
Vcc
1.5 V
3V
50%Vcc
GND
GND
Vcc
1. tr = 2.5 ns, tf = 2.5 ns
2. Input waveform : PRR = 10 MHz, duty cycle 50%
3. Waveform – A shows input conditions such that the output is "L" level when enable by the
output control.
4. Waveform – B shows input conditions such that the output is "H" level when enable by the
output control.
Rev.4.00 Jul. 23, 2004 page 5 of 6
HD74LVC125A
Package Dimensions
As of January, 2003
Unit: mm
10.06
10.5 Max
8
5.5
14
1
2.20 Max
*0.20 ± 0.05
7
1.42 Max
*0.40 ± 0.06
1.15
0˚ – 8˚
0.10 ± 0.10
1.27
0.20
7.80 +– 0.30
0.70 ± 0.20
0.15
0.12 M
Package Code
JEDEC
JEITA
Mass (reference value)
*Ni/Pd/Au plating
FP-14DAV
—
Conforms
0.23 g
As of January, 2003
Unit: mm
4.40
5.00
5.30 Max
14
8
1
7
0.65
1.0
*0.20 ± 0.05
0.13 M
6.40 ± 0.20
*Ni/Pd/Au plating
Rev.4.00 Jul. 23, 2004 page 6 of 6
0.07 +0.03
–0.04
0.10
*0.15 ± 0.05
1.10 Max
0.83 Max
0˚ – 8˚
0.50 ± 0.10
Package Code
JEDEC
JEITA
Mass (reference value)
TTP-14DV
—
—
0.05 g
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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