IS62WV20488ALL/BLL

IS62WV20488ALL
IS62WV20488BLL
2M x 8 HIGH-SPEED LOW POWER
CMOS STATIC RAM
FEATURES
• High-speed access times:
25, 35 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single power supply
– VDD 1.65V to 2.2V (IS62WV20488ALL)
speed = 35ns for Vcc = 1.65V to 2.2V
– VDD 2.4V to 3.6V (IS62WV20488BLL)
speed = 25ns for Vcc = 2.4V to 3.6V
• Packages available:
– 48-ball miniBGA (9mm x 11mm)
– 44-pin TSOP (Type II)
• Industrial Temperature Support
• Lead-free available
JANUARY 2008
DESCRIPTION
The ISSI IS62WV20488ALL/BLL is a high-speed, low
power, 2M-word by 8-bit CMOS static RAM. The
IS62WV20488ALL/BLL is fabricated using ISSI's highperformance CMOS technology. This highly reliable
process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices.
When CS1 is HIGH (deselected) or when CS2 is LOW
(deselected) or when CS1 is LOW, CS2 is HIGH, the device
assumes a standby mode at which the power dissipation
can be reduced down with CMOS input levels.
The IS62WV20488ALL/BLL operates from a single
power supply and all inputs are TTL-compatible.
The IS62WV20488ALL/BLL is available in 48 ball mini
BGA and 44-pin TSOP (Type II) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A20
DECODER
2M X 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VDD
GND
I/O0-I/O7
CS2
CS1
OE
CONTROL
CIRCUIT
WE
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
01/18/08
1
IS62WV20488ALL
IS62WV20488BLL
PIN CONFIGURATION
48-pin Mini BGA (M ) (9mm x 11mm)
1
2
3
4
5
44-pin TSOP (Type II )
6
A
NC
OE
A0
A1
A2
CS2
B
NC
NC
A3
A4
CS1
I/O0
C
NC
NC
A5
A6
I/O1
I/O2
D
GND
NC
A17
A7
I/O3
VDD
E
VDD
NC
NC
A16
I/O4
GND
F
NC
NC
A14
A15
I/O5
I/O6
G
NC
A19
A12
A13
WE
I/O7
H
A18
A8
A9
A10
A11
A20
NC
NC
A0
A1
A2
A3
A4
CS1
I/O0
I/O1
VDD
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
A20
A18
A17
A16
A15
OE
I/O7
I/O6
GND
VDD
I/O5
I/O4
A14
A13
A12
A11
A10
A19
NC
NC
PIN DESCRIPTIONS
2
A0-A20
Address Inputs
CS1, CS2
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Data Input / Output
VDD
Power
GND
Ground
NC
No Connection
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
01/18/08
IS62WV20488ALL
IS62WV20488BLL
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
WE
CS1
CS2
OE
I/O Operation
VDD Current
X
X
H
H
L
H
X
L
L
L
X
L
H
H
H
X
X
H
L
X
High-Z
ISB1, ISB2
High-Z
DOUT
DIN
ICC
ICC
ICC
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
VDD
TSTG
PT
Parameter
Terminal Voltage with Respect to GND
VDD Relates to GND
Storage Temperature
Power Dissipation
Value
–0.5 to VDD + 0.5
–0.3 to 4.0
–65 to +150
1.0
Unit
V
V
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol
Parameter
CIN
Input Capacitance
CI/O
Input/Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
01/18/08
3
IS62WV20488ALL
IS62WV20488BLL
OPERATING RANGE (VDD) (IS62WV20488ALL)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
VDD (35 nS)
1.65V-2.2V
1.65V-2.2V
OPERATING RANGE (VDD) (IS62WV20488BLL)(1)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
VDD (25 nS)
2.4V-3.6V
2.4V-3.6V
Note:
1. When operated in the range of 2.4V-3.6V, the device meets 25ns. When operated in
the range of 3.3V + 5%, the device meets 15ns.
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
01/18/08
IS62WV20488ALL
IS62WV20488BLL
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 2.4V-3.6V
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
VDD = Min., IOH = –1.0 mA
1.8
—
V
VOL
Output LOW Voltage
VDD = Min., IOL = 1.0 mA
—
0.4
V
VIH
Input HIGH Voltage
2.0
VDD + 0.3
V
VIL
Input LOW Voltage(1)
–0.3
0.8
V
ILI
Input Leakage
GND ≤ VIN ≤ VDD
–1
1
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
–1
1
µA
Note:
1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width - 2.0 ns). Not 100% tested.
VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width - 2.0 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 1.65V-2.2V
Symbol
Parameter
Test Conditions
VDD
Min.
Max.
Unit
VOH
Output HIGH Voltage
IOH = -0.1 mA
1.65-2.2V
1.4
—
V
VOL
Output LOW Voltage
IOL = 0.1 mA
1.65-2.2V
—
0.2
V
VIH
VIL(1)
Input HIGH Voltage
1.65-2.2V
1.4
VDD + 0.2
V
Input LOW Voltage
1.65-2.2V
–0.2
0.4
V
ILI
Input Leakage
GND ≤ VIN ≤ VDD
–1
1
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
–1
1
µA
Note:
1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width - 2.0 ns). Not 100% tested.
VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width - 2.0 ns). Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
01/18/08
5
IS62WV20488ALL
IS62WV20488BLL
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Test Conditions
ICC
VDD = Max.,
IOUT = 0 mA, f = fMAX
VDD Dynamic Operating
Supply Current
Min.
Com.
Ind.
typ.(2)
—
—
-25
Max.
25
30
-35
Min. Max.
—
—
20
Unit
20
25
mA
17
ICC1
Operating
Supply Current
VDD = Max.,
IOUT = 0 mA, f = 0
Com.
Ind.
—
—
10
15
—
—
10
15
mA
ISB1
TTL Standby Current
(TTL Inputs)
VDD = Max.,
Com.
VIN = VIH or VIL
Ind.
CS1 ≥ VIH, f = 0, CS2 = VIL
—
—
5
6
—
—
5
6
mA
ISB2
CMOS Standby
Current (CMOS Inputs)
VDD = Max.,
CS1 ≥ VDD – 0.2V,
CS2 ≤ 0.2V,
VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
—
—
1.5
1.5
—
—
1.5
1.5
mA
Com.
Ind.
typ.(2)
0.8
0.5
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
01/18/08
IS62WV20488ALL
IS62WV20488BLL
AC TEST CONDITIONS (LOW POWER)
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level (VRef)
Output Load
Unit
(2.4V-3.6V)
0.4V to VDD-0.3V
1.5ns
VDD/2
Unit
(1.65V-2.2V)
0.4V to VDD-0.2V
1.5ns
VDD/2
See Figures 1 and 2
See Figures 1 and 2
AC TEST LOADS
3070
3070
1.8V/3.3V
1.8V/3.3V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
3150
Figure 1
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
01/18/08
5 pF
Including
jig and
scope
3150
Figure 2
7
IS62WV20488ALL
IS62WV20488BLL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
Parameter
25ns
Min.
Max.
35ns
Min.
Max.
Unit
tRC
Read Cycle Time
25
—
35
—
ns
tAA
Address Access Time
—
25
—
35
ns
tOHA
Output Hold Time
4
—
4
—
ns
tACS1/tACS2
CS1/CS2 Access Time
—
25
—
35
ns
tDOE
OE Access Time
—
12
—
15
ns
(2)
OE to High-Z Output
—
8
—
10
ns
(2)
tLZOE
OE to Low-Z Output
5
—
5
—
ns
tHZCS1/tHZCS2(2)
CS1/CS2 to High-Z Output
0
8
0
10
ns
tLZCS1/tLZCS2(2)
CS1/CS2 to Low-Z Output
10
—
10
—
ns
tHZOE
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to VDD-0.2V/0.4V to VDD-0.3V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, CS2 = WE = VIH)
tRC
ADDRESS
tAA
tOHA
DOUT
8
PREVIOUS DATA VALID
tOHA
DATA VALID
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
01/18/08
IS62WV20488ALL
IS62WV20488BLL
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS1, CS2, OE Controlled)
tRC
ADDRESS
tAA
tOHA
OE
tDOE
CS1
tHZOE
tLZOE
tACS1/tACS2
CS2
DOUT
tLZCS1/
tLZCS2
HIGH-Z
tHZCS
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS1= VIL. CS2=WE=VIH.
3. Address is valid prior to or coincident with CS1 LOW and CS2 HIGH transition.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
01/18/08
9
IS62WV20488ALL
IS62WV20488BLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Parameter
25 ns
Min. Max.
Write Cycle Time
25
—
35
—
ns
tSCS1/tSCS2 CS1/CS2 to Write End
tAW
Address Setup Time to Write End
18
—
25
—
ns
15
—
25
—
ns
tHA
tSA
Address Hold from Write End
0
—
0
—
ns
Address Setup Time
0
—
0
—
ns
Symbol
tWC
35 ns
Min.
Max.
Unit
tPWE
tSD
WE Pulse Width
18
—
30
—
ns
Data Setup to Write End
12
—
15
—
ns
tHD
tHZWE(3)
Data Hold from Write End
0
—
0
—
ns
WE LOW to High-Z Output
—
12
—
20
ns
tLZWE(3)
WE HIGH to Low-Z Output
5
—
5
—
ns
(4)
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to VDD-0.2V/0.4V to VDD-0.3V and
output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the
write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
4. tPWE > tHZWE + tSD when OE is LOW.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OE = HIGH or LOW)
tWC
ADDRESS
tHA
tSCS1
CS1
tSCS2
CS2
tAW
tPWE
WE
tSA
DOUT
tHZWE
DATA UNDEFINED
tLZWE
HIGH-Z
tSD
DIN
10
tHD
DATA-IN VALID
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
01/18/08
IS62WV20488ALL
IS62WV20488BLL
AC WAVEFORMS
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
tWC
ADDRESS
OE
tHA
tSCS1
CS1
tSCS2
CS2
tAW
tPWE
WE
tSA
DOUT
tHZWE
tLZWE
HIGH-Z
DATA UNDEFINED
tSD
DIN
tHD
DATA-IN VALID
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
tWC
ADDRESS
OE
tHA
tSCS1
CS1
tSCS2
CS2
tAW
tPWE
WE
tSA
DOUT
DATA UNDEFINED
tHZWE
tLZWE
HIGH-Z
tSD
DIN
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
01/18/08
tHD
DATA-IN VALID
11
IS62WV20488ALL
IS62WV20488BLL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
VDR
Vcc for Data Retention
See Data Retention Waveform
1.2
IDR
Data Retention Current
Vcc = 1.2V, CS1/CS2 ≥ Vcc – 0.2V
—
tSDR
Data Retention Setup Time
See Data Retention Waveform
tRDR
Recovery Time
See Data Retention Waveform
Typ.(1) Max.
Unit
3.6
V
1.5
mA
0
—
ns
tRC
—
ns
0.5
Note:
1. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested.
DATA RETENTION WAVEFORM (CS1
CS1 Controlled)
Data Retention Mode
tSDR
3.0V
2.2V
tRDR
VCC
VDR
CS1 ≥ VCC
CS1
GND
- 0.2V
DATA RETENTION WAVEFORM (CS2 Controlled)
Data Retention Mode
3.0
VCC
CS2
2.2V
tSDR
tRDR
VDR
0.4V
CS2 ≤ 0.2V
GND
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
01/18/08
IS62WV20488ALL
IS62WV20488BLL
ORDERING INFORMATION
Industrial Range: -40°C to +85°C
Voltage Range: 2.4V to 3.6V
Speed (ns)
25
Order Part No.
Package
IS62WV20488BLL-25MI
IS62WV20488BLL-25MLI
IS62WV20488BLL-25TI
IS62WV20488BLL-25TLI
48 mini BGA (9mm x 11mm)
48 mini BGA (9mm x 11mm), Lead-free
TSOP (Type II)
TSOP (Type II), Lead-free
Industrial Range: -40°C to +85°C
Voltage Range: 1.65V to 2.2V
Speed (ns)
35
Order Part No.
Package
IS62WV20488ALL-35MI
IS62WV20488ALL-35MLI
IS62WV20488ALL-35TI
IS62WV20488ALL-35TLI
48 mini BGA (9mm x 11mm)
48 mini BGA (9mm x 11mm), Lead-free
TSOP (Type II)
TSOP (Type II), Lead-free
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
01/18/08
13
PACKAGING INFORMATION
Mini Ball Grid Array
Package Code: M (48-pin)
Top View
Bottom View
φ b (48x)
1
2
3
4
5 6
6
A
D
5
4
3
2
1
A
e
B
B
C
C
D
D
D1
E
E
F
F
G
G
H
H
e
E
E1
A2
A
SEATING PLANE
Notes:
1. Controlling dimensions are in millimeters.
A1
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
01/15/03
PACKAGING INFORMATION
Mini Ball Grid Array
Package Code: M (48-pin)
mBGA - 6mm x 8mm
MILLIMETERS
INCHES
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
48
A
—
—
1.20
.—
— 0.047
A1
0.25
—
0.40
0.010
— 0.016
A2
0.60
—
—
0.024
—
D
7.90
8.00
8.10
D1
E
0.311 0.314 0.319
5.60BSC
5.90
—
0.220BSC
6.00
6.10
0.232 0.236 0.240
E1
4.00BSC
0.157BSC
e
0.80BSC
0.031BSC
b
0.40 0.45
0.50
0.016 0.018 0.020
mBGA - 7.2mm x 8.7mm
mBGA - 9mm x 11mm
MILLIMETERS
INCHES
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
48
MILLIMETERS
INCHES
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
48
A
—
—
1.20
—
—
0.047
A
A1
0 .24
—
0.30
0.009
—
0.012
A1
A2
0.60
—
—
0.024
—
—
A2
D
8.60
8.70
8.80
0.339 0.343 0.346
D
10.90 11.00 11.10
0.429 0.433 0.437
5.25BSC
0.207BSC
7.30
0.280 0.283 0.287
E
D1
E
5.25BSC
7.10
7.20
0.207BSC
—
—
1.20
—
0.24
—
0.30
0.60
—
—
D1
8.90
9.00
9.10
—
0.047
0.009
—
0.012
0.024
—
—
0.350 0.354 0.358
E1
3.75BSC
0.148BSC
E1
3.75BSC
0.148BSC
e
0.75BSC
0.030BSC
e
0.75BSC
0.030BSC
0.012 0.014 0.016
b
b
2
0.30 0.35
0.40
0.30
0.35
0.40
0.012 0.014 0.016
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
01/15/03
PACKAGING INFORMATION
Plastic TSOP
Package Code: T (Type II)
N
N/2+1
E1
1
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the
bottom of the package.
4. Formed leads shall be planar with
respect to one another within
0.004 inches at the seating plane.
E
N/2
D
SEATING PLANE
A
ZD
.
b
e
Symbol
Ref. Std.
No. Leads
A
A1
b
C
D
E1
E
e
L
ZD
α
Millimeters
Min
Max
Inches
Min
Max
(N)
32
—
1.20
—
0.047
0.05 0.15
0.002 0.006
0.30 0.52
0.012 0.020
0.12 0.21
0.005 0.008
20.82 21.08
0.820 0.830
10.03 10.29
0.391 0.400
11.56 11.96
0.451 0.466
1.27 BSC
0.050 BSC
0.40 0.60
0.016 0.024
0.95 REF
0.037 REF
0°
5°
0°
5°
L
α
A1
Plastic TSOP (T - Type II)
Millimeters
Inches
Min
Max
Min Max
44
—
1.20
—
0.047
0.05 0.15
0.002 0.006
0.30 0.45
0.012 0.018
0.12 0.21
0.005 0.008
18.31 18.52
0.721 0.729
10.03 10.29
0.395 0.405
11.56 11.96
0.455 0.471
0.80 BSC
0.032 BSC
0.41 0.60
0.016 0.024
0.81 REF
0.032 REF
0°
5°
0°
5°
Millimeters
Min
Max
C
Inches
Min
Max
50
—
1.20
0.05 0.15
0.30 0.45
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
0.80 BSC
0.40 0.60
0.88 REF
0°
5°
—
0.047
0.002 0.006
0.012 0.018
0.005 0.008
0.820 0.830
0.395 0.405
0.455 0.471
0.031 BSC
0.016 0.024
0.035 REF
0°
5°
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
06/18/03