ISSI IS64LV25616AL

ISSI
IS64LV25616AL
256K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V SUPPLY
FEATURES
®
JULY 2006
DESCRIPTION
The ISSI IS64LV25616AL is a high-speed, 4,194,304-bit
• High-speed access time: 10, 12 ns
• CMOS low power operation
• Low stand-by power:
Less than 5 mA (typ.) CMOS stand-by
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Temperature Offerings:
Option A1: –40oC to +85oC
Option A2: –40oC to +105oC
Option A3: –40oC to +125oC
• Lead-free available
static RAM organized as 262,144 words by 16 bits. It is
fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative
circuit design techniques, yields high-performance and low
power consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS64LV25616AL is packaged in the JEDEC standard
44-pin TSOP Type II and 48-pin Mini BGA (8mm x 10mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 16
MEMORY ARRAY
VDD
GND
I/O0-I/O7
Lower Byte
I/O
DATA
CIRCUIT
I/O8-I/O15
Upper Byte
COLUMN I/O
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
07/05/06
1
ISSI
IS64LV25616AL
®
TRUTH TABLE
WE
CE
OE
LB
UB
Not Selected
X
H
X
X
X
High-Z
High-Z
ISB1, ISB2
Output Disabled
H
X
L
L
H
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
ICC
Read
H
H
H
L
L
L
L
L
L
L
H
L
H
L
L
DOUT
High-Z
DOUT
High-Z
DOUT
DOUT
I CC
Write
L
L
L
L
L
L
X
X
X
L
H
L
H
L
L
DIN
High-Z
DIN
High-Z
DIN
DIN
I CC
Mode
PIN CONFIGURATIONS
44-Pin TSOP (Type II)
A0
A1
A2
A3
A4
CE
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A5
A6
A7
A8
A9
2
I/O PIN
I/O0-I/O7
I/O8-I/O15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
VDD Current
PIN DESCRIPTIONS
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
A0-A17
Address Inputs
I/O0-I/O15
Data Inputs/Outputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
LB
Lower-byte Control (I/O0-I/O7)
UB
Upper-byte Control (I/O8-I/O15)
NC
No Connection
VDD
Power
GND
Ground
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
07/05/06
ISSI
IS64LV25616AL
PIN CONFIGURATIONS
48-Pin mini BGA
1
2
3
PIN DESCRIPTIONS
4
5
6
A0-A17
Address Inputs
I/O0-I/O15
Data Inputs/Outputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
A0
A1
A2
NC
LB
Lower-byte Control (I/O0-I/O7)
UB
A3
A4
CE
I/O0
UB
Upper-byte Control (I/O8-I/O15)
I/O9
I/O10
A5
A6
I/O1
I/O2
NC
No Connection
D
GND
I/O11
A17
A7
I/O3
VDD
VDD
Power
E
VDD
I/O12
NC
A16
I/O4
GND
GND
Ground
F
I/O14
I/O13
A14
A15
I/O5
I/O6
G
I/O15
NC
A12
A13
WE
I/O7
H
NC
A8
A9
A10
A11
NC
A
LB
OE
B
I/O8
C
®
1
2
3
4
5
6
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
07/05/06
3
ISSI
IS64LV25616AL
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
VTERM
Terminal Voltage with Respect to GND
–0.5 to VDD+0.5
V
VDD
VDD Related to GND
–0.3 to +4.0
V
TSTG
Storage Temperature
–65 to +150
°C
PT
Power Dissipation
1.0
W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
OPERATING RANGE
Options
Ambient Temperature
VDD
A1
–40°C to +85°C
3.3V +10%, -5%
A2
–40°C to +105°C
3.3V +10%, -5%
A3
–40°C to +125°C
3.3V +10%, -5%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
Test Conditions
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Options
Min.
Max.
Unit
VDD = Min., IOH = –4.0 mA
2.4
—
V
VDD = Min., IOL = 8.0 mA
—
0.4
V
Input HIGH Voltage
2.0
VDD + 0.3
V
VIL
Input LOW Voltage(1)
-0.3
0.8
V
ILI
Input Leakage
GND ≤ VIN ≤ VDD
A1
A2
A3
-2
-5
-10
2
5
10
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VDD,
Outputs Disabled
A1
A2
A3
-2
-5
-10
2
5
10
µA
Notes:
1. VIL (min.) = –2.0V for pulse width less than 10 ns.
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
07/05/06
ISSI
IS64LV25616AL
®
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Options
-10
Min. Max.
-12
Min. Max.
1
Symbol Parameter
Test Conditions
Unit
ICC
VDD Dynamic Operating
Supply Current
VDD = Max.,
IOUT = 0 mA, f = fMAX
A1
A2
A3
—
—
—
100
—
—
—
—
—
—
110
120
mA
ISB
TTL Standby Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = fMAX.
A1
A2
A3
—
—
—
50
—
—
—
—
—
—
55
60
mA
ISB1
TTL Standby Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = 0
A1
A2
A3
—
—
—
20
—
—
—
—
—
—
30
40
mA
ISB2
CMOS Standby
Current (CMOS Inputs)
VDD = Max.,
CE ≥ VDD – 0.2V,
VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
A1
A2
A3
typ(2)
—
—
—
—
15
—
—
5
—
—
—
—
—
25
35
5
mA
2
3
4
5
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. Shaded area product
in development
2. Typical values are measured at VDD = 3.3V, TA = 25oC and not 100% tested.
6
CAPACITANCE(1)
Symbol
Parameter
CIN
Input Capacitance
COUT
Input/Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
7
8
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
07/05/06
5
ISSI
IS64LV25616AL
®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
tRC
tAA
tOHA
tACE
tDOE
tHZOE(2)
tLZOE(2)
tHZCE(2
tLZCE(2)
tBA
tHZB(2)
tLZB(2)
tPU
tPD
-10
Min. Max.
Parameter
-12
Min. Max.
Unit
Read Cycle Time
10
—
12
—
ns
Address Access Time
—
10
—
12
ns
Output Hold Time
2
—
2
—
ns
CE Access Time
—
10
—
12
ns
OE Access Time
—
4
—
5
ns
OE to High-Z Output
—
4
—
5
ns
OE to Low-Z Output
0
—
0
—
ns
CE to High-Z Output
0
4
0
6
ns
CE to Low-Z Output
3
—
3
—
ns
LB, UB Access Time
—
4
—
5
ns
LB, UB to High-Z Output
0
3
0
4
ns
LB, UB to Low-Z Output
0
—
0
—
ns
Power Up Time
0
—
0
—
ns
Power Down Time
—
10
—
12
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
AC TEST LOADS
319 Ω
319 Ω
3.3V
3.3V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
353 Ω
5 pF
Including
jig and
scope
Figure 1
353 Ω
Figure 2
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing and Reference Level
Output Load
6
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
07/05/06
ISSI
IS64LV25616AL
®
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
1
t RC
2
ADDRESS
t AA
t OHA
t OHA
DOUT
3
DATA VALID
PREVIOUS DATA VALID
READ1.eps
4
READ CYCLE NO. 2(1,3)
5
tRC
ADDRESS
tAA
tOHA
6
OE
tHZOE
tDOE
CE
tLZOE
tACE
7
tHZCE
tLZCE
LB, UB
DOUT
VDD
HIGH-Z
tBA
tLZB
8
tHZB
tRC
DATA VALID
tPU
50%
Supply
Current
tPD
ICC
9
50%
ISB
UB_CEDR2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
07/05/06
7
ISSI
IS64LV25616AL
®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol
tWC
tSCE
tAW
tHA
tSA
tPBW
tPWE1
tPWE2
tSD
tHD
tHZWE(2)
tLZWE(2)
Parameter
-10
Min. Max.
-12
Min. Max.
Unit
Write Cycle Time
10
—
12
—
ns
CE to Write End
9
—
10
—
ns
Address Setup Time to Write End
8
—
8
—
ns
Address Hold from Write End
0
—
0
—
ns
Address Setup Time
0
—
0
—
ns
LB, UB Valid to End of Write
8
—
8
—
ns
WE Pulse Width
8
—
8
—
ns
WE Pulse Width (OE = LOW)
10
—
10
—
ns
Data Setup to Write End
6
—
6
—
ns
Data Hold from Write End
0
—
0
—
ns
WE LOW to High-Z Output
—
5
—
6
ns
WE HIGH to Low-Z Output
2
—
2
—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
07/05/06
ISSI
IS64LV25616AL
®
AC WAVEFORMS
WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 )
1
t WC
VALID ADDRESS
ADDRESS
t SA
t SCE
2
t HA
CE
t AW
t PWE1
t PWE2
WE
3
t PBW
UB, LB
t HZWE
DOUT
4
t LZWE
HIGH-Z
DATA UNDEFINED
t SD
t HD
5
DATAIN VALID
DIN
UB_CEWR1.eps
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of
the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
7
WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2)
8
t WC
ADDRESS
6
VALID ADDRESS
t HA
OE
CE
9
LOW
t AW
10
t PWE1
WE
t SA
t PBW
UB, LB
t HZWE
DOUT
DATA UNDEFINED
11
t LZWE
HIGH-Z
t SD
DIN
t HD
12
DATAIN VALID
UB_CEWR2.eps
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
07/05/06
9
ISSI
IS64LV25616AL
®
AC WAVEFORMS
WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1)
t WC
ADDRESS
VALID ADDRESS
OE
LOW
CE
LOW
t HA
t AW
t PWE2
WE
t SA
t PBW
UB, LB
t HZWE
DOUT
t LZWE
HIGH-Z
DATA UNDEFINED
t SD
t HD
DATAIN VALID
DIN
UB_CEWR3.eps
WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3)
t WC
ADDRESS
t WC
ADDRESS 1
ADDRESS 2
OE
t SA
CE
LOW
t HA
t SA
WE
UB, LB
t HA
t PBW
t PBW
WORD 1
WORD 2
t HZWE
DOUT
t LZWE
HIGH-Z
DATA UNDEFINED
t HD
t SD
DIN
DATAIN
VALID
t HD
t SD
DATAIN
VALID
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid
states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is referenced to the
rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
07/05/06
ISSI
IS64LV25616AL
®
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Condition
VDR
VDD for Data Retention
See Data Retention Waveform
IDR
Data Retention Current
VDD = 2.0V, CE ≥ VDD – 0.2V
tSDR
tRDR
Options
A1
A2
A3
Min.
Typ.(1)
Max.
Unit
2.0
—
3.6
V
—
—
—
5
—
—
10
15
20
mA
1
2
Data Retention Setup Time
See Data Retention Waveform
0
—
—
ns
Recovery Time
See Data Retention Waveform
tRC
—
—
ns
3
Note 1: Typical values are measured at VDD = 3.0V, TA = 25 C and not 100% tested.
O
4
DATA RETENTION WAVEFORM (CE Controlled)
5
tSDR
Data Retention Mode
tRDR
VDD
6
VDR
7
CE
GND
CE ≥ VDD - 0.2V
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
07/05/06
11
ISSI
IS64LV25616AL
®
ORDERING INFORMATION
Temperature Range (A1): –40°C to +85°C
Speed (ns)
10
Order Part No.
Package
IS64LV25616AL-10TA1
TSOP (Type II)
Temperature Range (A2): –40°C to +105°C
Speed (ns)
12
Order Part No.
Package
IS64LV25616AL-12TA2
IS64LV25616AL-12TLA2
IS64LV25616AL-12BA2
TSOP (Type II)
TSOP (Type II), Lead-free
Mini BGA (8mm x 10mm)
Temperature Range (A3): –40°C to +125°C
Speed (ns)
12
12
Order Part No.
Package
IS64LV25616AL-12TA3
IS64LV25616AL-12TLA3
IS64LV25616AL-12BA3
IS64LV25616AL-12BLA3
TSOP (Type II)
TSOP (Type II), Lead-free
Mini BGA (8mm x 10mm)
Mini BGA (8mm x 10mm), Lead-free
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
07/05/06
ISSI
®
PACKAGING INFORMATION
Mini Ball Grid Array
Package Code: B (48-pin)
Top View
Bottom View
φ b (48x)
1
2
3
4
5 6
6
A
4
3
2
1
A
e
B
B
C
C
D
D
D
5
D1
E
E
F
F
G
G
H
H
e
E
E1
A2
Notes:
1. Controlling dimensions are in millimeters.
A
A1
SEATING PLANE
mBGA - 6mm x 8mm
mBGA - 8mm x 10mm
MILLIMETERS
INCHES
MILLIMETER
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
48
Sym.
Min. Typ. Max.
N0.
Leads
48
INCHES
Min. Typ. Max.
A
—
—
1.20
—
—
0.047
A
—
—
1.20
—
—
0.047
A1
0.24
—
0.30
0.009
—
0.012
A1
0.24
—
0.30
0.009
—
0.012
A2
0.60
—
—
0.024
—
—
A2
0.60
—
—
0.024
—
—
D
7.90
—
8.10
0.311
—
0.319
D
9.90
—
10.10
0.390
—
0.398
D1
E
5.25 BSC
5.90
—
6.10
0.207 BSC
0.232
—
0.240
D1
E
5.25 BSC
7.90
—
0.207 BSC
8.10
0.311
—
0.319
E1
3.75 BSC
0.148 BSC
E1
3.75 BSC
0.148 BSC
e
0.75 BSC
0.030 BSC
e
0.75 BSC
0.030 BSC
0.012 0.014 0.016
b
b
0.30 0.35
0.40
0.30
0.35
0.40
0.012 0.014 0.016
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
01/15/03
ISSI
®
PACKAGING INFORMATION
Plastic TSOP
Package Code: T (Type II)
N
N/2+1
E1
1
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the
bottom of the package.
4. Formed leads shall be planar with
respect to one another within
0.004 inches at the seating plane.
E
N/2
D
SEATING PLANE
A
ZD
.
b
e
Symbol
Ref. Std.
No. Leads
A
A1
b
C
D
E1
E
e
L
ZD
α
Millimeters
Min
Max
Inches
Min
Max
(N)
32
—
1.20
—
0.047
0.05 0.15
0.002 0.006
0.30 0.52
0.012 0.020
0.12 0.21
0.005 0.008
20.82 21.08
0.820 0.830
10.03 10.29
0.391 0.400
11.56 11.96
0.451 0.466
1.27 BSC
0.050 BSC
0.40 0.60
0.016 0.024
0.95 REF
0.037 REF
0°
5°
0°
5°
L
α
A1
Plastic TSOP (T - Type II)
Millimeters
Inches
Min
Max
Min Max
44
—
1.20
—
0.047
0.05 0.15
0.002 0.006
0.30 0.45
0.012 0.018
0.12 0.21
0.005 0.008
18.31 18.52
0.721 0.729
10.03 10.29
0.395 0.405
11.56 11.96
0.455 0.471
0.80 BSC
0.032 BSC
0.41 0.60
0.016 0.024
0.81 REF
0.032 REF
0°
5°
0°
5°
Millimeters
Min
Max
C
Inches
Min
Max
50
—
1.20
0.05 0.15
0.30 0.45
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
0.80 BSC
0.40 0.60
0.88 REF
0°
5°
—
0.047
0.002 0.006
0.012 0.018
0.005 0.008
0.820 0.830
0.395 0.405
0.455 0.471
0.031 BSC
0.016 0.024
0.035 REF
0°
5°
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
06/18/03