IS39LV040 / IS39LV010 / IS39LV512

IS39LV040 / IS39LV010 / IS39LV512
4Mbit / 1Mbit / 512 Kbit 3.0 Volt-only CMOS Flash Memory
FEATURES
• Single Power Supply Operation
- Low voltage range: 2.70 V - 3.60 V
• Memory Organization
- IS39LV040: 512K x 8 (4 Mbit)
- IS39LV010: 128K x 8 (1 Mbit)
- IS39LV512: 64K x 8 (512 Kbit)
• High Performance Read
- 70 ns access time
• Cost Effective Sector/Block Architecture
- Uniform 4 Kbyte sectors
- Uniform 64 Kbyte blocks (sector group - except
IS39LV512)
• Data# Polling and Toggle Bit Features
• Hardware Data Protection
• Automatic Erase and Byte Program
- Build-in automatic program verification
- Typical 16 µs/byte programming time
- Typical 55 ms sector/block/chip erase time
• Low Power Consumption
- Typical 4 mA active read current
- Typical 8 mA program/erase current
- Typical 0.1 µA CMOS standby current
• High Product Endurance
-100,000 program/erase cycles per single sector
- Minimum 20 years data retention
• Industrial Standard Pin-out and Packaging
- 32-pin (8 mm x 14 mm) VSOP
- 32-pin PLCC
- Optional lead-free (Pb-free) package
• Operation temperature range
- IS39LV040/010/512
0oC~+85oC
GENERAL DESCRIPTION
The IS39LV040/010/512 are 4 Mbit / 1 Mbit / 512 Kbit 3.0 Volt-only Flash Memories. These devices are designed
to use a single low voltage, range from 2.70 Volt to 3.60 Volt, power supply to perform read, erase and program
operations. The 12.0 Volt VPP power supply for program and erase operations are not required. The devices can
be programmed in standard EPROM programmers as well.
The memory array of IS39LV512
is divided into uniform 4 Kbyte sectors for data or code storage. The memory
arrays of IS39LV010/040 are divided into uniform 4 Kbyte sectors or uniform 64 Kbyte blocks (sector group consists of sixteen adjacent sectors). The sector or block erase feature allows users to flexibly erase a memory
area as small as 4 Kbyte or as large as 64 Kbyte by one single erase operation without affecting the data in
others. The chip erase feature allows the whole memory array to be erased in one single erase operation. The
devices can be programmed on a byte-by-byte basis after performing the erase operation.
The devices have a standard
microprocessor interface as well as a JEDEC standard pin-out/command set. The
program operation is executed by issuing the program command code into command register. The internal control
logic automatically handles the programming voltage ramp-up and timing. The erase operation is executed by
block, or sector erase command code into command register. The internal control logic
issuing the chip erase,
the erase voltage ramp-up and timing. The preprogramming on the array which has not
automatically handles
been programmed is not required before an erase operation. The devices offer Data# Polling and Toggle Bit
functions, the progress or completion of program and erase operations can be detected by reading the Data#
Polling on I/O7 or the Toggle Bit on I/O6.
The IS39LV040/010/512
are manufactured on pFLASH™’s advanced nonvolatile CMOS technology. The devices
are offered in 32-pin VSOP and PLCC packages with 70 ns access time.
Integrated Silicon Solution, Inc. — www.issi.com1
Rev. B
07/29/2015
IS39LV040 / IS39LV010 / IS39LV512
A15
A16
VCC
WE#
A17
A15
A16
NC
VCC
WE#
NC
A15
NC
NC
VCC
WE#
NC
4
3
2
1
32
31
30
I S 3 9 L V 5 12
A7
A7
A7
5
A6
A6
A6
A5
A5
A5
A18
A12
A12
I S 3 9 L V 0 4 0 I S 3 9 L V 0 10
A12
I S 3 9 L V 5 12 I S 3 9 L V 0 10 I S 3 9 L V 0 4 0
CONNECTION DIAGRAMS
I S 3 9 L V 5 12 I S 3 9 L V 0 10 I S 3 9 L V 0 4 0
29
A14
A14
A14
6
28
A13
A13
A13
7
27
A8
A8
A8
A9
A9
A4
A4
A4
8
26
A9
A3
A3
A3
9
25
A11
A11
A11
24
OE#
OE#
OE#
A2
A2
A2
10
A1
A1
A1
11
23
A10
A10
A10
A0
A0
A0
12
22
CE#
CE#
CE#
13
21
I/O7
I/O7
I/O7
IS39LV512
IS39LV010
I/O4
I/O5
I/O6
I/O5
I/O6
I/O6
20
I/O4
I/O5
19
I/O3
I/O4
18
I/O3
I/O3
17
GND
GND
16
GND
I/O2
15
I/O2
I/O1
14
I/O2
IS39LV040
I S 3 9 L V 0 10
I S 3 9 L V 5 12
I/O0
I/O1
I/O0
I/O1
I/O0
32-Pin PLCC
IS39LV040 IS39LV010 IS39LV512
A11
A9
A8
A13
A14
A17
WE#
V CC
A18
A16
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
NC
WE#
V CC
NC
A16
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
NC
WE#
V CC
NC
NC
A15
A12
A7
A6
A5
A4
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE#
A10
CE#
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
OE#
A10
CE#
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
IS39LV040
OE#
A10
CE#
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
32-Pin VSOP
Integrated Silicon Solution, Inc. — www.issi.com2
Rev. B
07/29/2015
IS39LV040 / IS39LV010 / IS39LV512
PIN DESCRIPTIONS
SYMBOL
TYPE
DESCRIPTION
A0 - AMS(1)
INPUT
Address Inputs: For memory addresses input. Addresses are internally
latched on the falling edge of WE# during a write cycle.
CE#
INPUT
Chip Enable: CE# goes low activates the device’s internal circuitries for
device operation. CE# goes high deselects the device and switches into
standby mode to reduce the power consumption.
WE#
INPUT
Write Enable: Activate the device for write operation. WE# is active low.
OE#
INPUT
Output Enable: Control the device’s output buffers during a read cycle.
OE# is active low.
I/O0 - I/O7
INPUT/
OUTPUT
Data Inputs/Outputs: Input command/data during a write cycle or output
data during a read cycle. The I/O pins float to tri-state when OE# are
disabled.
VCC
Device Power Supply
GND
Ground
NC
No Connection
Note:
1.AMS is the most significant address where AMS = A15 for IS39LV512, A16 for IS39LV010, and A18 for
IS39LV040.
Integrated Silicon Solution, Inc. — www.issi.com3
Rev. B
07/29/2015
IS39LV040 / IS39LV010 / IS39LV512
BLOCK DIAGRAM
ERASE/PROGRAM
VOLTAGE
GENERATOR
I/O0-I/O7
I/ O BUF F ER S
HIGH V O L T A G E
SWITCH
WE#
COMMAND
REGISTER
C E, O E L O G I C
D AT A
LATCH
A0 - A M S
ADDRESS
LATCH
CE#
OE#
SENSE
AMP
Y-DECODER
Y-GATING
X-DECODER
MEMORY
ARRAY
DEVICE OPERATION
READ OPERATION
The access of IS39LV040/010/512 are similar to
EPROM. To read data, three control functions must
be satisfied:
• CE# is the chip enable and should be pulled low ( VIL ).
• OE# is the output enable and should be pulled low
( VIL).
• WE# is the write enable and should remains high (
VIH ).
PRODUCT IDENTIFICATION
The product identification mode can be used to identify
the manufacturer and the device through hardware or
software read ID operation. See Table 1 for pFLASH™
Manufacturer ID and Device ID. The hardware ID mode
is activated by applying a 12.0 Volt on A9 pin, typically
used by an external programmer for selecting the right
programming algorithm for the devices. Refer to Table
2 for Bus Operation Modes. The software ID mode is
activated by a three-bus-cycle command. See Table 3
for Software Command Definition.
BYTE PROGRAMMING
The programming is a four-bus-cycle operation and
the data is programmed into the devices (to a logical
“0”) on a byte-by-byte basis. See Table 3 for Software
Command Definition. A program operation is activated
by writing the three-byte command sequence followed
by program address and one byte of program data
into the devices. The addresses are latched on the
falling edge of WE# or CE# whichever occurs later,
and the data are latched on the rising edge of WE# or
CE# whichever occurs first. The internal control logic
automatically handles the internal programming voltages and timing.
A data “0” can not be programmed back to a “1”. Only
erase operation can convert the “0”s to “1”s. The Data#
Polling on I/O7 or Toggle Bit on I/O6 can be used to
detect the progress or completion of a program cycle.
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Rev. B
07/29/2015
IS39LV040 / IS39LV010 / IS39LV512
DEVICE OPERATION (CONTINUED)
CHIP ERASE
HARDWARE DATA PROTECTION
The entire memory array can be erased through a chip
erase operation. Pre-programs the devices are not
required prior to a chip erase operation. Chip erase
starts immediately after a six-bus-cycle chip erase
command sequence. All commands will be ignored
once the chip erase operation has started. The devices
will return to standby mode after the completion of chip
erase.
Hardware data protection protects the devices from unintentional erase or program operation. It is performed
in the following ways: (a) VCC sense: if VCC is below 1.8
V (typical), the write operation is inhibited. (b) Write
inhibit: holding any of the signal OE# low, CE# high, or
WE# high inhibits a write cycle. (c) Noise filter: pulses
of less than 5 ns (typical) on the WE# or CE# input will
not initiate a write operation.
SECTOR AND BLOCK ERASE
The memory array of IS39LV040/010/512 are organized
into uniform 4 Kbyte sectors. A sector erase operation
allows to erase any individual sector without affecting
the data in others. The memory array of IS39LV010/040,
excluding IS39LV512, are also organized into uniform
64 Kbyte blocks (sector group - consists of sixteen
adjacent sectors). A block erase operation allows to
erase any individual block. The sector or block erase
operation is similar to chip erase.
Table 1. Product Identification
Product Identification
Data
Manufacturer ID
9Dh
Device ID:
IS39LV040
3Eh
I/O7 DATA# POLLING
IS39LV010
1Ch
The IS39LV040/010/512 provide a Data# Polling feature to indicate the progress or completion of a program
and erase cycles. During a program cycle, an attempt
to read the devices will result in the complement of the
last loaded data on I/O7. Once the program operation
is completed, the true data of the last loaded data is
valid on all outputs. During a sector, block, or chip erase
cycle, an attempt to read the device will result a “0” on
I/O7. After the erase operation is completed, an attempt
to read the device will result a “1” on I/O7.
IS39LV512
1Bh
I/O6 TOGGLE BIT
The IS39LV040/010/512 also provide a Toggle Bit feature to detect the progress or completion of a program
and erase cycles. During a program or erase cycle, an
attempt to read data from the device will result a toggling between “1” and “0” on I/O6. When the program
or erase operation is complete, I/O6 will stop toggling
and valid data will be read. Toggle bit may be accessed
at any time during a program or erase cycle.
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Rev. B
07/29/2015
IS39LV040 / IS39LV010 / IS39LV512
SECTOR/BLOCK ADDRESS TABLE
Memory Density
Block
(1)
Block
0 (2)
512Kbit
Block
Size
(Kbytes)
64
1 Mbit
Block 1
64
4 Mbit
Sector
Sector
Size
(Kbytes)
Address Range
Sector 0
4
00000h - 00FFFh
Sector 1
4
01000h - 01FFFh
:
:
:
Sector
15
4
0F000h - 0FFFFh
Sector
16
4
10000h - 10FFFh
Sector
17
4
11000h - 11FFFh
:
:
:
Sector
31
4
1F000h - 1FFFFh
Block 2
64
“
“
20000h - 2FFFFh
Block 3
64
“
“
30000h - 3FFFFh
Block 4
64
“
“
40000h - 4FFFFh
Block 5
64
“
“
50000h - 5FFFFh
Block 6
64
“
“
60000h - 6FFFFh
Block 7
64
“
“
70000h - 7FFFFh
Notes:
1. A Block is a 64 Kbyte sector group which consists of sixteen adjecent sectors of 4 Kbyte each.
2. Block erase feature is available for IS39LV040/010 only. The chip erase command should be used to erase
the Block 0 for the IS39LV512.
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Rev. B
07/29/2015
IS39LV040 / IS39LV010 / IS39LV512
OPERATING MODES
Table 2. Bus Operation Modes
Mode
CE#
OE#
WE#
ADDRESS
I/O
Read
VIL
VIL
VIH
X (1)
DOUT
Write
VIL
VIH
VIL
X
DIN
Standby
VIH
X
X
X
High Z
X
VIH
X
X
High Z
Output Disable
Product Identification Hardware
VIL
VIL
A2 - AMS (2) = X, A9 = VH (3), A1 = VIL, A0 = VIL
Manufacturer ID
A2 - AMS (2) = X, A9 = VH (3),
A1 = VIL, A0 = VIH
Device I
VIH
Notes:
1. X can be VIL, VIH or addresses.
2.AMS = Most significant address;
AMS = A15 for IS39LV512, A16 for IS39LV010, and
A18 for IS39LV040.
3.VH = 12.0 V ± 0.5 V.
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Rev. B
07/29/2015
IS39LV040 / IS39LV010 / IS39LV512
COMMAND DEFINITION
Table 3. Software Command Definition
3rd Bus
Cycle
Addr
Data
4th Bus
Cycle
Addr Data
5th Bus
Cylce
Addr
Data
2AAh
55h
555h 80h
555h AAh
2AAh 55h
555h
10h
555h AAh
2AAh
55h
555h 80h
555h AAh
2AAh 55h
SA (1)
30h
6
555h AAh
2AAh
55h
555h 80h
555h AAh
2AAh 55h
BA (2)
50h
Byte Program
4
555h AAh
2AAh
55h
555h A0h
Addr DIN
Product ID
Entry
3
555h AAh
2AAh
55h
555h 90h
Product ID
Exit (3)
3
555h AAh
2AAh
55h
555h F0h
Product ID
Exit (3)
1
XXXh F0h
Bus
Cycle
1st Bus
Cycle
Addr Data
Read
1
Addr DOUT
Chip Erase
6
555h AAh
Sector Erase
6
Block Erase
Command
Sequence
2nd Bus
Cycle
Addr
Data
6th Bus
Cycle
Addr
Data
Notes:
1. SA = Sector address of the sector to be erased.
2. BA = Block address of the block to be erased.
3. Either one of the Product ID Exit command can be used.
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Rev. B
07/29/2015
IS39LV040 / IS39LV010 / IS39LV512
DEVICE OPERATIONS FLOWCHARTS
Start
Load Data AAh
to
Address 555h
Load Data 55h
to
Address 2AAh
Load Data A0h
to
Address 555h
Address
Increment
Load Program
Data to
Program Address
I/O7 = Data?
or
I/O6 Stop Toggle?
No
Yes
No
Last Address?
Yes
Programming
Completed
Chart 1. Automatic Programming Flowchart
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Rev. B
07/29/2015
IS39LV040 / IS39LV010 / IS39LV512
DEVICE OPERATIONS FLOWCHARTS (CONTINUED)
Start
Write Sector,
or Chip Erase
Command
No
Data = FFh?
or
I/O6 Stop Toggle?
Yes
Erasure
Completed
CHIP ERASE COMMAND
SECTOR ERASE COMMAND
BLOCK ERASE COMMAND
Load Data AAh
to
Address 555h
Load Data AAh
to
Address 555h
Load Data AAh
to
Address 555h
Load Data 55h
to
Address 2AAh
Load Data 55h
to
Address 2AAh
Load Data 55h
to
Address 2AAh
Load Data 80h
to
Address 555h
Load Data 80h
to
Address 555h
Load Data 80h
to
Address 555h
Load Data AAh
to
Address 555h
Load Data AAh
to
Address 555h
Load Data AAh
to
Address 555h
Load Data 55h
to
Address 2AAh
Load Data 55h
to
Address 2AAh
Load Data 55h
to
Address 2AAh
Load Data 10h
to
Address 555h
Load Data 30h
to
SA
Load Data 50h
to
BA
Chart 2. Automatic Erase Flowchart
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Rev. B
07/29/2015
IS39LV040 / IS39LV010 / IS39LV512
DEVICE OPERATIONS FLOWCHARTS (CONTINUED)
Load Data AAh
to
Address 555h
Load Data AAh
to
Address 555h
Load Data 55h
to
Address 2AAh
Load Data 55h
to
Address 2AAh
Load Data F0h
to
Address XXXh
or
Load Data 90h
to
Address 555h
Load Data F0h
to
Address 555h
Enter Product
Identification
Mode (1,2)
Exit Product
Identification
Mode (3)
Exit Product
Identification
Mode (3)
Notes:
1. The device will enter Product Identification mode after excuting the Product ID Entry command.
2. Under Product Identification mode, the Manufacturer ID and Device ID of devices can be read at address
X0000h and X0001h where X = Don’t Care.
3. The device returns to standby operation.
Chart 3. Software Product Identification Entry/Exit Flowchart
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Rev. B
07/29/2015
IS39LV040 / IS39LV010 / IS39LV512
ABSOLUTE MAXIMUM RATINGS (1)
Temperature Under Bias
-65°C to +125°C
Storage Temperature
Surface Mount Lead Soldering Temperature
-65°C to +125°C
240°C 3 Seconds
Input Voltage with Respect to Ground on All
Pins except A9 pin (2)
Input Voltage with Respect to Ground on A9
pin (3)
All Output Voltage with Respect to Ground
-0.5V to VCC + 0.5 V
VCC (2)
-0.5V to +6.0 V
-0.5V to +13.0 V
-0.5V to VCC + 0.5 V
Notes:
1. Stresses under those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. The functional operation of the device or
any other conditions under those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating condition for extended periods may
affected device reliability.
2. Maximum DC voltage on input or I/O pins are VCC + 0.5V. During voltage transitioning
period, input or I/O pins may overshoot to VCC + 2.0V for a period of time up to 20 ns.
Minimum DC voltage on input or I/O pins are -0.5V. During voltage transitioning period,
input or I/O pins may undershoot GND to -2.0V for a period of time up to 20 ns.
3. Maximum DC voltage on A9 pin is +13.0 V. During voltage transitioning period, A9 pin
may overshoot to +14.0 V for a period of time up to 20 ns. Minimum DC voltage on A9 pin
is -0.5V. During voltage transitioning period, A9 pin may undershoot GND to -2.0V for a
period of time up to 20 ns.
DC AND AC OPERATING RANGE
Part Number
Operating Temperature
Vcc Power Supply
IS39LV040/010/512
0° to +85°C
2.70 V - 3.60 V
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Rev. B
07/29/2015
IS39LV040 / IS39LV010 / IS39LV512
DC CHARACTERISTICS
Symbol
Parameter
Condition
ILI
ILO
ISB1
VIN= 0 V to V CC
VI/O = 0 V to V CC
CE#, OE# = V CC -0.3 V
VIL
VIH
VOL
Input Leakage Current
Output Leakage Current
VCC Standby Current
CMOS
VCC Standby Current TTL
VCC Active Read Current
VCC Program/Erase Current
Input Low Voltage
Input High Voltage
Output Low Voltage
VOH
Output High Voltage
ISB2
ICC1
ICC2(1)
Min
CE# = VIH to VCC
f = 5 MHz; IOUT = 0 mA
-0.5
0.7 VCC
IOL = 2.1 mA;
VCC = VCCmin
VCC - 0.2
IOH = -100 µA;
VCC = VCC min
Typ
Max
Units
0.1
1
1
5
µA
µA
µA
0.05
4
8
3
15
20
mA
mA
mA
0.8
VCC + 0.3
0.45
V
V
V
V
Note: 1. Characterized but not 100% tested.
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Rev. B
07/29/2015
IS39LV040 / IS39LV010 / IS39LV512
AC CHARACTERISTICS
READ OPERATIONS CHARACTERISTICS
Symbol
tRC
tACC
tCE
tOE
tDF
tOH
tVCS
Parameter
Read Cycle Time
Address to Output
Delay
CE# to Output Delay
OE# to Output Delay
CE# or OE# to Output
High Z
Output Hold from OE#,
CE# or Address, whichever occured first
VCC Set-up Time
IS39LV040/010/512
70
70
0
70
35
25
Units
ns
ns
ns
ns
ns
0
ns
50
µs
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Rev. B
07/29/2015
IS39LV040 / IS39LV010 / IS39LV512
AC CHARACTERISTICS (CONTINUED)
READ OPERATIONS AC WAVEFORMS
t RC
ADDRESS VALID
ADDRESS
t ACC
CE#
t CE
t OE
OE#
t DF
WE#
tO H
HIGH Z
OUTPUT
OUTPUT
VALID
t VCS
VCC
INPUT TEST WAVEFORMS AND
MEASUREMENT LEVEL
OUTPUT TEST LOAD
3.3 V
3.0 V
Input
1.8 K
1.5 V
0.0 V
OUTPUT PIN
AC
Measurement
Level
30 pF
(for 55 ns)
100 pF
(for 70 ns)
1.3 K
PIN CAPACITANCE ( f = 1 MHz, T = 25°C )
Typ
Max
Units
Conditions
CIN
4
6
pF
VIN = 0 V
COUT
8
12
pF
VOUT = 0 V
Note: These parameters are characterized but not 100% tested.
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Rev. B
07/29/2015
IS39LV040 / IS39LV010 / IS39LV512
AC CHARACTERISTICS (CONTINUED)
WRITE (PROGRAM/ERASE) OPERATIONS CHARACTERISTICS
IS39LV040/010/512
Symbol
Parameter
tWC
Write Cycle Time
Min
Max
70
Units
ns
tAS
Address Set-up Time
0
ns
tAH
Address Hold Time
30
ns
tCS
CE# and WE# Set-up Time
0
ns
tCH
CE# and WE# Hold Time
0
ns
tOEH
OE# High Hold Time
10
ns
tDS
Data Set-up Time
40
ns
tDH
Data Hold Time
0
ns
tWP
Write Pulse Width
35
ns
tWPH
Write Pulse Width High
20
ns
tBP
Byte Programming Time
40
µs
tEC
Chip or Block Erase Time
100
ms
tVCS
VCC Set-up Time
50
µs
PROGRAM OPERATIONS AC WAVEFORMS - WE# CONTROLLED
Program Cycle
OE#
tC H
tV C S
CE#
tW P
tC S
tB P
tW P H
WE#
tA S
A0 - A M S
tA H
555
tW C
DATA IN
555
2AA
tD S
AA
ADDRESS
tD H
55
A0
INPUT
DATA
VALID
DATA
V CC
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Rev. B
07/29/2015
IS39LV040 / IS39LV010 / IS39LV512
AC CHARACTERISTICS (CONTINUED)
Program Cycle
OE#
tC H
tV C S
WE#
tW P
tC S
t BP
tW P H
CE#
t AS
A0 - A M S
tA H
555
555
2AA
tW C
tD S
DATA IN
AA
ADDRESS
tD H
INPUT
DATA
A0
55
VALID
DATA
V CC
CHIP ERASE OPERATIONS AC WAVEFORMS
OE#
tV C S
CE#
tW P
tW P H
WE#
t AS
AO - A M S
DATA IN
tA H
555
tW C
tD H
2AA
555
555
2AA
555
tE C
tD S
AA
55
80
AA
55
10
V CC
Integrated Silicon Solution, Inc. — www.issi.com17
Rev. B
07/29/2015
IS39LV040 / IS39LV010 / IS39LV512
AC CHARACTERISTICS (CONTINUED)
SECTOR OR BLOCK ERASE OPERATIONS AC WAVEFORMS
OE#
tV C S
CE#
tW P
tW P H
WE#
t AS
tD H
tA H
555
tW C
AO - A M S
2AA
555
2AA
Sector
Address
tD S
AA
DATA IN
555
55
80
AA
55
tE C
30
V CC
TOGGLE BIT AC WAVEFORMS
WE#
CE#
tO E H
OE#
tO E
I/O6
DATA
TOGGLE
tO H
TOGGLE
STOP
TOGGLING
tD F
VALID
DATA
Toggling
CE#, OE#,
bothorOE#
CE#
willCE#
operate
Toggle Bit.
Note: Note:
Toggling
CE#,or
OE#,
bothand
OE#
and
will operate
Toggle Bit.
Integrated Silicon Solution, Inc. — www.issi.com18
Rev. B
07/29/2015
IS39LV040 / IS39LV010 / IS39LV512
AC CHARACTERISTICS (CONTINUED)
DATA# POLLING AC WAVEFORMS
WE#
t CH
t CE
CE#
t OEH
OE#
t DF
t OE
tO H
I/O7
I/O7#
VALID DATA
Note: Toggling CE#, OE#, or both OE# and CE# will operate Data# Polling.
PROGRAM/ERASE PERFORMANCE
Parameter
Typ
Max
Unit
Remarks
Sector Erase Time
55
100
ms
From writing erase command to erase completion
Block Erase Time
55
100
ms
From writing erase command to erase completion
Chip Erase Time
55
100
ms
From writing erase command to erase completion
Byte Programming
Time
16
40
µs
Excludes the time of four-cycle program command
execution
Note: 1. These parameters are characterized but not 100% tested.
2. Preliminary specification only and will be formalized after cycling qualification test.
Integrated Silicon Solution, Inc. — www.issi.com19
Rev. B
07/29/2015
IS39LV040 / IS39LV010 / IS39LV512
PACKAGE TYPE INFORMATION
PLCC
32-Pin Plastic Leaded Chip Carrier Dimensions in Inches (Millimeters)
.485(12.32)
.495(12.51)
.447(11.35)
.453(11.51)
.009
.015
025(.635)X30°
.585(14.86)
.595(15.11)
.123(3.12)
.140(3.56)
.076(1.93)
.095(2.41)
Pin 1 I.D.
.547(13.89)
.553(14.05)
SEATING
PLANE
.013(.33)
.021(.53)
.400
REF.
.510(12.95)
.530(13.46)
.050 REF.
.026(.66)
.032(.81)
VSOP
32-Pin Thin Small Outline Package (VSOP - 8 mm x 14 mm)( measure in millimeters)
.037(.95)
.041(1.05
Pin 1 I.D.
.006(.16)
.011(,27)
.315(7.90)
.319(8.10)
.020(0.5)
BSC
.020(0.5)
.006(.15)
.484(12.30)
.492(12.50)
.543(13.80)
.560(14.20)
.047(1.20)
MAX
.010(.25)
0°
5°
.004(.10)
.008(.20)
.020(.50)
.028(.70)
Integrated Silicon Solution, Inc. — www.issi.com20
Rev. B
07/29/2015
IS39LV040 / IS39LV010 / IS39LV512
PRODUCT ORDERING INFORMATION
IS39LVxxx
-70
J
C
E
Environmental Attribute
E = Lead-free (Pb-free) Package
Blank = Standard Package
Temperature Range
C = 0°C to +85°C
Package Type
J = 32-pin PLCC
V = 32-pin VSOP (8mm x 14mm)
Speed Option
-70 = 70ns
Device Number
IS39LV040 (4 Mbit)
IS39LV010 (1 Mbit)
IS39LV512 (512 Kbit)
Integrated Silicon Solution, Inc. — www.issi.com21
Rev. B
07/29/2015
IS39LV040 / IS39LV010 / IS39LV512
ORDERING INFORMATION
Density
Frequency
(MHz)
4M
100
1M
100
512K
100
Order Part Number
Package
IS39LV040-70JCE
IS39LV040-70VCE
IS39LV010-70JCE
IS39LV010-70VCE
IS39LV512-70JCE
IS39LV512-70VCE
32-pin PLCC
32-pin VSOP
32-pin PLCC
32-pin VSOP
32-pin PLCC
32-pin VSOP
Integrated Silicon Solution, Inc. — www.issi.com22
Rev. B
07/29/2015