L9D125G80BG4 - LOGIC Devices, Inc.

PreLIMINARY Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
Benefits
FEATURES
DDR SDRAM Data Rate = 200, 250,
266, and 333 Mbps
Package:
• 25mm x 25mm, Encapsulated
Laminate Ball Grid array (LBGA), 219
balls, 1.27mm pitch.
2.5V ±0.2V Core Power supply
2.5V ±0.2V I/O Power supply
(SSTL_2 compatible)
Differential Clock inputs (CLKx,
CLKx\)
Commands entered on each positive
CLKx edge
Internal pipelined double-datarate (DDR) Architecture; two data
accesses per clock cycle
Programmable Burst Length:
2, 4, or 8
Bidirectional data strobe (DQSLx,
DQsHx) per byte transmitted/
received with data
i.e. source-synchronous data capture
DQS edge-aligned with data for
READ; center-aligned with data for
WRITE
DLL to align DQx and DQSLx,
DQSHx transitions with CLKx
Four internal banks for concurrent
operation
One data mask per byte, IMOD contains (10) bytes
Programmable IOL/IOH Option
Auto PRECHARGE option
Auto REFRESH and SELF
REFRESH Modes
Available in INDUSTRIAL,
EXTENDED and Mil-Temp ranges
Organized as 16M x 72/80
Weight: LOGIC Devices, Inc.
L9D125G80BG4 = 2.75 grams
typical
53% SPACE savings vs. Monolithic,
TSOPII-66 solution
Reduced I/O routing (34%)
Reduced trace length providing
improved/reduced parasitic capacitance
Impedance matched (60ohm) packaging
High TCE organic laminate interposer
Suitable for High Reliability applications
*Note: This integrated product and/or its specifications are subject to change without notice.
Latest document should be retrieved from LDI prior to your design consideration.
IMOD SOLUTION
MONOLITHIC SOLUTION
O
P
T
I
O
N
S
11.9
11.9
11.9
S
A
V
I
N
G
S
11.9
11.9
25mm
22.3
25mm
AREA
5 X 265mm2 = 1328mm2 PLUS
625mm2
53%
I/O
5 X 66 pins = 320 pins total
219 Balls/Locations
34%
LOGIC Devices Incorporated
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1
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
L9D125G80BG4, DDR1 SIGNAL LOCATION DIAGRAM
1
A
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DQ0
DQ14
DQ15
VSS
VSS
A9
A10
A11
A8
VCCQ
VCCQ
DQ16
DQ17
DQ31
VSS
A
B
DQ1
DQ2
DQ12
DQ13
VSS
VSS
A0
A7
A6
A1
VCC
VCC
DQ18
DQ19
DQ29
DQ30
B
C
DQ3
DQ4
DQ10
DQ11
VCC
VCC
A2
A5
A4
A3
VSS
VSS
DQ20
DQ21
DQ27
DQ28
C
D
DQ6
DQ5
DQ8
DQ9
VCCQ
VCCQ
A12
RFU
RFU
RFU
VSS
VSS
DQ22
DQ23
DQ26
DQ25
D
E
DQ7
DQML0
VCC
BA0
BA1
Vref
DQML1
VSS
NC
DQ24
E
F
CAS0\
WE0\
VCC
CLK0
DQSL3
RAS1\
WE1\
VSS
DQMH1
CLK1
F
G
CS0\
RAS0\
VCC
CKE0
CLK0\
CAS1\
CS1\
VSS
CLK1\
CKE1
G
H
VSS
VSS
VCC
VCCQ
VSS
VCC
VSS
VSS
VCCQ
VCC
H
J
VSS
VSS
VCC
VCCQ
VSS
VCC
VSS
VSS
VCCQ
VCC
J
K
CLK3\
CKE3
VCC
CS3\
DQSL4
CLK2\
CKE2
VSS
RAS2\
CS2\
K
L
NC
CLK3
VCC
CAS3\
RAS3\
DQSL2
CLK2
VSS
WE2\
CAS2\
L
M
DQ56
DQMH3
VCC
WE3\
DQML3
CKE4
DQMH4
CLK4
CAS4\
WE4\
RAS4\
CS4\
DQMH2
VSS
DQML2
DQ39
M
N
DQ57
DQ58
DQ55
DQ54
DQSH4
CLK4\
DQ73
DQ72
DQ71
DQ70
DQML4 DQSH2
DQ41
DQ40
DQ37
DQ38
N
P
DQ60
DQ59
DQ53
DQ52
VSS
VSS
DQ75
DQ74
DQ69
DQ68
VCC
VCC
DQ43
DQ42
DQ36
DQ35
P
R
DQ62
DQ61
DQ51
DQ50
VCC
VCC
DQ77
DQ76
DQ67
DQ66
VSS
VSS
DQ45
DQ44
DQ34
DQ33
R
T
VSS
DQ63
DQ49
DQ48
VCCQ
VCCQ
DQ79
DQ78
DQ65
DQ64
VSS
VSS
DQ47
DQ46
DQ32
VCC
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LOGIC Devices Incorporated
DQMH0 DQSH3 DQSL0 DQSH0
DQSL1 DQSH1
VSS
V + (Core Power)
V + (I/O Power)
UNPOPULATED
Data IO
CNTRL
NC
Level REF
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Address
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
PreLIMINARY Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
Functional Block Diagram
VCCQ
VCC
VRef
VSS
A0-A12, BA0-1
A, BA
VSS VRef VCC VCCQ
CS0\
RAS0\
CAS0\
CKE0
CLK0
CLK0\
WE0\
DQML0
DQMH0
DQSL0
DQSH0
D0
A, BA
D1
D2
D3
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DQ 0
•
•
•
DQ 7
DQ 16
•
•
•
DQ 23
DQ 8
•
•
•
DQ 15
DQ 24
•
•
•
DQ 31
DQ 0
•
•
•
DQ 7
DQ 32
•
•
•
DQ 39
DQ 8
•
•
•
DQ 15
DQ 40
•
•
•
DQ 47
DQ 0
•
•
•
DQ 7
DQ 48
•
•
•
DQ 55
DQ 8
•
•
•
DQ 15
DQ 56
•
•
•
DQ 63
DQ 0
•
•
•
DQ 7
DQ 64
•
•
•
DQ 71
DQ 8
•
•
•
DQ 15
DQ 72
•
•
•
DQ 79
VSS VRef VCC VCCQ
CS4\
RAS4\
CAS4\
CKE4
CLK4
CLK4\
WE4\
DQML4
DQMH4
DQSL4
DQSH4
LOGIC Devices Incorporated
DQ 8
•
•
•
DQ 15
VSS VRef VCC VCCQ
CS3\
RAS3\
CAS3\
CKE3
CLK3
CLK3\
WE3\
DQML3
DQMH3
DQSL3
DQSH3
A, BA
DQ 8
•
•
•
DQ 15
VSS VRef VCC VCCQ
CS2\
RAS2\
CAS2\
CKE2
CLK2
CLK2\
WE2\
DQML2
DQMH2
DQSL2
DQSH2
A, BA
DQ 0
•
•
•
DQ 7
VSS VRef VCC VCCQ
CS1\
RAS1\
CAS1\
CKE1
CLK1
CLK1\
WE1\
DQML1
DQMH1
DQSL1
DQSH1
A, BA
DQ 0
•
•
•
DQ 7
D4
3
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
Pin/Ball Locations/Definitions and Functional Description
BGA Locations
Symbol
Type
F4, F16, G5, G15, K1,
Description
CKX,CKX\ CNTL. Input Clock: CKx and CKx\ are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CKx and negative edge of CKx\. Output data
K12, L2, L13, N6, M8
(DQ’s and DQS) is referenced to the crossings of the differential clock inputs.
G4, G16, K2, K13, M6
CKEx
CNTL. Input Clock Enable: CKE controls the clock inputs. CKE High enables, CKE Low disables the clock
input pins. Driving CKE Low provides PRECHARGE POWER-DOWN. CKE is synchronous
for POWER-DOWN entry and exit, and for SELF-REFRESH entry CKE is asynchronous for
SELF-REFRESH exit and disabling the outputs. CKE must be maintained High throughout
READ and WRITE accesses. Input buffers are disabled during POWER-DOWN, input buffers
are disabled during SELF-REFRESH. CKE is an SSTL-2 input but will detect an LVCMOS
LOW level after VCC is applied.
G1, G13, K4, K16, M12
CSX\
CNTL. Input Chip Select: CSx\ enables the COMMAND register(s) of each of the five (5) integrated
words. All commands are masked (registered) HIGH with CSx\ driven true. CSx\ provides for
external word/bank selection on systems with multiple banks. CSx\is considered part of the
COMMAND CODE.
F12, G2, K15, L5, M11
RASX\
CNTL. Input Row Address Strobe: Command input along with CASx\ and WEx\
F1, G12, L4, L16, M9
CASX\
CNTL. Input Column Address Strobe: Command input along with RASx\ and WEx\
F2, F13, L15, M4, M10
WEX\
CNTL. Input WRITE (word): Command input along with CASx\ and RASx\
E2, E4, E13, F15, M2,
DQMLX,
CNTL. Input Input Data Mask: DQM is an input mask signal for WRITE operations. Input Data is masked
when DQML/Hx is sampled HIGH at time of a WRITE access DQML/Hx is sampled on both
M5, M7, M13, M15, N11 DQMHX
edges of DQSL/Hx.
E5, E6, E7, E10, E11,
DQSLX,
Data Strobe: Output flag on READ data and Input flag on WRITE data. DQS is edge-aligned
F5, K5, L12, N5, N12
DQSHX
with READ data, centered in WRITE data operations.
E12
Vref
A7, A8, A9, A10, B7, B8, A0-A12
Level REF
Reference Voltage
Input
Address input: Provide the ROW address for ACTIVE commands and the COLUMN address
B9, B10, C7, C8, C9,
and AUTO PRE-CHARGE bit (A10) for READ/WRITE commands to select one location out of
C10, D7
the total array within a selected bank A10 sampled during a PRE-CHARGE command determines whether the PRE-CHARGE applies to one bank or all banks. The address inputs also
provide the OP-CODE during a MODE REGISTER SET command.
E8, E9
BA0, BA1
Input
Bank Address input: define which BANK is active during a READ, WRITE, or PRE-CHARGE
command.
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High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
PreLIMINARY Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
Pin/Ball Locations/Definitions and Functional Description Continued
BGA Locations
Symbol
Type
RFU
A2, A3, A4, A13, A14,
DQ0-DQ79 Input/Output Data I/O
Input
Description
Reserved Future Use: Pins reserved for future Address and Bank Select inputs
D8, D9, D10
A15, B1, B2, B3, B4,
B13, B14, B15, B16, C1,
C2, C3, C4, C13, C14,
C15, C16, D1, D2, D3,
D4, D13, D14, D15, D16,
E1, E16, M1, M16, N1,
N2, N3, N4, N7, N8, N9,
N10, N13, N14, N15,
N16, P1, P2, P3, P4, P7,
P8, P9, P10, P13, P14,
P15, P16, R1, R2, R3,
R4, R7, R8, R9, R10,
R13, R14, R15, R16, T2,
T3, T4, T7, T8, T9, T10,
T13, T14, T15
B11, B12, C5, C6, E3,
VCC
Supply
Core Power
VCCQ
Supply
I/O Power
VSS
Supply
Ground (Digital)
F3, G3, H3, H12, H16,
J3, J12, J16, K3, L3, M3,
P11, P12, R5, R6, T16
A11, A12, D5, D6, H4,
H15, J4, J15, T5, T6
A5, A6, A16, B5, B6,
C11, C12, D11, D12,
E14, F14, G14, H1, H2,
H5, H13, H14, J1, J2, J5,
J13, J14, K14, L14, M14,
P5, P6, R11, R12, T1,
T11, T12
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High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
PreLIMINARY Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
FUNCTIONAL DESCRIPTION
GENERAL DESCRIPTION
The LOGIC Devices, 2.5Gb, DDR SDRAM IMOD, is one member of its
Integrated Module family. This family of Integrated memory modules
contains DDR3/DDR2 and DDR device definitions in three package footprints including this 25mm2, a 16mm x 22mm package and a 25mm x
32mm footprint. This device, a high speed CMOS random-access, integrated memory device based on use of (5) silicon devices each containing 536,870,912 bits. Each chip is internally configured as a quad-bank
SDRAM. Each of the chips 134, 217, 728 bit banks is organized as 8,192
rows by 1024 columns by 16bits. Each of the Silicon devices equates to
a WORD or DUAL-BYTES, each BYTE containing Data Mask and Data
Strobes.
READ and WRITE accesses to the DDR SDRAM are burst oriented; accesses
start at a selected location and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the registration of an ACTIVE
command which is then followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command are used to select the
bank and row to be accessed (BA0 and BA1 select the bank, A0-A12 select the
row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
Prior to normal operation, the IMOD must be initialized. The following sections
provide detailed information covering device initialization, register definition,
command descriptions and device operation.
The 2.5Gb DDR IMOD uses the double-data-rate (DDR) architecture to
achieve high-speed operation. The double-data-rate architecture is a
2n-prefetch architecture with an interface designed to transfer two data
words per clock cycle via the I/O pins. A single READ or WRITE access
for the 2.5Gb DDR IMOD effectively consists of a single 2n-bit wide, one
clock cycle transfer at the internal DRAM core and two corresponding
n-bit wide, one-half-clock cycle data transfers at the DQ (I/O) pins.
A bidirectional data strobe (DQSLx, DQSHx) is transmitted externally,
along with data, for use in data capture at the end-point receiver. DQSLx,
DQSHx are strobes transmitted by the DDR SDRAM during READ operations and by the memory controller during WRITE operations. Each
strobe, DQSLx, DQSHx control each of two bytes contained within each
of the (5) silicon chips contained in LDI’s IMOD.
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined manner.
Operational procedures other than those specified may result in undefined
operation. Power must first be applied to VCC and VCCQ simultaneously, and
then to VREF (and to the System VTT). VTT must be applied after VCCQ to avoid
device latch-up, which may cause permanent damage to the device. VREF
can be applied after VCCQ but is expected to be nominally coincident with VTT.
Except for CKE, inputs are not recognized as valid until after FREF is applied.
CKE during power-up is required to ensure that the DQ and DQS outputs will
be in the High-Z state, where they will remain until driven in normal operation
(by a READ access). After all power supply and reference voltages are stable,
and the clock is stable, the IMOD requires a 200us delay prior to applying an
executable command.
The 2.5Gb DDR SDRAM operated from a differential clock (CLKx, CLKx\);
the crossing of CLKx going HIGH and CLKx\ going LOW will be referred
to as the positive edge of CLK. Commands (address and control signals)
are registered at every positive edge of CLK. Input data is registered on
both edges of DQS, and output data is referenced to both edges of DQS,
as well as to both edges of CLK.
Once the 200us delay has been satisfied, a DESELECT or NOP command
should be applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a LOAD MODE
REGISTER command should be issued for the extended mode register (BA1
LOW and BA0 HIGH) to enable the DLL, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1 both LOW) to reset the
DLL and to program the operating parameters. Two-hundred clock cycles are
required between the DLL reset and any READ command. A PRECHARGE
ALL command should then be applied, placing the device in the all banks idle
state.
READ and WRITE accesses to the DDR memory are burst oriented;
accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident with the READ
or WRITE command are used to select the bank and the starting column
location for the burst access.
The DDR IMOD provides for programmable READ or WRITE burst
lengths of 2, 4, or 8 locations. An AUTO-PRECHARGE function may be
enabled to provide a self-timed row PRECHARGE that is initiated at the
end of the burst access.
Once in the idle state, two AUTO PRECHARGE cycles must be performed
(tRFC must be satisfied). Additionally, a LOAD MODE REGISTER command
for the mode register with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL) is required. Following these requirements, the DDR IMOD is ready for normal operation.
The pipelined, multi-banked architecture of the DDR SDRAM architecture
allows for concurrent operations, therefore providing high effective bandwidth, by hiding row PRECHARGE and activation time.
An AUTO REFRESH mode is provided, along with a power-saving powerdown mode.
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High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
PreLIMINARY Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
REGISTER DEFINITION
Mode Register
Burst Length
The MODE REGISTER is used to define the specific mode of operation of the DDR IMOD. This
definition includes the selection of a burst length,
a burst type, a CAS latency as shown in Figure
2 and the operating mode, as shown in Figure 3.
The MODE REGISTER is programmed via the
MODE REGISTER SET command (with BA0=0
and BA1=0) and will retain the stored information
until it is programmed again or the device realizes a loss of power (except for bit A8 which is
self clearing).
Reprogramming the MODE REGISTER will not
alter the contents of the memory, provided it is
performed correctly. The MODE REGISTER
must be loaded (reloaded) when all banks are idle
and no bursts are in progress, and the controller
must wait the specified time before initiating the
subsequent operation. Violating either of these
requirements will result in unspecified operation.
MODE REGISTER bits A0-A2 specify the burst
length, A3 specifies the type of burst (sequential
or interleaved), A4-A6 specify the CAS latency,
and A7-A12 specify the operating mode.
Burst type
READ and WRITE accesses to the DDR IMOD
are burst oriented, with the burst length being
programmable, as shown in Figure 3. The
burst length determines the maximum number
of column locations that can be accessed for a
given READ or WRITE command. Burst lengths
of 2, 4, or 8 locations are available for both the
sequential and interleaved burst types.
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected
via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type and the
starting column address, as shown in Table 1.
Reserved states should not be used, as unknown
operation or incompatibility issues with future
version may result.
When a READ or WRITE command is issued,
a block of columns equal to the burst length is
effectively selected. All accesses for that burst
take place within this block, meaning that the
burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-Ai
when the burst length is set to two; by A2-Ai when
the burst length is set to four and by A3-Ai when
the burst length is set to eight. The remaining
(least significant) address bits are used to select
the starting location within the block. The programmed burst length applies to both the READ
and WRITE bursts.
Table 1: Burst Definition
Order of Accesses within a Burst
Burst Length
2
4
8
Starting Column Address Type = Sequential
Type = Interleaved
A0
0
0-1
0-1
1
1-0
1-0
A1
A0
0
0
0-1-2-3
0-1-2-3
1-0-3-2
0
1
1-2-3-0
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
A2
A1
A0
0-1-2-3-4-5-6-7
0
0
0
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
0
1
0
2-3-4-5-6-7-0-1
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
1
0
0
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
1
1
0
6-7-0-1-2-3-4-5
1
1
1
7-0-1-2-3-4-5-6
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7
Notes
1. For a burst length of two, A1-Ai selects a two-data-element block; A0 selects the
starting column within the block.
2. For a burst length of four, A2-Ai selects
a four-data-element block; A0-1 selects the
starting column within the block.
3. For a burst length of eight, A3-Ai selects
an eight-data-element block; A0-2 selects
the starting column within the block.
4. Whenever a boundary of the block is
reached within a given sequence above,
the following access wraps within the block.
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
PreLIMINARY Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
READ LATENCY
Table 2 - Cas Latency
Allowable Operating Frequency (MHz)
The READ latency is the delay in clock cycles, between the registration of
a READ command and the availability of the first bit of output data. The
latency can be set to 2 or 2.5 clocks.
If a READ command is registered at clock edge [n], and the latency is
[m] clocks, the data will be available by clock edge [n+m]. Table 2 indicates the operating frequencies at which each CAS latency setting can
be used.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Speed
CAS Latency = 2
CAS Latency = 2.5
-10
≤75
≤100
-8
≤100
≤125
-75
≤100
≤133
-6
≤133
≤166
OPERATING MODE
The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A12, each set to zero, and bits A0-A6, set to the desired
values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A12, each set to zero, bit A8 set to one, and bits A0-A6, set to
the desired values. Although not required, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should
always be followed by a LOAD MODE REGISTER command to select normal operating mode.
All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used because
unknown operation or incompatibility from future versions may result.
EXTENDED MODE REGISTER
The EXTENDED MODE REGISTER controls functions beyond those controlled by the MODE REGISTER; these additional functions are DLL enable/disable,
output drive strength, and QFC#. These functions are controlled via the bits shown in Figure 4. The EXTENDED MODE REGISTER command to the MODE
REGISTER (with BA0=1, BA1=0) and the register will retain the stored information until it is programmed again or the device realizes loss of power. The
enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the MODE REGISTER (BA0=BA1=LOW) to reset the DLL.
The EXTENDED MODE REGISTER must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before
initiating any subsequent operation. Violating either of these requirements could result in unspecified operation.
LOGIC Devices Incorporated
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8
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
REGISTER DEFINITION
Figure 1 - Mode Register Definition
BA1 BA0 An . . .
Mn + 2 Mn + 1
n+2
n+1
0
0
n1 . . .
8
7
6
5
4
3
A 2 A 1 A 0 Address bus
2
1
Base mode register
0
1
Extended mode register
1
0
1
1
Burst Type
Reserved
0
Sequential
Reserved
1
Interleaved
M7
M6–M0
Operating Mode
Mode register
(Mx)
M2 M1 M0 Burst Length
M3
M8
0
CAS Latency BT Burst length
Mode Register Definition
0
. . . M9
9
Operating mode
0
Mn
A9 A 8 A7 A6 A5 A4 A3
0
0
0
0
0
Valid
Normal operation
0
0
0
1
0
Valid
Normal operation/reset DLL
–
–
–
–
–
–
All other states reserved
0
0
0
Reserved
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
M6
M5
M4
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
2.5
1
1
1
Reserved
Note: 1. n is the most significant row address bit
LOGIC Devices Incorporated
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9
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
REGISTER DEFINITION
Figure 2 - Case Latency
T0
T1
T2
READ
NOP
NOP
T2n
T3
T3n
CK#
CK
Comman d
NOP
CL = 2
DQS
DQ
CK#
T0
T1
T2
T2n
T3
READ
NOP
NOP
NOP
T3n
CK
Comman d
CL = 2.5
DQS
DQ
CK#
T0
T1
T2
T3
READ
NOP
NOP
NOP
T3n
CK
Comman d
CL = 3
DQS
DQ
Transitioning Data
Note:
LOGIC Devices Incorporated
Don ’t Care
BL = 4 in the cases shown; shown with nominal t AC, t DQSCK, and t DQSQ.
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10
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
REGISTER DEFINITION
Figure 3 - Extended Mode Register
BA1
BA0
An . . . A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
n + 2 n + 1 n1 . . . 9 8 7 6
Operating Mode
0
1
Mn + 2 Mn + 1
5
4
3
Mode Register Definition
DLL
0
Enable
1
Disable
Base mode register
0
1
Extended mode register
1
0
Reserved
0
Normal
1
1
Reserved
1
Reduced
2
E1
Extended mode
register (Ex)
E0
0
Drive Strength
Operating Mode
0
0
0
0
0
0
0
0
0
0
Valid
Reserved
–
–
–
–
–
–
–
–
–
–
–
Reserved
1. n is the most significant row address
. bit.
2. The reduced drive strength option is available only on Design Revision F and K.
3. The QFC# option is not supported.
Output Drive Strength
DLL Enable/Disable
The DLL must be enabled for normal operation. The DLL enable is required
during power-up initialization and upon returning to normal operation after
having disabled the DLL for the purpose of debug or evaluation. When the
device exits SELF REFRESH mode, the DLL is enabled, 200 clock cycles
must occur before a READ command can be issued.
The normal full drive strength for all outputs are specified to be SSTL2,
Class II. The DDR IMOD supports an option for reduced drive. This option
is intended for the support of the lighter load and/or point-to-point environments. The selection of the reduced drive strength will alter the DQs and
DQSs from SSTL2, Class II drive strength to a reduced drive strength, which
is approximately 54% of the SSTL, Class II drive strength.
LOGIC Devices Incorporated
1 0
DS DLL
0
3
En . . . E9 E8 E7 E6 E5 E4 E3 E2 E1, E0
Notes:
2
Address bus
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11
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
REGISTER DEFINITION
Commands
The TRUTH TABLE (below) provides a quick reference of available commands, followed by a written description of each command.
Truth Table
CSx\
RASx\
CASx\
WEx\
ADDR Notes
Deselect (NOP)
H
X
X
X
X
1,9
No Operation (NOP)
L
H
H
H
X
1,9
ACTIVE (select bank and activate row)
L
L
H
H
Bank/Row
1,3
READ (select bank and column, and start READ burst)
L
H
L
H
Bank/Column
1,4
WRITE (select bank and column and start WRITE burst)
L
H
L
L
Bank/Column
1,4
BURST TERMINATE
L
H
H
L
X
1,8
PRECHARGE (deactivate row in bank or banks)
L
L
H
L
Code
1,5
AUTO REFRESH or SELF REFRESH (enter soft refresh mode)
L
L
L
H
X
6,7
LOAD MODE REGISTER
L
L
L
L
OP Code
1,2
Name (Function)
Truth Table - DM Operation
Name (Function)
DQMLx, DQMHx
Notes
DQSLx, DQSHx
WRITE ENABLE
L
Valid
1,10
WRITE INHIBIT
H
X
1,10
NOTES:
1. CKE is HIGH for all commands shown except SELF REFRESH.
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if
CKE is LOW.
2. A0-A12 define the op-code to be written to the selected MODE REGISTER BA0, BA1 select either the MODE REGISTER or the
EXTENDED MODE REGISTER.
7. Internal REFRESH counter controls row addressing; all inputs and I/Os
are “Don’t Care” except for CLE.
8. Applies only to READ bursts with AUTO PRECHARGE disabled. This
command is undefined (and should not be used) for READ burst with
AUTO PRECHARGE enabled.
3. A0-A12 provide row addresses, and BA0, BA1 provide bank addresses.
4. A0-A9 provide column address; A10 HIGH enables the AUTO
PRECHARGE feature (non-persistent), while A10 LOW disables the
AUTO PRECHARGE feature; BA0, BA1 provide bank address.
9. DESELECT and NOP are functionally interchangeable.
10. Used to mask WRITE data; provided coincident with the corresponding
data.
5. A10 LOW; BA0, BA1 determine the bank being PRECHARGED. A10
HIGH all banks PRECHARGED and BA0, BA1 or “Don’t Care”.
Deselect
The DESELECT function (CSx\=HIGH) prevents new commands from being executed by the DDR IMOD. The IMOD is effectively deselected. Operations
already in progress are not affected.
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High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
REGISTER DEFINITION
Active
No Operation (NOP)
The ACTIVE command is used to open (or activate) a row in a particular
bank for a subsequent access. The value on the BA0, BA1 inputs selects
the bank and the address provided on inputs A0-A12, selects the row. This
row remains active (or opens) for accesses until a PRECHARGE command
is issued to that bank. A PRECHARGE command must be issued before
opening a different row in the same bank.
The NO OPERATION command is used to perform a NOP to the selected
DDR Silicon within the IMOD (CSx\=LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already
in progress are not affected.
Load Mode Register
The MODE REGISTER is loaded via inputs A0-A12. The LOAD MODE REGISTER command can only be issued when all banks idle and a subsequent
executable command cannot be issued until tMRD is met.
Activating a Specific Row in a Specific Bank
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
Add ress
BA0, BA1
Row
Bank
Don ’t Care
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13
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
Read
The READ command is used to initiate a burst READ access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided
on inputs A0-A9 selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE
is selected, the row being accessed will be PRECHARGED at the end of the READ burst; If AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses.
READ Command
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
Address
Col
EN AP
A10
DIS AP
BA0, BA1
Bank
Don ’t Care
Note:
EN AP = enable auto precharge
DIS AP = disable auto precharge.
LOGIC Devices Incorporated
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14
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
Write
The WRITE command is used to initiate a burst WRITE access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided
on inputs A0-A9 selects the starting column location. The value on the input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be AUTO PRECHARGED at the end of the WRITE burst; If AUTO PRECHARGE is not selected, the row will
remain open for subsequent accesses. Input data appearing on the DQ lines is written to the memory array subject to DQMLx, DQMHx for each WORD. If a
given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will
be ignored, and a WRITE will not be executed to that byte column location.
WRITE Command
CK#
CK
CKE HIGH
CS#
RAS#
CAS#
WE#
Address
Col
EN AP
A10
DIS AP
BA0, BA1
Bank
Don ’t Care
Note:
EN AP = enable auto precharge
DIS AP = disable auto precharge..
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15
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
Precharge
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank or banks will be available for a
subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Except in the case of concurrent auto PRECHARGE, where a
READ or WRITE command to a different bank is allowed as long as it does not violate any other timing parameters. Input A10 determines whether one or all
banks are to be PRECHARGED and in the case where only one bank is to be PRECHARGED, inputs BA0, BA1 select the bank. In all other cases BA0, BA1
are treated as “Don’t Care”. Once a bank has been PRECHARGED, it is in the idle state and must be activated prior to any READ or WRITE commands being
issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank, or if the previously open row is already in the
process of PRECHARGING.
PRECHARGE Command
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
Address
All banks
A10
One bank
BA0, BA1
Bank1
Don ’t Care
Note:
1. If A10 is HIGH, bank address becomes “Don’t Care.”
Auto Precharge
AUTO PRECHARGE is a feature which performs the same individual bank PRECHARGE function described prior, but without requiring an explicit command.
This is accomplished by using A10 to enable the command/function in conjunction with a specific READ or WRITE command. A PRECHARGE of the bank/
row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. AUTO PRECHARGE is
non-persistent in that it is either enabled or disabled for each individual READ or WRITE command. The device supports concurrent AUTO PRECHARGE if
the command to the other bank does not interrupt the data transfer to the current bank.
AUTO PRECHARGE ensures that the PRECHARGE is initiated at the earliest valid stage within a burst. This earliest valid stage is determined as if an explicit
PRECHARGE command was issued at the earliest possible time without violating tRAS (MIN).
LOGIC Devices Incorporated
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16
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
Absolute Maximum Ratings
Burst Terminate
Parameter
The BURST TERMINATE command is used to truncate READ bursts.
The most recently registered READ command prior to the BURST TERMINATE command will be truncated. The open page which the READ
burst was terminated from, remains open.
Auto Refresh
AUTO REFRESH is used during normal operations of the IMOD and is
analogous to CASx\-BEFORE-RASx\ (CBR) REFRESH in conventional
DRAMs. This command is non-persistent so it must be issued each time
a REFRESH is required.
MIN
MAX
UNITS
VCC Supply Voltage relative to VSS
-1.0V
+3.6V
V
VCCQ I/O Supply Voltage relative to VSS
-1.0V
+3.6V
V
VREF and inputs Voltage relative to VSS
-1.0V
+3.6V
V
I/O pins Voltage relative to VSS
-0.5V
VCCQ + 0.5V
V
Storage Temperature
-55
+150
C
Short circuit current
−−
50
mA
Capacitance
The addressing is generated by the internal REFRESH controller. This
makes the address bits “Don’t Care” during an AUTO REFRESH command. Each DDR die within the IMOD, requires AUTO REFRESH cycles
at an average of 7.8125 us (maximum).
Parameter
To allow for improved efficiency in scheduling and switching between
tasks, some flexibility in the absolute REFRESH interval is provided. A
maximum of eight AUTO REFRESH commands can be posted to any
given DDR die, meaning that the maximum absolute interval between any
AUTO REFRESH command is 9 x 7.8125uS (70.3uS). This maximum
absolute interval is to allow future support for DLL updates internal to the
DDR SDRAM die.
SYMBOL
MAX
UNITS
Input Capacitance [CKx\CKx\]
Cl1
5
pF
Addresses, BA0-1
CA
30
pF
Input Capacitance [All other Input Pins]
C12
7
pF
DQ line
C10
8
pF
Although not a JEDEC requirement, to provide for future functionality
enhancements, CKEx must be active (HIGH) during the AUTO REFRESH
period. The AUTO REFRESH period begins when the AUTO REFRESH
command is registered and ends tRFC later.
Self Refresh
The SELF REFRESH command can be used to retain data in the DDR
IMOD even if the rest of the system is powered down. When in the SELF
REFRESH mode, the DDR IMOD retains data without external clocking.
The SELF REFRESH command is initiated like an AUTO REFRESH command except CKEx is disabled (LOW). The DLL is automatically enabled
upon entering SELF REFRESH (200 clock cycles must then occur before
a READ command can be issued). Input signals except CLEx are “Don’t
Care” during SELF REFRESH.
The procedure for exiting SELF REFRESH requires a sequence of commands. First, CLKx must be stable prior to CKEx going back to HIGH.
Once CLEx is HIGH, the DDR die must have a NOP command issued
for tXSNR, because time is required for the completion of any internal
REFRESH in progress.
A simple algorithm for meeting both REFRESH and DLL requirements is
to apply NOPs for 200 clock cycles before applying any other command.
LOGIC Devices Incorporated
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17
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
DC Electrical Characteristics and Operating Conditions
(NotesO
1,utline
6) Dimensions
Package
VCC, VCCQ=+2.5V±0.2V;-55°C≤TA≤+125°C
Parameter
Symbol
MIN
TYP
MAX
Units
VCC
2.3
2.5
2.7
V
I/O Supply Voltage
VCCQ
2.3
2.5
2.7
V
I/O Reference Voltage
Supply Voltage
VREF
0.49 x VCCQ
0.50 x VCCQ
0.51 x VCCQ
V
I/O Termination Voltage
VTT
VREF - 0.04
VREF
VREF + 0.04
V
Input High Voltage
VIH
Input Low Voltage
VIL
II
-2
+2
uA
IOZ
-5
+5
uA
Full Drive Output Option
IOH
-16.8
−−
mA
IOL
+16.8
−−
mA
Reduced Drive Output Option
IOH
-9
−−
mA
IOL
+9
−−
mA
Input Leakage Current:
Any input 0V≤VIN≤VCC, VREF pin 0V≤VIN≤1.35V
All other pins not under test = 0V
Output Leakage Current:
DQ lines disabled; 0V≤VOUT≤VCCQ
Ambient Operating Temperature
LOGIC Devices Incorporated
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Industrial = “I”
TA
-40
25
85
°C
Extended = “E”
TA
-40
25
105
°C
Mil-Temp = “M”
TA
-55
25
125
°C
18
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
ICC Operating Specification limits and Conditions (NotesP1-5,
10, O
12,
14) Dimensions
ackage
utline
VCC, VCCQ=+2.5V±0.2V;-55°C≤TA≤+125°C
333 Mbps
266/250 Mbps
200 Mbps
Symbol
@CL=2
@CL=2
@CL=2
Units
ICC0
640
600
520
mA
ICC1
790
710
650
mA
ICC2P
25
25
25
mA
ICC2F
225
225
195
mA
ICC3P
175
175
150
mA
ICC3N
225
225
200
mA
ICC4R
350
300
245
mA
ICC4W
1250
1025
775
mA
tREF=tRC (MIN) (notes: 27, 50)
ICC5
1450
1450
1400
mA
tREF=7.8125us (notes: 27, 50) =tRC (MIN)
ICC5A
50
50
50
mA
mA
mA
Parameter
OPERATING current: One bank active - precharge
tCL=tCK(MIN), tRC=tRC(MIN), tRAS=tRAS MIN(ICC); DQ, DQM, DQS inputs
changing once per clock cycle; Address and Control inputs changing once
every two clock cycles
OPERATING current: One bank active - READ - precharge current
Active-Read-Precharge; Burst=2; tRC=tRC(MIN); tCK=tCK(MIN); IOUT=0mA;
Address and control inputs changing once per clock cycle (notes: 22, 48)
Precharge POWER-DOWN current
All banks idle; POWER-DOWN mode; tCK=tCK(MIN), CKE=LOW (notes: 23,
32, 50)
IDLE STANDBY current
CS\=HIGH; All banks idle; POWER-DOWN mode; tCK=tCK(MIN);
CKE=HIGH; Address and other Control inputs changing once per clock cycle;
VSS=VREF for DQ, DQS and DM (note: 51)
ACTIVE POWER-DOWN, STANDBY current
One bank active; POWER-DOWN mode; tCK=tCK(MIN), CKE=LOW (notes:
23, 32, 50)
ACTIVE STANDBY current
CS\=HIGH; CKE=HIGH; One bank Active Precharge; tRC=tRAS(MAX);
tCK=tCK(MIN); DQ, DQM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per cycle (note: 22)
OPERATING current Burst=2 READS
Continuous Burst; One bank active; Address and Control inputs changing
once per clock cycle; tCK=tCK(MIN); IOUT=0mA cycle (notes: 22, 48)
OPERATING current Burst=2 WRITES
Continuous Burst; One bank active; Address and Control inputs changing
once per clock cycle; tCK=tCK(MIN); DQ, DQM and DQS inputs changing
twice per clock cycle (note: 22)
AUTO REFRESH current
SELF REFRESH current; CKE=≤0.2V
ICC6
25
25
25
OPERATING current
ICC7
2000
1925
1700
Four bank interleaving READS (BL=4) with AUTO PRECHARGE; tRC=tRC
(MIN); tCK=tCK (MIN); Address and Control inputs change only during
ACTIVE READ or WRITE commands (notes: 22, 49)
LOGIC Devices Incorporated
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19
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC Electrical Specifications and Recommend OperatingPCackage
haracteristics
otes 1-5, 14-17, 33)
Outline (N
Dimensions
-6, 333 [266]Mbps
-75, 266 [250]Mbps
167 MHz,
133 MHz
CLKx CL = 2.5 [2]
Parameter
Symbol
MIN
100 MHz
CLKx CL = 2.5 [2]
MIN
MAX
-0.7
0.7
-0.75
0.75
-0.8
0.8
-0.8
0.8
ns
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCLK
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCLK
6
13
7.5
13
8
13
10
13
ns
7.5
13
10
13
10
13
13
Access window of DQs from CLKx / CLKx\
CLKx High level Width
tCH
CLKx Low level Width
tCL
CL=2.5
tCK
CL=2
tCK
DQ and DM Input Hold Time relative to DQS
tDH
0.45
DQ and DM Input Setup Time relative to DQS
tDS
tDIPW
DQ and DM Input Pulse Width
-10, 200 [167] Mbps
125 MHz
CLKx CL = 2.5 [2]
MAX
tAC
Clock Cycle Time
CLKx CL = 2.5 [2]
-8, 250 [200]Mbps
MIN
0.5
0.6
0.45
0.5
0.6
1.75
1.75
2
MAX
MIN
MAX
UNITS
15
ns
0.6
ns
0.6
ns
ns
2
tDQSCK
-0.6
DQS Input HIGH Pulse Width
tDQSH
0.35
0.35
0.35
0.35
tCLK
DQS Input LOW Pulse Width
tDQSL
0.35
0.35
0.35
0.35
tCLK
DQS-DQ Ske, DQS to last DQ valid, per grp.
tDQSQ
WRITE command to first DQS latching transition
tDQSS
0.75
DQS falling edge to CLKx rising - setup time
tDSS
0.2
0.2
0.2
0.2
tCLK
DQS falling edge to CLKx rising - hold time
tDSH
0.2
0.2
0.2
0.2
tCLK
Half Clock period
tHP
tCH,tCL
tCH,tCL
tCH,tCL
tCH,tCL
ns
Data-Out HIGH impedance window from CLKx / CLKx\
tHZ
Data-Out LOW impedance window from CLKx / CLKx\
tLZ
-0.07
-0.75
-0.8
-0.8
ns
Address and Control Input hold time
tIHF
0.75
0.9
1.1
1.1
ns
Address and Control Input setup time
tISF
0.75
0.9
1.1
1.1
ns
Address and Control Input hold time
tHIS
0.8
1
1.1
1.1
Address and Control Input setup time
tISS
0.8
1
1.1
1.1
tMRD
12
15
tHP-tQHS
16
16
Access window of DQs from CLKx / CLKx\
Load Mode Register
DQ-DQS hold. DQS to first DQ to go non-valid
0.6
-0.75
0.45
1.25
tHP-tQHS
-0.8
0.5
0.75
0.7
tQH
0.75
1.25
-0.8
0.8
0.6
0.75
0.75
0.75
1.25
0.8
0.6
ns
1.25
tCLK
0.8
0.8
tHP-tQHS
ns
ns
ns
tHP-tQHS
ns
1
ms
120000
ms
Data Hold skew factor
tQHS
ACTIVE to PRECHARGE command
tRAS
42
ACTIVE to READ with AUTO PRECHARGE command
tRAP
15
20
20
20
ms
tRC
60
65
70
70
ns
AUTO REFRESH command period
tRFC
72
75
80
80
ns
ACTIVE to READ or WRITE delay
tRCD
15
20
20
20
ns
ACTIVE to ACTIVE/AUTO REFRESH command per.
0.55
70000
0.75
40
120000
1
40
120000
40
tRP
15
DQS READ Preamble
tRPRC
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCLK
DQS READ Postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCLK
tRRD
12
PRECHARGE command period
ACTIVE bank to ACTIVE bank b command
DQS WRITE Preamble
DQS READ Preamble Setup Time
LOGIC Devices Incorporated
www.logicdevices.com
15
tWPRC
0.25
0.25
tWPRCS
0
0
20
20
20
ns
20
15
ns
0.25
0.25
tCLK
0
0
ns
15
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC Electrical Specifications and Recommend OperatingPCackage
haracteristics
otes 1-5, 14-17, 33)
Outline (N
Dimensions
-6, 333 [266]Mbps
-75, 266 [250]Mbps
167 MHz,
133 MHz
CLKx CL = 2.5 [2]
Parameter
Symbol
MIN
DQS WRITE Postamble
tWPST
0.4
WRITE Recovery Time
tWR
12
Internal WRITE to READ command delay
tWTR
na
Data Valid Output Window
MAX
CLKx CL = 2.5 [2]
MIN
MAX
-8, 250 [200]Mbps
-10, 200 [167] Mbps
125 MHz
CLKx CL = 2.5 [2]
100 MHz
CLKx CL = 2.5 [2]
MIN
MAX
MIN
MAX
UNITS
0.4
0.4
0.6
0.4
0.6
tCLK
15
15
15
ns
tCLK
1
1
1
1
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
us
70.3
70.3
70.3
70.3
us
53
53
us
REFRESH to REFRESH command Interval (Industrial)
tREFC
REFRESH to REFRESH command Interval (Extended)
tREFC
35
53
REFRESH to REFRESH command Interval (Mil-Temp)
tREFC
7.8
35
35
35
us
Average Periodic REFRESH Interval (Industrial)
tREFI
3.9
7.8
7.8
7.8
us
Average Periodic REFRESH Interval (Extended)
tREFI
5.9
5.9
5.9
5.9
us
Average Periodic REFRESH Interval (Mil-Temp)
tREFI
3.9
3.9
3.9
us
Terminating delay reference to VDD
Exit Self REFRESH to non-READ Command
Exit Self REFRESH to READ Command
LOGIC Devices Incorporated
www.logicdevices.com
3.9
tVTD
0
0
0
0
tXSNR
75
75
80
80
ns
200
tCLK
tXSRD
200
21
200
200
ns
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC Specification Notes
1.All voltages referenced to VSS
V/ns, functionality is uncertain.
2.Tests for AC timing, IDD, and electrical AC and DC characteristics may be
conducted at nominal reference/supply voltage levels, but the related specifications and the device operation are guaranteed for the full voltage range
specified.
16. The CK/CK# input reference level (for timing referenced to CK/CK#) is
the point at which CK and CK# cross; the input reference level for signals
other than CK/CK# is VREF.
17. Inputs are not recognized as valid until VREF stabilizes. Once initialized,
including self refresh mode, VREF must be powered within specified range.
Exception: during the period before VREF stabilizes, CKE < 0.3 × VDD is
recognized as LOW.
3. Outputs (except for IDD measurements) measured with equivalent load:
VTT
Output
(VOUT)
50Ω
Reference
point
30pF
18. The output timing reference level, as measured at the timing reference
point (indicated in Note 3), is VTT.
19. tHZ and tLZ transitions occur in the same access time windows as data
valid transitions. These parameters are not referenced to a specific voltage
level, but specify when the device output is no longer driving (High-Z) or
begins driving (Low-Z).
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test
environment, but input timing is still referenced to VREF (or to the crossing
point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate
for the input signals used to test the device is 1 V/ns in the range between
VIL(AC) and VIH(AC).
20. The intent of the “Don’t Care” state after completion of the postamble
is the DQS-driven signal should either be HIGH, LOW, or High-Z, and that
any signal transition within the input switching region must follow valid input
requirements. That is, if DQS transitions HIGH (above VIH[DC] MIN) then it
must not transition LOW (below VIH[DC] prior to tDQSH [MIN]).
5. The AC and DC input level specifications are as defined in the SSTL_2
standard (that is, the receiver will effectively switch as a result of the signal
crossing the AC input level and will remain in that state as long as the signal
does not ring back above [below] the DC input LOW [HIGH] level).
21. This is not a device limit. The device will operate with a negative value,
but system performance could be degraded due to bus turnaround.
6. All speeds may not be offered on all device grades. Refer to “Ordering
Information” for availability.
22. It is recommended that DQS be valid (HIGH or LOW) on or before the
WRITE command. The case shown (DQS going from High-Z to logic LOW)
applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending
on tDQSS.
7. VREF is expected to equal VDDQ/2 of the transmitting device and to track
variations in the DC level of the same. Peak-to-peak noise (noncommon
mode) on VREF may not exceed ±2% of the DC value. Thus, from VDDQ/2,
VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise.
This measurement is to be taken at the nearest VREF bypass capacitor.
23. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK
that meets the minimum absolute value for the respective parameter. tRAS
(MAX) for IDD measurements is the largest multiple of tCK that meets the
maximum absolute value for tRAS.
8. VTT is not applied directly to the device. VTT is a system supply for signal
termination resistors, it is expected to be set equal to VREF, and it must track
variations in the DC level of VREF.
24. The refresh period is 64ms. This equates to an average refresh rate
of 7.8125μs (15.625μs for 128Mb DDR). However, an AUTO REFRESH
command must be asserted at least once every 70.3μs (140.6μs for 128Mb
DDR); burst refreshing or posting by the DRAM controller greater than 8
REFRESH cycles is not allowed.
9. VID is the magnitude of the difference between the input level on CK and
the input level on CK#.
10. The value of VIX and VMP is expected to equal VDDQ/2 of the transmitting
device and must track variations in the DC level of the same.
25. The I/O capacitance per DQS and DQ byte/group will not differ by more
than this maximum amount for any given device.
11. IDD is dependent on output loading and cycle rates. Specified values are
obtained with minimum cycle times.
26. The data valid window is derived by achieving other specifications: tHP
(tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates
in direct proportion to the clock duty cycle and a practical data valid window
can be derived. The clock is allowed a maximum duty cycle variation of 45/55,
because functionality is uncertain when operating beyond a 45/55 ratio. 27.
Referenced to each output group: x4 = DQS with DQ0–DQ3; x8 = DQS with
DQ0–DQ7; x16 = LDQS with DQ0–DQ7 and UDQS with DQ8–DQ15.
12. Enables on-chip refresh and address counters.
13. IDD specifications are tested after the device is properly initialized and is
averaged at the defined cycle rate.
14. This parameter is sampled. VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V,
VREF = VSS, f = 100MHz, TA= 25°C, VOUT(DC) = VDDQ/2, VOUT (peak-topeak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they
are matched in loading.
28. This limit is actually a nominal value and does not result in a fail value.
CKE is HIGH during the REFRESH command period (tRFC [MIN]), else CKE
is LOW (that is, during standby).
15. For slew rates less than 1 V/ns and greater than or equal to 0.5 V/ns. If
the slew rate is less than 0.5 V/ns, timing must be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew rate from the 500 mV/ns.
tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5
LOGIC Devices Incorporated
www.logicdevices.com
22
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC Specification Notes
29. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC).
from 0.1V to 1.0V.
Figurevoltages
4 - Full
Drive Pull-Down Characteristics
160
140
120
100
IOUT (mA)
30. The input capacitance per pin group will not differ by more than this maximum amount for any given device.
80
60
31. CK and CK# input slew rate must be ≥1 V/ns (≥2 V/ns if measured
differentially).
40
32. DQ and DM input slew rates must not deviate from DQS by more than
10%. If the DQ/DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100 mV/ns reduction in
slew rate.
0
20
0.0
0.5
1.0
1.5
2.0
2.5
VOUT (V)
Figure 5 - Full Drive Pull-Up Characteristics
33. VDD must not vary more than 4% if CKE is not active while any bank is
active.
0
34. The clock is allowed up to ±150ps of jitter. Each timing parameter is
allowed to vary by the same amount.
-20
-40
35. tHP (MIN) is the lesser of tCL (MIN) and tCH (MIN) actually applied to the
device CK and CK# inputs, collectively, during bank active.
IOUT (mA)
-60
36. READs and WRITEs with auto precharge are not allowed to be issued
until tRAS (MIN) can be satisfied prior to the internal PRECHARGE command being issued.
-80
-100
-120
-140
-160
37. Any positive glitch must be less than 1/3 of the clock cycle and not more
than +400mV or 2.9V, whichever is less. Any negative glitch must be less
than 1/3 of the clock cycle and not exceed either –300mV or 2.2V, whichever
is more positive. The average cannot be below the +2.5V minimum.
-180
-200
0.0
0.5
1.0
1.5
2.0
2.5
VDDQ - VOUT (V)
38. Normal output drive curves:
a. The full driver pull-down current variation from MIN to MAX process; temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 4.
b. The driver pull-down current variation, within nominal voltage and temperature limits, is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of
Figure 4.
c. The full driver pull-up current variation from MIN to MAX process; temperature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 5.
d. The driver pull-up current variation within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 5.
e. The full ratio variation of MAX to MIN pull-up and pull-down current should be between 0.71 and 1.4 for drain-to-source voltages from 0.1V to 1.0V at the same voltage and temperature.
39. Reduced output drive curves:
f. The full ratio variation of the nominal pull-up to pull-down
current should be unity ±10% for device drain-to-source LOGIC Devices Incorporated
www.logicdevices.com
23
a. The full driver pull-down current variation from MIN to MAX process; temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 6.
b. The driver pull-down current variation, within nominal voltage and temperature limits, is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 6.
c. The full driver pull-up current variation from MIN to MAX process; temperature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 7.
d. The driver pull-up current variation, within nominal voltage and temperature limits, is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 7.
e. The full ratio variation of the MAX-to-MIN pull-up and pull-
down current should be between 0.71 and 1.4 for device
drain-to-source voltages from 0.1V to 1.0V at the same voltage and temperature.
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC Specification Notes
f. The full ratio variation of the nominal pull-up to pull-down current should be unity ±10%, for device drain-to-source
voltages from 0.1V to 1.0V.
45. During initialization, VDDQ, VTT, and VREF must be equal to or less than
VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power-up,
even if VDD/VDDQ are 0V, provided a minimum of 42Ω of series resistance is
used between the VTT supply and the input pin.
Figure 6 - Reduced Drive Pull-Down Characteristics
46. The current LDI part operates below 83 MHz (slowest specified JEDEC
operating frequency). As such, future die may not reflect this option.
80
70
47. When an input signal is HIGH or LOW, it is defined as a steady state logic
HIGH or LOW.
60
IOUT (mA)
50
48. Random address is changing; 50% of data is changing at every transfer.
40
30
49. Random address is changing; 100% of data is changing at every transfer.
20
10
50. CKE must be active (HIGH) during the entire time a REFRESH command is executed. That is, from the time the AUTO REFRESH command
is registered, CKE must be active at each rising clock edge, until tRFC has
been satisfied.
0
0.0
0.5
1.0
1.5
2.0
2.5
VOUT (V)
51. IDD2N specifies the DQ, DQS, and DM to be driven to a valid HIGH or
LOW logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address
and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are
similar, IDD2F is “worst case.”
Figure 7 - Reduced Drive Pull-Up Characteristics
0
52. Whenever the operating frequency is altered, not including jitter, the DLL
is required to be reset followed by 200 clock cycles before any READ command.
-10
-20
IOUT (mA)
-30
53. This is the DC voltage supplied at the DRAM and is inclusive of all noise
up to 20 MHz. Any noise above 20 MHz at the DRAM generated from any
source other than that of the DRAM itself may not exceed the DC voltage
range of 2.6V ±100mV.
-40
-50
-60
54. The -6 speed grades will operate with tRAS (MIN) = 40ns and
tRAS (MAX) = 120,000ns at any slower frequency.
-70
-80
0.0
0.5
1.0
1.5
2.0
2.5
VDDQ - VOUT (V)
40. The voltage levels used are derived from a minimum VDD level and the
referenced test load. In practice, the voltage levels obtained from a properly
terminated bus will provide significantly different voltage values.
41. VIH overshoot: VIH (MAX) = VDDQ + 1.5V for a pulse width ≤ 3ns, and
the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot:
VIL (MIN) = –1.5V for a pulse width ≤ 3ns, and the pulse width can not be
greater than 1/3 of the cycle rate.
42. VDD and VDDQ must track each other.
43. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ
(MIN) will prevail over tDQSCK (MIN) + tRPRE (MAX) condition.
44. tRPST end point and tRPRE begin point are not referenced to a specific
voltage level but specify when the device output is no longer driving (tRPST)
or begins driving (tRPRE).
LOGIC Devices Incorporated
www.logicdevices.com
24
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
AC Switching diagrams reference 16 bits, LDI’s IMOD contains (5) 16 bit devices totaling 80 bits
Figure 8 - Read Burst
T0
T1
T2
Command
READ
NOP
NOP
Address
Bank a,
Col n
CK#
T2n
T3
T3n
T4
T5
NOP
NOP
T4
T5
NOP
NOP
CK
NOP
CL = 2
DQS
DO
n
DQ
T0
T1
T2
Command
READ
NOP
NOP
Address
Bank a,
Col n
CK#
T2n
T3
T3n
CK
NOP
CL = 2.5
DQS
DO
n
DQ
T0
T1
T2
T3
Command
READ
NOP
NOP
NOP
Address
Bank a,
Col n
T3n
T4
T4n
T5
CK#
CK
NOP
NOP
CL = 3
DQS
DO
n
DQ
Transitioning Data
Notes:
LOGIC Devices Incorporated
1.
2.
3.
4.
Don’t Care
DO n = data-out from column n.
BL = 4.
Three subsequent elements of data-out appear in the programmed order following DO n.
Shown with nominal t AC, t DQSCK, and t DQSQ.
www.logicdevices.com
25
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Figure 9 - Consecutive Read Burst
T0
T1
T2
Command
READ
NOP
READ
Address
Bank,
Col n
CK#
T2n
T3
T3n
T4
T4n
T5
T5n
CK
NOP
NOP
NOP
Bank,
Col b
CL = 2
DQS
DO
n
DQ
CK#
T0
T1
READ
NOP
T2
DO
b
T2n
T3
T3n
T4
T4n
T5
T5n
CK
Command
Address
READ
Bank,
Col n
NOP
NOP
NOP
Bank,
Col b
CL = 2.5
DQS
DO
n
DQ
T0
T1
Command
READ
NOP
Address
Bank,
Col n
CK#
DO
b
T2
T3
T3n
READ
NOP
T4
T4n
T5
T5n
CK
NOP
NOP
Bank,
Col b
CL = 3
DQS
DO
n
DQ
DO
b
Transitioning Data
Notes:
LOGIC Devices Incorporated
Don’t Care
1. DO n (or b) = data-out from column n (or column b).
2. BL = 4 or BL = 8 (if BL = 4, the bursts are concatenated; if BL = 8, the second burst interrupts
the first).
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Three (or seven) subsequent elements of data-out appear in the programmed order following DO b.
5. Shown with nominal t AC, t DQSCK, and t DQSQ.
6. Example applies only when READ commands are issued to same device.
www.logicdevices.com
26
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Figure 10 - Nonconsecutive Read Burst
CK#
T0
T1
T2
READ
NOP
NOP
T2n
T3
T3n
T4
T5
NOP
NOP
T5n
T6
CK
Comman d
Add ress
READ
Bank,
Col n
NOP
Bank,
Col b
CL = 2
DQS
DO
DQ
CK#
DO
b
n
T0
T1
T2
READ
NOP
NOP
T2n
T3
T3n
T4
T5
NOP
NOP
T5n
T6
CK
Comman d
Add ress
READ
Bank,
Col n
NOP
Bank,
Col b
CL = 2.5
DQS
DO
n
DQ
CK#
T0
T1
T2
READ
NOP
NOP
DO
b
T3
T3n
T4n
T4
T5
T6
NOP
NOP
CK
Comman d
Add ress
READ
Bank,
Col n
NOP
Bank,
Col b
CL = 3
DQS
DO
n
DQ
DO
b
Transitioning Data
Notes:
LOGIC Devices Incorporated
Don ’t Care
1. DO n (or b) = data-out from column n (or column b).
2. BL = 4 or BL = 8 (if BL = 4, the bursts are concatenated; if BL = 8, the second burst interrupts
the first).
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Three (or seven) subsequent elements of data-out appear in the programmed order following DO b.
5. Shown with nominal t AC, t DQSCK, and t DQSQ.
www.logicdevices.com
27
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Figure 11 - Random Read Accesses
CK#
T0
T1
T2
T2n
READ
READ
READ
Bank,
Col n
Bank,
Col x
Bank,
Col b
T3
T3n
T4
T4n
T5
T5n
CK
Comman d
Add ress
READ
NOP
NOP
Bank,
Col g
CL = 2
DQS
DO
n
DQ
CK#
T0
T1
T2
DO
n'
T2n
DO
x
T3
DO
x'
T3n
DO
b
T4
DO
b'
T4n
DO
g
T5
T5n
CK
Command
READ
READ
READ
READ
Address
Bank,
Col n
Bank,
Col x
Bank,
Col b
Bank,
Col g
NOP
NOP
CL = 2.5
DQS
DO
n
DQ
DO
n'
T0
T1
T2
T3
Command
READ
READ
READ
READ
Address
Bank,
Col n
Bank,
Col x
Bank,
Col b
Bank,
Col g
CK#
DO
x
T3n
DO
x'
T4
DO
b
T4n
DO
b'
T5
T5n
CK
NOP
NOP
CL = 3
DQS
DO
n
DQ
DO
n'
DO
x
Transitioning Data
Notes:
LOGIC Devices Incorporated
1.
2.
3.
4.
5.
DO
x'
DO
b
DO
b'
Don’t Care
DO n (or x or b or g) = data-out from column n (or column x (or column b or column g).
BL = 2, BL = 4, or BL = 8 (if BL = 4 or BL = 8, the following burst interrupts the previous).
n', x', b', or g' indicate the next data-out following DO n, DO x, DO b, or DO g, respectively.
READs are to an active row in any bank .
Shown with nominal t AC, t DQSCK, and t DQSQ.
www.logicdevices.com
28
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Figure 12 - Terminating a Read Burst
T0
T1
T2
READ
BST1
NOP
T2n
T3
T4
T5
NOP
NOP
NOP
T3
T4
T5
NOP
NOP
NOP
T4
T5
NOP
NOP
CK#
CK
Command
Address
Bank a ,
Col n
CL = 2
DQS
DO
n
DQ
T0
T1
T2
Command
READ
BST1
NOP
Address
Bank a,
Col n
CK#
T2n
CK
CL = 2.5
DQS
DO
n
DQ
T0
T1
T2
T3
Command
READ
BST1
NOP
NOP
Address
Bank a,
Col n
T3n
CK#
CK
CL = 3
DQS
DO
n
DQ
Transitioning Data
Notes:
LOGIC Devices Incorporated
1.
2.
3.
4.
5.
Don’t Care
Page remains open.
DO n = data-out from column n.
BL = 4.
Subseqent element of data-out appears in the programmed order following DO n.
Shown with nominal t AC, t DQSCK, and t DQSQ.
www.logicdevices.com
29
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Figure 13 - Read to Write
T0
T1
T2
Command
READ
1
BST
NOP
Address
Bank,
Col n
CK#
T2n
T3
T4
T4n
T5
T5n
CK
WRITE
NOP
NOP
Bank,
Col b
t DQSS
(NOM)
CL = 2
DQS
DO
n
DQ
DI
b
DM
T0
T1
T2
Command
READ
1
BST
NOP
Address
Bank,
Col n
CK#
T2n
T3
T4
T3n
T5
T5n
CK
NOP
WRITE
NOP
Bank,
Col b
t DQSS
(NOM)
CL = 2.5
DQS
DO
n
DQ
DI
b
DM
T0
T1
T2
T3
Command
READ
BST1
NOP
NOP
Address
Bank a,
Col n
CK#
T3n
T4
T5
T5n
WRITE
NOP
CK
t DQSS
(NOM)
CL = 3
DQS
DO
n
DQ
DI
b
DM
Transitioning Data
Notes:
LOGIC Devices Incorporated
1.
2.
3.
4.
5.
6.
Don’t Care
Page remains open.
DO n = data-out from column n; DI b = data-in from column b .
BL = 4 (applies for bursts of 8 as well; if BL = 2, the BURST command shown can be NOP).
One subsequent element of data-out appears in the programmed order following DO n.
Data-in elements are applied following DI b in the programmed order.
Shown with nominal t AC, t DQSCK, and t DQSQ.
www.logicdevices.com
30
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Figure 14 - Read to Precharge
T0
T1
T2
Command
READ
NOP
PRE
Address
Bank a,
Col n
CK#
T2n
T3
T3n
T4
T5
NOP
ACT
CK
NOP
Bank a,
(a or all )
Bank a,
Row
t RP
CL = 2
DQS
DO
n
DQ
T0
T1
Command
READ
NOP
Address
Bank a,
Col n
CK#
T2
T2n
T3
T3n
T4
T5
CK
PRE
NOP
Bank a,
(a or all )
NOP
ACT
Bank a,
Row
t RP
CL = 2.5
DQS
DO
n
DQ
T0
T1
T2
T3
Command
READ
NOP
PRE
NOP
Address
Bank a,
Col n
CK#
T3n
T4
T4n
T5
CK
Bank a,
(a or all )
NOP
Bank a,
Row
t RP
CL = 3
ACT
DQS
DO
n
DQ
Transitioning Data
Notes:
LOGIC Devices Incorporated
Don’t Care
t RAS
1. Provided
(MIN) is met, a READ command with auto precharge enabled would cause a
precharge to be performed at x number of clock cycles after the READ command, where
x = BL/2.
2. DO n = data-out from column n.
3. BL = 4 or an interrupted burst of 8.
4. Three subsequent elements of data-out appear in the programmed order following DO n.
5. Shown with nominal t AC, t DQSCK, and t DQSQ.
6. READ-to-PRECHARGE equals two clocks, which allows two data pairs of data-out; it is also
assumed that t RAS (MIN) is met.
7. An ACTIVE command to the same bank is only allowed if t RC (MIN) is met.
www.logicdevices.com
31
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Figure 15 - Bank Read Without Precharge
CK#
T1
T0
T2
T3
T4
T5
2
READ
1
NOP
3
PRE
T5n
T6
T6n
T7
T8
1
NOP
ACT
CK
t IS t IH
t CK
t CH
t CL
CKE
t IS
t IH
1
NOP
Command
1
NOP
ACT
t IS
Address
Row
A10
Row
1
NOP
t IH
Col n
t IS
Row
t IH
All banks
4
Row
One bank
t IS
BA0, BA1
t IH
Bank x
5
Bank x
t RCD
Bank x
Bank x
CL = 2
t RAS3
t RP
t RC
DM
Case 1: t AC (MIN) and t DQSCK(MIN)
t RPRE
t DQSCK(MIN)
t RPST
DQS
t LZ (MIN)
DO
n
DQ
t LZ (MIN)
Case 2: t AC (MAX) and t DQSCK(MAX)
t AC (MIN)
t RPRE t DQSCK (MAX)
t RPST
DQS
DO
n
DQ
t AC (MAX)
t HZ (MAX)
Transitioning Data
Notes:
LOGIC Devices Incorporated
Don’t Care
1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. BL = 4.
3. The PRECHARGE command can only be applied at T5 if t RAS (MIN) is met.
4. Disable auto precharge.
5. “Don’t Care” if A10 is HIGH at T5.
6. DO n (or b) = data-out from column n (or column b); subsequent elements are provided in
the programmed order.
www.logicdevices.com
32
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Figure 16 - Data Output Timing – tDQSQ, tQH, and Data Valid Window
CK#
T1
T2
T2n
T3
T3n
T4
CK
t HP1
t HP1
t HP1
t DQSQ 2
t HP1
t HP1
t HP1
t DQSQ 2
t DQSQ 2
t DQSQ 2
LDQS3
DQ (last data valid)
4
4
DQ
4
DQ
4
DQ
DQ
DQ
DQ (first data no longer valid)
4
Lower byte
DQ
4
4
4
t QH5
t QH5
DQ (last data valid)
4
4
DQ (first data no longer vali d)
DQ0–DQ7 and LDQS Collectively
6
T3
T3n
T2
T2n
T3
T3n
T2
T2n
T3
T3n
Data valid
window
Data valid
window
DQ (last data valid)
t QH5
T2n
t DQSQ 2
t DQSQ 2
UDQS
t QH5
T2
Data valid
window
t DQSQ 2
Data valid
window
t DQSQ 2
3
7
Upper byte
7
DQ
7
DQ
7
DQ
7
DQ
7
DQ
7
DQ
7
DQ (first data no longer vali d)
t QH5
DQ (last data valid)
DQ (first data no longer vali d)
7
7
6
DQ8–DQ15 and UDQS Collectively
Notes:
LOGIC Devices Incorporated
t QH5
t QH5
t QH5
T3
T3n
T2
T2n
T2
T2n
T2
T2n
T3
T3n
Data valid
window
Data valid
window
Data valid
window
Data valid
window
T3
T3n
1. t HP is the lesser of t CL or t CH clock transition collectively when a bank is active.
2. t DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
transition, and ends with the last valid DQ transition.
3. DQ transitioning after DQS transition define the t DQSQ window. LDQS defines the lower
byte, and UDQS defines the upper byte.
4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
5. t QH is derived from t HP: t QH = t HP - t QHS.
6. The data valid window is derived for each DQS transition and is t QH - t DQSQ.
7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.
www.logicdevices.com
33
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Figure 17 - Data Output Timing - tAC and tDQSCK
CK#
T01
T1
T2
T3
T2n
T3n
T4
T4n
CK
DQ (last data valid)
T2
DQ (first data valid)
All DQ values collectively 4
t LZ (MIN)
LOGIC Devices Incorporated
T6
t RPST
t RPRE
DQS or LDQS/UDQS 3
Notes:
T5n
t
t DQSCK 2 (MAX) HZ (MAX)
t DQSCK 2 (MIN)
t DQSCK2 (MAX)
t DQSCK2 (MIN)
t LZ (MIN)
T5
T2n
T3
T3n
T2
T2n
T3
T3n
T2
T2n
T3
T3n
t AC5 (MIN)
T4
T4n
T5
T5n
T4
T4n
T5
T5n
T4
T4n
T5
T5n
t AC5 (MAX)
t HZ (MAX)
1. READ command with CL = 2 issued at T0.
2. t DQSCK is the DQS output window relative to CK and is the “long term” component of the
DQS skew.
3. DQ transitioning after DQ S transition define the t DQSQ window.
4. All DQ must transition by t DQSQ after DQS transitions, regardless of t AC.
5. t AC is the DQ output window relative to CK and is the “long term” component of DQ skew.
6. t LZ (MIN) and t AC (MIN) are the first valid signal transitions.
7. t HZ (MAX) and t AC (MAX) are the latest valid signal transitions.
www.logicdevices.com
34
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Figure 18 - Write Burst
T0
T1
T2
Command
WRITE
NOP
NOP
Address
Bank a,
Col b
CK#
T2n
T3
CK
t DQSS (NOM)
DQS
NOP
t DQSS
DI
b
DQ
DM
t DQSS (MIN)
DQS
DQ
t DQSS
DI
b
DM
t DQSS (MAX)
DQS
DQ
t DQSS
DI
b
DM
Transitioning Data
Notes:
LOGIC Devices Incorporated
1.
2.
3.
4.
Don’t Care
DI b = data-in for column b.
Three subsequent elements of data-in are applied in the programmed order following DI b.
An uninterrupted burst of 4 is shown.
A10 is LOW with the WRITE command (auto precharge is disabled).
www.logicdevices.com
35
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Figure 19 - Consecutive Write to Write
CK#
T0
T1
W RITE
NOP
T1n
T2
T2n
T3
T3n
T4
T4n
T5
CK
Command
Address
Bank,
Col b
t DQSS (NOM)
W RITE
NOP
NOP
NOP
Bank,
Col n
t DQSS
DQS
DI
b
DQ
DI
n
DM
Transitioning Data
Notes:
LOGIC Devices Incorporated
1.
2.
3.
4.
5.
Don’t Care
DI b (or n) = data-in from column b (or column n).
Three subsequent elements of data-in are applied in the programmed order following DI b.
Three subsequent elements of data-in are applied in the programmed order following DI n.
An uninterrupted burst of 4 is shown.
Each WRITE command may be to any bank.
www.logicdevices.com
36
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Figure 20 - Nonconsecutive Write to Write
CK#
T0
T1
T1n
W R IT E
NOP
T2
T2n
T3
T4
T4n
T5
T5n
CK
Command
Address
NOP
WRITE
Bank,
Col b
NOP
NOP
Bank,
Col n
t DQSS
t DQSS (NOM)
DQS
DI
b
DQ
DI
n
DM
Transitioning Data
Notes:
1.
2.
3.
4.
5.
Don’t Care
DI b (or n) = data-in from column b (or column n).
Three subsequent elements of data-in are applied in the programmed order following DI b.
Three subsequent elements of data-in are applied in the programmed order following DI n.
An uninterrupted burst of 4 is shown.
Each WRITE command may be to any bank.
Figure 21 - Random Write Cycles
CK#
T0
T1
T1n
T2
T2n
T3
T3n
T4
WRITE
WRITE
WRITE
WRITE
WRITE
Bank,
Col b
Bank,
Col x
Bank,
Col n
Bank,
Col a
Bank,
Col g
T4n
T5
T5n
CK
Command
Address
NOP
t DQSS (NOM)
DQS
DQ
DI
b
DI
b'
DI
x
DI
x'
DI
n
DI
n'
DI
a
DI
a'
DI
g
DI
g'
DM
Transitioning Data
Notes:
LOGIC Devices Incorporated
Don’t Care
1. DI b (or x or n or a or g) = data-in from column b (or column x, or column n, or column a, or
column g).
2. b', x', n', a' or g' indicate the next data-in following DO b, DO x, DO n, DO a, or DO g,
respectively.
3. Programmed BL = 2, BL = 4, or BL = 8 in cases shown.
4. Each WRITE command may be to any bank.
www.logicdevices.com
37
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Figure 22 - Write to Read Uninterrupted
CK#
T0
T1
W RITE
NOP
T1n
T2
T2n
T3
T4
T5
T6
T6n
NOP
REA D
NOP
NOP
CK
Command
NOP
t WTR
Bank a,
Col b
Address
t DQSS (NOM)
Bank a,
Col n
t DQSS
CL = 2
DQS
DI
b
DQ
DO
n
DM
t DQSS (MIN)
t DQSS
CL = 2
DQS
DI
b
DQ
DO
n
DM
t DQSS (MAX)
t DQSS
CL = 2
DQS
DI
b
DQ
DO
n
DM
Transitioning Data
Notes:
LOGIC Devices Incorporated
Don’t Care
1.
2.
3.
4.
5.
DI b = data-in for column b; DO n = data-out for column n.
Three subsequent elements of data-in are applied in the programmed order following DI b.
An uninterrupted burst of 4 is shown.
t WTR is referenced from the first positive CK edge after the last data-in pair.
The READ and WRITE commands are to the same device. However, the READ and WRITE
commands may be to different devices, in which case t WTR is not required, and the READ
command could be applied earlier.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
www.logicdevices.com
38
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Figure 23 - Write to Read Interrupting
CK#
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T3n
T4
T5
T5n
NOP
NOP
T6
T6n
CK
Command
NOP
READ
NOP
t WTR
Bank a,
Col b
Address
t DQSS (NOM)
Bank a,
Col n
t DQSS
CL = 2
DQS
DI
b
DQ
DO
n
DM
t DQSS (MIN)
t DQSS
CL = 2
DQS
DI
b
DQ
DO
n
DM
t DQSS (MAX)
t DQSS
CL = 2
DQS
DI
b
DQ
DO
n
DM
Transitioning Data
Notes:
LOGIC Devices Incorporated
1.
2.
3.
4.
5.
6.
7.
Don’t Care
DI b = data-in for column b; DO n = data-out for column n.
An interrupted burst of 4 is shown; two data elements are written.
One subsequent element of data-in is applied in the programmed order following DI b.
t WTR is referenced from the first positive CK edge after the last data-in pair.
A10 is LOW with the WRITE command (auto precharge is disabled).
DQS is required at T2 and T2n (nominal case) to register DM.
If the burst of 8 is used, DM and DQS are required at T3 and T3n because the READ
command will not mask these two data elements.
www.logicdevices.com
39
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Figure 24 - Write to Read, Odd Number of Data, Interrupting
CK#
T0
T1
W RITE
NOP
T1n
T2
T2n
T3
T3n
T4
T5
NOP
NOP
T5n
T6
T6n
CK
Command
NOP
READ
NOP
t WTR
Bank a,
Col b
Address
t DQSS (NOM)
Bank a,
Col n
t DQSS
CL = 2
DQS
DI
b
DQ
DO
n
DM
t DQSS
t DQSS (MIN)
CL = 2
DQS
DI
b
DQ
DO
n
DM
t DQSS (MAX)
t DQSS
CL = 2
DQS
DI
b
DQ
DO
n
DM
Transitioning Data
Notes:
LOGIC Devices Incorporated
Don’t Care
1. DI b = data-in for column b; DO n = data-out for column n.
2. An interrupted burst of 4 is shown; one data element is written.
3. t WTR is referenced from the first positive CK edge after the last desired data-in pair (not
the last two data elements).
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. DQS is required at T1n, T2, and T2n (nominal case) to register DM.
6. If the burst of 8 is used, DM and DQS are required at T3–T3n because the READ command
will not mask these data elements.
www.logicdevices.com
40
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Figure 25 - Write to Precharge - Uninterrupted
CK#
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T4
T5
NOP
PRE
T6
CK
Command
NOP
NOP
Bank,
(a or all )
Bank a,
Col b
Address
t DQSS (NOM)
NOP
t RP
t WR
t DQSS
DQS
DI
b
DQ
DM
t DQSS (MIN)
t DQSS
DQS
DI
b
DQ
DM
t DQSS (MAX)
t DQSS
DQS
DI
b
DQ
DM
Transitioning Data
Notes:
LOGIC Devices Incorporated
Don’t Care
1.
2.
3.
4.
5.
DI b = data-in for column b.
Three subsequent elements of data-in are applied in the programmed order following DI b.
An uninterrupted burst of 4 is shown.
t WR is referenced from the first positive CK edge after the last data-in pair.
The PRECHARGE and WRITE commands are to the same device. However, the PRECHARGE
and WRITE commands may be to different devices, in which case t WR is not required and
the PRECHARGE command could be applied earlier.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
www.logicdevices.com
41
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Figure 26 - Write to Precharge - Interrupting
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T6
CK#
CK
Command
NOP
NOP
PRE
NOP
Bank,
(a or all )
Bank a,
Col b
Address
t DQSS (NOM)
NOP
t RP
t WR
t DQSS
DQS
DI
b
DQ
DM
t DQSS (MIN)
t DQSS
DQS
DI
b
DQ
DM
t DQSS (MAX)
t DQSS
DQS
DI
b
DQ
DM
Transitioning Data
Notes:
LOGIC Devices Incorporated
1.
2.
3.
4.
5.
6.
7.
Don’t Care
DI b = data-in for column b.
Subsequent element of data-in is applied in the programmed order following DI b.
An interrupted burst of 8 is shown; two data elements are written.
t WR is referenced from the first positive CK edge after the last data-in pair.
A10 is LOW with the WRITE command (auto precharge is disabled).
DQS is required at T4 and T4n (nominal case) to register DM.
If the burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n.
www.logicdevices.com
42
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
AC SWITCHING DIAGRAMS
Figure 27 - Data Input Timing
1
T0
T1
T1n
T2
T2n
T3
CK#
CK
t DSH2
t DQSS
t DSS3
t DSH2
t DSS3
t DQSL
t DQSH
t WPST
DQS
t WPRES t WPRE
DI
b
DQ
DM
t DS
t DH
Transitioning Data
Notes:
LOGIC Devices Incorporated
1.
2.
3.
4.
5.
Don’t Care
WRITE command issued at T0.
t
DSH (MIN) generally occurs during t DQSS (MIN).
t
DSS (MIN) generally occurs during t DQSS (MAX).
For x16, LDQS controls the lower byte and UDQS controls the upper byte.
DI b = data-in from column b.
www.logicdevices.com
43
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
Mechanical Drawing
25 ± 0.15
2.35 ± 0.15
0.60 ± 0.04
19.05 ± 0.10
SQ
25 ± 0.15
1.27
± 0.10
1.75 ± 0.11
1.27 ± 0.10
219 X 0.76 ± 0.05
8.89 ± 0.10
SQ
LOGIC Devices Incorporated
www.logicdevices.com
44
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A
preliminary Information
L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
Ordering Information
Package Outline Dimensions
Part Number
Core FREQ.
Data Transfer Rate
Package
Grade
L9D125G80BG4I6
166 MHz
333 Mbps
25mm2-219 LBGA
INDUSTRIAL
L9D125G80BG4E6
166 MHz
333 Mbps
25mm2-219 LBGA
EXTENDED
L9D125G80BG4M6
166 MHz
333 Mbps
25mm2-219 LBGA
MIL-TEMP
L9D125G80BG4I75
133 MHz
266 Mbps
25mm2-219 LBGA
INDUSTRIAL
L9D125G80BG4E75
133 MHz
266 Mbps
25mm2-219 LBGA
EXTENDED
L9D125G80BG4M75
133 MHz
266 Mbps
25mm2-219 LBGA
MIL-TEMP
L9D125G80BG4I8
125 MHz
250 Mbps
25mm2-219 LBGA
INDUSTRIAL
L9D125G80BG4E8
125 MHz
250 Mbps
25mm2-219 LBGA
EXTENDED
L9D125G80BG4M8
125 MHz
250 Mbps
25mm2-219 LBGA
MIL-TEMP
L9D125G80BG4I10
100 MHz
200 MHz
25mm2-219 LBGA
INDUSTRIAL
L9D125G80BG4E10
100 MHz
200 MHz
25mm2-219 LBGA
EXTENDED
L9D125G80BG4M10
100 MHz
200 MHz
25mm2-219 LBGA
MIL-TEMP
Revision History
Revision
Engineer
Issue Date Description Of Change
A
DH/JM
11/12/2008
INITIATE
LOGIC Devices Incorporated reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its
products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. LOGIC Devices does not assume any liability arising out
of the application or use of any product or circuit described herein. In no event shall any liability exceed the product purchase price. Products of
LOGIC Devices are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with LOGIC Devices. Furthermore, LOGIC Devices does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user.
LOGIC Devices Incorporated
www.logicdevices.com
45
High Performance, Integrated Memory Module Product
Nov 12, 2008 LDS-L9D125G80BG4-A