PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) Benefits FEATURES DDR3 Integrated Module [iMOD]: • Vcc=VccQ=1.5V ± 0.075V • 1.5V center-terminated, push/pull I/O • Package: 16mm x 22mm, 13 x 21 matrix w/ 271balls • Matrix ball pitch: 1.00mm Space saving footprint Thermally enhanced, Impedance matched, integrated packaging Differential, bidirectional data strobe 8n-bit prefetch architecture 8 internal banks (per word, 4 words integrated in package) Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals. CAS (READ) latency (CL): 6, 8, and 10 CAS (WRITE) latency (CWL): 6, 7 and 8 Fixed burst length (BL) of 8 and burst chop (BC) of 4 Selectable BC4 or BL8 on-the-fly (OTF) Self/Auto Refresh modes Operating Temperature Range (Case Temp=Tc) • Industrial: -40˚C to 85˚C supporting SELF & AUTO REFRESH • Extended: -40˚C to 105˚C; manual REFRESH only • Mil-Temp: -55˚C to 125˚C; manual REFRESH only CORE clocking frequencies: • Industrial: 667MHz, 533MHz and 400MHz • Extended: 533MHz and 400MHz • Mil-Temp: 400MHz Data Transfer Rates: • Industrial: 1333, 1066 and 800 Mbps • Extended: 1066 and 800 Mbps • Mil-Temp: 800 Mbps Write leveling Multipurpose register Output Driver Calibration 40% space savings while providing a surface mount friendly pitch (1.00mm) Reduced I/O routing (34%) 30% improvement in routings for your memory array Reduced trace lengths due to the highly integrated, impedance matched packaging Thermally enhanced packaging technology allow silicon integration without performance degradation due to power dissipation (heat) High TCE organic laminate interposer for improved glass stability over a wide operating temperature Suitability of use in High Reliability applications requiring Mil-temp, nonhermetic device operation *Note: This integrated product and/or its specifications are subject to change without notice. Latest document should be retrieved from LDI prior to your design consideration. iMOD Part Information ORDER NUMBER SPEED GRADE DEVICE GRADE L9D340G64BG2I15 DDR3-1333 Industrial L9D340G64BG2E19 DDR3-1066 Extended L9D340G64BG2M25 DDR3-800 Mil-Temp PKG FOOTPRINT 16mm x 22mm I/O PITCH 271 1.00mm PKG NO. BG2 integrated module products LOGIC Devices Incorporated www.logicdevices.com 1 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) INTEGRATED VS. MONOLITHIC SOLUTIONS - HIGHLIGHTS Monolithic Soluon O P T I O N S IMOD Soluon DDR3 DDR3 DDR3 DDR3 9.0mm x 15.5mm 9.0mm x 15.5mm 9.0mm x 15.5mm 9.0mm x 15.5mm 96 ball FBGA 96 ball FBGA 96 ball FBGA 96 ball FBGA 22.0 S A V I N G S L9D34G64BG2M3 LOT CODE 22.0 DATE CODE ASSM CODE 16.0 16.0 352mm2 271 Balls/Locaons 4 x 139.5mm2 = 558mm2 PLUS 4 x 96 pins = 384 pins total Area I/O ~40% 30% TABLE 1: KEY TIMING PARAMETERS Information CORE Freq. [MHz] Support Data Rate [Mbps] Support L9D340G64BG2I15 667/533/400 1333/1066/800 Device Speed Speed Part Ordering Grade Grade Mark Target tRCD tRP CL tRCD-tRP-CL [ns] [ns] [ns] 10-10-10/8-8-8/6-6-6 15 15 15 INDUSTRIAL DDR3-1333 15 EXTENDED DDR3-1066 19 L9D340G64BG2E19 533/400 1066/800 8-8-8/6-6-6 15 15 15 MIL-TEMP DDR3-800 25 L9D340G64BG2M25 400 800 6-6-6 15 15 15 LOGIC Devices Incorporated www.logicdevices.com 2 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FEATURES FIGURE 1 - 1Gb DDR3 PART NUMBERS Sample Part Number: L9D3 40G L9D340G64BG2M15 BG2 64 DDR3 iMOD Code Total Density= 4.0Gb 25 Speed Grade t CK = 2.50ns 19 t CK = 1.875ns 15 t CK = 1.5ns Organization= 64M x 64 16 x 22mm PBGA Temperature Code Industrial Temperature I Extended Temperature E Military Temperature M Note: Not all options can be combined. Please see our Part Catalog for available offerings. TABLE 2: ADDRESSING Parameter LOGIC Devices Incorporated 64 Meg x 64 Configuration [8 Meg x 8 banks x 16] x 4 Refresh Count 8K ROW Addressing 8K (A[12:0]) Back Addressing 8 (BA[2:0]) Column Addressing 1K (A[9:0]) www.logicdevices.com 3 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) STATE DIAGRAM FIGURE 2 - SIMPLIFIED STATE DIAGRAM CKE L Power applied Power on Reset Procedure MRS, MPR, write leveling Initialization Self refresh SRE ZQCL MRS SRX From any state RESET ZQ Calibration REF ZQCL/ZQCS Idle Refreshing PDE ACT PDX Active PowerDown Preharge PowerDown Activating PDX CKE L CKE L PDE Bank Active WRITE WRITE READ WRITE AP READ AP READ Writing READ Reading WRITE READ AP WRITE AP WRITE AP READ AP PRE, PREA Writing PRE, PREA PRE, PREA Preharging Reading Automatic Sequence Command Sequence ACT = ACTIVATE MPR = Multipurpose register MRS = Mode register set PDE = Power-down entry PDX = Power-down exit PRE = PRECHARGE LOGIC Devices Incorporated www.logicdevices.com PREA=PRECHARGE ALL READ = RD, RDS4, RDS8 READ AP = RDAP, RDAPS4, RDAPS8 REF = REFRESH RESET = START RESET PROCEDURE SRE = Self refresh entry 4 SRX = Self refresh exit WRITE = WR, WRS4, WRS8 WRITE AP = WRAP, WRAPS4, WRAPS8 ZQCL = ZQ LONG CALIBRATION ZQCS = ZQ SHORT CALIBRATION High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) INDUSTRIAL TEMPERATURE FUNCTIONAL DESCRIPTION The industrial temperature (I) device requires the case temperature not exceed -40˚C or +85˚C. JEDEC specifications require the REFRESH rate to double when Tc exceeds +85˚C; this also requires use of the hightemperature SELF REFRESH option. Additionally, ODT resistance and the INPUT/OUTPUT impedance must be derated when the Tc is <0˚C or >+85˚C. The DDR3 SDRAM uses double data rate architecture to achieve high speed operation. The double data rate (DDR) architecture is an 8n prefetch with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE access for the DDR3 SDRAM consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal memory core and eight corresponding n-bit-wide, one-half-clock-cycle data transfer at the I/O pin. The differential strobes (LDQSx, LDQSx\, UDQSx, UDQSx\) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The READ data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. EXTENDED TEMPERATURE The Extended temperature (E) device requires the case temperature not exceed -40˚C or +105˚C. JEDEC specifications require the refresh rate to double when Tc exceeds +85˚C; this also requires use of the hightemperature SELF REFRESH option. Additionally, ODT resistance and the INPUT/OUTPUT impedance must be derated when the Tc is <0˚C or >85˚C. The DDR3 SDRAM operates from a differential clock (CKx, CKx\). The crossing of CK going HIGH and CK\ going LOW is referred to as the positive edge of Clock (CK). Control, Command, and Address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble. MILITARY, EXTREME OPERATING TEMPERATURE READ and WRITE accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and the starting column location for the burst access. The Mil-Temp (M) device requires the case temperature not exceed -55˚C or +125˚C. JEDEC requires the REFRESH rate double when Tc exceeds +85˚C and LDI recommends an additional derating as specified in this document as to properly maintain the DRAM core cell charge at temperatures above Tc>105˚C. DDR3 SDRAM devices use READ and WRITE BL8 and BC4. An AUTO PRECHARGE function may be enabled to provide a self-timed ROW PRECHARGE that is initiated at the end of the burst access. As with standard DDR SDRAM devices, the pipelined, multi-bank architecture of the DDR3 SDRAM allows for concurrent operation, thereby providing high bandwidth by hiding ROW PRECHARGE and ACTIVATION time. A SELF REFRESH mode is provided for all temperature grade offerings along with AUTO SELF REFRESH for Industrial product, as well as, powersaving, POWER-DOWN mode. LOGIC Devices Incorporated www.logicdevices.com 5 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 3 - FUNCTIONAL BLOCK DIAGRAM CS\ RAS\ CAS\ CKE WE\ VCCQ VCC VSSQ VSS RESET\ A0-A12, BA0-1 A, BA CK0 CK0\ LDQS0 LDQS0\ UDQS0 UDQS0\ RST\ VSS VSSQ VCC VCCQ WE\ CKE CAS\ RAS\ CS\ D0 LDM0 UDM0 A, BA CK1 CK1\ LDQS1 LDQS1\ UDQS1 UDQS1\ LDM1 UDM1 CK2 CK2\ LDQS2 LDQS2\ UDQS2 UDQS2\ LDM2 UDM2 CK3 CK3\ LDQS3 LDQS3\ UDQS3 UDQS3\ D3 UDM3 www.logicdevices.com DQ 8 DQ 15 DQ 0 DQ 7 DQ 16 DQ 23 DQ 8 DQ 15 DQ 24 DQ 31 DQ 0 DQ 7 DQ 32 DQ 39 DQ 8 DQ 15 DQ 40 DQ 47 DQ 0 DQ 7 DQ 48 DQ 55 DQ 8 DQ 15 DQ 56 DQ 63 RST\ VSS VSSQ VCC VCCQ WE\ CKE CAS\ RAS\ CS\ LDM3 LOGIC Devices Incorporated DQ 8 DQ 15 RST\ VSS VSSQ VCC VCCQ WE\ CKE CAS\ RAS\ CS\ D2 A, BA DQ 0 DQ 7 RST\ VSS VSSQ VCC VCCQ WE\ CKE CAS\ RAS\ CS\ D1 A, BA DQ 0 DQ 7 6 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) BALL /SIGNAL LOCATION (PBGA) FIGURE 4 - SDRAM - DDR3 PINOUT TOP VIEW 1 A 2 3 4 5 6 7 8 9 10 11 12 13 VssQ VccQ VccQ NC NC VssQ NC NC VccQ VccQ VssQ VssQ A Vcc Vss Vcc Vcc Vss Vcc Vcc Vss Vcc Vss VssQ B B VssQ C VccQ Vcc Vss NC ZQ3 ZQ2 NC NC NC NC Vss Vcc VccQ C D VccQ Vss NC NC ZQ0 ZQ1 NC NC DQ34 CK3 CK3\ Vss VccQ D E NC DQ35 DQ51 NC NC DQ50 DQ53 DQ37 CK2\ CK2 NC E F NC DQ52 DQ36 DQ33 NC BA2 RFU DQ39 LDQS2 LDQS3 DQ48 DQ32 NC F G NC LDM3 LDM2 DQ49 DQ43 DQ59 RFU DQ55 DQ58 DQ42 NC G H NC DQ38 DQ54 DQ60 DQ57 UDM2 Vss DQ63 DQ56 DQ40 NC H J NC UDM3 DQ44 DQ41 DQ46 DQ62 Vcc UDQS2\ DQ47 NC J K VssQ Vcc A6 A10 A9 Vcc Vss Vcc A3 A12 RFU Vcc VssQ K L VssQ Vss A0 A11 Vcc Vss VrefDA Vss Vcc A1 BA1 Vss VssQ L M VssQ Vcc A2 A4 A8 Vcc Vss Vcc BA0 A5 A7 Vcc VssQ M N NC DQ15 UDQS0\ Vcc DQ30 DQ14 DQ9 DQ12 UDM1 NC N P NC DQ8 DQ24 DQ31 Vss UDM0 DQ25 DQ28 DQ22 DQ6 NC P R NC DQ10 DQ26 DQ23 ODT DQ27 DQ11 DQ17 LDM0 LDM1 NC R T NC DQ0 DQ16 DQ7 NC NC NC DQ1 DQ4 DQ20 NC T U NC CK0 CK0\ DQ5 DQ21 DQ18 NC NC CKE WE\ DQ19 DQ3 NC U V VccQ Vss CK1\ CK1 DQ2 RAS\ CAS\ NC NC NC NC Vss VccQ V W VccQ Vcc Vss NC NC CS\ NC NC NC NC Vss Vcc VccQ W Y VssQ Vss Vcc Vss Vcc Vcc Vss Vcc Vcc Vss Vcc Vss VssQ Y AA VssQ VssQ VccQ VccQ NC NC VssQ NC NC VccQ VccQ VssQ VssQ AA 1 2 3 4 5 6 7 8 9 10 11 12 13 UDQS1\ UDQS1 UDQS0 DQ13 DQ29 LDQS1\ LDQS0\ LDQS1 LDQS0 RESET\ VrefCA LDQS2\ LDQS3\ DQ61 DQ45 UDQS2 UDQS3 UDQS3\ GND (Core) V + (Core Power) UNPOPULATED GND (I/O) V + (I/O Power) NC Data IO CNTRL Address Level REF Rev.A, 9/08, 271BGA-1.00MM PITCH - X64, SCB LOGIC Devices Incorporated www.logicdevices.com 7 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 3 - BALL/SIGNAL LOCATION AND DESCRIPTION Ball Assignments Symbol Type Input Address Inputs: Provide the ROW address for ACTIVATE commands, and the column address Description L3, L10, M3, K9, M4, A0, A1, A2, M10, K3, M11, M5, K5, A3, A4, A5, and auto precharge bit (A10) for READY/WRITE commands, to select one location out of the K4, L4, K10 A6, A7, A8, memory array in the respective bank. A10 sampled during a PRECHARGE command determines A9, A10 /AP, whether the PRECHARGE applies to one bank (A10 LOW), bank selected by BA[2:0] or all banks A11, A12 /BC (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VrefCA. A12/BC#: when enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop, LOW = BC4 burst chop). M9, L11, F6 BA0, BA1, BA2 Input Bank Address Inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MRE, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VrefCA. K11, G7, F7 RFU U2, U3, V4, V3, E12, CKX, CKX\ Input Future Address: A13, A14, A15 Input Clock: CKx and CKx\ are differential clock inputs, one differential pair per WORD, four WORDs contained in the L9D3xxG64 product. All control and address input signals are sampled on the E11, D10, D11 crossing of the positive edge of CKx and the negative edge of CKx\. Output data strobes (UDQSx/ UDQSx\ and LDQSx/LDQSx\) is referenced to the crossing of CKx and CKx\. U9 CKE Input Clock Enable: CKE enables and disables internal circuitry and clocks on the SDRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CKx, CKx\, CKE, RESET#, and ODT) are disabled during SELF REFRESH. CKE is referenced to VrefCA. W6 CS\ Input Chip Select: CS\ enables (registered LOW) and disables the command decoder. All commands are masked when CS\ is registered HIGH. CS\ provides for external rank selection on systems with multiple ranks. CS\ is considered part of the command code. CS\ is referenced to VrefCA. R11, P8, R12, N12, LDMx, Input Input Data Mask: LDMx is the Lower-byte of a WORD, UDMx is the Upperbyte of a WORD, the G3, H6, G2, UDMx L9D3xxG64 contains four WORDS. The data mask input, masks WRITE data. Lower byte data masked when LDMx is sampled HIGH, upper byte data masked when UDMx is sampled HIGH. J2 The UDMx and LDMx pins are structured as inputs only, the pins electrical loading is designed to match that of the DQ and LDQSx\, UDQSx and UDQSx\ pins. V6 RAS\ Input ROW Address Strobe/Select: Defines the command being entered along CAS\, WE\, and CS\. This input pin is referenced to VrefCA. V7 CAS\ Input COLUMN Address Strobe/Select: Defines the command being entered along with RAS\, WE\, and CS\. This input pin is referenced to VrefCA. U10 WE\ Input WRITE Enable Input: Defines the command being entered along with CAS\, RAS\,, and CS\. This input pin is referenced to VrefCA. LOGIC Devices Incorporated www.logicdevices.com 8 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 3 - BALL/SIGNAL LOCATION AND DESCRIPTION CONTINUED Ball Assignments Symbol R7 ODT Type Description Input On-Die Termination: ODT enables (when registered HIGH) and disables termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following signals: DQ[63:0], LDQXx\, UDQSx\, UDMx, and LDMx. The ODT input is ignored if disabled via the LOAD MODE register command. ODT is referenced to VrefCA. F5 RESET\ Input RESET: An input control pin, active LOW referenced to Vss. The RESET\ input receiver is a CMOS input defined as a rail to rail signal with DC HIGH ≥ 0.8 x Vcc and DC LOW ≤ 0.2 x VccQ. RESET\ assertion and de-assertion are asynchronous. T5, R3, T4, R2, F9, G11, LDQSx, F10, G12 LDQSx\ N4, N6, N3, N2, J10, J8, UDQSx, J11, J12 UDQSx\ T2, T10, V5, U12, T11, DQ0, DQ1, U4, P12, T6 DQ2, DQ3, Input Data Strobe, LOW Byte (per WORD): Output, edge-aligned with READ data. Input, centeraligned with WRITE data. Input Data Strobe, HIGH Byte (per WORD): Output, edge-aligned with READ data. Input, centeraligned with WRITE data. I/O Data Input/Output: LOW Byte, LOW WORD (WORD 1). Pin referenced to VrefDQ. I/O Data Input/Output: HIGH Byte, LOW WORD (WORD 1). Pin referenced to VrefDQ. I/O Data Input/Output: LOW Byte, WORD 2. Pin referenced to VrefDQ. I/O Data Input/Output: HIGH Byte, WORD 2. Pin referenced to VrefDQ. I/O Data Input/Output: LOW Byte, WORD 3. Pin referenced to VrefDQ. I/O Data Input/Output: HIGH Byte, WORD 3. Pin referenced to VrefDQ. DQ4, DQ5, DQ6, DQ7 P4, N10, R4, R9, N11, DQ8, DQ9, P2, N9, N5 DQ10, DQ11, DQ12, DQ13, DQ14, DQ15 T3, R10, U6, U11, T12, DQ16, DQ17, U5, P11, R6 DQ18, DQ19, DQ20, DQ21, DQ22, DQ23 P5, P9, R5, R8, P10, P3, DQ24, DQ25, N8, P6 DQ26, DQ27, DQ28, DQ29, DQ30, DQ31 F12, F4, D9, E2, F3, DQ32, DQ33, E10, H2, F8 DQ34, DQ35, DQ36, DQ37, DQ38, DQ39 H10, J4, G10, G5, J3, DQ40, DQ41, H12, J5, J9 DQ42, DQ43, DQ44, DQ45, DQ46, DQ47 LOGIC Devices Incorporated www.logicdevices.com 9 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 3 - BALL/SIGNAL LOCATION AND DESCRIPTION CONTINUED Ball Assignments Symbol Type Description F11, G4, E8, E3, F2, E9, DQ48, DQ49, Supply Data Input/Output: LOW Byte, HIGH WORD (WORD 4). Pin referenced to VrefDQ. DQ50, DQ51, H3, G8 DQ52, DQ53, DQ54, DQ55 H9, H5, G9, G6, H4, H11, J6, H8 DQ56, DQ57, Supply Data Input/Output: HIGH Byte, HIGH WORD (WORD 4). Pin referenced to VrefDQ. DQ58, DQ59, DQ60, DQ61, DQ62, DQ63 B3, B5, B6, B8, B9, B11, Vcc Supply Power Supply: 1.5V ± 0.075V C2, C12, J7, K2, K6, K8, K12, L5, L9, M2, M6, M8, M12, N7, W2, W12, Y3, Y5, Y6, Y8, Y9, Y11 A3, A4, A10, A11, C1, VccQ Supply Data I/O Supply: 1.5V ± 0.075V C13, D1, D13, K1, K13, M1, M13, V13, W1, W13, AA3, AA4, AA10, AA11 B4, B7, B10, C3, C11, Vss Supply Ground D2, D12, H7, K7, L2, L6, L8, L12, M7, P7, V2, V12, W3, W11, Y2, Y4, Y7, Y10, Y12 VssQ Supply Data I/O Ground: Isolated from Core for improved noise immunity E7 VrefCA Supply Voltage Reference CORE: VrefCA must be maintained at all times Supply Voltage Reference I/O: VrefDQ must be maintained at all times. A2, A7, A12, A13, B1, B13, L1, L13, Y1, Y13, AA1, AA2, AA7, AA12, AA13 L7 VrefDQ C5, C6, D5, D6 ZQx A1 UNPOPULATED A5, A6, A8, A9, C4, C7, NC C8, C9, C10, D3, D4, Ref. External Reference for output drive calibration Unpopulated, un-plated matrix location(s) _ No Connect: These ball locations have no electrical connection internally. Locations other than those indicating an upgrade or alternative function should be left isolated (non-connected) D7, D8, E1, E4, E5, E13, F1, F5, F13, G1, G13, H1, H13, J1, J13, N1, N13, P1, P13, R1, R13, T1, T7, T8, T9, T13, U1, U7, U8, U13, V8, V9, V10, V11, W4, W5, W7, W8, W9, W10, AA5, AA6, AA8, AA9 LOGIC Devices Incorporated www.logicdevices.com 10 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 5 - MECHANICAL DRAWING 15.95 16.15 21.95 22.15 0.05 MAX 271 x Ø 0.60 NOM 0.50 NOM 20.00 NOM 1.00 NOM 1.00 NOM 12.00 NOM 1.75 MAX Note: All dimensions in mm LOGIC Devices Incorporated www.logicdevices.com 11 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 5: ABSOLUTE MAXIMUM RATINGS Symbol MIN MAX UNITS NOTES Vcc Vcc Supply Voltage relative to Vss Parameter -0.4 1.975 V 1 VccQ Vcc Supply Voltage relative to VssQ -0.4 1.975 V 1 VIN, VOUT Voltage on any pin relative to Vss -0.4 1.975 V 1 TcIndustrial Operating Case Temperature 0 85 °C 2,3 TcExtended Operating Case Temperature -40 105 °C 2,3 TcMiltemp Operating Case Temperature -55 125 °C 2,3 TSTG Storage Temperature -55 120 °C 2,3 NOTES: 1. Vcc and VccQ must be within 300mV of each other at all times and VREF must not be greater than 0.6 x VccQ. When Vcc and VccQ are less than 500MV, VREF may be ≤300mV. 2. Max operating case temperature. Tc is measured in the center of the package. 3. Device Functionality is not guaranteed if the DRAM device exceeds the Maximum Tc during operation. TABLE 6: INPUT/OUTPUT CAPACITANCE PACKAGE OUTLINE DIMENSIONS DDR3-800 Capacitance Parameter Symbol DDR3-1066 DDR3-1333 MIN MAX MIN MAX MIN MAX UNITS NOTES CK and CK\ CCK 3.1 6.2 3.1 6.2 3.0 6.1 pF ∆C: CK to CK\ CDCK 0 0.2 0 0.2 0 0.2 pF Single-end I/O: DQ, DM C10 1.5 3.0 1.5 3.0 1.5 2.5 pF 2 Differential I/O: DQS, DQS\ C10 1.5 3.0 1.5 3.0 1.5 2.5 pF 3 CCCQS 0 0.2 0 0.2 0 0.2 pF 3 ∆C: DQ to DQS CDI0 -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 4 ∆C: CNTL to CK CDI_CNTL -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 6 CDI_CMD_ADDR -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 7 CI_Shared 2.9 5.5 2.9 5.3 2.9 5.1 pF 5 ∆C: DQS to DQS\ ∆C: cmd_ADDR to CK Inputs (RAS\, CAS\, WE\, CS\, CKE, ADDR) NOTES: 1. Vcc = +1.5V± 0.075mV, VccQ = Vcc, VREF = Vss, f= 100MHz, Tc = 25°C, VOUT (DC) = 0.5 x VccQ, VOUT (peak to peak) = 0.1V 2. DM input is grouped with I/O pins, reflecting the signal is grouped with DQ and therefore matched in loading. 3. CCCQS is for DQS vs. DQS\ 4. CDIO = CIO (DQ) - 0.5 x (CIO [DQS] + CIO [DQS\]) 5. Excludes CK, CK\ 6. CDI_CNTL = CI(CNTL) - 0.5 x (CCK[CK] + CCK [CK\]); CNTL = ODT, CS\ and CKE 7. CDI_CMD_ADDR = CI (CMD_ADDR) - 0.5 x (CCK [CK] + CCK [CK\]); CMD = RAS\, CAS\, and WE\ ADDR = [n:0] LOGIC Devices Incorporated www.logicdevices.com 12 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 8: TIMING PARAMETERS FOR ICC MEASUREMENTS - CLOCK UNITS DDR3-800 DDR3-1066 DDR3-1333 -25 -19 -15 6-6-6 8-8-8 10-10-10 UNITS 2.5 1.875 1.5 ns CL ICC 6 8 10 CK tRCD (MIN) ICC 6 8 10 CK tRC (MIN) ICC 21 28 34 CK tRAS (MIN) ICC 15 20 24 CK 6 8 10 CK 20 27 30 CK ICC Parameter tCK (MIN) ICC tRP (MIN) ICC tFAW x64 tRRD ICC x64 tRFC 64M x 16 (4X) LOGIC Devices Incorporated 4 6 5 CK 44 59 74 CK www.logicdevices.com 13 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 0 Sub-Loop 1 2 3 4 5 6 7 CKE Static HIGH Cycle Number 0 1 2 3 4 n RAS n RC n RC + 1 n RC + 2 n RC + 3 n RC + 4 n RC + n RAS 2 x nRC 4 x n RC 6 x n RC 8 x n RC 10 x n RC 12 x n RC 14 x n RC ACT D D D\ D\ 0 1 1 1 1 ACT D D D\ D\ 0 0 1 1 1 1 0 CS\ PRE Command PRE RAS\ CAS\ WE\ ODT BA [2:0] A [15:11] A [10] A [9:7] A [6:3] 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 Repeat cycles 1 through 4 until n RAS - 1, truncate if needed 0 1 0 0 0 0 0 0 0 Repeat cycles 1 through 4 until n RC - 1, truncate if needed 0 1 1 0 0 0 0 0 F 0 0 0 0 0 0 0 0 F 0 0 0 0 0 0 0 0 F 1 1 1 0 0 0 0 0 F 1 1 1 0 0 0 0 0 F Repeat cycles n RC +1 through n RC +4 until n RC - 1 + n RAS - 1, truncate if needed 0 1 0 0 0 0 0 0 F Repeat cycles n RC +1 through n RC +4 until 2 x RC - 1, truncate if needed Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 0 0 0 0 0 - 0 0 0 0 0 - - - Data 0 A [2:0] 0 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 14 www.logicdevices.com LOGIC Devices Incorporated CK, CK\ Toggling L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 9: ICC0 MEASUREMENT LOOP 0 Sub-Loop 1 2 3 4 5 6 7 CKE Static HIGH 0 1 2 3 4 n RCD n RAS n RC n RC +1 nRC +2 n RC +3 n RC +4 n RC + nRCD n RC + nRAS Cycle Number 2 x n RC 2 x n RC 2 x n RC 2 x n RC 2 x n RC 2 x n RC 2 x n RC ACT D D D\ D\ 0 1 1 1 1 0 0 0 1 1 PRE ACT D D D\ D\ RD 0 0 1 1 1 1 0 0 0 1 0 0 0 1 1 0 1 RAS\ 0 CS\ RD Command PRE CAS\ WE\ ODT BA [2:0] A [15:11] A [10] A [9:7] A [6:3] 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 Repeat cycles 1 through 4 until nRCD - 1, truncate if needed 0 1 0 0 0 0 0 0 Repeat cycles 1 through 4 until nRAS - 1, truncate if needed 1 0 0 0 0 0 0 0 Repeat cycles 1 through 4 until nRC - 1, truncate if needed 1 1 0 0 0 0 0 F 0 0 0 0 0 0 0 F 0 0 0 0 0 0 0 F 1 1 0 0 0 0 0 F 1 1 0 0 0 0 0 F Repeat cycles nRC + 1 through nRC + 4 until nRC + nRCD - 1, truncate if needed 0 1 0 0 0 0 0 F Repeat cycles nRC + 1 through nRC + 4 until nRC + nRAS - 1, truncate if needed 1 0 0 0 0 0 0 F Repeat cycle nRC + 1 through nRC + 4 until 2 x nRC - 1, truncate if needed Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 - 00000000 0 0 0 0 0 0 00110011 - 0 - 0 0 0 0 0 - Data 0 A [2:0] 0 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 15 www.logicdevices.com LOGIC Devices Incorporated CK, CK\ Toggling L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 10: ICC1 MEASUREMENT LOOP PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 11: ICC MEASUREMENT CONDITIONS FOR POWER-DOWN CURRENTS Icc2P0 Icc2P1 Icc2Q Precharge Power- Precharge PowerPrecharge Quiet Down Current Down Current Standby Current (Slow Exit) (Fast Exit) Name Timing Pattern CKE External Clock Icc3P Active PowerDown Current n/a n/a n/a n/a LOW LOW HIGH LOW Toggling Toggling Toggling Toggling tCK tCK (MIN) ICC tCK (MIN) ICC tCK (MIN) ICC tCK (MIN) ICC tRC n\a n\a n\a n\a tRAS n\a n\a n\a n\a tRCD n\a n\a n\a n\a tRRD n\a n\a n\a n\a tRC n\a n\a n\a n\a CL n\a n\a n\a n\a AL n\a n\a n\a n\a CS\ HIGH HIGH HIGH HIGH Command Inputs LOW LOW LOW LOW ROW/COLUMN Addr LOW LOW LOW LOW Bank Address LOW LOW LOW LOW DM LOW LOW LOW LOW Data I/O Mid-level Mid-level Mid-level Mid-level Output Buffer DQ, DQS Enabled Enabled Enabled Enabled Enabled, OFF Enabled, OFF Enabled, OFF Enabled, OFF 8 8 8 8 ODT Burst Length None None None None IDLE Bank(s) All All All All Special Notes n\a n\a n\a n\a ACTIVE Bank(s) LOGIC Devices Incorporated www.logicdevices.com 16 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 12: ICC2N / ICC3N MEASUREMENT LOOP Toggling CK, CK\ Static HIGH CKE 0 1 2 3 4 5 6 7 0 1 2 3 4-7 8-11 12-15 16-19 20-23 24-27 28-31 D D D\ D\ 1 1 1 1 CS\ 0 0 1 1 RAS\ 0 0 1 1 CAS\ 0 0 1 1 WE\ ODT BA [2:0] A [15:11] A [10] 0 0 0 0 A [9:7] 0 0 F F A [6:3] 0 0 0 0 A [2:0] - www.logicdevices.com Cycle Number Command 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 LOGIC Devices Incorporated Sub-Loop Data 17 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A CKE Static HIGH 0 Sub-Loop 1 2 3 4 5 6 7 Cycle Number 0 1 2 3 4-7 8-11 12-15 16-19 20-23 24-27 28-31 D D D\ D\ Command 1 1 1 1 CS\ 0 0 1 1 RAS\ 0 0 1 1 WE\ ODT BA [2:0] A [15:11] A [10] 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 Repeat sub-loop 0, use BA [2:0] = 1; ODT = 0 Repeat sub-loop 0, use BA [2:0] = 2; ODT = 1 Repeat sub-loop 0, use BA [2:0] = 3; ODT = 1 Repeat sub-loop 0, use BA [2:0] = 4; ODT = 0 Repeat sub-loop 0, use BA [2:0] = 5; ODT = 0 Repeat sub-loop 0, use BA [2:0] = 6; ODT = 1 Repeat sub-loop 0, use BA [2:0] = 7; ODT = 1 0 0 0 0 A [9:7] 0 0 F F A [6:3] 0 0 0 0 A [2:0] - High Performance, Integrated Memory Module Product CAS\ Data May 19, 2009 LDS-L9D340G6BG2-A 18 www.logicdevices.com LOGIC Devices Incorporated CK, CK\ Toggling L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 13: ICC2NT MEASUREMENT LOOP CKE Static HIGH 0 Sub-Loop 1 2 3 4 5 6 7 Cycle Number 0 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63 RD D D\ D\ RD D D\ D\ Command 0 1 1 1 0 1 1 1 CS\ 1 0 1 1 1 0 1 1 RAS\ 0 0 1 1 0 0 1 1 CAS\ 1 0 1 1 1 0 1 1 ODT BA [2:0] A [15:11] A [10] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 0 0 0 0 0 0 0 0 A [9:7] 0 0 0 0 F F F F A [6:3] 0 0 0 0 0 0 0 0 A [2:0] 00000000 00110011 - High Performance, Integrated Memory Module Product WE\ Data May 19, 2009 LDS-L9D340G6BG2-A 19 www.logicdevices.com LOGIC Devices Incorporated CK, CK\ Toggling L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 14: ICC4R MEASUREMENT LOOP CKE Stac HIGH 0 Sub-Loop 1 2 3 4 5 6 7 Cycle Number 0 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63 WR D D\ D\ WR D D\ D\ Command 0 1 1 1 0 1 1 1 CS\ 1 0 1 1 1 0 1 1 RAS\ 0 0 1 1 0 0 1 1 CAS\ 0 0 1 1 0 0 1 1 ODT BA [2:0] A [15:11] 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 0 0 0 0 0 0 0 0 A [10] 0 0 0 0 0 0 0 0 A [9:7] 0 0 0 0 F F F F A [6:3] 0 0 0 0 0 0 0 0 A [2:0] 00000000 00110011 - High Performance, Integrated Memory Module Product WE\ Data May 19, 2009 LDS-L9D340G6BG2-A 20 www.logicdevices.com LOGIC Devices Incorporated CK, CK\ Toggling L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 15: ICC4W MEASUREMENT LOOP CKE Static HIGH 1a 0 Sub-Loop 1b 1c 1d 1e 1f 1g 1h 2 Cycle Number 0 1 2 3 4 5-8 9-12 13-16 17-20 21-24 25-28 29-32 33-n RFC-1 Command REF D D D\ D\ CAS\ WE\ ODT BA [2:0] A [15:11] A [10] A [9:7] Repeat sub-loop 1a, use BA [2:0] = 1 Repeat sub-loop 1a, use BA [2:0] = 2 Repeat sub-loop 1a, use BA [2:0] = 3 Repeat sub-loop 1a, use BA [2:0] = 4 Repeat sub-loop 1a, use BA [2:0] = 5 Repeat sub-loop 1a, use BA [2:0] = 6 Repeat sub-loop 1a, use BA [2:0] = 7 Repeat sub-loop 1a through 1h until n RFC - 1, truncate if needed High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 21 www.logicdevices.com LOGIC Devices Incorporated CK, CK\ Toggling L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 16: ICC5B MEASUREMENT LOOP CS\ RAS\ A [6:3] A [2:0] Data PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) PACKAGE OUTLINE DIMENSIONS TABLE 17: ICC MEASUREMENT LOOP Industrial Range Tc =-40°C to 85°C Extended or Mil Temperature Range, Tc = -40°C to 85°C or -55°C to 125°C Icc6: Self Refresh Current Icc6E/M: Self Refresh Current Icc8: Reset CKE LOW LOW Mid-level External Clock Off, CK and CK\ = LOW Off, CK and CK\ = LOW Mid-level tCK n\a n\a n\a ICC Test tRC n\a n\a n\a tRAS n\a n\a n\a tRCD n\a n\a n\a tRRD n\a n\a n\a tRC n\a n\a n\a CL n\a n\a n\a AL n\a n\a n\a CS\ Mid-level Mid-level Mid-level Command Inputs Mid-level Mid-level Mid-level ROW/COLMUN addresses Mid-level Mid-level Mid-level BANK addresses Mid-level Mid-level Mid-level Data I/O Mid-level Mid-level Mid-level Output buffer DQ, DQS Enabled Enabled Mid-level ODT Enabled, Mid-level Enabled, Mid-level Mid-level Burst Length n\a n\a n\a Active BANKS n\a n\a None IDLE BANKS n\a n\a All SRT Disabled (normal) Enabled (extended) n\a ASR Disabled Disabled n\a LOGIC Devices Incorporated www.logicdevices.com 22 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A CKE Static HIGH 15 16 17 18 14 12 13 11 10 9 5 6 7 8 4 2 3 1 0 Sub-Loop 19 Cycle Number 0 1 2 3 n RRD n RRD + 1 n RRD + 2 n RRD + 3 2 x n RRD 3x n RRD 4 x n RRD 4 x n RRD + 1 n FAW n FAW + n RRD n FAW + 2xn RRD n FAW + 3xn RRD n FAW + 4xn RRD n FAW + 4xn RRD+1 2 x n FAW 2 x n FAW + 1 2 x n FAW + 2 2 x n FAW + 3 2 x n FAW + n RRD 2 x n FAW + n RRD+1 2 x n FAW + n RRD+2 2 x n FAW + n RRD+3 2 x nFAW + 2x n RRD 2 x n FAW + 3x n RRD 2 x n FAW + 4x n RRD 2 x n FAW+4x n RRD+1 3 x nFAW 3 x nFAW + nRRD 3 x nFAW + 2x nRRD 3 x nFAW + 3x nRRD 3 x nFAW + 4x nRRD 3 x nFAW + 4x nRRD +1 ACT RDA D 0 0 1 0 1 0 D D ACT RDA D ACT RDA D D 1 1 0 0 1 0 0 1 1 1 0 0 0 1 0 0 1 0 0 0 0 1 0 RAS\ 0 0 1 CS\ ACT RDA D Command D CAS\ WE\ ODT BA [2:0] A [15:11] A [10] A [9:7] 1 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 Repeat cycle 2 until n RRD - 1 1 1 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 0 0 Repeat cycle n RRD + 2 until 2 x n RRD - 1 Repeat sub-loop 0, use BA[2:0] = 2 Repeat sub-loop 0, use BA[2:0] = 3 0 0 0 3 0 0 0 Repeat cycle 4 x n RRD until n FAW - 1, if needed Repeat sub-loop 0, use BA[2:0] = 4 Repeat sub-loop 1, use BA[2:0] = 5 Repeat sub-loop 0, use BA[2:0] = 6 Repeat sub-loop 1, use BA[2:0] = 7 0 0 0 7 0 0 0 Repeat cycle n FAW + 4 x n RRD until 2 x n FAW - 1, if needed 1 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 Repeat cycle 2 x n FAW + 2 until 2 x n FAW + n RRD - 1 1 1 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 0 0 Repeat cycle 2 x n FAW + n RRD + 2 until 2 x n FAW + 2 x n RRD - 1 Repeat sub-loop 10, use BA[2:0] = 2 Repeat sub-loop 11, use BA[2:0] = 3 0 0 0 3 0 0 0 Repeat cycle 2 x n FAW + 4 x n RRD until 3 x n FAW - 1, if needed Repeat sub-loop 10, use BA[2:0] = 4 Repeat sub-loop 11, use BA[2:0] = 5 Repeat sub-loop 10, use BA[2:0] = 6 Repeat sub-loop 11, use BA[2:0] = 7 0 0 0 7 0 0 0 Repeat cycle 3 x n FAW + 4 x n RRD until 4 x n FAW - 1, if needed 0 0 0 0 0 0 0 0 0 - 00110011 - 00000000 - 0 0 0 0 F F F F F F F F 0 Data 0 0 0 0 0 0 - 00000000 - 00110011 - 0 0 - A [2:0] 0 A [6:3] 0 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 23 www.logicdevices.com LOGIC Devices Incorporated CK, CK\ Toggling L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 18: ICC7 MEASUREMENT LOOP PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 19: ICC MAXIMUM LIMITS Speed Bin ICC Icc0 Icc1 Icc2P0 Icc2P1 Icc2Q Icc2N Icc2NT Icc3P Icc3N Icc4R Icc4W Icc5B Icc6 Icc7 Icc8 IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP IND EXT MIL-TEMP DDR3-800 DDR3-1066 DDR3-1333 UNITS Notes 350 365 380 435 463 482 47 61 176 118 153 176 184 239 275 195 253 290 314 405 465 118 123 130 196 200 215 902 920 940 941 960 980 784 800 816 24 43 75 1372 1475 1590 ICC2P + 2mA ICC2P + 2.1mA ICC2P + 2.4mA 390 406 435 510 530 585 47 61 47 137 178 157 212 275 240 215 279 255 372 484 412 138 145 157 215 219 235 1020 1041 1137 1137 1160 1392 862 880 941 24 43 24 1489 1600 1646 ICC2P + 2mA ICC2P + 2.1mA ICC2P + 2mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 NOTES: 1. Tc = 0°C to ≤ 85°C; SRT and ASR are disabled, enabling ASR could increase ICCx by up to an additional 2mA. 2. Tc = -40°C to ≤ 105°C; SRT and ASR are disabled, enabling ASR could 3. Tc = -55°C to ≤ 125°C; SRT and ASR are disabled, enabling ASR could increase ICCx by up to an additional 2mA. increase ICCx by up to an additional 2mA. LOGIC Devices Incorporated www.logicdevices.com 24 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 20: DC ELECTRICAL CHARACTERISTICS AND OPERATINGPC ONDITIONS ACKAGE OUTLINE DIMENSIONS All Voltages are referenced to Vss Parameter/Condition Supply Voltage I/O Supply Voltage Input Leakage Current: Symbol MIN TYP MAX UNITS NOTES Vcc 1.425 1.5 1.575 V 1,2 VccQ 1.425 1.5 1.575 V 1,2 II -2 - 2 μA IVREF -1 - 1 μA Any input 0V≤VIN≤Vcc, VREF pin 0V≤VIN≤1.1V All other pins not under test = 0V VREF Supply Leakage Current: 3,4 VREFDQ = Vcc/2 or VREFCA = Vcc/2 All other pins not under test = 0V NOTES: 1. Vcc and VccQ must track one another, VccQ must be less than or equal 3. VREF (see Table 22). 4. The minimum limit requirement is for testing purposes. The leakage to Vcc, Vss = VssQ. 2. current on the VREF pin should be minimal. Vcc and VccQ may include AC noise of ± 50mV (250 kHz to 20MHz) in addition to the DC (0Hz to 250kHz) specifications, Vcc and VccQ must be at the same level for valid AC timing parameters. TABLE 21: DC ELECTRICAL CHARACTERISTICS AND INPUT CONDITIONS PACKAGE OUTLINE DIMENSIONS All Voltages are referenced to Vss Parameter/Condition VIN low; DC/commands/address busses VIN high; DC/commands/address busses Symbol MIN TYP VIL Vss n/a VIH See Table 20 MAX UNITS See Table 20 V n/a Vcc V NOTES Input reference voltage command/address bus VREFCA(DC) 0.49 x Vcc 0.5 x Vcc 0.51 x Vcc V 1,2 I/O reference voltage DQ bus VREFDQ(DC) 0.49 x Vcc 0.5 x Vcc 0.51 x Vcc V 2,3 I/O reference voltage DQ bus in SELF REFRESH VREFDQ(SR) Vss 0.5 x Vcc Vcc V 4 VTT - 0.5 x VccQ - V 5 Command/address termination voltage (system level, not direct DRAM input) NOTES: 1. VREFCA(DC) is expected to be approximately 0.5 x Vcc and to track vari- mon mode) on VREFDQ may not exceed ± 1% x Vcc around the ations in the DC level. Externally generated peak noise (noncommon VREFDQ(DC) value. Peak-to-peak AC noise on VREFDQ should not mode) on VREFCA may not exceed ± 1% x Vcc around the VREFCA(DC) exceed ± 2% of VREFDQ(DC). value. Peak-to-peak AC noise on VREFCA should not exceed ± 2% of VREFCA(DC). 4. VREFDQ(DC) may transition to VREFDQ(SR) and back to VREFDQ(DC) when in SELF zREFRESH, within restrictions outlined in the SELF 2. DC values are determined to be less than 20MHz in frequency. DRAM REFRESH section. must meet specifications if the DRAM induces additional AC noise greater than 20MHz in frequency. 5. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors. MIN and MAX values are system-depen- 3. VREFDQ(DC) is expected to be approximately 0.5 x Vcc and to track dent. variations in the DC level. Externally generated peak noise (noncom- LOGIC Devices Incorporated www.logicdevices.com 25 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 22: INPUT SWITCHING CONDITIONS PACKAGE OUTLINE DIMENSIONS Symbol DDR3-1066 DDR3-900 Input high AC voltage: Logic 1 VIH (AC175) MIN +175 +175 mV Input high AC voltage: Logic 1 VIH (AC150) MIN +150 +150 mV mV Parameter/Condition DDR1333 UNITS Command and Address Input high DC voltage: Logic 1 VIH (DC100) MIN +100 +100 Input high DC voltage: Logic 0 VIL (DC100) MAX -100 -100 mV mV Input high AC voltage: Logic 0 VIL (AC150) MAX -150 -150 Input high AC voltage: Logic 0 VIL (AC175) MAX -175 -175 mV VIH (AC175) MIN +175 - mV mV DQ and DM Input high AC voltage: Logic 1 Input high AC voltage: Logic 1 VIH (AC150) MIN +150 +150 Input high DC voltage: Logic 1 VIH (DC100) MIN +100 +100 mV mV Input high DC voltage: Logic 0 VIL (DC100) MAX -100 -100 Input high AC voltage: Logic 0 VIL (AC150) MAX -150 -150 mV -175 - mV Input high AC voltage: Logic 0 VIL (AC175) MAX NOTES: 1. All voltages are referenced to VREF, VREF is VREFCA for control, com- 3. mand, and address. All slew rates and setup/hold times are specified at Input hold timing parameters (tIH and tDH) are referenced at VIL(DC)/ VIH(DC), not VREF(AC). the DRAM ball. VREF is VREFDQ for DQ and DM inputs. 4. 2. Input setup timing parameters (tIS and tDS) are referenced at VIL(AC)/ Single-ended input slew rate = 1V/ns; maximum input voltage swing under test is 900mV (peak-to-peak). VIH(AC), not VREF(DC). LOGIC Devices Incorporated www.logicdevices.com 26 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) OPERATING CONDITIONS FIGURE 6 - INPUT SIGNAL VIL and VIH levels with ringback 1.90V VDDQ + 0.4V narrow pulse width 1.50V VDDQ Minimum VIL and VIH levels VIH (AC) 0.925V 0.925V VIH (AC) VIH (DC) VIH (DC) 0.850V 0.850V 0.780V 0.765V 0.750V 0.735V 0.720V 0.780V 0.765V 0.750V 0.735V 0.720V VREF + AC noise VREF + DC error VREF + DC error VREF + AC noise 0.650V VIL (DQ) 0.575V VIL (AC) 0.650V VIL (DC) 0.575V VIL (AC) VSS 0.0V VSS 0.4V narrow pulse width -0.40V Notes: LOGIC Devices Incorporated www.logicdevices.com 1. Numbers in diagrams reflect nominal values. 27 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) AC OVERSHOOT/UNDERSHOOT SPECIFICATION TABLE 23: CONTROL AND ADDRESS PINS PACKAGE OUTLINE DIMENSIONS Parameter DDR3-800 DDR3-1066 DDR3-1333 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V Maximum overshoot area above Vcc (see Figure 16 on page 38) 0.67Vns 0.5Vns 0.4Vns Maximum undershoot area below Vss (see Figure 17 on page 39) 0.67Vns 0.5Vns 0.4Vns Maximum peak amplitude allowed for overshoot area (see Figure 16 on page 38) Maximum peak amplitude allowed for overshoot area (see Figure 17 on page 39) TABLE 24: CLOCK, DATA, STROBE, AND MASK PINS PACKAGE OUTLINE DIMENSIONS Parameter DDR3-800 Maximum peak amplitude allowed for overshoot area DDR3-1066 DDR3-1333 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V 0.25Vns 0.19Vns 0.15Vns 0.25Vns 0.19Vns 0.15Vns (see Figure 16 on page 38) Maximum peak amplitude allowed for overshoot area (see Figure 17 on page 39) Maximum overshoot area above Vcc/ VccQ (see Figure 16 on page 38) Maximum undershoot area below Vss/ VssQ (see Figure 17 on page 39) FIGURE 7 & 8: OVERSHOOT/UNDERSHOOT SPECIFICATIONS Maximum amplitude Volts (V) Figure 7: Overshoot Overshoot area VCC/VCCQ Time (ns) Time (ns) Figure 8: Undershoot VSS/VSSQ Volts (V) Maximum amplitude LOGIC Devices Incorporated www.logicdevices.com 28 Undershoot area High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 25: DIFFERENTIAL INPUT OPERATING CONDITIONS (CKXP, ACKAGE CKX\, DQS X, AND DQSX\) OUTLINE DIMENSIONS Parameter/Condition Symbol MIN MAX UNITS NOTES Differential input voltage, logic high - slew VIH DIFF(AC)slew +200 n/a mV 4 Differential input voltage, logic low - slew VIL DIFF(AC)slew n/a -200 mV 4 Differential input voltage, logic high VIH DIFF(AC) 2x(VIH(AC)-VREF) Vcc/VccQ mV 5 Differential input voltage, logic low VIL DIFF(AC) Vss/VssQ 2x(VREF-VIL(AC)) mV 6 VIX VREF(DC) - 150 VREF(DC) + 150 mV 7 VIX(175) VREF(DC) - 175 VREF(DC) + 175 mV 7,8 VSHE VccQ/2 + VIH(AC) VccQ mV 5 Vcc/2 + VIH(AC Vcc VssQ VccQ/2-VIL(AC) mV 6 Vss Vcc/2-VIL(AC) Differential input crossing voltage relative to Vcc/2 for DQS, DQS\, CK, CK\ Differential input crossing voltage relative to Vcc/2 for CK, CK\ Single-ended high level for strobes Single-ended high level for CK, CK\ Single-ended low level for strobes VSEL Single-ended low level for CK, CK\ NOTES: 1. 6. Clock is referenced to VccD and Vss. Data strobe is referenced to MIN limit is relative to single-ended signals, the undershoot specifications are applicable. VccQ and VssQ. 2. Reference is VREFCA(DC) for clock and for VREFDQ(DC) for strobe. 7. The typical value of VIX(AC) is expected to be about 0.5 x Vcc of the 3. Differential input slew rate = 2V/ms. 4. Defines slew rate reference points relative to input crossing voltages. 5. MAX limit is relative to single-ended signals, the overshoot specifica- VIX extended range is only allowed when the following conditions are tions are applicable. met: The single-ended input signals are monotonic, have the single- transmitting device and VIX(AC) is expected to track variations in Vcc. VIX(AC) indicates the voltage at which differential input signals must cross. 8. The VIX extended range (±175mV) is allowed only for the clock and this ended swing VSEL, VSEH of at least Vcc/2 ±250mV, and the differential slew rate of CK, CK\ is greater than 3V/ns. LOGIC Devices Incorporated www.logicdevices.com 29 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) OVERSHOOT/UNDERSHOOT SPECIFICATIONS FIGURE 9 - VIX FOR DIFFERENTIAL SIGNALS VCC, VCCQ VCC, VCCQ CK#, DQS# CK#, DQS# VIX X VIX VCC/2, VCCQ/2 X VCC/2, VCCQ/2 X VIX VIX X CK, DQS CK, DQS VSS, VSSQ VSS, VSSQ FIGURE 10 - SINGLE-ENDED REQUIREMENTS FOR DIFFERENTIAL SIGNALS V CC or VCC Q VSEH (MIN) V CC /2 or VCC Q/2 VSEH CK or DQS VSEL (MAX) VSEL VSS or VSS Q LOGIC Devices Incorporated www.logicdevices.com 30 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) OVERSHOOT/UNDERSHOOT SPECIFICATIONS FIGURE 11 - DEFINITION OF DIFFERENTIAL AC-SWING AND tDVAC t DVAC V IHDIFF ( A C) MIN V IHDIFF (MIN) V IHDIFF ( DC) MIN CK - CK# DQ S - DQS # 0.0 V ILDIFF ( DC) MAX V ILDIFF (MAX) V ILDIFF ( A C) MAX t DVAC half cycle TABLE 26: DIFFERENTIAL INPUT OPERATING CONDITIONS (tDVAC) FOR CK X, CKD X\, DQSX, AND DQSX\ PACKAGE OUTLINE IMENSIONS Below VIL (AC) tDVAC (ps) at [VIHDIFF(AC) to VILDiff(AC)] LOGIC Devices Incorporated Slew Rate (V/ns) 350mV 300mV -4.0 75 175 4.0 57 170 3.0 50 167 2.0 38 163 1.9 34 162 1.6 29 161 1.4 22 159 1.2 13 155 1.0 0 150 <1.0 0 150 www.logicdevices.com 31 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) SLEW RATE DEFINITIONS FOR SINGLE-ENDED INPUT SIGNALS Hold (tIH and tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC) MAX and the first crossing of VREF. Hold (tIH and tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC) MIN and the first crossing of VREF. Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew-rate between the last crossing of VREF and the first crossing VIH(AC) MIN. Setup (tIS and tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF an the first crossing of VIL(AC) MAX. TABLE 27: SINGLE-ENDED INPUT SLEW RATE Measured Input Slew Rate (Linear Signals) Input PACKAGE OUTLINE DIMENSIONS Edge From To Rising VREF VIH(AC)MIN Falling VREF VIL(AC)MAX Rising VIL(DC)Max VREF Setup Calculation VIH(AC) MIN - VREF VREF - VIL(AC) MAX ∆TFS VREF - VIL(DC) MAX ∆TFH Hold Falling VIH(DC)MIN VREF VIH(DC) MIN - VREF ∆TRSH LOGIC Devices Incorporated www.logicdevices.com 32 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) SLEW RATE DEFINITIONS FOR SINGLE-ENDED INPUT SIGNALS FIGURE 12 - NOMINAL SLEW RATE DEFINITION FOR SINGLE-ENDED INPUT SIGNALS # ! ! " # # ! " # LOGIC Devices Incorporated www.logicdevices.com 33 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) SLEW RATE DEFINITIONS FOR DIFFERENTIAL INPUT SIGNALS Input slew rate for differential signals (CKx, CKx\, UDQSx , UDQSx\, LDQSx and LDQSx\) are defined and measured as shown in Table 28. The nominal slew rate for a rising signal is defined as the slew rate between VIL(DIFF) MAX and VIH(DIFF) MIN. The nominal slew rate for a falling signal is defined as the slew rate between VIH(DIFF) MIN and VIL(DIFF) MAX. TABLE 28: DIFFERENTIAL INPUT SLEW RATE DEFINITION Measured Input Slew Rate (Linear Signals) Input Edge PACKAGE OUTLINE DIMENSIONS From Rising VREF To Calculation VIH(DIFF) MIN - VIL(DIFF) MAX VIH(AC)MIN CK and DQS ∆TR(DIFF) Reference VIH(DIFF) MIN - VIL(DIFF) MAX Falling VREF VIL(AC)MAX ∆TF(DIFF) FIGURE 13 - NOMINAL DIFFERENTIAL INPUT SLEW RATE DEFINITION FOR DQS, DQS# AND CK, CK# !" #"$" % % LOGIC Devices Incorporated www.logicdevices.com 34 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) ODT CHARACTERISTICS FIGURE 14 - ODT LEVELS AND I-V CHARACTERISTICS Chip in termination mode ODT’s effective resistance RTT is defined by MR1[9,6 and 2]. ODT is applied to the DQx, UDMx, LDMx, UDQSx, UDQSx\, LDQSx and LDQSx\ balls. The ODT target values are listed in Table 29. ODT VCCQ IPU IOUT = IPD - IPU To other circuitry such as RCV, . . . RTTPU DQ IOUT R TTPD VOUT IPD VSSQ TABLE 29: ON-DIE TERMINATION DC ELECTRICAL CHARACTERISTICS Parameter/Condition Symbol RTT effective impedance RTT_EFF Deviation of VM with respect to VccQ/2 ∆VM MIN TYP MAX UNITS NOTES % 1, 2, 3, 4 1, 2, 4 See Table 30 -5 5 NOTES: 1. Tolerance limits are applicable after a proper ZQ calibration has been 3. Measure voltage (VM) at the tested pin with no load: performed at a stable temperature and voltage (VccQ=Vcc, VssQ-Vss). Refer to “ODT Sensitivity” on page 37 if either the temperature or voltage ∆VM = changes after calibration. 2. 2 x VM -1 x 100 VccQ Measurement definition for RTT: Apply VIH(AC) to a pin under test and measure the current I[VIH(AC)], then apply VIL(AC) to pin under test and 4. For extended MIL-temp devices, the minimum values are derated by 6% when the device is between -40°C and 0°C (Tc). measure current I[VIL(AC)]: VIL(AC) - VIL(AC) RTT = LOGIC Devices Incorporated I[VIH(AC))-I(VIL(AC))] www.logicdevices.com 35 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 30: RTT EFFECTIVE IMPEDANCES MR1 [9,6,2] RTT PACKAGE OUTLINE DIMENSIONS Resistor RTT120PD240 0, 1, 0 120Ω RTT120PU240 120Ω RTT60PD120 0, 0, 1 60Ω RTT60PU240 60Ω RTT40PD80 0, 1, 1 40Ω RTT40PU80 40Ω RTT30PD60 1, 0, 1 30Ω RTT30PU60 30Ω RTT20PD40 1, 0, 0 20Ω RTT20PU40 20Ω LOGIC Devices Incorporated www.logicdevices.com VOUT MIN TYP MAX UNITS 0.2 x VccQ 0.6 1.0 1.1 RZQ/1 0.5 x VccQ 0.9 1.0 1.1 RZQ/1 0.8 x VccQ 0.9 1.0 1.4 RZQ/1 0.2 x VccQ 0.9 1.0 1.4 RZQ/1 0.5 x VccQ 0.9 1.0 1.1 RZQ/1 0.8 x VccQ 0.9 1.0 1.1 RZQ/1 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/2 0.2 x VccQ 0.6 1.0 1.1 RZQ/2 0.5 x VccQ 0.9 1.0 1.1 RZQ/2 0.8 x VccQ 0.9 1.0 1.4 RZQ/2 0.2 x VccQ 0.9 1.0 1.4 RZQ/2 0.5 x VccQ 0.9 1.0 1.1 RZQ/2 0.8 x VccQ 0.9 1.0 1.1 RZQ/2 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/4 0.2 x VccQ 0.6 1.0 1.1 RZQ/3 0.5 x VccQ 0.9 1.0 1.1 RZQ/3 0.8 x VccQ 0.9 1.0 1.4 RZQ/3 0.2 x VccQ 0.9 1.0 1.4 RZQ/3 0.5 x VccQ 0.9 1.0 1.1 RZQ/3 0.8 x VccQ 0.9 1.0 1.1 RZQ/3 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/6 0.2 x VccQ 0.6 1.0 1.1 RZQ/4 0.5 x VccQ 0.9 1.0 1.1 RZQ/4 0.8 x VccQ 0.9 1.0 1.4 RZQ/4 0.2 x VccQ 0.9 1.0 1.4 RZQ/4 0.5 x VccQ 0.9 1.0 1.1 RZQ/4 0.8 x VccQ 0.9 1.0 1.1 RZQ/4 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/8 0.2 x VccQ 0.6 1.0 1.1 RZQ/6 0.5 x VccQ 0.9 1.0 1.1 RZQ/6 0.8 x VccQ 0.9 1.0 1.4 RZQ/6 0.2 x VccQ 0.9 1.0 1.4 RZQ/6 0.5 x VccQ 0.9 1.0 1.1 RZQ/6 0.8 x VccQ 0.9 1.0 1.1 RZQ/6 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/12 36 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) ODT SENSITIVITY If either the temperature or voltage changes after I/O calibration, the tolerance limits listed in Table 29 can be expected to widen according to Tables 31 and 32. TABLE 31: ODT SENSITIVITY DEFINITION Symbol RTT MIN 0.9 - dRTTdT x dRTTdV x [DV] MAX UNITS RZQ/(2, 4, 6, 8, 12) 1.6 + dRTTdT x [DT] + dRTTdV x [DV] TABLE 32 - ODT TEMPERATURE & VOLTAGE SENSITIVITY Change MIN MAX UNITS dRTTdT 0 1.5 0 dRTTdV 0 0.15 0 FIGURE 15 - ODT TIMING REFERENCE LOAD ODT TIMING DEFINITIONS ODT loading differs from that used in AC timing measurements. Two parameters define when ODT turns on or off synchronously, two define when ODT turns on or off Asynchronously and, another defines when ODT turns on or off dynamically. Table 33 outlines and provides definition and measurement reference settings for each parameter. DUT CK, CK# ODT turn-on time begins when the output leaves HIGH-Z and ODT resistance begins to turn on. ODT turn-off time begins when the output leaves LOW-Z and ODT resistance begins to turn-off. VREF DQ, DM DQS, DQS# ZQ VCCQ/2 RTT = 25Ω VTT = VSSQ Timing reference point RZQ = 240Ω VSSQ LOGIC Devices Incorporated www.logicdevices.com 37 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) ODT TIMING DEFINITIONS TABLE 33: ODT TIMING DEFINITIONS Symbol PACKAGE OUTLINE DIMENSIONS End Point Definition Figure Rising edge of CK-CK\ defined by the end point of ODTL on Begin Point Definition Extrapolated point at VssQ Figure 25 on page 60 tAOF Rising edge of CK-CK\ defined by the end point of ODTL off Extrapolated point at VRTT_NORM Figure 25 on page 60 tAONPD Rising edge of CK-CK\ with ODT first being registered HIGH Extrapolated point at VssQ Figure 26 on page 61 Rising edge of CK-CK\ with ODT first being registered LOW Extrapolated point at VRTT_NOM Figure 26 on page 61 Rising edge of CK-CK\ defined by the end point of ODTLCNW, Extrapolated points at VRTT_WR and VRTT_NOM Figure 27 on page 62 tAON tAOFPD tADC ODTLCWN4, or ODTLCWN8 TABLE 34: REFERENCE SETTINGS FOR ODT TIMING MEASUREMENTS PACKAGE OUTLINE DIMENSIONS Measured Parameter RTT_NORM Setting tAON tAOF tAONPD VSW1 VSW2 RZQ/4 (60Ω) RTT_WR_Setting n/a 50mV 100mV RZQ/12 (20Ω) n/a 100mV 200mV RZQ/4 (60Ω) n/a 50mV 100mV RZQ/12 (20Ω) n/a 100mV 200mV RZQ/4 (60Ω) n/a 50mV 100mV RZQ/12 (20Ω) n/a 100mV 200mV tAOFPD RZQ/4 (60Ω) n/a 50mV 100mV RZQ/12 (20Ω) n/a 100mV 200mV tADC RZQ/12 (20Ω) RZQ/2 (120Ω) 200mV 300mV FIGURE 16 - tAON AND tAOF DEFINITIONS t AON t AOF Begin point: Rising edge of CK - CK# defined by the end point of ODTL off Begin point: Rising edge of CK - CK# defined by the end point of ODTL on CK CK VCCQ/2 CK# CK# t AON t AOF End point: Extrapolated point at VRTT_NOM TSW 2 VRTT_NOM TSW 1 TSW 1 TSW 1 VSW 2 DQ, DM DQS, DQS# VSS Q VSW 2 VSW 1 VSW 1 VSS Q End point: Extrapolated point at VSS Q LOGIC Devices Incorporated www.logicdevices.com 38 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) ODT CHARACTERISTICS FIGURE 17 - tAONPD AND tAOFPD DEFINITION t AONPD t AOFPD Begin point: Rising edge of CK - CK# with ODT first registered HIGH Begin point: Rising edge of CK - CK# with ODT first registered LOW CK CK VCCQ/2 CK# CK# t AONPD t AOFPD End point: Extrapolated point at VRTT_NOM VRTT_NOM TSW 2 TSW 2 TSW 1 TSW 1 VSW 2 VSW 2 DQ, DM DQS, DQS# VSW 1 VSW1 VSS Q VSS Q End point: Extrapolated point at VSS Q FIGURE 18 - tADC DEFINITION Begin point: Rising edge of CK - CK# defined by the end point of ODTLCNW Begin point: Rising edge of CK - CK# defined by the end point of ODTLCNW4 or ODTLCNW8 CK VCCQ/2 CK# t ADC VRTT_NOM DQ, DM DQS, DQS# End point: Extrapolated point at VRTT_NOM t ADC VRTT_NOM TSW 21 TSW 11 VSW 2 TSW 22 TSW 12 VSW 1 VRTT_WR End point: Extrapolated point at VRTT_WR VSS Q LOGIC Devices Incorporated www.logicdevices.com 39 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) OUTPUT DRIVER IMPEDANCE FIGURE 19 - OUTPUT DRIVER 34 OHM OUTPUT DRIVER IMPEDANCE The 34Ω driver (MR1[5,1]=01) is the default driver. Unless otherwise stated, all timings and specifications listed herein apply to the 34Ω driver only. Its impedance RON is defined by the value of the external reference resistor RZQ as follows: RON34=RZQ/7 (with nominal RZQ=240Ω±1%) and is actually 34.3Ω±1%. The 34Ω output driver impedance characteristics are listed in Table 35. Chip in drive mode Output driver VCCQ IPU To other circuitry such as RCV, . . . RONPU DQ IOUT RONPD IPD VOUT VSSQ TABLE 35: 34Ω DRIVER IMPEDANCE CHARACTERISTICS MR1[5,1] RON RESISTOR RON34PD 0, 1 34.3Ω RON34PU Pull-Up/Pull-Down mismatch (MMPUPD) PACKAGE OUTLINE DIMENSIONS VOUT MIN TYP MAX UNITS NOTES 0.2/VccQ 0.6 1.0 1.1 RZQ/7 1 0.5/VccQ 0.9 1.0 1.1 RZQ/7 1 0.8/VccQ 0.9 1.0 1.4 RZQ/7 1 0.2/VccQ 0.9 1.0 1.4 RZQ/7 1 0.5/VccQ 0.9 1.0 1.1 RZQ/7 1 0.8/VccQ 0.6 1.0 1.1 RZQ/7 1 0.5/VccQ -10 n/a 10 % 1, 2 NOTES: 1. Tolerance limits assume RZQ of 240Ω (±1%) and are applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VccQ = Vcc, VssQ = Vss). Refer to “34 Ohm drive sensitivity” if either the temperature or the voltage changes after calibration 2. Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Mearure both RONPU and RONPD at 0.5 x VccQ: MMPUD = RONPU - RONPD RONNOM LOGIC Devices Incorporated www.logicdevices.com 40 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) 34 OHM OUTPUT DRIVER IMPEDANCE 34 OHM DRIVER The 34Ω driver’s current range has been calculated and summarized in Table 37 for Vcc=1.5V, Table 38 for Vcc=1.575V and Table 39 for Vcc=1.425V. The individual pull-up and pull-down resistors (RON34PD and RON34PU) are defined as follows with the Impedance Calculations listed in Table 36. • RON34PD=(VOUT)/[IOUT]: RON34PU is turned off • RON34PU=(VccQ-VOUT)/[IOUT]: RON34PD is turned off TABLE 36: 34Ω DRIVER PULL-UP AND PULL-DOWN IMPEDANCE CALCULATIONS PACKAGE OUTLINE DIMENSIONS MR1[5,1] RON RON MIN RZQ = 240Ω±1% RZQ = (240Ω±1%)/7 RESISTOR RON34PD 0, 1 34.3Ω RON34PU VOUT TYP MAX UNITS 237.6 240 242.4 Ω 33.9 34.3 34.6 Ω MIN TYP MAX 0.2/VccQ 2.04 34.3 38.1 UNITS Ω 0.5/VccQ 30.5 34.3 38.1 Ω 0.8/VccQ 30.5 34.3 48.5 Ω 0.2/VccQ 30.5 34.3 48.5 Ω 0.5/VccQ 30.5 34.3 38.1 Ω 0.8/VccQ 20.4 34.3 38.1 Ω TABLE 37: 34Ω DRIVER IOH/IOL CHARACTERISTICS: VCC = VPCC Q = 1.5V ACKAGE OUTLINE DIMENSIONS MR1[5,1] RON RESISTOR RON34PD 0, 1 34.3Ω RON34PU VOUT MIN TYP MAX UNITS IOL @ 0.2 x VccQ 14.7 8.8 7.9 mA IOL @ 0.5 x VccQ 24.6 21.9 19.7 mA IOL @ 0.8 x VccQ 39.3 35 24.8 mA IOL @ 0.2 x VccQ 39.3 35 24.8 mA IOL @ 0.5 x VccQ 24.6 21.9 19.7 mA IOL @ 0.8 x VccQ 14.7 8.8 7.9 mA TABLE 38: 34Ω DRIVER IOH/IOL CHARACTERISTICS: VCC=VCC Q=1.575V PACKAGE OUTLINE DIMENSIONS MR1[5,1] RON RESISTOR RON34PD 0, 1 34.3Ω RON34PU LOGIC Devices Incorporated www.logicdevices.com VOUT MIN TYP IOL @ 0.2 x VccQ 15.5 9.2 8.3 mA IOL @ 0.5 x VccQ 25.8 23 20.7 mA IOL @ 0.8 x VccQ 41.2 36.8 26 mA IOL @ 0.2 x VccQ 41.2 36.8 26 mA IOL @ 0.5 x VccQ 25.8 23 20.7 mA IOL @ 0.8 x VccQ 15.5 9.2 8.3 mA 41 MAX UNITS High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) 34 OHM OUTPUT DRIVER IMPEDANCE TABLE 39: 34Ω DRIVER IOH/IOL CHARACTERISTICS: VCC=VCC Q=1.425V PACKAGE OUTLINE DIMENSIONS MR1[5,1] RON RESISTOR RON34PD 0, 1 34.3Ω RON34PU VOUT MIN TYP MAX UNITS IOL @ 0.2 x VccQ 14 8.3 7.5 mA IOL @ 0.5 x VccQ 23.3 20.8 18.7 mA IOL @ 0.8 x VccQ 37.3 33.3 23.5 mA IOL @ 0.2 x VccQ 37.3 33.3 23.5 mA IOL @ 0.5 x VccQ 23.3 20.8 18.7 mA IOL @ 0.8 x VccQ 14 8.3 7.5 mA 34Ω OUTPUT DRIVER SENSITIVITY If either the temperature or voltage changes after ZQ calibration, the tolerance limits listed in Table 35 can be expected to widen according to Table 40 and 41. TABLE 40: 34Ω OUTPUT DRIVER SENSITIVITY DEFINITION Symbol MIN MAX UNITS RON @ 0.8 x VccQ 0.9 - dRONdTH x [∆T] + dRONdVH x [∆V] 1.1 - dRONdTH x [∆T] + dRONdVH x [∆V] RZQ/7 RON @ 0.5 x VccQ 0.9 - dRONdTM x [∆T] + dRONdVM x [∆V] 1.1 - dRONdTM x [∆T] + dRONdVM x [∆V] RZQ/7 RON @ 0.2 x VccQ 0.9 - dRONdTL x [∆T] + dRONdVL x [∆V] 1.1 - dRONdTL x [∆T] + dRONdVL x [∆V] RZQ/7 TABLE 41: 34Ω OUTPUT DRIVER VOLTAGE AND TEMPERATURE SENSITIVITY Change MIN MAX UNITS dRONdTM 0 1.5 %/°C dRONdVM 0 0.13 %/mV dRONdTL 0 1.5 %/°C dRONdVL 0 0.13 %/mV dRONdTH 0 1.5 %/°C dRONdVH 0 0.13 %/mV LOGIC Devices Incorporated www.logicdevices.com 42 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) ALTERNATIVE 40 OHM DRIVER TABLE 42 - 40Ω DRIVER IMPEDANCE CHARACTERISTICS MR1[5,1] RON RESISTOR RON40PD 0, 1 40.0Ω RON40PU Pull-Up/Pull-Down mismatch (MMPUPD) PACKAGE OUTLINE DIMENSIONS VOUT MIN TYP MAX UNITS NOTES 0.2/VccQ 0.6 1.0 1.1 RZQ/6 1 0.5/VccQ 0.9 1.0 1.1 RZQ/6 1 0.8/VccQ 0.9 1.0 1.4 RZQ/6 1 0.2/VccQ 0.9 1.0 1.4 RZQ/6 1 0.5/VccQ 0.9 1.0 1.1 RZQ/6 1 0.8/VccQ 0.6 1.0 1.1 RZQ/6 1 0.5/VccQ -10 n/a 10 % 1, 2 NOTES: 1. Tolerance limits assume RZQ of 240Ω (±1%) and are applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VccQ = Vcc, VssQ = Vss). Refer to “40 Ohm drive sensitivity” if either the temperature or the voltage changes after calibration 2. Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Mearure both RONPU and RONPD at 0.5 x VccQ: MMPUPD = RONPU - RONPD x 100 RONNOM 40Ω OUTPUT DRIVER SENSITIVITY If either the temperature or voltage changes after I/O calibration, the tolerance limits listed in Table 42 can be expected to widen according to Table 43 and 44. TABLE 43: 40Ω OUTPUT DRIVER SENSITIVITY DEFINITION Symbol MIN MAX UNITS RON @ 0.8 x VccQ 0.9 - dRONdTH x [∆T] + dRONdVH x [∆V] 1.1 - dRONdTH x [∆T] + dRONdVH x [∆V] RZQ/6 RON @ 0.5 x VccQ 0.9 - dRONdTM x [∆T] + dRONdVM x [∆V] 1.1 - dRONdTM x [∆T] + dRONdVM x [∆V] RZQ/6 RON @ 0.2 x VccQ 0.9 - dRONdTL x [∆T] + dRONdVL x [∆V] 1.1 - dRONdTL x [∆T] + dRONdVL x [∆V] RZQ/6 LOGIC Devices Incorporated www.logicdevices.com 43 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) ALTERNATIVE 40 OHM DRIVER TABLE 44: 40Ω OUTPUT DRIVER VOLTAGE AND TEMPERATURE SENSITIVITY Change MIN MAX dRONdTM 0 1.5 UNITS %/°C dRONdVM 0 0.15 %/mV dRONdTL 0 1.5 %/°C dRONdVL 0 0.15 %/mV dRONdTH 0 1.5 %/°C dRONdVH 0 0.15 %/mV OUTPUT CHARACTERISTICS AND OPERATING CONDITIONS The SDRAM uses both single-ended and differential output drivers. The single-ended output driver is summarized in Table 45 while the differential output driver is summarized in Table 46. TABLE 45: SINGLE-ENDED OUTPUT DRIVER CHARACTERISTICS PACKAGE OUTLINE DIMENSIONS Parameter/Condition Output leakage current: DQ are disabled; Symbol MIN UNITS NOTES IOZ -5 MAX 5 uA 1 SRQSE 2.5 6 V/ns 1, 2, 3, 4 0V ≤ VOUT≤ VccQ; ODT is disabled; ODT is HIGH Output slew rate: Single-ended; for rising and falling edges, measure between VOL(AC) = VREF - 0.1 x VccQ and VOH (AC) = VREF + 0.1 x VccQ Single-ended DC high-level output voltage VOH(DC) 0.8 x VccQ V 1, 2, 5 Single-ended DC mid-point level output voltage VOM(DC) 0.5 x VccQ V 1, 2, 5 Single-ended DC low-point level output voltage VOL(DC) 0.2 x VccQ V 1, 2, 5 Single-ended DC high-point level output voltage VOH(AC) VTT + 0.1 x VccQ V 1, 2, 3, 6 Single-ended DC low-point level output voltage VOL(AC) VTT - 0.1 x VccQ V 1, 2, 3, 6 Delta RON between pull-up and pull-down for DQ/DQS MMPUPD % 1, 7 Test load for AC timing and output slew rates -10 10 3 Output to VTT (VccQ/2) via 25Ω resistor NOTES: 1. RZQ of 240Ω (±1%) with RZQ/7 enabled (default 34Ω driver) and is appli- 5. See Table 35 on page 40 IV curve linearity. Do not use AC Test load. cable after proper ZQ calibration has been performed at a stable tem- 6. See Table 47 on page 47 for output slew rate. perature and voltage (VccQ = Vcc, VssQ = Vss). 7. See Table 35 on page 40 for additional information. 2. VTT = VccQ/2 8. See Figure 29 on page 66 for an example of a single-ended output 3. See Figure 31 on page 68 for the test load configuration. 4. The 6V/ns maximum is applicable for a single DQ signal when it is switch- signal. ing from either HIGH to LOW or LOW to HIGH while the remaining DQ signals in the same byte lane are combinations, the maximum limit of 6V/ ns maximum is reduced to 5V/ns. LOGIC Devices Incorporated www.logicdevices.com 44 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 46: DIFFERENTIAL OUTPUT DRIVER CHARACTERISTICS PACKAGE OUTLINE DIMENSIONS Parameter/Condition Output leakage current: DQ are disabled; Symbol MIN MAX UNITS NOTES IOZ -5 5 uA 1 SRQDIFF 5 12 V/ns 1 VOX(AC) VREF-150 VREF+150 mV 1, 2, 3 0V ≤ VOUT≤ VccQ; ODT is HIGH Output slew rate: Differential; for rising and falling edges, measure between VOLDIFF(AC) = - 0.2 x VccQ and VOH (AC) = + 0.2 x VccQ Output differential cross-point voltage Differential high-level output voltage VOHDIFF(AC) + 0.2 x VccQ V 1, 4 Differential low-level output voltage VOLDIFF(AC) - 0.2 x VccQ V 1, 4 % 1, 5 Delta RON between pull-up and pull-down for DQ/DQS MMPUPD -10 10 Output to VTT (VccQ/2) via 25Ω resistor Test load for AC timing and output slew rates 3 NOTES: 1. RZQ of 240Ω (±1%) with RZQ/7 enabled (default 34Ω driver) and is appli- 4. See Table 48 on page 65 for the output slew rate. cable after proper ZQ calibration has been performed at a stable tem- 5. See Table 35 on page 58 for additional information. perature and voltage (VccQ = Vcc, VssQ = Vss). 6. See Figure 30 on page 67 for an example of a differential output 2. VREF = VccQ/2 signal. 3. See Figure 31 on page 68 for the test load configuration. FIGURE 20 - DQ OUTPUT SIGNAL MAX output VOH(AC) VOL(AC) MIN output LOGIC Devices Incorporated www.logicdevices.com 45 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) OUTPUT CHARACTERISTICS AND OPERATING CONDITIONS FIGURE 21 - DIFFERENTIAL OUTPUT SIGNAL MAX output VOH(DIFF) X X VOX(AC) MAX X VOX(AC) MIN X VOL(DIFF) MIN output REFERENCE OUTPUT LOAD Figure 22 represents the effective reference load of 25Ω used in defining the relevant device AC timing parameters (except ODT reference timing) as well as the output slew rate measurements. It is not intended to be a precise representation of a particular system environment or a depiction of the actual load presented by any specific Industry test system/apparatus. System designers should use IBIS or other simulation tools to correlate the timing reference load presented or exhibited on the system or system environment. FIGURE 22 - REFERENCE OUTPUT LOAD FOR AC TIMING AND OUTPUT SLEW RATE DUT VREF DQ DQS DQS# VCCQ/2 RTT = 25Ω VTT = VCCQ/2 Timing Reference Point ZQ RZQ = 240Ω VSS LOGIC Devices Incorporated www.logicdevices.com 46 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) SLEW RATE DEFINITIONS FOR SINGLE-ENDED OUTPUT SIGNALS The single-ended output driver is summarized in Table 45. With the reference load for timing measurements, the output slew-rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single-ended signals as indicated in Table 47 and Figure 23. TABLE 47: SINGLE-ENDED OUTPUT SLEW RATE Measured Output Slew Rate (Linear Signals) Output PACKAGE OUTLINE DIMENSIONS Edge From To Rising VOL(AC) VOH(AC) Falling VOH(AC) VOL(AC) Calculation VOH(AC) - VOL (AC) ∆TRSE DQ VOH(AC) - VOL(AC) ∆TFSE FIGURE 23 - NOMINAL SLEW RATE DEFINITION FOR SINGLE-ENDED OUTPUT SIGNALS LOGIC Devices Incorporated www.logicdevices.com 47 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) SLEW RATE DEFINITIONS FOR DIFFERENTIAL OUTPUT SIGNALS The differential output driver is summarized in Table 46. With the reference load for timing measurements, the output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for differential signals, as shown in Table 48 and Figure 33. TABLE 48: DIFFERENTIAL OUTPUT SLEW RATE DEFINITION Measured Output Slew Rate (Linear Signals) Output PACKAGE OUTLINE DIMENSIONS Edge From To Rising VOLDIFF(AC) VOHDIFF(AC) Falling VOHDIFF(AC) VOLDIFF(AC) Calculation VOHDIFF(AC) - VOL DIFF(AC) ∆TRDIFF DQS, DQS\ VOHDIFF(AC) - VOLDIFF(AC) ∆TFDIFF FIGURE 24 - NOMINAL DIFFERENTIAL OUTPUT SLEW RATE DEFINITION FOR DQS, DQS# LOGIC Devices Incorporated www.logicdevices.com 48 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 49: SPEED BINS PACKAGE OUTLINE DIMENSIONS -25 (DDR3-800) [CWL=2.5; 6-6-6] Parameter -19 (DDR3-1066) -15 (DDR3-1333) [CWL=1.875; 8-8-8] [CWL=1.5; 10-10-10] Symbol MIN MAX MIN MAX MIN tRCD 15 - 15 - 15 - ns PRECHARGE command period tRP 15 - 15 - 15 - ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC 52.5 - 52.5 - 51 - ns tRAS 37.5 60ms 37.5 60ms 36 60ms ns 1 CWL=5 tCK (AVG) 3 3.3 3 3.3 3 3.3 ns 2 CWL=6 tCK (AVG) ns 3 ns 3 ns 2 ACTIVATE to internal READ or WRITE delay time ACTIVATE-to-PRECHARGE command period CL=5 CL=6 CL=8 CL=10 MAX UNITS NOTES CWL=7 tCK (AVG) CWL=5 tCK (AVG) CWL=6 tCK (AVG) ns 3 CWL=7 tCK (AVG) ns 3 CWL=5 tCK (AVG) CWL=6 tCK (AVG) CWL=7 2.5 3.3 3.3 2.5 3.3 2.5 ns 3 ns 2,3 tCK (AVG) ns 3 CWL=5 tCK (AVG) ns 3 CWL=6 tCK (AVG) CWL=7 tCK (AVG) 1.875 <2.5 1.875 1.5 Supported CL Settings Supported CWL Settings <2 <1.875 ns 3 ns 2,3 5,6 5, 6, 8 5, 6, 8, 10 CK 5 5, 6 5, 6, 7 CK NOTES: 1. tREFI depends on tOPER 2. The CL and CWL setting result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be ful- 3. Reserved (filled blocks) settings are not allowed. filled. LOGIC Devices Incorporated www.logicdevices.com 49 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A Parameter TC = 0˚C to <85˚C Clock period average: DLL TC = 85˚C to 105˚C disable mode TC = >105˚C to ≤125˚C Clock period average: DLL enable mode HIGH pulse width average LOW pulse width average Clock period JITTER DLL LOCKED DLL LOCKING t Symbol CKDLL_DIS -19 (DDR3-1066) -15 (DDR3-1333) [CWL=1.875; 8-8-8] [CWL=1.5; 10-10-10] MIN MAX MIN MAX 8 7800 8 7800 8 3900 8 3900 8 2900 8 2900 Units ns Notes 9,42 9,42 9,42 10,11 12 12 13 13 See SPEED BIN TABLE (#49) for tCK range allowed -25 (DDR3-800) [CWL=2.5; 6-6-6] MIN MAX 8 7800 8 3900 8 2900 ns CK CK ps ps ps 14 CK (AVG) tCK (AVG) 15 t - tCK (AVG) t -175 -194 -209 -222 -232 -241 -249 -257 -263 -269 200 180 147 -132 180 160 132 -118 160 140 175 -157 157 -140 194 -175 175 -155 209 -188 188 -168 222 -200 200 -177 232 -209 209 -186 241 -217 217 -193 249 -224 224 -200 257 -231 231 -205 263 -237 237 -210 269 -242 242 -215 tERRnPER MIN = (1+0.68ln[n]) x tJITPER MIN tERRnPER MAX = (1+0.68ln[n]) x tJITPER MAX 140 155 168 177 186 193 200 205 210 215 118 ps ps ps ps ps ps ps ps ps ps ps ps ps ps 17 17 17 17 17 17 17 17 17 17 17 16 16 17 MIN=tCK (AVG) MIN+tJITPER MIN; MAX=tCK (AVG)MAX+tJITPER MAX 0.53 0.53 80 70 0.43 - 0.47 0.47 -80 -70 - 0.43 0.53 0.53 90 80 0.43 - 0.47 0.47 -90 -80 - 0.43 ERRnPER 0.53 0.53 100 90 0.43 - 0.47 0.47 -100 -90 CH (ABS) 0.43 t CH (AVG) t CL (AVG) t JITPER t JITPER, LCK t CLK (ABS) CL (ABS) -147 Clock absolute HIGH pusle width Clock absolute period t JITCC t JITCC, LCK ERR2PERR t ERR3PERR t t ERR4PERR t ERR5PERR t ERR6PERR t ERR7PERR t ERR8PERR t ERR9PERR t ERR10PERR t ERR11PERR ERR12PERR t t DLL LOCKED DLL LOCKING 2 Cycles t Clock absolute LOW pulse width Cycle-to-Cycle JITTER Cumulave error across 3 Cycles 4 Cycles 5 Cycles 6 Cycles 7 Cycles 8 Cycles 9 Cycles 10 Cycles 11 Cycles 12 Cycles n = 13, 14 … 49, 50 Cycles High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 50 www.logicdevices.com LOGIC Devices Incorporated L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 50 (SHEET 1 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS Parameter Data SETUP me to DQS, DQS\ Data SETUP me to DQS, DQS\ Data HOLD me from DQS, DQS\ Minimum Data Pulse Width DQS, DQS\ to DQ SKEW, per access Units Notes -19 (DDR3-1066) -15 (DDR3-1333) [CWL=1.875; 8-8-8] [CWL=1.5; 10-10-10] MIN MAX MIN MAX 18,19 19,20 18,19 19,20 18,19 19,20 41 21 ps ps ps ps ps ps ps 22,23 - tCK (AVG) 22,23 30 180 65 165 400 ps - - ps 25 200 75 250 100 200 490 250 ps 0.38 250 125 - - -500 0.38 300 300 150 - - -600 0.38 400 400 Base (specificaon) VREF @ 1V/ns Base (specificaon) VREF @ 1V/ns Base (specificaon) VREF @ 1V/ns -25 (DDR3-800) [CWL=2.5; 6-6-6] Symbol MIN MAX DQ Input Timing 75 t DS AC175 250 125 t DS AC150 275 150 t DH AC100 250 t 600 DIPW DQ Ouput Timing 200 DQSQ QH -800 t t LZ (DQ) t DQ LOW-Z me from CK, CK\ DQ Output HOLD me from DQS, DQS\ DQ HIGH-A me from CK, CK\ 0.3 0.38 0.38 -800 0.9 1 Note 27 400 400 Note 24 10 400 0.25 0.55 0.55 - 0.3 0.38 0.38 -600 0.9 1 -300 -0.25 0.45 0.45 0.2 0.2 0.9 0.3 Note 27 300 300 Note 24 10 300 0.25 0.55 0.55 - 0.3 0.4 0.4 -500 0.9 1 -255 -0.25 0.45 0.45 0.2 0.2 0.9 0.3 Note 27 250 250 Note 24 10 255 0.25 0.55 0.55 - CK CK CK ps ps CK ns ps CK CK CK CK CK CK CK 23,27 21 21 22,23 22,23 23,24 26 23 25 25 25 RPST t t DQSCK t DQSK DLL_DIS t QSH t QSL t LZ (DQS) t HZ (DQS) t RPRE t -0.25 DQSS t 0.45 DQSL t 0.45 DQSH t 0.2 DSS t 0.2 DSH t 0.9 WPRE t 0.3 WPST DQ Strobe Output Timing -400 t HZ (DQ) DQ Strobe Input Timing DQS,DQS\ RISING to CK, CK\ RISING DQS, DQS\ DIFFERENTIAL Input Low pulse width DQS, DQS\ DIFFERENTIAL Input HIGH pulse width DQS, DQS\ FALLING Setup to CK, CK\ RISING DQS, DQS\ FALLING Hold from CK, CK\ RISING DQS, DQS\ DIFFERENTIAL WRITE preamble DQS, DQS\ DIFFERENTIAL WRITE postamble DQS, DQS\ RISING to/from RISING CK, CK\ DQS, DQS\ RISING to/from RISING CK, CK\ when DLL is disabled DQS, DQS\ DIFFERENTIAL Output HIGH me DQS, DQS\ DIFFERENTIAL Output LOW me DQS, DQS\ LOW-Z me (RL-1) DQS, DQS\ HIGH-Z me (RL+BL/2) DQS, DQS\ DIFFERENTIAL READ preamble DQS, DQS\ DIFFERENTIAL READ postamble High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 51 www.logicdevices.com LOGIC Devices Incorporated L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 50 (SHEET 2 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS Parameter 2KB page size 1KB page size DLL Locking me Base (specificaon) CTRL, CMD, ADDR setup to CK, VREF @ 1V/ns CK\ Base (specificaon) CTRL, CMD, ADDR setup to CK, VREF @ 1V/ns CK\ Base (specificaon) CTRL, CMD, ADDR hold to CK, VREF @ 1V/ns CK\ Minimum CTRL, CMD, ADDR pulse width ACTIVATE to Internal READ or WRITE delay PRECHARGE command period ACTIVATE-to-PRECHARGE command period ACTIVATE-to-ACTIVATE command period ACTIVATE-to-ACTIVATE minimum command period Four ACTIVATE windows for 1KB page size Four ACTIVATE windows for 2KB page size WRITE recovery me Delay from start of internal WRITE transacon to internal READ command READ-to-PRECHARE me CAS\-to-CAS\ command delay Auto precharge WRITE recovery + PRECHARGE me MODE REGISTER SET command cycle me MODE REGISTER SET command update delay MULTIPURPOSE REGISTER READ burst end to mode register set for mulpurpose register exit CK ps ps ps ps ps ps ps ns ns ns ns Units 31 28 29,30 20,30 29,30 20,30 29,30 20,30 41 31 31 31,32 31 Notes 31 CK CK -25 (DDR3-800) -19 (DDR3-1066) -15 (DDR3-1333) [CWL=2.5; 6-6-6] [CWL=1.875; 8-8-8] [CWL=1.5; 10-10-10] Symbol MIN MAX MIN MAX MIN MAX Command and Address Timing t 512 512 512 DLLK 200 125 65 t IS AC175 375 300 240 350 275 190 t IS AC150 500 425 340 275 200 140 t IH DC100 375 300 240 t 900 780 620 IPW t See "Speed Bin Table (#49) for tRCD RCD t See "Speed Bin Table (#49) for tRP RP t See "Speed Bin Table (#49) for tRAS RAS t See "Speed Bin Table (#49) for tRC RCD MIN=greater of 4CK MIN=greater of 4CK MIN=greater of 4CK or 6ns or 10ns or 7.5ns MIN=greater of 4CK or 6ns MIN=greater of 4CK or 10ns 31 31 t RRD ns ns - 31,32,33 t 30 45 CK 31,34 MIN = 15ns; MAX = n/a CK t 37.5 50 WR MIN = greater of 4CK or 7.5ns; MAX = n/a CK CK CK - WTR MIN = greater of 4CK or 7.5ns; MAX = n/a MIN = 4CK; MAX = n/a t t MOD 40 50 t RTP t CCD MIN = WR + tRP/tCK (AVG); MAX = n/a CK CK FAW DAL MIN = 4CK; MAX = n/a MIN = greater of 12CK or 15ns; MAX = n/a CK t MRD MIN = 1CK; MAX = n/a MPRR t t High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 52 www.logicdevices.com LOGIC Devices Incorporated L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 50 (SHEET 3 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS ZQCL command: Long Calibraon me Parameter Normal operaon POWER-UP and RESET operaon ZQCS command: Short Calibraon Time Exit RESET from CKE HIGH to a valid command ZQINIT 512 - -25 (DDR3-800) [CWL=2.5; 6-6-6] Symbol MIN MAX Calibraon Timing t VDDPR t XPR - 512 CK Units - CK CK -19 (DDR3-1066) -15 (DDR3-1333) [CWL=1.875; 8-8-8] [CWL=1.5; 10-10-10] MIN MAX MIN MAX 512 - CK ms ms ns ms ms ms μs μs μs MIN = 0; MAX = 200 MIN = n/a; MAX = 200 64 32 24 7.8 3.9 2.9 CK ns MIN = greater of 5CK or tRFC + 10ns; MAX = n/a CK MIN = 110; MAX = 9 x tREFI MIN = n/a; MAX = 200 t 256 256 256 ZQOPER t 64 64 64 ZQCS Inializaon and RESET Timing MIN = greater of 5CK or tRFC + 10ns; MAX = n/a t t RPS t IOZ REFRESH Timing Begin power supply ramp to power supplies stable RESET\ LOW to power supplies stable RESET\ LOW to I/O and RTT HIGH-Z t XS MIN = tDLLK (MIN); MAX = n/a CK - XSDLL MIN = tCKE (MIN) + CK; MAX = n/a t SELF REFRESH Timing t REFI CKESR CK CK MIN = greater of 5CK or 10ns; MAX = n/a t t t CKSRX t MIN = greater of 5CK or 10ns; MAX = n/a CKSRE RFC REFRESH-to-ACTIVATE or REFRESH command period Maximum REFRESH period Maximum REFRESH period/interval TC ≤ 85˚C TC >85˚C ≤ 105˚C TC >105˚C ≤ 125˚C TC ≤ 85˚C TC >85˚C ≤ 105˚C TC >105˚C ≤ 125˚C Exit SELF REFRESH TO commands not requiring a locked DLL EXIT SELF REFRESH TO commands requiring a locked DLL MINIMUM CKE LOW pulse width for SELF REFRESH entry to SELF REFRESH exit ming Valid clocks aer SELF REFRESH entry or POWER-DOWN entry Valid clocks before SELF REFRESH exit, POWER-DOWN exit, or RESET exit Notes 35 36 36 36 36 36 36 28 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 53 www.logicdevices.com LOGIC Devices Incorporated L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 50 (SHEET 4 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS CKE MIN pulse width Parameter -25 (DDR3-800) -19 (DDR3-1066) -15 (DDR3-1333) [CWL=2.5; 6-6-6] [CWL=1.875; 8-8-8] [CWL=1.5; 10-10-10] Symbol MIN MAX MIN MAX MIN MAX POWER-DOWN Timing Greater of 3CK or Greater of 3CK or Greater of 3CK or t CKE (MIN) 7.5ns 5.625ns 5.625ns MIN = 1; MAX = n/a MIN = tCKE (MIN); MAX = 60ms t CPDED t PD Units CK CK CK CK Command pass disable delay POWER-DOWN entry to POWER-DOWN exit ming WL - 1CK t ANPD Begin POWER-DOWN period prior to CKE registered HIGH CK CK ANPD + tXPDLL CK Greater of tANPD or tRFC - REFRESH command to CKE LOW me MIN = 1 CK PDE MIN = 1 CK CK CK t t MIN = WL + 4 + tWR/tCK (AVG) CK t WRPDEN MIN = WL + 2 + tWR/tCK (AVG) CK t ACTPDEN MIN = 1 CK PDX PRPDEN MIN = RL + 4 + 1 MIN = tMOD (MIN) POWER-DOWN Entry MINIMUM Timing POWER-DOWN entry period: ODT eher synchronous or asynchronous POWER-DOWN exit period: ODT either synchronous or asynchronous ACTIVATE command to POWER-DOWN entry PRECHARGE/PRECHARGE ALL command to POWER-DOWN entry REFRESH command to POWER-DOWN entry MRS command to POWER-DOWN entry RDPDEN t REFPDEN t MRSPDEN WRPDEN MIN = WL + 4 + WR + 1 t WRAPDEN BL8 (OTF, MRS) BC4OTF t MIN = Greater of 3CK or 7.5ns; MAX = n/a CK CK CK XP MIN = Greater of 10CK or 24ns; MAX = n/a MIN = Greater of 3CK or 6ns; MAX = n/a MIN = WL + 2 + WR + 1 t BL8 (OTF, MRS) BC4OTF BC4MRS t XPDLL t t WRAPDEN POWER-DOWN Exit Timing BC4MRS READ/READ with AUTO PRECHARGE commant to POWER-DOWN entry WRITE Command to POWERDOWN entry WRITE with AUTO PRECHARGE command to POWER-DOWN entry DLL on, any valid command, or DLL off to commands not requiring DLL locked PRECHARGE POWER-DOWN with DLL off to command requiring DLL locked Notes 37 28 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 54 www.logicdevices.com LOGIC Devices Incorporated L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 50 (SHEET 5 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS Parameter RTT synchronous TURN-ON delay RTT synchronous TURN-OFF delay RTT TURN-ON from ODTL ON reference RTT TURN-OFF from ODTL OFF reference Asynchronous RTT TURN-ON delay (POWER-DOWN with DLL OFF) Asynchronous RTT TURN-OFF delay (POWER-DOWN with DLL OFF) ODT HIGH me without WRITE command or with WRITE command and BC8 ODT HIGH me without WRITE command or with WRITE command and BC4 RTT_NOM-to=RTT_WR change skew RTT_WR-to-RTT_NOM change skew - BC4 RTT_WR-to-RTT_NOM change skew - BC8 RTT dynamic change skew First DQS, DQS\ RISING edge DQS; DQS\ delay WRITE Leveling SETUP from rising CK, CK\ crossing to rising DQS, DQS\ crossing WRITE Leveling HOLD from rising DQS, DQS\ crossing to rising CK, CK\ crossing WRITE Leveling output delay WRITE Leveling output error AON AOF AONPD t t -400 0.3 400 0.7 -25 (DDR3-800) [CWL=2.5; 6-6-6] Symbol MIN MAX ODT Timing ODTL on ODTL off t 300 0.7 -250 0.3 250 0.7 -19 (DDR3-1066) -15 (DDR3-1333) [CWL=1.875; 8-8-8] [CWL=1.5; 10-10-10] MIN MAX MIN MAX -300 0.3 MIN = 2; MAX = 8.5 t t CK CK ps CK Units 38 38 40 23,38 39,40 Notes 39 40 ns CK CK CK CK ns 0.7 CK CK MIN = 2; MAX = 8.5 0.3 - ps AOFPD WL - 2CK 4CK + ODTL OFF 6CK + ODTL OFF 0.3 0.7 40 25 - ps t - 195 - ns ns CK 0.7 40 25 - 195 9 2 MIN = 6; MAX = n/a - 245 - 0 0 ODTH8 Dynamic ODT Timing ODTLCNW ODTLCNW4 ODTLCNW8 t 0.3 ADC WRITE Leveling Timing 40 25 - 245 9 2 CK 325 - 0 0 MIN = 4; MAX = n/a WLS 325 9 2 ODTH4 WLH 0 0 t WLMRD t WLDQSEN t WLO WLOE t High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 55 www.logicdevices.com LOGIC Devices Incorporated L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 50 (SHEET 6 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) NOTES 1. Parameters are applicable with 0˚C ≤ Tc ≤ +95˚C and Vcc/VccQ = + 1.5V ± 0.075V. 2. All voltages are referenced to Vss. 3. Output timings are only valid for RON34 output buffer selection. 4. Unit tCK (AVG) represents the actual tCK (AVG) of the input clock under operation. Unit CK represents one clock cycle of the input clock, counting the actual clock edges. 5. 6. 7. deviate from one cycle to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL locking time. AC timing and ICC tests may use a VIL-to-VIH swing of up to 900mV I the test environment, but input timing is still referenced to VREF (except tIS, tIH, tDS, and tDH use the AC/DC trip points and CK, CK\ and DQS, DQS\ use their crossing points). The minimum slew rate for the input signals used to test the device is 1V/ns for single-ended inputs and 2V/ ns for differential inputs in the range between VIL (AC) and VIH (AC). All timings that use time-based values (ns, μs, ms) should use tCK (AVG) to determine the correct number of clocks (Table 50 uses CK or CK (AVG) interchangeably). In the case of non-interger results, all minimum limits are to be rounded up to the nearest whole integer. The use of STROBE or DQSDIFF refers to the DQS and DQS\ differential crossing point when DQS is the rising edge. The use of CLOCK or CK refers to the CK and CK\ differential crossing point when CK is the rising edge. 8. This output load is used for all AC timing (except ODT reference timing) and slew rates. The actual test load may be different. The output signal voltage reference point is VccQ/2 for single-ended signals and the crossing point for differential signals. 9. When operating in DLL disable mode, LOGIC Devices, Inc. (LDI) does not warrant compliance with normal mode timings or functionality. 17. The cumulative jitter error (tERRnPER), where n is the number of clocks between 2 and 50, is the amount of clock time allowed to accumulate consecutively away from the average clock over n number of clock cycles. 18. tDS (base) and tDH (base) values are for a single-ended 1V/ns DQ slew rate and 2V/ns for differential DQS, DQS\ slew rate. 19. These parameters are measured from a data signal (DM, DQ0, DQ1 … DQn and so forth) transition edge to its respective data strobe signal (DQS, DQS\) crossing. 20. The setup and hold times are listed converting the base specification values (to which derating tables apply) to VREF when the slew rate is 1V/ns. These values, with a slew rate of 1V/ns are for reference only. 21. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJITPER (larger of tJITPER (MIN) or tJITPER (MAX) of the input clock (output deratings are relative to the SDRAM input clock). 22. Single-ended signal parameter. 23. The SDRAM output timing is aligned to the nominal or average clock. Most output parameters must be derated by the actual jitter error when input clock jitter is present, even when within specification. This results in each parameter becoming larger. The following parameters are required to be derated by subtracting tERR10PER (MAX); tDQSCK (MIN), tLZ (DQS) MAX, tLZ (DQ) MAX, and tAON (MAX). The parameter tRPRE (MIN) is derated by subtracting tJITPER (MAX), while tRPRE (MAX) is derated by tJITPER (MIN). 24. The maximum preamble is bound by tLZDQS (MAX). 10. The clock’s tCK (AVG) is the average clock over any 200 consecutive clocks and tCK (AVG) MIN is the smallest clock rate allowed, with the exception of a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed values specified and must be of a random Gaussian distribution in nature. 25. These parameters are measured from a data strobe signal (DQS, DQS\) crossing to its respective clock signal (CK, CK\) crossing. The specification values are not affected by the amount of clock jitter applied, as these are relative to the clock signal crossing. These parameters should be met whether clock jitter is present or not. 11. Spread spectrum is not included in the jitter specification values. However, the input clock can accommodate spread-spectrum at a sweep rate in the range of 20-60kHz with and additional 1% of tCK (AVG) as a long-term jitter component; however, the spread-spectrum may not use a clock rate below tCK (AVG) MIN. 26. The tDQSCK DLL_DIS parameter begins CL + AL - 1 cycles after the READ command. 27. The maximum postamble is bound by tHZDQS (MAX). 28. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT commands. In addition, after any change of latency tXPDLL, timing must be met. 29. tIS 30. These parameters are measured from a command/address signal transition edge to its respective clock (CK, CK\) signal crossing. The specification values are not affected by the amount of clock jitter applied as the setup and hold times are relative to the clock signal crossing that latches the command/address. These parameters should be met whether clock jitter is present or not. 31. For these parameters, the DDR3 SDRAM device supports tnPARAM (nCK) = RU (tPARAM [ns]/ tCK[AVG][ns]), assuming all input clock 12. 13. The clock’s tCH (AVG) and tCL (AVG) are the average half clock period over any 200 consecutive clocks and is the smallest clock half period allowed, with the exception of values specified and must of a random Gaussian distribution in nature. The period jitter (tJITPER) is the maximum deviation in the clock period from the average or nominal clock. It is allowed in either the positive or negative direction. 14. tCH (ABS) is the absolute instantaneous clock high pulse width as measured from one rising edge to the following falling edge. 15. tCL (ABS) is the absolute instantaneous clock low pulse width as measured from one falling edge to the following rising edge. 16. The cycle-to-cycle jitter (tJITCC) is the amount the clock period can LOGIC Devices Incorporated www.logicdevices.com 56 (base) and tIH (base) values are for a single-ended 1 V/ns control/command/ address slew rate and 2 V/ns CK, CK# differential slew rate. High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) NOTES CONTINUED 37. Although CKE is allowed to be registered LOW after a REFRESH command when tREFPDEN (MIN) is satisfied, there are cases where additional time such as tXPDLL (MIN) is required. 38. ODT turn-on time MIN is when the device leaves HIGH-Z and ODT resistance begins to turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT reference load is shown in Figure 23. 39. Half-clock output parameters must derated by the actual tERR10PER and tJITDTY when input clock jitter is present. This results in each parameter becoming larger. The parameters tADC (MIN) and tAOF(MIN) are each required to be derated by subtracting both tERR10PER (MAX) and tJITDTY (MAX). The parameters tADC (MAX) and tAOF (MAX) are required to be derated by subtracting both tERR10PER (MAX) and tJITDTY (MAX). 40. ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT turn-off time maximum is when the SDRAM buffer is in HIGH-Z. The ODT reference load is shown in Figure 24. This output load is used for ODT timings (see Figure 31). • For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL. 41. Pulse width of an input signal is defined as the width between the first crossing of VREF (DC) and the consecutive crossing of VREF(DC). 35. RESET\ should be LOW as soon as power starts to ramp to ensure the outputs are in HIGH-Z Until RESET\ is LOW, the outputs are at risk of driving the bus and could result in excessive current, depending on the bus activity. 42. 36. The refresh period is 64ms when Tc is less than or equal to 85˚C. This equates to an average refresh rate of 7.8124μs. However, nine REFRESH commands should be asserted at least once every 70.3μs. When Tc is greater than 85˚C, the refresh period is 32ms and when Tc is greater than 105˚C, the refresh period is 24ms. Should the clock rate be larger than tRFC(MIN), an AUTO REFRESH command should have at least one NOP command between it and another AUTO REFRESH command. Additionally, if the clock rate is slower than 40ns (25MHz) all REFRESH commands should be followed by a PRECHARGE ALL command. jitter specifications are satisfied. For example, the device will support tnRP (nCK) = RU (tRP)/tCK[AVG]) if all input clock jitter specifications are met. This means for DDR2-800; 6-6-6, of which tRP = 15ns, the device will support tnRP = RU (tRP/tCK [AVG]) = 6 as long as the input clock jitter specifications are met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0+6 are valid even if six clocks are less than 15ns due to input clock jitter. 32. During READs and WRITEs with AUTO PRECHARGE, the DDR3 SDRAM will hold off the internal PRECHARGE command until tRAS (MIN) has been satisfied. 33. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for tWR. 34. The start of the write recovery time is defined as follows: • For BL8 (fixed by MRS and OTF): Rising clock edge four clock cycles after WL. • For BC4 (OTF): Rising clock edge four clock cycles after WL. LOGIC Devices Incorporated www.logicdevices.com 57 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) COMMAND AND ADDRESS SETUP, HOLD, AND DERATING The total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH (base) values (Tables 51) to the ∆tIS and ∆tIH derating values (Table 52), respectively. Although the total setup time for slow slew rates might be negative, a valid input signal is still required to complete the transition and to reach VIH(AC)/VIL(AC) (see Figure 14 for input signal requirements). For slew rates which fall between the values listed in Table 52 and Table 53, the derating values may be obtained by linear interpolation. Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC) MIN. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC) MAX. If the actual signal is always earlier than the nominal slew rate line between the shaded “VREF(DC)-to-AC region”, use the nominal slew rate for derating value (see Figure 25). If the actual signal is later than the nominal slew rate line anywhere between the shaded “VREF(DC)-to-AC region”, the slew rate of a tangent line to the actual signal from the AC level to the DC level is used for the derating value (see Figure 27). Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC) MAX and the first crossing of VREF(DC). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC) MIN and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between the shaded “DC-to-VREF(DC) region”, use the nominal slew rate for derating value (see Figure 26). If the actual signal is earlier than the nominal slew rate line anywhere between the shaded ”DC-to-VREF(DC) region”, the slew rate of a tangent line to the actual signal from the DC level to the VREF(DC) level is used for the derating value (see Figure 28). TABLE 51: COMMAND AND ADDRESS SETUP AND HOLD VALUES REFERENCED AT 1V/NS – AC/DC BASED DDR3-1333 UNITS tIS(base)AC175 Symbol DDR3-800 200 DDR3-1066 125 65 ps REFERENCE VIH(AC)/VIL(AC) tIS(base)AC150 350 275 190 ps VIH(AC)/VIL(AC) tIH(base)DC100 275 200 140 ps VIH(AC)/VIL(AC) TABLE 52: DERATING VALUES FOR tIS/tIH – AC175/DC100-BASED Shaded cells indicate slew-rate combinations not supported ∆tIS, ∆tIH Derating (ps) - AC/DC-Based, AC175 Threshold; VIH(AC) = VREF(DC) + 175mV, VIL(AC) = VREF(DC) - 175mV CMD/ADDR Slew Rate V/ns CK, CK\ Differential Slew Rate 4.0V/ns 3.0V/ns 2.0V/ns 1.8V/ns 1.6V/ns 1.4V/ns 1.2V/ns 1.0V/ns ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH 2.0 88 50 88 50 88 50 96 58 96 66 112 74 120 84 128 100 1.5 59 34 50 34 59 34 67 42 67 50 83 58 91 68 99 84 1.0 0 0 0 0 0 0 8 8 8 16 24 24 32 34 40 50 0.9 -2 -4 -2 -4 -2 -4 6 4 6 12 22 20 30 30 38 46 0.8 -6 -10 -6 -10 -6 -10 2 -2 2 6 18 14 26 24 34 40 0.7 -11 -16 -11 -16 -11 -16 -3 -8 -3 0 13 8 21 18 29 34 0.6 -17 -26 -17 -26 -17 -26 -9 -18 -9 -10 7 -2 15 8 23 24 0.5 -35 -40 -35 -40 -35 -40 -27 -32 -27 -24 -11 -16 -2 -6 5 10 0.4 -62 -60 -62 -60 -62 -60 -54 -52 -54 -44 -38 -36 -30 -26 -22 -10 LOGIC Devices Incorporated www.logicdevices.com 58 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 53: DERATING VALUES FOR tIS/tIH – AC150/DC100-BASED Shaded cells indicate slew-rate combinations not supported ∆tIS, ∆tIH Derating (ps) - AC/DC-Based, AC150 Threshold; VIH(AC) = VREF(DC) + 150mV, VIL(AC) = VREF(DC) - 150mV CMD/ADDR Slew Rate V/ns CK, CK\ Differential Slew Rate 4.0V/ns 3.0V/ns 2.0V/ns 1.8V/ns 1.6V/ns 1.4V/ns 1.2V/ns 1.0V/ns ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH 2.0 75 50 75 50 75 50 83 58 91 66 99 74 107 84 115 100 1.5 50 34 50 34 50 34 58 42 66 50 74 58 82 68 90 84 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 0 -4 0 -4 0 -4 8 4 16 12 24 20 32 30 40 46 0.8 0 -10 0 -10 0 -10 8 -2 16 6 24 14 32 24 40 40 0.7 0 -16 0 -16 0 -16 8 -8 16 0 24 8 32 18 40 34 0.6 -1 -26 -1 -26 -1 -26 7 -18 15 -10 23 -2 31 8 39 24 0.5 -10 -40 -10 -40 -10 -40 -2 -32 6 -24 14 -16 22 -6 30 10 0.4 -25 -60 -25 -60 -25 -60 -17 -52 -9 -44 -1 -36 7 -26 15 -10 TABLE 54: MINIMUM REQUIRED TIME tVAC ABOVE VIH(AC) FOR A VALID TRANSITION Below VIL(AC) tVAC Slew Rate (V/ns) at 175mV(ps) tVAC at 150mV(ps) >2.0 75 175 2.0 57 170 1.5 50 167 1.0 38 163 0.9 34 162 0.8 29 161 0.7 22 159 0.6 13 155 0.5 0 150 <0.5 0 150 LOGIC Devices Incorporated www.logicdevices.com 59 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 25 - NOMINAL SLEW RATE AND tVAC FOR tIS (COMMAND AND ADDRESS – CLOCK) t IS t IH t IS t IH CK CK# DQS# DQS VCCQ t VAC VIH(AC) MIN VREF to AC region VIH(DC) MIN Nominal slew rate VREF(DC) Nominal slew rate VIL(DC) MAX VREF to AC region VIL(DC) MAX t VAC VSS ∆TF Setup slew rate falling signal ∆TR VREF(DC) - VIL(AC) MAX Setup slew rate risin g signal = ∆TF Notes: LOGIC Devices Incorporated VIH(AC) MIN - V REF(DC) = ∆TR 1. Both the clock and the strobe are drawn on different time scales. www.logicdevices.com 60 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 26 - NOMINAL SLEW RATE FOR tIH (COMMAND AND ADDRESS – CLOCK) t IS t IH t IS t IH CK CK# DQS# DQS VCCQ VIH(AC) MIN VIH(DC) MIN Nominal slew rate DC to V REF region VREF(DC) Nominal slew rate DC to V REF region VIL(DC) MAX VIL(AC) MAX VSS ∆TF ∆TR Hol d slew rate = rising signal VREF(DC) - VIL(DC) MAX Hol d slew rate falling signal = ∆TR Notes: LOGIC Devices Incorporated www.logicdevices.com VIH(DC) MIN - V REF(DC) ∆TF 1. Both the clock and the strobe are drawn on different time scales. 61 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 27 - TANGENT LINE FOR tIS (COMMAND AND ADDRESS – CLOCK) t IS t IH t IS t IH CK CK# DQS# DQS VCCQ t VAC Nominal line VIH(AC) MIN VREF to AC region VIH(DC) MIN Tangent line VREF(DC) Tangent line VIL(DC) MAX VREF to AC region VIL(AC) MAX Nominal line t VAC ∆TR VSS Setup slew rate rising signal = ∆TF Notes: LOGIC Devices Incorporated Tangent line (V IH [ DC] MIN - VREF[ DC ]) ∆TR Tangent line (VREF [ DC] - V IL[ AC] MAX) Setup slew rate falling signal = ∆TF 1. Both the clock and the strobe are drawn on different time scales. www.logicdevices.com 62 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 28 - TANGENT LINE FOR tIH (COMMAND AND ADDRESS – CLOCK) t IS t IH t IS t IH CK CK# DQS # DQS VCCQ VIH(AC) MIN Nominal line VIH(DC) MIN DC to V REF region Tangent line VREF(DC) DC to V REF region Tangent line Nominal line VIL( DC) MAX VIL( AC) MAX VSS ∆TR ∆TR Hol d slew rate rising signal = Tangent line (V REF [ DC] - V IL[ DC] MAX) Hol d slew rate falling signal = Tangent line (V IH [ DC] MIN - VREF[ DC]) ∆TR ∆TF Notes: LOGIC Devices Incorporated 1. Both the clock and the strobe are drawn on different time scales. www.logicdevices.com 63 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) DATA SETUP, HOLD AND DERATING The total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS (base) and tDH (base) values (see Table 55) to the ∆tDS and ∆tDH derating values (see Table 56), respectively. Although the total setup time for slow slew rates might be negative, a valid input signal is still required to complete the transition and to reach VIH/VIL(AC). For slew rates which fall between the values listed in Table 57, the derating values may be obtained by linear interpolation. Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC) MIN. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC) MAX. If the actual signal is always earlier than the nominal slew rate line between the shaded “VREF(DC)-to-AC region”, use the nominal slew rate derating value (see Figure 29). If the actual signal is later than the nominal slew rate line anywhere between the shaded “VREF(DC)-to-AC region”, the slew rate of a tangent line to the actual signal from the AC level to the DC level is used for the derating value (see Figure 31). Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC) MAX and the first crossing of VREF(DC). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC) MIN and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between the shaded “DC-to-VREF(DC) region”, use the nominal slew rate for derating value (see Figure 30). If the actual signal is earlier than the nominal slew rate line anywhere between the shaded “DC-to-VREF(DC) region”, the slew rate of a tangent line to the actual signal from the “DC-to-VREF(DC) region”, is used for the derating value (see Figure 32). TABLE 55: DATA SETUP AND HOLD VALUES AT 1V/NS (DQSX, DQSX\ AT 2V/NS) – AC/DC BASED Symbol DDR3-800 DDR3-1333 UNITS 25 - ps VIH(AC)/VIL(AC) 125 75 30 ps VIH(AC)/VIL(AC) 150 100 65 ps VIH(AC)/VIL(AC) tDS(base)AC175 75 tDS(base)AC150 tDS(base)DC100 DDR3-1066 REFERENCE TABLE 56: DERATING VALUE FOR tDS/tDH – AC175/DC100 - BASED Shaded cells indicate slew-rate combinations not supported ∆tDS, ∆tDH Derating (ps) – AC175/D100-Based DQ Slew Rate V/ns DQS, DQS# Differential Slew Rate 4.0V/ns 3.0V/ns 2.0V/ns 1.8V/ns 2.0 88 50 88 50 88 50 1.5 59 34 59 34 59 34 67 42 1.0 0 0 0.9 0.8 1.4V/ns 1.2V/ns 1.0V/ns 0 0 0 0 8 8 16 16 -2 -4 -2 -4 6 4 14 12 22 20 -6 -10 2 -2 10 6 18 14 26 24 -3 -8 5 0 13 8 21 18 29 34 -1 -10 7 -2 15 8 23 24 -11 -16 -2 -6 5 10 -30 -26 -22 -10 0.7 0.6 0.5 0.4 LOGIC Devices Incorporated 1.6V/ns ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH www.logicdevices.com 64 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 57: DERATING VALUE FOR tDS/tDH – AC150/DC100 - BASED Shaded cells indicate slew-rate combinations not supported ∆tDS, ∆tDH Derating (ps) – AC150/DC100-Based DQ Slew Rate V/ns DQS, DQS# Differential Slew Rate 4.0V/ns 3.0V/ns 2.0V/ns 1.8V/ns 1.6V/ns 1.4V/ns 1.2V/ns 1.0V/ns ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH 2.0 75 50 75 50 75 50 1.5 50 34 50 34 50 34 58 42 1.0 0 0 0 0 0 0 8 8 16 16 0 -4 0 -4 8 4 16 12 24 20 0 -10 8 -2 16 6 24 14 32 24 8 -8 16 0 24 8 32 18 40 34 15 -10 23 -2 31 8 39 24 14 -16 22 -6 30 10 7 -26 15 -10 0.9 0.8 0.7 0.6 0.5 0.4 TABLE 58: REQUIRED TIME tVAC ABOVE VIH(AC) (BELOW VIL[AC]) FOR A VALID TRANSITION tVAC Slew Rate (V/ns) at 175mV(ps) [MIN] tVAC at 150mV(ps) [MIN] >2.0 75 175 2.0 57 170 1.5 50 167 1.0 38 163 0.9 34 162 0.8 29 161 0.7 22 159 0.6 13 155 0.5 0 150 <0.5 0 150 LOGIC Devices Incorporated www.logicdevices.com 65 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 29 - NOMINAL SLEW RATE AND tVAC FOR tDS (DQ – STROBE) CK CK# DQS# DQS t DS t DH t DS t DH VCCQ t VAC VIH(AC) MIN VREF to AC region VIH(DC) MIN Nominal slew rate VREF(DC) Nominal slew rate VIL(DC) MAX VREF to AC region VIL(AC) MAX t VAC VSS ∆TF Setup slew rate = rising signal Notes: LOGIC Devices Incorporated ∆TR VREF(DC) - VIL(AC) MAX ∆TF Setup slew rate = rising signal VIH(AC) MIN - VREF (DC) ∆TR 1. Both the clock and the strobe are drawn on different time scales. www.logicdevices.com 66 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 30 - NOMINAL SLEW RATE FOR tDH (DQ – STROBE) CK CK# DQS# DQS t DS t DH t DS t DH VCCQ VIH(AC) MIN VIH(DC) MIN Nominal slew rate DC to V REF region VREF(DC) Nominal slew rate DC to V REF region VIL(DC) MAX VIL(AC) MAX VSS ∆TF ∆TR Hold slew rate = rising signal Notes: LOGIC Devices Incorporated VREF(DC) - VIL(DC) MAX ∆TR Hold slew rate = falling signal VIH(DC) MIN - V REF(DC) ∆TF 1. Both the clock and the strobe are drawn on different time scales. www.logicdevices.com 67 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 31 - NOMINAL SLEW RATE AND tVAC FOR tDS (DQ – STROBE) CK CK# DQS# DQS t DS t DH t DS t DH VCCQ Nominal line t VAC VIH(AC) MIN VREF to AC region VIH(DC) MIN Tangent line VREF(DC) Tangent line VIL(DC) MAX VREF to AC region VIL(AC) MAX Nominal line t VAC ∆TR VSS Setup slew rate rising signal = Tangent line (V IH[ AC ] MIN - V REF [ DC]) ∆TR ∆TF Setup slew rate falling signal = Tangent line (V REF[ DC] - V IL[ AC] MAX) ∆TF Notes: LOGIC Devices Incorporated 1. Both the clock and the strobe are drawn on different time scales. www.logicdevices.com 68 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 32 - NOMINAL SLEW RATE FOR tDH (DQ – STROBE) CK CK# DQS# DQS t DS t DH t DS t DH VCCQ VIH(AC) MIN Nominal line VIH(DC) MIN DC to VREF region Tangent line VREF(DC) DC to VREF region Tangent line Nominal line VIL(DC) MAX VIL(AC) MAX VSS ∆TR Notes: LOGIC Devices Incorporated ∆TF Tangent line (V REF[ DC] - V IL[ DC] MAX) Hol d slew rate falling signal = Hol d slew rate falling signal = ∆TR Tangent line (V IH [ DC] MIN - VREF[ DC]) ∆TF 1. Both the clock and the strobe are drawn on different time scales. www.logicdevices.com 69 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) COMMANDS TRUTH TABLE TABLE 59: TRUTH TABLE - COMMAND PACKAGE OUTLINE DIMENSIONS CKE Function Symbol Prev Cycle Next Cycle CS\ RAS\ CAS\ WE\ BA[2:0] An A12 A10 A[11,0:0] Notes Mode Register Set MRS H H L L L L BA REFRESH REF H H L L L H V V V V V SELF REFRESH entry SRE H L L L L H V V V V V 6 SELF REFRESH exit SRX L H H L V H V H V H V V V V V 6,7 PRE H H L L L L VBA V V L V PREA H H L L L L V V V H V ACT H H L L L H BA WR H H L H H L BA RFU V L CA 8 BC4OTF WRS4 H H L H H L BA RFU L L CA 8 BL8OTF WRS8 H H L H H L BA RFU H L CA 8 BL8MRS BC4MRS WRAP H H L H H L BA RFU V H CA 8 BC4OTF WRAPS4 H H L H H L BA RFU L H CA 8 BL8OTF WRAPS8 H H L H H L BA RFU H H CA 8 BL8MRS BC4MRS RD H H L H H H BA RFU V L CA 8 BC4OTF RDS4 H H L H H H BA RFU L L CA 8 BL8OTF RDS8 H H L H H H BA RFU H L CA 8 Single-Bank PRECHARGE PRECHARGE all banks Bank ACTIVATE BL8MRS BC4MRS WRITE WRITE with AUTO PRECHARGE READ READ with AUTO PRECHARGE CA RDAP H H L H H H BA RFU V H CA 8 BC4OTF RDAPS4 H H L H H H BA RFU L H CA 8 BL8OTF BL8MRS BC4MRS RDAPS8 H H L H H H BA RFU H H CA 8 NO OPERATION NOP H H L H H H V V V V V 9 Device DESELECTED DES H H H X X X X X X X X PDE H H V H V H V H V 10 POWER-DOWN entry H V H V V V V V V 6 V V V V V 6,11 12 PDX L H L H L H ZQ CALIBRATION LONG ZQCL H H L H H L X X X H X ZQ CALIBRATION SHORT ZQCS H H L H H L X X X L X POWER-DOWN exit L NOTES: 1. Commands are defined by states of CS\, RAS\, CAS\, WE\, and CKE at 8. the rising edge of the clock. The MSB of BA, RA, and CA are devicedensity and configuration-dependent. 2. Burst READs or WRITEs cannot be terminated or interrupted, MRS (fixed) and OTF BL/BC are defined in MR0. 9. RESET\ is LOW enabled and used only for asynchronous RESET. Thus, The purpose of the NOP command is to prevent the SDRAM from registering any unwanted commands. A NOP will not terminate and opera- RESET\ must be held HIGH during any normal operation. tion that is in execution. 3. The state of ODT does not affect the states described in this table. 10. The DES and NOP commands perform similarly. 4. Operations apply to the bank defined by the bank address. For MRS, BA 11. The POWER-DOWN mode does not perform any REFRESH opera- selects one of four mode registers. tions. 5. “V” means “H” or “L” (a defined logic level), and “X” means “Don’t Care”. 6. See Table 59 for additional information on CKE transition. mand during initialization) or ZQOPER (ZQCL command after initializa- 7. SELF REFRESH exit is asynchronous. tion). LOGIC Devices Incorporated www.logicdevices.com 12. 70 ZQ CALIBRATION LONG is used for either ZQINT (first ZQCL com- High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 60: TRUTH TABLE - CKE CKE Current State 3 (n-1) (n) Previous Cycle 4 Present Cycle 4 (RAS\, CAS\, WE\, CS\) Command 5 Action 5 Notes L L “Don’t Care” Maintain POWER-DOWN 1,2 L H DES or NOP POWER-DOWN exit 1,2 POWER-DOWN SELF REFRESH L L “Don’t Care” Maintain SELF REFRESH 1,2 Bank(s) ACTIVE H H DES or NOP SELF REFRESH exit 1,2 READING H L DES or NOP Active POWER-DOWN entry 1,2 WRITING H L DES or NOP POWER-DOWN entry 1,2 PRECHARGING H L DES or NOP POWER-DOWN entry 1,2 REFRESHING H L DES or NOP PRECHARGE POWER-DOWN entry 1,2 All Banks IDLE H L DES or NOP PRECHARGE POWER-DOWN entry 1,2,6 H L REFRESH SELF REFRESH NOTES: 1. All states and sequences not shown are illegal or reserved unless explic- 4. itly described elsewhere in this document. 2. tCKE(MIN) state of CKE at the previous clock edge. means CKE must be registered at multiple consecutive posi- 5. COMMAND is the command registered at the clock edge (must be a tive clock edges. CKE must remain at the valid input level the entire time legal command as defined in Table 58). Action is a result of COM- it takes to achieve the required number of registration clocks. Thus, after MAND. ODT does not affect the states described in this table and is any CKE transition, CKE may not transition from its valid level during the time period of tIS + tCKE(MIN) + tIH. 3. CKE (n) is the logic state of CKE at clock edge n, CKE (n-1) was the not listed. 6. Idle state = all banks are closed, no data bursts are in progress, CKE is Current state = The state of the SDRAM immediately prior to clock edge HIGH and all timings from previous operations are satisfied. All SELF n. REFRESH exit and POWER-DOWN exit parameters are also satisfied. NO OPERATION (NOP) DESELECT (DES) The DES command (CS\ HIGH) prevents new commands from being executed by the SDRAM. Operations already in progress are not affected. The NOP command (CS\ LOW) prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. ZQ CALIBRATION ZQ Calibration LONG (ZQCL) The ZQCL command is used to perform the initial calibration during a power-up initialization and reset sequence. This command may be issued at any time by the controller depending on the system environment. The ZQCL command triggers the calibration engine inside the SDRAM. After calibration is achieved, the calibrated values are transferred from the calibration engine to the SDRAM I/O, which are reflected as updated RON and ODT values. The SDRAM is allowed a timing window defined by either tZQINIT or tZQOPER to perform the full calibration and transfer of values. When ZQCL is issued during the initialization sequence, the timing parameter tZQINIT must be satisfied. When initialization is complete, subsequent ZQCL commands require the timing parameter tZQOPER to be satisfied. ZQ Calibration SHORT (ZQCS) The ZQCS command is used to perform periodic calibrations to account for small voltage and temperature variations. The shorter timing window is provided to perform the reduced calibration and transfer of values as defined by timing parameter tZQCS. A ZQCS command can effectively correct a minimum of 0.5% RON and RTT impedance errors within 64 clock cycles, assuming the maximum sensitivities specified in Table 40 and Table 41. LOGIC Devices Incorporated www.logicdevices.com 71 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) ACTIVATE READ The ACTIVATE command is used to open (or ACTIVATE) a row in a particular bank for a subsequent access. The value on the BA [2:0] inputs selects the bank, and the address provided on inputs A[n:0] selects the row. This row remains open (or ACTIVE) for accesses until a PRECHARGE command is issued to that bank. The READ command is used to initiate a burst READ access to an ACTIVE row. The address provided on inputs A[2:0] selects the starting column address depending on the burst length and burst type selected (see table 65). The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be PRECHARGED at the end of the READ burst. If AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. The value on input A12 (if enabled in the MODE REGISTER) when the READ command is issued, determines whether BC4 (chop) or BL8 is used. After a READ command is issued, the READ burst may not be interrupted. A summary of READ commands is shown in Table 61. A PRECHARGE command must be issued before opening a different row in the same bank. TABLE 61: READ COMMAND SUMMARY CKE Function READ READ with AUTO PRECHARGE Symbol BL8MRS BC4MRS RD BC4OTF RDS4 Prev Cycle Next Cycle CS\ RAS\ H L H H L H CAS\ WE\ BA[2:0] L H BA L H BA H An A12 A10 A[11,0:0] Notes RFU V L CA RFU L L CA BL8OTF RDS8 H L L H BA RFU H L CA BL8MRS BC4MRS RDAP H L H L H BA RFU V H CA H L H BA RFU L H CA H L H BA RFU H H CA BC4OTF RDAPS4 H L BL8OTF RDAPS8 H L WRITE The WRITE command is used to initiate a burst WRITE access to an ACTIVE row. The value on the BA[2:0] inputs selects the bank. The value on input A10 determines whether or not AUTO PRECHARGE is used. The value on input A12 (if enabled in the MODE REGISTER [MR]) when the WRITE command is issued, determines whether BC4 (chop) or BL8 is used. The WRITE command summary is shown in Table 62. TABLE 62: WRITE COMMAND SUMMARY CKE Function Symbol BL8MRS BC4MRS WRITE WRITE with AUTO PRECHARGE WR Prev Cycle Next Cycle CS\ RAS\ CAS\ WE\ BA[2:0] An H L H L L BA RFU H A12 A10 A[11,0:0] Notes V L CA BC4OTF WRS4 H L L L BA RFU L L CA BL8OTF WRS8 H L H L L BA RFU H L CA H BL8MRS BC4MRS WRAP H L L L BA RFU V H CA BC4OTF WRAPS4 H L H L L BA RFU L H CA H L H L L BA RFU H H CA BL8OTF LOGIC Devices Incorporated WRAPS8 www.logicdevices.com 72 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) PRECHARGE REFRESH The PRECHARGE command is used to DEACTIVATE the open row in a particular bank or in all banks. The bank(s) are available for a subsequent row access at a specified time (tRP) after the PRECHARGE command is issued, except in the case of concurrent AUTO PRECHARGE. A READ or WRITE command to a different bank is allowed during concurrent AUTO PRECHARGE as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Input A10 determines whether one or all banks are precharged. In the case where only one bank is recharged. Inputs BA[2:0] select the bank; otherwise, BA[2:0] are treated as “Don’t Care”. After a bank is PRECHARGED, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is treated as a NOP if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. However, the PRECHARGE period is determined by the last PRECHARGE command issued to the bank. REFRESH is used during normal operation of the SDRAM and is analogous to CAS\-before RAS\ (CBR) refresh or AUTO REFRESH. This command is non-persistent, so it must be issued each time a REFRESH is required. The addressing is generated by the internal REFRESH command. The SDRAM requires REFRESH cycles at an average interval of 7.8μs (maximum when Tc≤85˚C or 3.9μs MAX when Tc≤95˚C). The REFRESH period begins when the REFRESH command is registered and ends tRFC (MIN) later. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute REFRESH interval is provided. A maximum of eight REFRESH commands can be posted to any given SDRAM, meaning that the maximum absolute interval between any REFRESH command and the next REFRESH command is nine times the maximum average interval refresh rate. SELF REFRESH may be entered with up to eight REFRESH commands being posted. After exiting SELF REFRESH (when entered with posted REFRESH commands) additional posting of REFRESH commands is allowed to the extent the maximum number of cumulative posted REFRESH commands (both pre and post SELF REFRESH) does not exceed eight REFRESH commands. FIGURE 33 - REFRESH MODE T0 T2 T1 T3 T4 Ta0 Ta1 Tb0 Tb1 Valid 1 Valid 1 NOP1 NOP1 Tb2 CK# CK t CK t CH t CL Valid 1 CKE Command NOP 1 PRE NOP 1 NOP 1 REF NOP 1 REF 2 ACT Address RA All banks A10 RA One bank Bank(s) 3 BA[2:0] BA DQS, DQS# 4 DQ4 DM 4 t RP t RFC (MIN) t RFC 2 Indicates A Break in Time Scale Notes: LOGIC Devices Incorporated Don’t Care 1. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be active during the PRECHARGE, ACTIVATE, and REFRESH commands, but may be inactive at other times (see “Power-Down Mode” on page 153). www.logicdevices.com 73 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) SELF REFRESH The SELF REFRESH command is used to retain data in the SDRAM, even if the rest of the system is powered down. When in the SELF REFRESH mode, the SDRAM retains data without external clocking. The SELF REFRESH mode is also a convenient method used to enable/disable the DLL as well as to change the clock frequency within the allowed synchronous operating range. All power supply inputs (including VREFCA and VREFDQ) must be maintained at valid levels upon entry/exit and during SELF REFRESH mode operation. All power supply inputs (including VREFCA and VREFDQ) must be maintained at valid levels upon entry/exit and during SELF REFRESH mode under certain conditions: • Vss< VREFDQ< Vcc is maintained • VREFDQ is valid and stable prior to CKE going back HIGH • The first WRITE operation may not occur earlier than 512 clocks after VREFDQ is valid • All other SELF REFRESH mode exit time requirements are met. DLL DISABLE MODE If the DLL is disabled by the MODE REGISTER (MR1[0] can be switched during initialization or later), the SDRAM is targeted, but not guaranteed to operate similarly to the NORMAL mode with a few notable exceptions: • • • The SDRAM supports only one value of CAS latency (CL=6) and one value of CAS WRITE latency (CWL=6). DLL DISABLE mode affects the READ data clock-to-data strobe relationship (tDQSCK), but not the READ data-to-data strobe relationship (tDQSQ, tQH). Special attention is needed to line the READ data up with the controller time domain when the DLL is disabled. In NORMAL operation (DLL on), tDQSCK starts from the rising clock edge AL + CL cycles after the READ command. In DLL DISABLE mode, tDQSCK starts AL = CL – 1 cycles after the READ command. Additionally, with the DLL disabled, the value of tDQSCK could be larger than tCK. The ODT feature is not supported during DLL DISABLE mode (including dynamic ODT). The ODT resistors must be disabled by continuously registering the ODT ball LOW by programming RTT_NORM MR1[9,6,2] and RTT_WR MR2[10,9] to “0” while in DLL DISABLE mode. Specific steps must be followed to switch between the DLL enable and DLL DISABLE modes due to a gap in the allowed clock rates between the two modes (tCK[AVG]MAX and tCK[DLL DISABLE] MIN, respectively). The only time the clock is allowed to cross this clock rate gap is during SELF REFRESH mode. Thus, the required procedure for switching from the DLL ENABLE to DLL DISABLE mode is to change frequency curing self refresh (see Figure 34): 1. 2. 3. 4. 5. Starting from the IDLE state (all banks are PRECHARGED, all timings are fulfilled, ODT is turned off, and RTT_NOM and RTT_WR are HIGH-Z), set MR1[0] to “1” to DISABLE the DLL. Enter SELF REFRESH mode after tMOD has been satisfied. After tCKSRE is satisfied, change the frequency to the desired clock rate. SELF REFRESH may be exited when the clock is stabled with the new frequency for tCKSRX. The SDRAM will be ready for its next command in the DLL DISABLE mode after the greater of tMRD or tMOD has been satisfied. A ZQCL command should be issued with appropriate timing met as well. LOGIC Devices Incorporated www.logicdevices.com 74 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 34 - DLL ENABLE MODE TO DLL DISABLE MODE T0 T1 Ta0 Ta1 Tb0 Tc0 Td0 Td1 Te0 Te1 Tf0 CK# CK Vali d 1 CKE Command MRS2 6 NOP SRE 3 t MOD SRX 4 NOP t CKSRE t CKSRX 8 7 NOP MRS5 NOP Vali d 1 t MOD t XS t CKESR ODT 9 Vali d 1 Indicates a Break in Time Scale NOTES: 1. Any valid command. 2. Disable DLL by setting MR1[0] to “1.” 3. Wait tXS, then set MR1[0] to “0” to enable DLL. 4. Wait tMRD, then set MR0[8] to “1” to begin DLL RESET. 5. Wait tMRD, update registers (CL, CWL, and write recovery may be necessary). 6. Wait tMOD, any valid command. 7. Starting with the idle state. 8. Change frequency. 9. Clock must be stable at least tCKSRX. 10. Static LOW in case RTT_NOM or RTT_WR is enabled; otherwise, static LOW or HIGH. Don ’t Care A similar procedure is required for switching from the DLL disable mode back to the DLL enable mode. This also requires changing the frequency during self refresh mode (see Figure 44 on page 100). 1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT is turned off, and RTT_NOM and RTT_WR are High-Z), enter self refresh mode. 2. After tCKSRE is satisfied, change the frequency to the new clock rate. 3. Self refresh may be exited when the clock is stable with the new frequency for tCKSRX. After tXS is satisfied, update the mode registers with the appropriate values. At a minimum, set MR1[0] to “0” to enable the DLL. Wait tMRD, then set MR0[8] to “1” to enable DLL RESET. 4. After another tMRD delay is satisfied, then update the remaining mode registers with the appropriate values. 5. The DRAM will be ready for its next command in the DLL enable mode after the greater of tMRD or tMOD has been satisfied. However, before applying any command or function requiring a locked DLL, a delay of tDLLK after DLL RESET must be satisfied. A ZQCL command should be issued with the appropriate timings met as well. LOGIC Devices Incorporated www.logicdevices.com 75 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 35- DLL DISABLE MODE TO DLL ENABLE MODE T0 Ta0 Ta1 Tb0 Tc0 Tc1 Td0 Te0 Tf0 Tg0 Th0 CK# CK CKE Vali d t DLLK Command SRE1 NOP SRX2 NOP t CKSRE 7 t CKSRX 9 8 MRS3 t XS MRS4 t MRD MRS5 Vali d 6 t MRD ODTL off + 1 × t CK t CKESR ODT10 Indicates a Break in Time Scale Don ’t Care NOTES: 1. Enter SELF REFRESH. 2. Exit SELF REFRESH. 3. Wait tXS, then set MR1[0] to “0” to enable DLL. 4. Wait tMRD, then set MR0[8] to “1” to begin DLL RESET. 5. Wait tMRD, update registers (CL, CWL, and write recovery may be necessary). 6. Wait tMOD, any valid command. 7. Starting with the idle state. 8. Change frequency. 9. Clock must be stable at least tCKSRX. 10. Static LOW in case RTT_NOM or RTT_WR is enabled; otherwise, static LOW or HIGH. The clock frequency range for the DLL disable mode is specified by the parameter tCKDLL_DIS. Due to latency counter and timing restrictions, only CL = 6 and CWL = 6 are supported. DLL disable mode will affect the read data clock to data strobe relationship (tDQSCK) but not the data strobe to data relationship (tDQSQ, tQH). Special attention is needed to the controller time domain. Compared to the DLL on mode where tDQSCK starts from the rising clock edge AL + CL cycles after the READ command, the DLL disable mode tDQSCK starts AL + CL - 1 cycles after the READ command (see Figure 45 on page 101). WRITE operations function similarly between the DLL enable and DLL disable modes; however, ODT functionality is not allowed with DLL disable mode. LOGIC Devices Incorporated www.logicdevices.com 76 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 36 - DLL DISABLE tDQSCK TIMING T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 READ NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command Add ress Vali d RL = AL + C L = 6 (C L = 6, AL = 0) CL = 6 DQS, DQS# DLL on DI b DQ BL8 DLL on DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 RL (DLLdisable) = AL + (C L - 1) = 5 t DQSCK (DLL_DIS) MIN DQS, DQS# DLL off DI b DQ BL8 DLL disable DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 DI b+3 DI b+4 DI b+5 DI b+6 t DQSCK (DLL_ DIS) MAX DQS, DQS# DLL off DI b DQ BL8 DLL disable DI b+1 DI b+2 Transitioning Data DI b+7 Don ’t Care INPUT CLOCK FREQUENCY CHANGE When the DDR3 SDRAM is initialized, it requires the clock to be stable during most NORMAL states of operation. This means that after the clock frequency has been set to the stable state, the clock period is not allowed to deviate except what is allowed for by the clock jitter and spread spectrum clocking (SSC) specifications. The input clock frequency can be changed from one stable clock rate to another under two conditions: SELF REFRESH mode and PRECHARGE power-down mode. Outside of these two modes, it is illegal to change the clock frequency. For the SELF REFRESH mode condition, when the DDR3 SDRAM has been successfully placed into SELF REFRESH mode and tCKSRE has been satisfied, the state of the clock becomes a “Don’t Care”. When the clock becomes a “Don’t Care”, changing the clock frequency is permissible, provided the new clock frequency is stable prior to tCKSRX. When entering and exiting self refresh mode for the sole purpose of changing the clock frequency, the SELF REFRESH entry and exit specifications must still be met. The PRECHARGE power-down mode condition is when the DDR3 SDRAM is in PRECHARGE power-down mode (either fast exit mode or slow exit mode). Either ODT must be at a logic LOW or RTT_NOM and RTT_WR must be disabled via MR1 and MR2. This ensures RTT_NOM and RTT_WR are in an off state prior to entering PRECHARGE power-down mode while maintaining CKE at a logic LOW. A minimum of tCKSRE must occur after CKE goes LOW before the clock frequency can change. The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed/temperature grade (tCK [AVG] MIN to tCK [AVG] MAX) device. During the input clock frequency change, CKE must be held at a stable LOW level. When the input clock frequency is changed, a stable clock must be provided to the SDRAM, tCKSRX before PRECHARGE power-down may be exited. After PRECHARGE power-down is exited and tXP has been satisfied, the DLL must be reset via the MRS. Depending on the new clock frequency, additional MRS commands may need to be issued. During the DLL lock time, RTT_NOM and RTT_WR must remain in an off state. After the DLL lock time, the SDRAM is ready to operate with a new clock frequency (period). This process is depicted in Figure 37. LOGIC Devices Incorporated www.logicdevices.com 77 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 37- CHANGE FREQUENCY DURING PRECHARGE POWER-DOWN Previous clock frequency T0 T1 T2 New clock fre quency Ta0 Tb0 Tc1 Tc0 Td0 Td1 Te0 Te1 CK# CK t CH t CL t CH t CK t CK t CKSRE t IS t IH t CH b t CK b t CL b t CH b b b t CL t CK b b t CKSRX t CKE t IH CKE t IS t CPDED Command t CL b NOP NOP NOP NOP NOP Address MRS NOP Valid DLL RESET t AOFPD/ t AOF t XP Valid t IH t IS ODT DQS, DQS# High-Z High-Z DQ DM t DLLK Enter precharge power-down mode Frequency change Exit precharge power-down mode Indicates a Break in Time Scale Don’t Care NOTES: 1. Applicable for both slow-exit and fast-exit precharge power-down modes. 2. tAOFPD and tAOF must be satisfied and outputs High-Z prior to T1 (see “On-Die Termination (ODT)” on page 161 for exact requirements). 3. If the RTT_NOM feature was enabled in the mode register prior to entering precharge power-down mode, the ODT signal must be continuously registered LOW ensuring RTT is in an off state. If the RTT_NOM feature was disabled in the mode register prior to entering precharge power-down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or HIGH in this case. LOGIC Devices Incorporated www.logicdevices.com 78 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) WRITE LEVELING For better signal integrity, DDR3 SDRAM memory sub-system designs have adopted use of fly-by topology for the commands, addresses, control signals and clocks. WRITE leveling is a scheme for the memory controller to de-skew the DQSx strobe (DQSx, DQSx\) to CK relationship at the SDRAM with a simple feedback feature provided it by the DDR3 SDRAM itself. WRITE leveling is generally used as part of the initialization process, if required. For NORMAL SDRAM operation, this feature must be disabled. This is the only SDRAM operation where the DQS functions as an input (to capture the incoming clock) and the DQs function as outputs (to report the stat of the clock). Note that nonstandard ODT schemes are required. The memory controller using the WRITE leveling procedure must have adjustable delay setting on its DQS strobe to align the rising edge of DQS to the clock at the SDRAM pins. This is accomplished when the SDRAM asynchronously feeds back the CK status via the DQ bus and samples with the rising edge of DQS. The controller repeatedly delays the DQS strobe until a CK transition from “0” to “1” is detected. The DQS delay established through this procedure helps ensure tDQSS, tDSS, and tDSH specifications in systems that use fly by topology by de-skewing the trace length mismatch. A conceptual timing of this procedure is shown in Figure 38. FIGURE 38- WRITE LEVELING CONCEPT T0 T1 T2 T3 T4 T5 T6 T7 CK# CK Source Differential DQS Tn T0 T1 T2 T3 T4 T5 T4 T5 T6 CK# CK Destination Differential DQS 0 DQ Destination Tn T0 T1 0 T2 T3 T6 CK# CK Push DQS to capture 0–1 transition Differential DQS 1 DQ 1 Don’t Care LOGIC Devices Incorporated www.logicdevices.com 79 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) WRITE LEVELING When WRITE leveling is enabled, the rising edge of DQS samples CK and the rime DQ outputs the sampled CK’s status. The prime DQ for each of the (4) words contained in the iMOD is DQ0 for the low byte, DQ8 for the high byte. It outputs the status of CK sampled by LDQSx and UDQSx. All other DQs (DQ[7:1], DQ[15:9] for the low word, DQ[23:17],DQ[31:25] for the next word, DQ[39:33], DQ[47:41] for the next and DQ[55:49], DQ[63:57] for the HIGH word) continue to drive LOW. Two prime DQ on each of the (4) words contained in the LDI iMOD allow each byte lane to be leveled independently. WRITE LEVELING PROCEDURE A memory controller initiates the SDRAM WRITE Leveling mode by setting the MR1[7] to a “1”, assuming the other programmable features (MR0, MR1, MR2, and MR3) are first set and the DLL is fully reset and locked. The DQ balls enter the WRITE Leveling mode going from a “HIGH-Z” state to an undefined driving state so the DQ bus should not be driven. During WRITE Leveling mode, only the NOP and DES commands are allowed. The memory controller should attempt to level only one rank at a time; thus, the outputs of other ranks should be disabled by setting MR1[12] to a “1”. The memory controller may assert ODT after a tMOD delay as the SDRAM will be ready to process the ODTL on delay (WL-2tCK), provided it does not violate the aforementioned tMOD delay requirement. The memory controller may drive LDQSx, UDQSx LOW and LDQSx\, UDQSx\ HIGH after tWLDQSEN has been satisfied. The controller may begin to toggle LDQSx, UDQSx after tWLMRD (one L[U]DQSs toggle is DQSs transitioning from a LOW state to a HIGH state with L[U]DQSx\ transitioning from a HIGH state to a LOW state, then both transition back to their original states). At a minimum, ODTL on and tAON must be satisfied at least one clock prior to DQS toggling. After tWLMRD and DQS LOW preamble (tWPRE) have been satisfied, the memory controller may provide either a single DQSx toggle or multiple DQSx toggles to sample CK for a given DQSx to CK skew. Each DQS toggle must not violate tDQSL (MIN) and tDQSH (MIN) specifications. tDQSL (MAX) and tDQSH (MAX) specifications are not applicable during WRITE leveling mode. The DQSx must be able to distinguish the CK’s rising edge within tWLS and tWLH. The prime DQ will output the CK’s status asynchronously from the associated DQSx rising edge CK capture within tWLO. The remaining DQs that always drive LOW when DQS is toggling must be LOW within tWLOE after the first tWLO is satisfied (the prime DQs going LOW). As previously noted, DQSx is an input and not an output during this process. Figure 39 depicts the basic timing parameters for the overall write leveling procedure. The memory controller will likely sample each applicable prime DQ state and determine whether to increment or decrement it DQS delay setting. After the memory controller performs enough DQSx toggles to detect the CK’s “0-1” transition, the memory controller should lock the DQS delay setting for the SDRAM iMOD device. After locking the DQS setting, leveling for the rank will have been achieved, and the WRITE leveling mode for the rank should be disabled or reprogrammed (if WRITE leveling of another rank follows). LOGIC Devices Incorporated www.logicdevices.com 80 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 39- WRITE LEVELING SEQUENCE T1 T2 t WLS t WLH CK# CK Command MRS1 NOP2 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP t MOD ODT t WLDQSEN t DQSL3 t DQSH3 t DQSL3 t DQSH3 Differential DQS4 t WLMRD t WLO t WLO Prime DQ 5 t WLO t WLOE Early remaining DQ t WLO Late remaining DQ Indicates a Break in Time Scale Undefined Driving Mode Don’t Care NOTES: 1. MRS: Load MR1 to enter write leveling mode. 2. NOP: NOP or DES. 3. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH (MIN) and tDQSL (MIN) as defined for regular writes. The maximum pulse width is system-dependent. 4. Differential DQS is the differential data strobe (DQS, DQS#). Timing reference points are the zero crossings. The solid line represents DQS; the dotted line represents DQS#. 5. DRAM drives leveling feedback on a prime DQ (DQ0 for x4 and x8). The remaining DQ are driven LOW and remain in this state throughout the leveling procedure. WRITE LEVELING EXIT MODE After the DDR3 SDRAM iMOD has been WRITE leveled, the controller must exit from WRITE Leveling mode before the NORMAL mode can be used. Figure 40 depicts a general procedure in exiting WRITE Leveling. After the last rising DQS (capturing a “1” at T0), the memory controller should stop driving the DQS signals after tWLO (MAX) delay plus enough delay to enable the memory controller to capture the applicable prime DQ state (at – Tb0). The DQ balls become undefined when DQS no longer remains LOW and they remain undefined until tMOD after the MRS command (at Te1). The ODT input should be deasserted LOW such that ODTL off (MIN) expires after the DQSx is no longer driving LOW. When ODT LOW satisfies tIS, ODT must be kept LOW (at –Tb0) until the SDRAM is ready for either another rank to be leveled or until the NORMAL mode can be used. After DQS termination is switched off, WRITE level mode should be disabled via the MRS command (at Tc2). After tMOD is satisfied (at Te1), any valid command may be registered by the SDRAM. Some MRS commands may be issued after tMRD (at Td1). LOGIC Devices Incorporated www.logicdevices.com 81 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 40- EXIT WRITE LEVELING T0 T1 T2 Ta0 Tb0 Tc0 Tc1 Tc2 Td0 Td1 Te0 Te1 NOP NOP NOP NOP NOP NOP NOP M RS NOP t MRD Valid NOP Valid CK# CK Command Add ress MR1 t IS Valid Valid t MOD ODT ODTL off R TT DQS, R TT DQS# t AOF (MIN) RTT_NOM t AOF (MAX) DQS, DQS# RTT_DQ t WLO + t WLOE DQ CK = 1 Indicates a Break in Time Scale Undefined Driving Mode Transitioning Don ’t Care Notes: 1. The DQ result, “= 1,” between Ta0 and Tc0, is a result of the DQS, DQS# signals capturing CK HIGH just after the T0 state. LOGIC Devices Incorporated www.logicdevices.com 82 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) OPERATIONS Initialization The following sequence is required for power up and initialization, as shown in Figure 41. 1. Apply power. RESET\ is recommended to be below 0.2 x VccQ during power ramp to ensure the outputs remain disabled (HIGH-Z) and ODT off (RTT is also HIGH-Z). All other inputs, including ODT may be undefined. During power up, either of the following conditions may exist and must be met: • Condition A: • Vcc and VccQ are driven from a single power source and are ramped with a maximum delta voltage between them of ∆V≤300mV. Slope reversal of any power supply signal is allowed. The voltage levels on all balls other than Vcc, VccQ, Vss and VssQ must be less than or equal to VccQ and Vcc on one side and must be greater than or equal to VssQ and Vss on the other side. • Both Vcc and VccQ power supplies ramp to Vcc (MIN) and VccQ (MIN) within tVccPR=200ms. • Both Vcc and VccQ power supplies ramp to Vcc (MIN) and VccQ (MIN) within tVccPR=200ms. • VREFDQ tracks Vcc x 0.5, VREFCA tracks Vcc x 0.5. • VTT is limited to 0.95V when the power ramp is complete and is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device latchup. • Condition B: • Vcc may be applied before or at the same time as VccQ. • VccQ may be applied before or at the same time as VTT, VREFDQ and VREFCA. • No slope reversals are allowed in the power supply ramp for this condition. 2. Until stable power, maintain RESET\ LOW to ensure the outputs remain disabled (HIGH-Z). After the power is stable, RESET\ must be LOW for at least 200μs to begin the initialization process. ODT will remain in the HIGH-Z state while RESET\ is LOW and until CKE is registered HIGH. 3. CKE must be LOW 10ns prior to RESET\ transitioning HIGH. 4. After RESET\ transitions HIGH, wait 500μs (minus one clock) with CKE LOW. 5. After this CKE LOW time, CKE may be brought HIGH (synchronously) and only NOP or DES commands may be issued. The clock must be present and valid for at least 10ns (and a minimum of five clocks) and ODT must be driven LOW at least tIS prior to CKE being registered HIGH. When CKE is registered HIGH, it must be continuously registered HIGH until the full initialization process is complete. 6. After CKE is registered HIGH and after tXPR has been satisfied, MRS commands may be issued. Issue an MRS (LOAD MODE) command to MR2 with the applicable settings (provide LOW to BA2 and BA0 and HIGH to BA1). 7. Issue an MRS command to MR3 with the applicable settings. 8. Issue an MRS command to MR1 with the applicable settings, including enabling the DLL and configuring ODT. 9. Issue and MRS command to MR0 with the applicable settings, including a DLL RESET command. tDLLK (512) cycles of clock input are required to lock the DLL. 10. Issue a ZQCL command to calibrate RTT and RON values for the process voltage temperature (PVT). Prior to NORMAL operation. tZQINIT must be satisfied. 11. When tDLLK and tZQINIT have been satisfied, the DDR3 SDRAM will be ready for normal operation. LOGIC Devices Incorporated www.logicdevices.com 83 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 41- INITIALIZATION SEQUENCE T (MAX) = 200ms VCC VCCQ VTT See power-up c onditions in the initialization sequence text, set up 1 VREF Power-up ramp t VTD Sta ble and vali d clo ck T0 T1 t CK Tc0 Tb0 Ta0 Td0 CK# CK t CKSRX t CL t CL t IOz = 20ns RESET# t IS T (MIN) = 10ns Valid CKE Valid ODT t IS Command NOP MRS MRS MRS MRS ZQCL Add ress Code Code Code Code A10 Code Code Code Code BA0 = L BA1 = H BA2 = L BA0 = H BA1 = H BA2 = L BA0 = H BA1 = L BA2 = L BA0 = L BA1 = L BA2 = L Valid DM BA[2:0] Valid Valid A10 = H Valid DQS DQ RTT T = 200μs (MIN) T = 500μs (MIN) MR2 All voltage supplies valid and stable t MRD t MRD t XPR MR3 MR1 with DLL ena ble t MRD t MOD MR0 with DLL reset t ZQ INIT ZQ cali bration t DLLK DRAM ready for external commands Normal operation Indicates a Break in Time Scale LOGIC Devices Incorporated www.logicdevices.com 84 Don ’t Care High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) MODE REGISTERS Mode registers (MR0-MR3) are used to define various modes of programmable operation of the DDR3 SDRAM iMOD. A mode register is programmed via the MODE REGISTER SET (MRS) command during initialization and it retains the stored information (except for MR0[8] which is self-clearing) until it is either reprogrammed, RESET\ goes LOW, or until the device loses power. Contents of a mode register can be altered by re-executing the MRS command. If the user chooses to modify only a subset of the mode register’s variables, all variables must be programmed when the MRS command is issued. Reprogramming the mode register will not alter the contents of the memory array, provided it is performed correctly. The MRS command can only be issued (or re-issued) when all banks are idle and in the PRECHARGED state (tRP is satisfied and no data bursts are in progress). After an MRS command has been issued, two parameters must be satisfied: tMRD and tMOD. The controller must wait tMRD before initiating any subsequent MRS commands (see Figure 42). FIGURE 42- MRS-TO-MRS COMMAND TIMING (tMRD) T0 T1 T2 Ta0 Ta1 Ta2 MRS1 NOP NOP NOP NOP MRS2 CK# CK Command t MRD Add ress Valid Valid CKE 3 Indicates a Break in Time Scale Don ’t Care NOTES: 1. Prior to issuing the MRS command, all banks must be idle and precharged, tRP (MIN) must be satisfied, 2. tMRD 3. CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN) (see “Power-Down and no data bursts can be in progress.the leveling procedure. specifies the MRS-to-MRS command minimum cycle time. Mode” on page 153). 4. For a CAS latency change, tXPDLL timing must be met before any nonMRS command. The controller must also wait tMOD before initiating any nonMRS commands (excluding NOP and DES), as shown in Figure 52 on page 111. The DRAM requires tMOD in order to update the requested features, with the exception of DLL RESET, which requires additional time. Until tMOD has been satisfied, the updated features are to be assumed unavailable. LOGIC Devices Incorporated www.logicdevices.com 85 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 43- MRS-TO-NONMRS COMMAND TIMING (tMOD) T1 T2 t WLS t WLH CK# CK Command MRS1 NOP2 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP t MOD ODT t WLDQSEN t DQSL3 t DQSH3 t DQSL3 t DQSH3 Differential DQS4 t WLMRD t WLO t WLO Prime DQ 5 t WLO t WLOE Early remaining DQ t WLO Late remaining DQ Indicates a Break in Time Scale Undefined Driving Mode Don’t Care NOTES: 1. Prior to issuing the MRS command, all banks must be idle (they must be precharged, tRP must be satisfied, and no data bursts can be in progress). 2. Prior to Ta2 when tMOD (MIN) is being satisfied, no commands (except NOP/DES) may be issued. 3. If RTT was previously enabled, ODT must be registered LOW at T0 so that ODTL is satisfied prior to Ta1. ODT must also be registered LOW at each rising CK edge from T0 until tMOD (MIN) is satisfied at Ta2. 4. CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN), at which time power-down may occur (see “Power-Down Mode” on page 133). MODE REGISTER 0 (MR0) The base register, MR0 is used to define various DDR3 iMOD modes of operation. These definitions include the selection of a burst length, burst type, CAS latency, operating mode, DLL RESET, WRITE recovery and PRECHARGE power-down mode, as shown in Figure 44. LOGIC Devices Incorporated www.logicdevices.com 86 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) MODE REGISTER 0 (MR0) BURST TYPE BURST LENGTH Accesses within a given burst may be programmed to either a sequential or an interleaved order. The burst type is selected via MR0[3], as shown in Figure 44. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 65. DDR3 only supports 4-bit burst chop and 8-bit burst access modes. Full interleaved address ordering is supported for READs, while WRITEs are restricted to nibble (BC4) or word (BL8) boundaries. Burst length is defined by MR0[1:0] (see Figure 44). READ and WRITE accesses to the DDR3 SDRAM iMOD are burst-oriented, with the burst length being programmable to “4” (chop mode). “8” (fixed burst), or selectable using A12 during a READ/WRITE command (on the fly). The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. When MR0[1:0] is set to “01” during a READ/WRITE command, if A12=0, then BC4 (chop) mode is selected. If A12=1, then BL8 mode is selected. Specific timing diagrams, and turnaround between READ/WRITE are shown in the READ/WRITE sections of this document. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A[i:2] when the burst length is set to “4” and by A[i:3] when the burst length is set to “8” (where Ai is the most significant column address bit for a given starting location within the block. The programmed burst length applies to both READ and WRITE bursts. FIGURE 44- MODE REGISTER 0 (MR0) DEFINITIONS M15 M14 BA2 BA 1 BA 0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus 16 15 14 13 12 11 10 WR 01 0 0 01 PD Mode register 0 (MR0) 9 8 7 6 5 4 3 2 DLL 01 CAS# latency BT 01 1 0 BL M1 M0 Mode Register 0 0 0 1 Burst Length Fixed BL8 0 0 Mode register 0 (MR0) 0 1 Mode register 1 (MR1) M12 Precharge PD 1 0 Mode register 2 (MR2) 0 DLL off (slow exit) 0 No 1 0 Fixed BC4 (chop) 1 1 Mode register 3 (MR3) 1 DLL on (fast exit) 1 Yes 1 1 Reserved LOGIC Devices Incorporated Write Recovery M6 M5 M4 4 or 8 (on-the-fly via A12) CAS Latency M3 READ Burst Type 0 0 0 Reserved 0 0 0 Reserved 0 Sequential (nibble) 0 0 1 5 0 0 1 5 1 Interleaved 0 1 0 6 0 1 0 6 0 1 1 7 0 1 1 7 1 0 0 8 1 0 0 8 1 0 1 10 1 0 1 9 1 1 0 12 1 1 0 10 1 1 1 Reserved 1 1 1 11 M11 M10 M9 Notes: M8 DLL Reset 1. MR0[16, 13, 7, 2] are reserved for future use and must be programmed to “0.” www.logicdevices.com 87 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 65: BURST ORDER Burst Length Read/Write 4 CHOP Starting Column Address (A[2,1,0]) READ WRITE 8 READ WRITE 000 001 Burst Type (Decimal) Type = Sequential Type = Interleaved 0,1,2,3,Z,Z,Z,Z 1,2 1,2,3,0,Z,Z,Z,Z 1,0,3,2,Z,Z,Z,Z 1,2 010 2,3,0,1,Z,Z,Z,Z 2,3,0,1,Z,Z,Z,Z 1,2 011 3,0,1,2,Z,Z,Z,Z 3,2,1,0,Z,Z,Z,Z 1,2 100 4,5,6,7,Z,Z,Z,Z 4,5,6,7,Z,Z,Z,Z 1,2 101 5,6,7,4,Z,Z,Z,Z 5,4,7,6,Z,Z,Z,Z 1,2 110 6,7,4,5,Z,Z,Z,Z 6,7,4,5,Z,Z,Z,Z 1,2 111 7,4,5,6,Z,Z,Z,Z 7,6,5,4,Z,Z,Z,Z 1,2 0VV 0,1,2,3,X,X,X,X 0,1,2,3,X,X,X,X 1,3,4 1VV 4,5,6,7,X,X,X,X 4,5,6,7,X,X,X,X 1,3,4 000 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 1 001 1,2.3,0,5,6,7,4 1,0,3,2,5,4,7,6 1 010 2,3,0,1,6,7,4,5 2,3,0,1,6,7,4,5 1 011 3,0,1,2,7,4,5,6 3,2,1,0,7,6,5,4 1 100 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3 1 101 5,6,7,4,1,2,3,0 5,4,7,6,1,0,3,2 1 110 6,7,4,5,2,3,0,1 6,7,4,5,2,3,0,1 1 111 7,4,5,6,3,0,1,2 7,6,5,4,3,2,1,0 1 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 1,3 VVV NOTES: 1. Internal READ and WRITE operations start at the same point in time for BC4 as they do for BL8. DLL RESET 2. Z = Data and Strobe output drivers in tri-state. 3. X=”Don’t Care” WRITE RECOVERY DLL RESET is defined by MR0[8] (see Figure 44). Programming MR0[8] to “1” activates the DLL RESET function. MR0[8] is self-clearing, meaning it returns to a value of “0” after the DLL RESET function has been initiated. WRITE RECOVERY time is defined by MR0[11:9] (see Figure 44). WRITE RECOVERY values of 5,6,7,8,10 or 12 may be used by programming MR0[11:9]. The user is required to program the correct value of WRITE RECOVERY and is calculated by dividing tWR (ns) by tCK (ns) and rounding up a non-integer value to the next integer: WR (cycles)=roundup (tWR[ns]/tCK [ns]). Anytime the DLL RESET function has been initiated, CKE must be HIGH and the clock held stable for 512 (tDLLK) clock cycles before a READ command can be issued. This is to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in invalid output timing specifications such as tDQSCK timings. LOGIC Devices Incorporated Notes 0,1,2,3,Z,Z,Z,Z www.logicdevices.com 88 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) CAS Latency (CL) PRECHARGE POWER-DOWN (PRECHARGE PD) The PRECHARGE PD bit applies only when PRECHARGE power-down mode is being used. When MR0[12] is set to “0”, the DLL is off during PRECHARGE power-down providing a lower standby current mode; however, tXPDLL must be satisfied when exiting. When MR0[12] is set to “1”, the DLL continues to run during PRECHARGE power-down mode to enable a faster exit of PRECHARGE power-down mode; however, tXP must be satisfied when exiting (see Power-Down mode on Page 133). The CL is defined by MR0[6:4], as shown in Figure 44. CAS latency is the delay, as measured in clock cycles, between the internal READ command and the availability of the first bit of valid output data. The CL can be set to 5,6, 8, or 10. DDR3 SDRAM iMODs do not support half-clock latencies. Examples of CL=6 and CL=8 are shown in Figure 45 (below). If an internal READ command is registered at clock edge n, and the CAS latency is m clocks, the data will be available nominally coincident with clock edge n+m. Table 49 indicates the CLs supported at available operating frequencies. FIGURE 45- READ LATENCY T0 T1 T2 T3 T4 T5 T6 T7 T8 READ NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command AL = 0, CL = 6 DQS, DQS# DI n DQ DI n+1 DI n+2 DI n+3 DI n+4 T0 T1 T2 T3 T4 T5 T6 T7 T8 READ NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command AL = 0, CL = 8 DQS, DQS# DI n DQ Transitioning Data Don’t Care NOTES: 1. For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are possible. 2. LOGIC Devices Incorporated Shown with nominal tDQSCK and nominal tDSDQ. www.logicdevices.com 89 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) MODE REGISTER 1 (MR1) The MODE REGISTER 1 (MR1) controls additional functions and features not available in the other mode registers; Q OFF (OUTPUT DISABLE), DLL ENABLE/DLL DISABLE, RTT_NOM value (ODT), WRITE LEVELING, POSTED CAS ADDITIVE latency, and OUTPUT DRIVE STRENGTH. These functions are controlled via the bits shown in Figure 46 below. The MR1 register is programmed via the MR5 command and retains the stored information until it is reprogrammed, until RESET\ goes LOW (true), or until the device loses power. Reprogramming the MR1 register will not alter the contents of the memory array, provided the operation is performed correctly. The MR1 register must be loaded when all banks are idle and no bursts are in progress. The controller must satisfy the specified timing parameters tMRD and tMOD before initiating a subsequent operation. FIGURE 46- MODE REGISTER 1 (MR1) DEFINITION BA2 BA 1 BA 0 A13 A12 A11 A10 A9 A 8 A7 A6 A5 A4 A3 A 2 A1 A0 Address bus 16 15 14 13 12 11 10 9 8 7 6 5 01 0 1 01 Q Off TDQS 01 RTT 01 WL RTT ODS M15 M14 4 3 2 1 0 AL RTT ODS DLL Mode register 1 (MR1) Mode Register 0 0 Mode register set 0 (MR0) M12 Q Off M11 TDQS 0 1 Mode register set 1 (MR1) 0 Enabled 0 Disabled 1 0 Mode register set 2 (MR2) 1 Disabled 1 Enabled 1 1 Mode register set 3 (MR3) RTT_NOM (ODT)2 M0 DLL Enable 0 Enable (normal) 1 Disable M5 M1 Output Drive Strength RTT_NOM (ODT)3 M7 Write Levelization M9 M6 M2 Non-Writes Writes 0 Disable (normal) 0 0 0 RTT_NOM disabled RTT_NOM disabled 1 Enable 0 0 1 RZQ/4 (60Ω [NOM]) RZQ/4 (60Ω [NOM]) 0 0 RZQ/6 (40Ω [NOM]) 0 1 RZQ/7 (34Ω [NOM]) 1 0 Reserved 1 1 Reserved 0 1 0 RZQ/2 (120Ω [NOM]) RZQ/2 (120Ω [NOM]) 0 1 1 RZQ/6 (40Ω [NOM]) RZQ/6 (40Ω [NOM]) M4 M3 Additive Latency (AL) 1 0 0 RZQ/12 (20Ω [NOM]) n/a 0 0 Disabled (AL = 0) 1 0 1 RZQ/8 (30Ω [NOM]) n/a 0 1 AL = CL - 1 1 1 0 Reserved Reserved 1 0 AL = CL - 2 1 1 1 Reserved Reserved 1 1 Reserved NOTES: 1. 2. MR1[16, 13, 10, 8] are reserved for future use and must be programmed to “0.” During write leveling, if MR1[7] and MR1[12] are “1” then all RTT_NOM values are available for use. 3. During write leveling, if MR1[7] is a “1,” but MR1[12] is a “0,” then only RTT_NOM write values are available for use. LOGIC Devices Incorporated www.logicdevices.com 90 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) ON-DIE TERMINATION (ODT) DLL ENABLE/DLL DISABLE The DLL may be enabled or disabled by programming MR1[0] during the LOAD MODE command, as shown in Figure 46 (previous page). The DLL must be enabled for NORMAL operation. DLL ENABLE is required during power-up initialization and upon returning to NORMAL operation after having DISABLED the DLL for the purpose of debugging or evaluation. ENABLING the DLL should always be followed by resetting the DLL using the appropriate LOAD MODE command. ODT resistance RTT_NOM is defined by MR1[9,6,2] (see Figure 46). The RTT termination value applies to the DQx, LDMx, UDMx, L[U]DQSx and L[U]DQSx\. The DDR3 device architecture supports multiple RTT termination values based on RZQ/n where n can be 3,4,6,8 or 12 and RZQ is 240Ω. Unlike DDR2, DDR3 ODT must be turned off prior to READING data out and must remain off during READ burst. RTT_NOM termination is allowed any time after the DRAM is initialized, calibrated, and not performing READ accesses, or in SELF REFRESH mode. Additionally, WRITE accesses with dynamic ODT enabled (RTT_WR) temporarily replaces RTT_NOM with RTT_WR. If the DLL is enabled prior to entering SELF REFRESH mode, the DLL is automatically DISABLED when entering SELF REFRESH operation and is automatically RE-ENABLED and RESET upon exit of SELF REFRESH. If the DLL is DISABLED prior to entering SELF REFRESH, the DLL remains DISABLED even upon exit of the SELF REFRESH operation until it has been RE-ENABLED and RESET. The actual effective termination, RTT_EFF, may be different from the RTT targeted value due to non-linearity of the termination. For RTT_EFF values and calculations, see the ON-DIE TERMINATION (ODT) description later in this DS. The SDRAM is not tested, nor does LDI warrant compliance with NORMAL mode timings or functionality when the DLL is disabled. An attempt has been made for the SDRAM to operate in the NORMAL mode whenever possible when the DLL is disabled; however, by industry standards, the following exceptions have been observed, defined and listed: The ODT feature is designed to improve signal integrity of the memory device by enabling the DDR3 SDRAM controller to independently turn ON/ OFF ODT for any or all devices in the end designs array. The ODT input control pin is used to determine when RTT is turned on (ODTLon) and off (ODTLoff), assuming ODT has been ENABLED via MR1[9,6,2]. 1. ODT is NOT ALLOWED to be used 2. The OUTPUT DATA is no longer edge-aligned to the clock 3. CL and CWL can only be six clocks Timings for ODT are detailed in the “ON-DIE Termination (ODT)” description later in this DS. When the DLL is DISABLED, timing and functionality can vary from the NORMAL operational specifications when the DLL is enabled. DISABLING the DLL also implies the need to change the clock frequency. WRITE LEVELING OUTPUT DRIVE STRENGTH The WRITE LEVELING function is enabled by MR1[7], as shown in Figure 46, WRITE LEVELING is used (during initialization) to de-skew the DQSx strobe to clock offset as a result of fly-by topology designs. For better signal integrity, some end use designs of DDR3 devices adopted fly-by topology for the commands, addresses, control signals and clocks. The DDR3 SDRAM iMOD uses a programmable impedance output buffer. The drive strength mode register setting is defined by MR1[5:1], RZQ/7 (34Ω [NOM]) is the primary output driver impedance setting for the device. To calibrate the output driver impedance, and external precision resistor (RZQ) is connected between the ZQ ball and VssQ. The value of the resistor is 240Ω±1%. The fly-by topology benefits from a reduced number of stubs and their lengths, however, fly-by topology induces flight time skew between the clock and DQSx strobe (and DQx) at each SDRAM in the array. Controllers will have a difficult time maintaining tDQSS, tDSS and tDSH specifications without supporting WRITE LEVELING in systems which use fly-by topology based designs. WRITE LEVELING timing and detailed operation information is provided in “WRITE LEVELING. The output impedance is set during initialization. Additional impedance calibration updates do not affect device operation and all data sheet timings and current specifications are met during an update. To meet the 34Ω specification, the output drive strength must be set to 34Ω during initialization. To obtain a calibrated output driver impedance after power-up, the DDR3 iMOD SDRAM needs a calibration command that is part of the initialization and reset procedure. OUTPUT ENABLE/DISABLE The OUTPUT ENABLE function is defined by MR1[12], as shown in Figure 46. When enabled (MR1[12]=0), all outputs (DQx, DQSx, DQSx\) are tri-stated. The output DISABLE feature is intended to be used during Icc characterization of the READ current and during tDQSS margining (WRITE LEVELING) only. LOGIC Devices Incorporated www.logicdevices.com 91 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) POSTED CAS ADDITIVE LATENCY (AL) AL is supported to make the command and data bus efficient for sustainable bandwidths in DDR3 SRAMs. MR1[4,3] define the value of AL (see Figure 46). MR1[4,3] enables the user to program the DDR3 SDRAM with an AL=0, CL-1, or CL-2. With this feature, the DDR3 SDRAM enables a READ or WRITE command to be issued after the ACTIVATE command for that bank prior to tRCD(MIN). The only restriction is ACTIVATE to READ or WRITE + AL ≥ tRCD(MIN) must be satisfied. Assuming tRCD(MIN) = CL, a typical application using this feature, sets AL=CL – 1tCK = tRCD(MIN-1tCK. The READ or WRITE command is held for the time of the AL before it is released internally to the DDR3 SDRAM iMOD device. READ latency (RL) is controlled by the sum of the AL and CAS latency (CL), RL=AL+CL, WRITE latency (WL) is the sum of CAS WRITE latency and AL, WL=AL + CWL (see “MODE REGISTER 2 (MR2))”. Examples of READ and WRITE latencies are shown in Figure 47 and Figure 49. FIGURE 47- READ LATENCY (AL = 5, CL = 6) BC4 T0 T1 ACTIVE n READ n T2 T6 T11 T12 T13 T14 NOP NOP NOP NOP NOP NOP CK# CK Command t RCD (MIN) DQS, DQS# AL = 5 CL = 6 DO n DQ DO n+1 DO n+2 DO n+3 RL = AL + CL = 11 Indicates a Break in Time Scale LOGIC Devices Incorporated www.logicdevices.com 92 Transitioning Data Don’t Care High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) MODE REGISTER 2 (MR2) The MODE REGISTER 2 (MR2) controls additional functions and features not available in the other mode registers. These additional functions are CAS WRITE latency (CWL), AUTO SELF REFRESH (ASR), SELF REFRESH TEMPERATURE (SRT) and DYNAMIC ODT (RTT_WR). These functions are controlled via the bits shown in Figure 48. The MR2 is programmed via the MRS command and will retain the stored information until it is programmed again or until the device loses power. Reprogramming the MR2 register will not alter the contents of the memory array, provided that the operation has been performed correctly. The MR2 register must be loaded when all banks are idle and no data bursts are in progress and the memory controller must wait for the specified time tMRD and tMOD before initiating a subsequent operation. FIGURE 48- MODE REGISTER 2 (MR2) DEFINITION *) *) *) ) A12 ) A10 A9 A8 A7 A 6 A5 A4 A3 A2 A1 A0 Address bus % $ 9 8 7 6 2243 12 )1 Mode Register 2 (MR2) 5 M15 M14 Mode Register & % 2 1 0 ,*35:08<",50# &,/" ,/>&# 0 Mode register set 0 (MR0) "= ,&= ,# 0 1 Mode register set 1 (MR1) .;"=,(&= ,# 1 0 Mode register set 2 (MR2) ,/"&) ,/>'&# ',/"'&) ,/>&# 1 1 Mode register set 3 (MR3) ,/"&) ,/>&# LOGIC Devices Incorporated 3 0 ( Notes: ' 394 4 +3/ -<:8 1-4 " 4475# 4475: 62$% 62$ * 39 "1:# -: . *:8 1. MR2[16, 13:11, 8, and 2:0] are reserved for future use and must all be programmed to “0.” www.logicdevices.com 93 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) CAS WRITE LATENCY (CWL) CWL is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of the internal WRITE to the latching of the first data in. CWL must be correctly set to the corresponding operating clock frequency (see Figure 48). The overall WRITE LATENCY (WL) is equal to CWL + AL (see Figure 46). FIGURE 49- CAS WRITE LATENCY BC4 T0 T1 ACTIVE n WRITE n T2 T6 T11 T12 T13 T14 NOP NOP NOP NOP NOP NOP CK# CK Command t RCD (MIN) DQS, DQS# AL = 5 CWL = 6 DI n DQ DI n+1 DI n+2 DI n+3 WL = AL + CWL = 11 Indicates A Break in Time Scale Transitioning Data Don’t Care optional extended temperature range of +95˚C while in SELF REFRESH mode. The standard SELF REFRESH current test specifies test conditions to normal case temperature (85˚C) only, meaning if SRT is enabled, the standard SELF REFRESH current specifications do not apply. AUTO SELF REFRESH (ASR) Mode register MR2[6] is used to DISABLE/ENABLE the ASR function. When ASR is DISABLED, the SELF REFRESH mode’s REFRESH rate is assumed to be at the normal 85˚C limit (commonly referred to as the 1X REFRESH rate). In the DISABLED mode, ASR requires the user to ensure the SDRAM never exceeds a Tc of 85˚C while in SELF REFRESH unless the user enables the SRT feature listed below, supporting an elevated temp up to +95˚C while in SELF REFRESH. SRT vs. ASR If the normal case temperature limit of 85˚C is not exceeded, then neither SRT nor ASR is required, and both can be DISABLED throughout operation. If the extended temperature option is used, the user is required to provide a 2X refresh rate during (manual) refresh for Extended temp devices or 3X refresh rate for Mil-temp devices. SRT and ASR should be enabled for automatic REFRESH services on all devices used in temperature environments ≤95˚C The standard SELF REFRESH current test specifies test conditions to normal case temperature (85˚C) only, meaning if ASR is enabled, the standard SELF REFRESH current specification does not apply (see the “EXTENDED TEMPERATURE USAGE” description later in this DS). SRT forces the SDRAM to switch the internal SELF REFRESH rate from 1X to 2X. SELF REFRESH is performed at 2X regardless of Tc. SELF REFRESH TEMPERATURE (SRT) ASR automatically switches the SDRAM’s internal SELF REFRESH rate from 1X to 2X, however, while in SELF REFRESH mode, ASR enables the REFRESH rate automatically adjust between 1X and 2X REFRESH rate over the supported temperature range. One other disadvantage with ASR is the SDRAM cannot always switch from a 1X to a 2X refresh rate at an exact case Temperature of 85˚C. Although the SDRAM will support data integrity when it switches from a 1X to 2X rate, it may switch at a lower temperature than 85˚C. Mode register MR2[7] is used to DISABLE/ENABLE the SRT function. When SRT is Disabled, the SELF REFRESH mode’s refresh rate is assumed to be at the normal 85˚C limit. In the DISABLED mode, SRT requires the user to ensure the SDRAM never exceeds the Tc limit of 85˚C while in SELF REFRESH mode unless the user enables ASR. When SRT is enabled, the SDRAM SELF REFRESH is changed internally from 1X to 2X, regardless of the case temperature (Tc). This enables the user to operate the SDRAM beyond the standard 85˚C limit up to the LOGIC Devices Incorporated www.logicdevices.com Since only one mode is necessary at one instant in time, SRT and ASR cannot be simultaneously enabled. 94 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) DYNAMIC ODT The dynamic ODT (RTT_WR) feature is defined by MR2[10,9]. Dynamic ODT is enabled when a value is selected. This new DDR3 feature enables the ODT termination value to change without issuing an MRS command, essentially changing the ODT termination “on-the-fly”. With dynamic ODT (RTT_WR) when beginning a WRITE burst and subsequently switches back to ODT (RTT_WR) is enabled: ODTLCNW, ODTLCNW4, ODTLCNW* ODTH4, ODTH8 and tADC. Dynamic ODT is only applicable during WRITE cycles, If ODT (RTT_NOM) is disabled, dynamic ODT (RTT_WR) is still permitted. RTT_NOM and RTT_WR can be used independent of one another. Dynamic ODT is not available during WRITE LEVELING mode, regardless of the state of ODT (RTT_NOM). For details on ODT operation, refer to the “On-Die-Termination (ODT)” section. MODE REGISTER (MR3) The mode register 3 (MR3) controls additional functions and features not available via MR0, MR1 or MR2. Currently defined as the MULTIPURPOSE REGISTER (MPR). This function is controlled via the bits shown in Figure 50. The MR3 is programmed via the LOAD MODE command and retains the stored information until it is programmed again or until the device loses power. Reprogramming the MR3 register will not alter the contents of the memory array, provided the programming of the MR3 has been performed correctly. The MR3 register must be loaded when all banks are idle and no data bursts are in progress and the memory controller must wait the specified time tMRD and tMOD before initiating a subsequent operation. FIGURE 50 - MODE REGISTER 3 (MR3) DEFINITION BA2 BA 1 BA 0 A13 A12 A11 A10 A9 16 01 A8 A7 A 6 A5 A4 A3 0 MPR Enable Normal DRAM operations 2 1 Mode register set 1 (MR1) 1 Dataflow from MPR 0 Mode register set 2 (MR2) 1 Mode register set 3 (MR3) 0 0 0 1 1 A1 A0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 01 01 01 01 01 01 01 01 01 01 01 MPR MPR_RF Mo de register set (MR0) M15 M14 A2 Mode Register M2 M1 M0 Address bus Mode register 3 (MR3) 0 0 MPR READ Function Predefined pattern 3 0 1 Reserved 1 0 Reserved 1 1 Reserved NOTES: LOGIC Devices Incorporated 1. MR3[16 and 13:4] are reserved for future use and must all be programmed to “0.” 2. When MPR control is set for normal DRAM operation, MR3[1, 0] will be ignored. 3. Intended to be used for READ synchronization. www.logicdevices.com 95 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) MULTIPURPOSE REGISTER (MPR) The MULTIPURPOSE REGISTER function is used to output a predefined system timing calibration bit sequence. Bit 2 is the master bit that enables or disables access to the MPR register and bits 1 and 0 determine which mode the MPR is placed in. The basic concept of the multipurpose register is shown in Figure 51. If MR3[2] is a “0”, then the MPR access is disabled and the SDRAM operates in normal mode. However, if MR3[2] is a “1”, then SDRAM no longer outputs normal read data but outputs MPR data as defined by MR3[0,1]. If MR3[0,1] is equal to “00”, then a predefined read pattern for system calibration is selected. To enable the MPR, the MRS command is issued to MR3 and MR3[2]=1 (see Table 66). Prior to issuing the MRS command, all banks must be in the idle state (all banks are precharged, and tRP is met). When the MPR is enabled, any subsequent READ or RDAP commands are redirected to the multipurpose register. The resulting operation when either a READ or a RDAP command is issued is defined by MR3[1:0]when MPR is enabled (see Table 67). When the MPR is enabled, only READ or RDAP commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3[2]=0). POWER-DOWN, SELF REFRESH and any other NON READ or RDAP command is not allowed. The RESET function is supported during MPR enable mode. FIGURE 51 - MULTIPURPOSE REGISTER (MPR) BLOCK DIAGRAM Memory core MR3[2] = 0 (MPR off) Multipurpose register pre defined data for READs MR3[2] = 1 (MPR on) DQ, DM, DQ S, DQS# NOTES: 1. A predefined data pattern can be read out of the MPR with an external READ command. 2. MR3[2] defines whether the data flow comes from the memory core or the MPR. When the data flow is defined, the MPR contents can be read out continuously with a regular READ or RDAP command. LOGIC Devices Incorporated www.logicdevices.com 96 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 66: BURST ORDER MR3[2] MPR 0 MR3[1:0] MPR READ Function Function “Don’t Care” Normal Operation, no MPR transaction. All subsequent READs come from the SDRAM memory array. All subsequent WRITEs go to the SDRAM memory array. 1 A[1:0] (See Table 66) Enable MPR mode, subsequent READ/RDAP commands defined by bits 1 and 2. MPR FUNCTIONAL DESCRIPTION The MPR JEDEC definition allows for either a prime DQ0 for lower byte and DQ8 for the upper byte of each of the (4) words contained in the LDI iMOD, to output the MPR data with the remaining DQs driven LOW, or for all DQs to output the MPR data. The MPR readout supports fixed READ burst and READ burst chop (MRS and OTF via A12/BC#) with regular READ latencies and AC timings applicable. This providing the DLL is locked as required. MPR addressing for a valid MPR READ is as follows: • A[1:0] must be set to “00” as the burst order is fixed per nibble • A2 selects the burst order • BL8, A2 is set to “0”, and the burst order is fixed to 0,1,2,3,4,5,6,7 • For burst chop 4 cases, the burst order is switched on the nibble base and: • A2=0: burst order =0,1,2,3 • A2=1: burst order =4,5,6,7 • Burst order bit 0 (the first bit) is assigned to LSB, and burst order bit 7 (the last bit) is assigned to MSB • A[9:3] are a “Don’t Care” • A10 is a “Don’t Care” • A11 is a “Don’t Care” • A12: Selects burst chop mode on-the-fly, if enabled within MR0 • A13 is a “Don’t Care” • BA[2:0] are a “Don’t Care” LOGIC Devices Incorporated www.logicdevices.com 97 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) MPR REGISTER ADDRESS DEFINITIONS and BURSTING ORDER The MPR currently supports a single data format. This data format is a predefined READ pattern for system calibration. The predefined pattern is always a repeating 0-1 bit pattern. Examples of the different type of predefined READ pattern bursts are shown in Figures 52, 53, and 54. TABLE 67: BURST ORDER MR3[2] MR3[1:0] Function Burst Length 00 READ predefined pattern for BL8 1 Read A[2:0] 000 Burst Order and Data Pattern Burst Order: 0,1,2,3,4,5,6,7 Predefined pattern: 0,1,0,1,0,1,0,1 system calibration BC4 000 Burst Order: 0,1,2,3 Predefined pattern: 0,1,0,1 BC4 100 Burst Order: 4,5,6,7 Predefined pattern: 0,1,0,1 1 1 1 LOGIC Devices Incorporated 01 RFU 10 RFU 11 RFU www.logicdevices.com n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 98 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A CK# CK Command Bank add ress T0 Ta0 Tb0 Vali d MRS t MOD PREA 3 READ1 t RP Tb1 Tc0 NOP Tc1 NOP Tc2 NOP Tc3 NOP Tc4 NOP Tc5 NOP Tc6 MRS Tc7 NOP Tc8 NOP Tc9 Valid Tc10 0 Vali d 1 Val i d 0 0 0 t MOD NOP 3 A 11 0 Val i d Indicates a Break in Time Scale Don ’t Care NOP t MPRR 0 Vali d 02 00 02 1 Vali d 0 A2 00 0 A[1:0] A[9:3] Vali d A12/BC# 0 A10/AP 0 1 RL 1. READ with BL8 either by MRS or OTF. 2. Memory controller must drive 0 on A[2:0]. A [ 15:13] DQS, DQS# DQ Notes: High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 99 www.logicdevices.com LOGIC Devices Incorporated L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) Figure 52 - MPR System Read Calibration with BL8: Fixed Burst Order Single Readout CK# CK T0 Ta Tb Tc0 Tc1 NOP Tc2 NOP Tc3 NO Tc4 NOP Tc5 NOP Tc6 NOP Tc7 NOP Tc8 NOP Tc9 MRS Tc10 Vali d Td t MOD NOP 3 t MPRR READ1 t CCD READ1 t MOD MRS t RP Vali d A11 0 0 Vali d Vali d Vali d Vali d 1 Vali d 0 0 0 Don ’t Care PREA Vali d 0 3 12 00 Bank add ress 02 Vali d Vali d 1 Vali d 0 02 A2 00 Vali d 02 A[9:3] Vali d A12/BC# Vali d 1. READ with BL8 either by MRS or OTF. 2. Memory controller must drive 0 on A[2:0]. RL 0 A10/AP 0 0 1 A[1:0] Command RL Indicates a Break in Time Scale A[15:13] DQS, DQS# DQ Notes: High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 100 www.logicdevices.com LOGIC Devices Incorporated L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) Figure 53 - MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout CK# CK Command Bank add ress T0 Ta Tb Tc0 Tc1 Tc2 Tc3 Tc4 NOP Tc5 NOP Tc6 NOP Tc7 MRS Tc8 NOP Tc9 NOP Tc10 Valid Td t MOD NOP 3 NOP t MPRR NOP Vali d NOP t CCD READ1 Vali d READ1 t MOD 0 Don ’t Care MRS 3 14 00 Indicates a Break in Time Scale PREA t RF 03 Vali d 0 Vali d 1 Val i d Vali d 0 02 00 Val i d Vali d 0 02 A2 0 Val i d Vali d 1 0 A [ 9:3] 0 Vali d 1 1 A 11 0 0 A 10/A P A12/BC# Vali d READ with BC4 either by MRS or OTF. Memory controller must drive 0 on A[1:0]. A2 = 0 selects lower 4 nibble bits 0 . . . 3. A2 = 1 selects upper 4 nibble bits 4 . . . 7. RL Vali d A[1:0] RL 0 DQS, DQS# DQ Notes: A[15:13] 1. 2. 3. 4. High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 101 www.logicdevices.com LOGIC Devices Incorporated L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) Figure 54 - MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble CK# CK Command T0 Ta Tb Tc0 NOP Tc1 NOP Tc2 NOP Tc3 NOP Tc4 NOP Tc5 NOP Tc6 NOP Tc7 MR S Tc8 NOP Tc9 NOP Tc10 Valid Td Vali d Vali d 1 Vali d Vali d 1 0 0 t MOD READ1 02 0 3 02 04 00 t MPRR 0 13 Vali d 0 Vali d READ1 t CCD A[1:0] 1 Val i d Vali d Vali d MRS t MOD A2 00 Val i d 3 A [ 9:3] 0 1 0 A 10/A P Vali d 0 Val i d A 11 A12/BC# 0 RL Don ’t Care PREA t RF RL A [ 15:13] DQS, DQS# DQ READ with BC4 either by MRS or OTF. Memory controller must drive 0 on A[1:0]. A2 = 1 selects upper 4 nibble bits 4 . . . 7. A2 = 0 selects lower 4 nibble bits 0 . . . 3. Indicates a Break in Time Scale Val i d Notes: 0 Bank add ress 1. 2. 3. 4. High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 102 www.logicdevices.com LOGIC Devices Incorporated L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) Figure 55 - MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) MPR READ PREDEFINED PATTERN The predetermined READ calibration pattern is a fixed pattern of 0,1,0,1,0,1,0,1. The following is an example of using the READ out predetermined READ calibration pattern. The example is to perform multiple READS from the MULTIPURPOSE REGISTER (MPR) in order to do system level READ timing calibration based on the predetermined and standardized pattern. The following protocol outlines the steps used to perform the READ calibration: • Precharge all banks • After tRP is satisfied, set MRS, MR3[2] = 1 and MR3[1:0]=00. This redirects all subsequent READs and Loads the predefined pattern into the MPR. As soon as tMRD and tMOD are satisfied, the MPR is available. • Data WRITE operations are not allowed until the MPR returns to the normal SDRAM state • Issue a READ with burst order information (all other address pins are “Don’t Care”): • A[1:0] = 00 (data burst order is fixed starting at nibble) • A2 = 0 (for BL8, burst order is fixed as 0,1,2,3,4,5,6,7) • A12 = 1 (use BL8) • After RL = AL + CL, the SDRAM bursts out the predefined READ calibration pattern (0,1,0,1,0,1,0,1) • The memory controller repeats the calibration READs until READ data capture at the memory controller is optimized • After the last MPR READ burst and after tMPRR has been satisfied, issue MRS, MR3[2] = 0 and MR3[1:0] = “Don’t Care” to the normal SDRAM state. All subsequent READ and WRITE accesses will be regular READS and WRITES from/to the SDRAM array • When tMRD and tMOD are satisfied from the last MRS, the regular SDRAM commands (such as ACTIVATE a Memory bank for regular READ or WRITE access) are permitted MODE REGISTER SET (MRS) The mode registers are loaded via inputs BA[2:0], A[13:0]. BA[2:0] determines which mode register is programmed: • BA2 = 0, BA1 = 0, BA0 = 0 for MR0 • BA2 = 0, BA1 = 0, BA0 = 1 for MR1 • BA2 = 0, BA1 = 1, BA0 = 0 for MR2 • BA2 = 0, BA1 = 1, BA0 = 1 for MR3 The MRS command can only be issued (or reissued) when all banks are idle and in the precharged state (tRP is satisfied and no data bursts are in progress). The controller must wait the specified time tMRD before initiating a subsequent operation such as an ACTIVATE command. There is also a restriction after issuing an MRS command with regard to when the updated functions become available. This parameter is specified by tMOD. Both tMRD and tMOD parameters are shown in Figure 42 and 43. Violating either of these requirements will result in unspecified operation. ZQ CALIBRATION The ZQ CALIBRATION command is used to calibrate the SDRAM output drivers (RON) and ODT values (RTT) over process, voltage, and temperature, provided a dedicated 240Ω (±1%) external resistor is connected from the SDRAM’s ZQ ball to VssQ. DDR3 SDRAMs need a longer time to calibrate RON and ODT at power up INITIALIZATION and SELF REFRESH exit and a relatively shorter time to perform periodic calibrations. DDR3 SDRAM defines two ZQ CALIBRATION commands: ZQ CALIBRATION LONG (ZQCL) and ZQ CALIBRATION SHORT (ZQCS). An example of ZQ CALIBRATION timing is shown in Figure 56. All banks must be PRECHARGED and tRP must be met before ZQCL or ZQCS commands can be issued to the SDRAM. No other activities (other than another ZQCL or ZQCS command may be issued to the SDRAM) can be performed on the SDRAM array by the controller for the duration of tZQINIT or tZQOPER. The quiet time on the SDRAM array helps accurately calibrate RON and ODT. After SDRAM calibration is achieved, the SDRAM should disable the ZQ ball’s current consumption path to reduce overall power usage. ZQ CALIBRATION commands can be issued in parallel to DLL RESET and locking time. Upon SELF REFRESH exit, an explicit ZQCL is required if ZQ CALIBRATION is desired. In dual rank system designs that share the ZQ resistor between devices, the controller must not allow overlap of tZQINT, tZQOPER or tZQCS between ranks. LOGIC Devices Incorporated www.logicdevices.com 103 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 56 - ZQ CALIBRATION TIMING (ZQCL AND ZQCS) T0 T1 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tc0 Tc1 Tc2 ZQCL NOP NOP NOP Valid Vali d ZQCS NOP NOP NOP Valid Address Vali d Vali d Vali d A10 Vali d Vali d Vali d CK# CK Command CKE 1 Vali d Vali d 1 Vali d ODT 2 Vali d Vali d 2 Vali d DQ 3 A ctivities 3 High-Z Activities High-Z t ZQ INIT or t ZQ OPER t ZQCS Indicates a Break in Time Scale Don ’t Care NOTES: 1. CKE must be continuously registered HIGH during the calibration procedure. 2. ODT must be disabled via the ODT signal or the MRS during the calibration procedure. 3. All devices connected to the DQ bus should be High-Z during calibration. ACTIVATE Before any READ or WRITE commands can be issued to a bank within the SDRAM, a ROW in that bank must be opened (ACTIVATED). This is accomplished via the ACTIVATE command, which selects both the BANK and the ROW to be ACTIVATED. After a ROW is opened with an ACTIVATE command, a READ or WRITE command may be issued to that ROW, subject to the tRCD specification. However, if the additive latency is programmed correctly, a READ or WRITE command may be issued prior to tRCD (MIN). In this operation, the SDRAM enables a READ or WRITE command to be issued after the ACTIVATE command for that bank, but prior to tRCD (MIN) (see “POSTED CAS ADDITIVE LATENCY (AL)). tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVATE command on which the READ or WRITE command can be entered. The same procedure is used to convert other specification limits from time units to clock cycles. When at least one bank is open, any READ-to-READ command delay or WRITE-to-WRITE command delay is restricted to tCCD (MIN). A subsequent ACTIVATE command to a different ROW in the same BANK can only be issued after the previous ACTIVE ROW has been closed (PRECHARGED). The minimum time interval between successive ACTIVATE commands to the same BANK is defined by tRC. A subsequent ACTIVATE command to another BANK can be issued while the first BANK is being accessed, which results in a reduction of total ROW-ACCESS overhead. The minimum time interval between successive ACTIVATE commands may be issued in a given tFAW (MIN) period, and the tRRD (MIN) restriction still applies. The tFAW (MIN) parameter applies, regardless of the number of BANKS already opened or closed. LOGIC Devices Incorporated www.logicdevices.com 104 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 57 - EXAMPLE: MEETING tRRD (MIN) AND tRCD (MIN) T0 T1 T2 T3 T4 T5 T8 T9 T10 T11 Command ACT NOP NOP ACT NOP NOP NOP NOP NOP RD/WR Add ress Row BA[2:0] Bank x CK# CK Row Col Bank y Bank y t RRD t RCD Indicates a Break in Time Scale Don ’t Care FIGURE 58 - EXAMPLE: tFAW CK# T0 T1 T4 T5 T8 T9 T10 T11 T19 T20 ACT NOP ACT NOP A CT NOP ACT NOP NOP A CT CK Command Add ress BA[2:0] Row Bank a Row Row Row Row Bank b Bank c Bank d Bank ye t RRD t FAW Indicates a Break in Time Scale LOGIC Devices Incorporated www.logicdevices.com 105 Don ’t Care High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) READ READ bursts are initiated with a READ command. The starting COLUMN and BANK addresses are provided with the READ command and AUTO PRECHARGE is either enabled or disabled for that burst access. If AUTO PRECHARGE is enabled, the ROW being accessed is automatically PRECHARGED at the completion of the burst sequence. If AUTO PRECHARGE is disabled, the ROW will be left open after the completion of the burst. During READ bursts, the valid data out element from the starting column address is available at READ LATENCY (RL) clocks later. RL is defined as the sum of POSTED CAS ADDITIVE LATENCY (AL) and CAS LATENCY (CL) (RL = AL + CL). The value of AL and CL is programmable in the mode register via the MRS command. Each subsequent data-out element will be valid nominally at the next positive or negative clock edge (that is, at the next crossing of CK and CK\). Figure 59 shows an example of RL based on a CL setting of 8 as well as AL=0. FIGURE 59 - READ LATENCY T0 T7 T8 T9 T10 T11 T12 T12 Command READ NOP NOP NOP NOP NOP NOP NOP Add ress Bank a, Col n CK# CK CL = 8, AL = 0 DQS, DQS# DO n DQ Indicates a Break in Time Scale Notes: Don ’t Care 1. DO n = data-out from column n. 2. Subsequent elements of data-out appear in the programmed order following DO . n. A READ burst may be followed by a PRECHARGE command to the same bank provided AUTO PRECHARGE is not ACTIVATED. The minimum READ-to-PRECHARGE command spacing to the same bank is four clocks and must also satisfy a minimum analog time from the READ command. This time is called tRTP (READ-to-PRECHARGE). tRTP starts AL cycles later than the READ command. Examples for BL8 are shown in Figure 65 and BC4 in Figure 66. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. The PRECHARGE command followed by another PRECHARGE command to the same bank is allowed. However, the precharge period will be determined by the last PRECHARGE command issued to the bank. L[U]DQSx, L[U]DQSx\ is driven by the SDRAM along with the output data. The initial LOW state on L[U]DQSx and HIGH state on L[U]DQSx\, is known as the READ preamble (tRPRE). The LOW state on DQSx and the HIGH state on L[U]DQSx\, coincident with the last data-out element, is known as the READ postamble (tRPST). Upon completion of a burst, assuming no other commands have been initiated, the DQ will go HIGH-Z. A detailed explanation of tDQSQ (valid data-out skew), tQH (data-out window hold), and the valid data window are depicted in Figure 71. A detailed explanation of tDQSCK (DQS transition skew to CK) is also depicted in Figure 71. Data from any READ burst may be concatenated with data from a subsequent READ command to provide a continuous flow of data. The first data element from the new burst follows the last element of a completed burst. The new READ command should be issued tCCD cycles after the first READ command. This is shown for BL8 in Figure 60. If BC4 is enabled, tCCD must still be met which will cause a gap in the data output, as shown in Figure 61. Nonconsecutive READ data is reflected in Figure 62. DDR3 SDRAMs do not allow interrupting or truncating any READ burst. If A10 is HIGH when a READ command is issued, the READ with AUTO PRECHARGE function is engaged. The SDRAM starts an AUTO PRECHARGE operation on the rising edge which is AL + tRTP cycles after the READ command. DDR3 SDRAMs support a tRAS lockout feature (see Figure 68). If tRAS (MIN) is not satisfied at the edge, the starting point of the AUTO PRECHARGE operation will be delayed until tRAS (MIN) is satisfied. In case the internal PRECHARGE operation is pushed out by tRTP, tRP starts at the point at which the internal PRECHARGE happens. The time from READ with AUTO PRECHARGE to the next ACTIVATE command the same bank is AL + (tRTP + tRP)*, where “*” means rounded up to the next integer. In any event, internal RECHARGE does not start earlier than four clocks after the last 8n-bit prefetch. Data from any READ burst must be completed before a subsequent WRITE burst is allowed. An example of a READ burst followed by a WRITE burst for BL8 is shown in Figure 63. To ensure the READ data is completed before the WRITE data is on the bus, the minimum READ-to-WRITE timing is RL + tCCD – WL + 2tCK. LOGIC Devices Incorporated Transitioning Data www.logicdevices.com 106 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A CK# REA D T0 Command 1 Bank, Col n CK Add ress 2 DQS, DQS# DQ3 T1 NOP Notes: T2 NOP RL = 5 T3 NOP T4 REA D Bank, Col b t RPRE T5 NOP DO n T6 NOP DO n+1 T7 DO n+4 NOP DO n+3 RL = 5 DO n+2 T8 DO n+6 NOP DO n+5 T9 NOP DO n+7 DO b T10 DO b+2 NOP DO b+1 T11 DO b+4 NO P DO b+3 T12 NO P DO b+5 DO b+6 T13 NOP t RPST DO b+7 Transitioning Data T14 NOP Don ’t Care NOP commands are shown for ease of illustration; other commands may be valid at these times. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ command at T0 and T4. DO n (or b) = data-out from column n (or column b). BL8, RL = 5 (CL = 5, AL = 0). t CCD 1. 2. 3. 4. High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 107 www.logicdevices.com LOGIC Devices Incorporated L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) Figure 60 - Consecutive READ Bursts (BL8) CK# CK Comman d 1 Address 2 DQS, DQS# DQ3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 NOP T10 NOP T11 NOP T12 NOP T13 NOP T14 DO b+3 t RPST NOP DO b+2 NOP t RPST DO n+3 DO b+1 NOP t RPRE DO b NOP RL = 5 NOP DO n+2 READ t CCD Bank, Col b DO n+1 NOP t RPRE DO n NOP RL = 5 Don ’t Care NOP commands are shown for ease of illustration; other commands may be valid at these times. The BC4 setting is activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ command at T0 and T4. DO n (or b) = data-out from column n (or column b). BC4, RL = 5 (CL = 5, AL = 0). Transitioning Data NOP Bank, Col n Notes: READ 1. 2. 3. 4. High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 108 www.logicdevices.com LOGIC Devices Incorporated L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) Figure 61 - Consecutive READ Bursts (BC4) T0 T1 NOP T2 NOP T3 NOP T4 READ T5 NOP T6 NOP T7 NOP T8 NOP T9 NOP T10 NOP T11 NOP T12 NOP T13 NOP T14 NOP T15 NOP T16 NOP T17 CK# NOP CL = 8 READ CK Bank a, Col b Add ress DO b Don ’t Care Command CL = 8 DO n AL = 0, RL = 8. DO n (or b) = data-out from column n (or column b). Seven subsequent elements of data-out appear in the programmed order following DO n. Seven subsequent elements of data-out appear in the programmed order following DO b. Transitioning Data Bank a, Col n DQ DQS, DQS# Notes: 1. 2. 3. 4. High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 109 www.logicdevices.com LOGIC Devices Incorporated L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) Figure 62 - Nonconsecutive READ Bursts CK CK# Command 1 Add ress 2 DQ3 DQS, DQS# T0 READ Bank, Col n T1 NOP T2 NOP RL = 5 T3 NOP T4 NOP t RPRE T5 NOP READ-to-WRITE command delay = RL + t CCD + 2t CK - WL Notes: DO n T6 WRITE DO n+2 Bank, Col b DO n+1 T7 DO n+4 NOP DO n+3 T8 DO n+6 NOP DO n+5 T9 NOP t RPST DO n+7 WL = 5 T10 NOP t WPRE T11 NOP DI n DI n+1 T12 NOP DI n+2 T13 NOP DI n+4 t BL = 4 clocks DI n+3 DI n+5 T14 NOP DI n+6 Transitioning Data T15 t WTR t WR NOP t WPST DI n+7 Don ’t Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the READ command at T0, and the WRITE command at T6. High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 110 www.logicdevices.com LOGIC Devices Incorporated L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) Figure 63 - READ (BL8) to WRITE (BL8) CK CK# Command 1 Add ress2 DQS, DQS# DQ3 T0 T1 T2 T3 T4 T5 T6 NOP T7 NOP T8 NOP T9 NOP T10 NOP T11 NOP T12 NOP T13 NOP T14 NOP T15 t WR t WTR NOP DI n +3 t WPST t BL = 4 clo cks NOP DI n +2 WRITE t WPRE DI n +1 NOP t RPST DO n+ 3 DI n NOP DO n +2 NOP DO n +1 Don ’t Care READ t RPRE Bank, Col b DO n WL = 5 Transitioning Data NOP commands are shown for ease of illustration; other commands may be valid at these times. The BC4 OTF setting is activated by MR0[1:0] and A12 = 0 during READ command at T0 and WRITE command at T4. DO n = data-out from column n; DI n = data-in from column b. BC4, RL = 5 (AL - 0, CL = 5), WL = 5 (AL = 0, CWL = 5). RL = 5 READ-to-WRITE command delay = RL + t CC D/2 + 2 t CK - WL Bank, Col n Notes: 1. 2. 3. 4. High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 111 www.logicdevices.com LOGIC Devices Incorporated L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) Figure 64 - READ (BC4) to WRITE (BC4) OTF CK CK# Command 1 Add ress 2 DQ3 DQS, DQS# T0 READ Bank, Col n T1 NOP T2 NOP RL = 5 T3 NOP T4 NOP t RPRE T5 NOP READ-to-WRITE command delay = RL + t CCD + 2t CK - WL Notes: DO n T6 WRITE DO n+2 Bank, Col b DO n+1 T7 DO n+4 NOP DO n+3 T8 DO n+6 NOP DO n+5 T9 NOP t RPST DO n+7 WL = 5 T10 NOP t WPRE T11 NOP DI n DI n+1 T12 NOP DI n+2 T13 NOP DI n+4 t BL = 4 clocks DI n+3 DI n+5 T14 NOP DI n+6 Transitioning Data T15 t WTR t WR NOP t WPST DI n+7 Don ’t Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the READ command at T0, and the WRITE command at T6. 3. DO n = data-out from column, DI b = data-in for column b. 4. BL8, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5). High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 112 www.logicdevices.com LOGIC Devices Incorporated L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) Figure 65 - READ to PRECHARGE (BL8) PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) Figure 66 - READ to PRECHARGE (BC4) T0 NOP T1 NOP T2 NOP T3 NOP T4 PRE T5 NOP T6 NOP T7 NOP T8 NOP T9 NOP T10 NOP T11 NOP T12 ACT T13 NOP T14 NOP T15 NOP T16 NOP T17 C K# READ CK Command Bank a, Col n t RTP t RAS Add ress DQS, DQS# DQ Bank a, (or all) DO n DO n+2 t RP DO n+1 DO n+3 Bank a, Row b Transitioning Data Don ’t Care LOGIC Devices Incorporated www.logicdevices.com 113 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) Figure 67 - READ to PRECHARGE (AL = 5, CL = 6) BC4 CK CK# Command DQS, DQS# DQ T0 ACTIVE n T1 READ n t RCD (MIN) T2 T6 NOP T11 NOP CL = 6 T12 NOP DO n DO n+1 T13 NOP DO n+2 Transitioning Data DO n+3 114 T14 NOP Don’t Care www.logicdevices.com NOP AL = 5 RL = AL + CL = 11 Indicates a Break in Time Scale LOGIC Devices Incorporated High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) Figure 68 - READ with Auto Precharge (AL = 4, CL = 6) T0 READ CK# Command Bank a, Col n CK Add ress DQS, DQS# DQ T1 NOP T2 NOP AL = 4 T3 NOP T4 NOP T5 NOP T6 NOP t RTP (MIN) t RAS (MIN) T7 NOP CL = 6 T8 NOP T9 NOP T10 NOP DO n DO n+1 DO n+3 T12 NOP T13 NOP NOP t RP Transitioning Data Ta0 115 ACT Bank a, Row b Don ’t Care www.logicdevices.com T11 NOP DO n+2 Indicates A Break in Time Scale LOGIC Devices Incorporated High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) READ A DQSx to DQ output timing is shown in Figure 69. The DQ transitions between valid data outputs must be within tDQSQ of the crossing point of L[U]DQSx, L[U]DQSx\. DQS must also maintain a minimum HIGH and LOW time of tQSH and tQSL. Prior to the READ preamble, the DQ balls will either be floating or terminated depending on the status of the ODT signal. Figure 70 shows the strobe-to-clock timing during a READ. The crossing point DQSx, DQSx\ must transition with ± tDQSCK of the clock crossing point. The data out has no timing relationship to clock, only to DQS, as shown in Figure 70. Figure 70 also shows the READ preamble and postamble. Normally, both DQSx and DQSx\ are HIGH-Z to save power (VccQ). Prior to data output from the SDRAM, DQSx is driven LOW and DQSx\ driven HIGH for tRPRE. This is known as the READ preamble. The READ postamble, tRPST, is one half clock from the last L[U]DQSx, L[U]DQSx\ transition. During the READ postamble, L[U]DQSx is driven LOW and L[U] DQSx\ driven HIGH. When complete, the DQ will either be disabled or will continue terminating depending on the state of the ODT signal. Figure 75 demonstrates how to measure tRPST. LOGIC Devices Incorporated www.logicdevices.com 116 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A T0 T1 T2 T3 T4 NOP T5 NOP T6 NOP T7 NOP T8 NOP T9 NOP T10 CK# NOP CK NOP RL = AL + CL NOP DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 Don ’t Care t HZ (DQ) MAX NOP t RPST READ DO n+2 t QH DO DO DO DO DO DO DO n+1 n+2 n+3 n+4 n+5 n+6 n+7 DO DO DO DO DO DO DO n+3 n+1 n+2 n+4 n+5 n+6 n+7 t DQSQ (MAX) Command 1 t RPRE t DQSQ (MAX) t LZ (DQ) MIN Bank, Col n t QH DO n DO n+1 Data valid Transitioning Data NOP commands are shown for ease of illustration; other commands may be valid at these times. The BL8 setting is activated by either MR0[1, 0] = 0, 0 or MR0[0, 1] = 0, 1 and A12 = 1 during READ command at T0. DO n = data-out from column n. BL8, RL = 5 (AL = 0, CL = 5). Output timings are referenced to VCCQ/2 and DLL on and locked. t DQSQ defines the skew between DQS, DQS# to data and does not define DQS, DQS# to clock. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can vary (either early or late) within a burst. Data valid DO n DO n Add ress 2 DQS, DQS# DQ3 (last data valid) DQ3 (first data no lon ger valid) All DQ collectively Notes: 1. 2. 3. 4. 5. 6. 7. High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 117 www.logicdevices.com LOGIC Devices Incorporated L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) Figure 69 - Data Output Timing – tDQSQ and Data Valid Window PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) OUTPUT TIMING tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving tHZ (DQS) and tHZ (DQ) or begins driving tLZ (DQS). tLZ (DQ), Figure 71 shows a method to calculate the point when the device is not longer driving tHZ (DQS) and tHZ (DQ) or begins driving tLZ (DQS), tLZ (DQ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. The parameters tLZ (DQS), tLZ (DQ), tHZ (DQS) and tHZ (DQ) are defined as single-ended. LOGIC Devices Incorporated www.logicdevices.com 118 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A CK CK# DQS, DQS# early strobe DQS, DQS# late strobe T0 t LZ (DQS)MIN t RPRE T2 t QSH Bit 3 Bit 2 Bit 4 Bit 3 T3 Bit 5 Bit 4 Bit 5 Bit 6 Bit 7 Bit 6 Bit 7 T5 t HZ (DQS) MAX t RPST t HZ (DQS) MIN t RPST t DQSCK(MAX) T4 t DQSCK(MIN) t DQSCK(MAX) t QSL t DQSCK(MIN) t QSL t QSH t DQSCK(MAX) t QSL t DQSCK(MIN) Bit 2 Bit 1 t QSL t QSH t DQSCK(MAX) Bit 1 t QSH T1 RL measured to this point Bit 0 t DQSCK(MIN) t LZ (DQS)MAX t RPRE Bit 0 T6 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 119 www.logicdevices.com LOGIC Devices Incorporated L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) Figure 70 - Data Strobe Timing – READs PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) Figure 71 - Method for Calculating tLZ and tHZ VOH - xmV VTT + 2xmV VOH - 2xmV VTT + xmV t LZ (DQS), t LZ (DQ) t HZ (DQS), t HZ (DQ) T2 T1 VOL + 2xmV VTT - xmV VOL + xmV VTT - 2xmV LOGIC Devices Incorporated T2 t LZ (DQS),t LZ (DQ) begin point = 2 × T1 - T2 t HZ (DQS),t HZ (DQ) end point = 2 × T1 - T2 Notes: T1 1. Within a burst, the rising strobe edge is not necessarily fixed at t DQSCK (MIN) or t DQSCK (MAX). Instead, the rising strobe edge can vary between t DQSCK (MIN) and t DQSCK (MAX). 2. The DQS high pulse width is defined by t QSH, and the DQS low pulse width is defined by t QSL. Likewise, t LZ (DQS) MIN and t HZ (DQS) MIN are not tied to t DQSCK (MIN) (early strobe case) and t LZ (DQS) MAX and t HZ (DQS) MAX are not tied to t DQSCK (MAX) (late strobe case); however, they tend to track one another. 3. The minimum pulse width of the READ preamble is defined by t RPRE (MIN). The minimum pulse width of the READ postamble is defined by t RPST (MIN). www.logicdevices.com 120 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 72 - tRPRE TIMING CK VTT CK# tA tB DQS VTT Single-ended signal, provided as background information tC tD VTT DQS# Single-ended signal, provided as background information T1 t RPRE begins DQS - DQS# t RPRE 0V T2 t RPRE ends Resultin g differential signal relevant for t RPRE specification FIGURE 73 - tRPST TIMING CK VTT CK# tA DQS Single-ended signal, provided as background information VTT tB tC tD DQS# VTT Single-ended signal, provided as background information t RPST DQS - DQS# Resultin g differential signal relevant for t RPST specification LOGIC Devices Incorporated www.logicdevices.com 0V T1 t RPST begins 121 T2 t RPST ends High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 74 - tWPRE TIMING CK VTT CK# T1 t WPRE begins DQS - DQS# 0V t WPRE T2 t WPRE ends Resulting differential signal relevant for t WPRE specification FIGURE 75 - tWPST TIMING CK VTT CK# t WPST DQS - DQS# Resulting differential signal relevant for t WPST specification LOGIC Devices Incorporated www.logicdevices.com 0V T1 t WPST begins T2 t WPST ends 122 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) WRITE WRITE bursts are initiated with a WRITE command. The starting COLUMN and BANK addresses are provided with the WRITE command, and AUTO PRECHARGE is selected, the ROW being accessed will be PRECHARGED at the end of WRITE burst. If AUTO PRECHARGE is not selected, the ROW will remain open for subsequent accesses. After a WRITE command has been issued, the WRITE burst may not be interrupted. For the generic WRITE commands used in Figure 76 though Figure 84, AUTO PRECHARGE is disabled. During WRITE bursts, the first valid data-in element is registered on a rising edge of DQSx following the WRITE LATENCY (WL) clocks later and subsequent data elements will be registered on successive edges of DQSx. WRITE LATENCY (WL) is defined as the sum of POSTED CAS ADDITIVE LATENCY (AL) and CAS WRITE LATENCY (CWL): WL = AL + CWL. The values of AL and CWL are programmed in the MR- and MR2 registers, respectively. Prior to the first valid DQSx edge, a full cycle is needed (including a dummy crossover of DQSx, DQSx\) and specified as the WRITE preamble shown in Figure 76. The half cycle on DQSx following the last data-in element is known as the WRITE postamble. The time between the WRITE command and the first valid edge of DQSx is WL clocks ± tDQSS. Figure 77 through Figure 84 show the nominal case where tDQSS = 0ns; however, Figure 76 includes tDQSS (MIN) and tDQSS (MAX) cases. Data may be masked from completing a WRITE using data mask. The mask occurs on the DM ball aligned to the WRITE data. If DM is LOW, the WRITE completes normally. If DM is HIGH, that bit of data is masked. Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain HIGH-Z and any additional input data will be ignored. Data for any WRITE burst may be concatenated with a subsequent WRITE command to provide a continuous flow of input data. The new WRITE command can be tCCD clocks following the previous WRITE command. The first data element from the new burst is applied after the last element of a completed burst. Figures 77 and 78 show concatenated bursts. An example of nonconsecutive WRITES is shown in Figure 79. Data for any WRITE burst may be followed by a subsequent READ command after tWTR has been met (see Figures 80, 81 and 82). Data for any WRITE burst may be followed by a subsequent PRECHARGE command providing tWR has been met, as shown in Figure 83 and Figure 84. Both tWTR and tWR starting time may vary depending on the mode register settings (fixed BC4, BL8 vs. OTF). LOGIC Devices Incorporated www.logicdevices.com 123 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 76 - WRITE BURST T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command 1 WL = AL + CWL Address 2 Bank, Col n t DQSS t DSH t DSH t DSH t DSH t WPRE t DQSS(MIN) t WPST DQS, DQS# t DQSH t DQSL t DQSH DI n DQ3 t DQSL t DQSH DI n+1 DI n+2 t DQSL t DQSH DI n+3 t DSH DI n+4 t DQSL t DQSH DI n+5 t DSH DI n+6 t DQSL DI n+7 t DSH t DSH t WPRE t DQSS(NOM) t WPST DQS, DQS# t DQSH t DQSL t DQSH t DSS DI n DQ3 t DQSL t DQSH t DQSL t DQSH t DQSL t DQSH t DQSL t DSS t DSS t DSS t DSS DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 t DQSS t WPRE t DQSS(MAX) t WPST DQS, DQS# t DQSH t DQSL t DQSH t DSS DI n DQ3 t DQSL t DQSH t DSS DI n+1 t DQSL t DQSH t DSS DI n+2 DI n+3 t DQSL t DQSH t DSS DI n+4 DI n+5 t DQSL t DSS DI n+6 DI n+7 Transitioning Data Notes: LOGIC Devices Incorporated Don ’t Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the WRITE command at T0. 3. DI n = data-in for column n. 4. BL8, WL = 5 (AL = 0, CWL = 5). 5. t DQSS must be met at each rising clock edge. 6. t WPST is usually depicted as ending at the crossing of DQS, DQS#; however, t WPST actually ends when DQS no longer drives LOW and DQS# no longer drives HIGH. www.logicdevices.com 124 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 77 - CONSECUTIVE WRITE (BL8) TO WRITE (BL8) T0 T1 WRITE NOP T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 NOP NOP WRITE NOP NOP NOP NOP NOP NOP NOP t BL = 4 clocks NOP NOP T14 C K# CK Command 1 t CCD NOP t WR t WTR Add ress 2 Valid Valid t WPST t WPRE DQS, DQS# DI n DQ3 DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 WL = 5 WL = 5 Transitioning Data Notes: Don ’t Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the WRITE commands at T0 and T4. 3. DI n (or b) = data-in for column n (or column b). 4. BL8, WL = 5 (AL = 0, CWL = 5). FIGURE 78 - CONSECUTIVE WRITE (BC4) TO WRITE (BC4) VIA MRS OR OTF T0 T1 WRITE NOP T2 T3 T4 T5 T6 T7 T8 T9 T10 NOP NOP WRITE NOP NOP NOP NOP NOP NOP T11 T12 T13 NOP NOP NOP T14 C K# CK Command 1 t CCD t BL = 4 clo cks NOP t WR t WTR Address2 Vali d Vali d t WPRE t WPST t WPRE t WPST DQS, DQS# DI n DQ3 DI n+1 DI n+2 DI n+3 DI b DI b+1 DI b+2 DI b+3 WL = 5 WL = 5 Transitioning Data Notes: LOGIC Devices Incorporated 1. 2. 3. 4. Don ’t Care NOP commands are shown for ease of illustration; other commands may be valid at these times. BC4, WL = 5 (AL = 0, CWL = 5). DI n (or b) = data-in for column n (or column b). The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and T4. www.logicdevices.com 125 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 79 - NONCONSECUTIVE WRITE TO WRITE T0 T1 T2 T3 T4 WRITE NOP NOP NOP NOP T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 NOP NOP NOP NOP NOP NOP NOP NOP C K# CK C ommand Add ress NOP WRITE Vali d NOP NOP NOP Vali d WL = C WL + AL = 7 WL = C WL + AL = 7 DQS, DQS# DI n DQ DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 DM Transitioning Data Notes: 1. 2. 3. 4. Don't Care DI n (or b) = data-in for column n (or column b). Seven subsequent elements of data-in are applied in the programmed order following DO n. Each WRITE command may be to any bank. Shown for WL = 7 (CWL = 7, AL = 0). FIGURE 80 - WRITE (BL8) TO READ (BL8) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP T11 Ta0 NOP READ CK# CK Command 1 t WTR 2 Add ress3 Vali d Vali d t WPRE t WPST DQS, DQS# DI n DQ4 DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 WL = 5 Indicates a Break in Time Scale Notes: LOGIC Devices Incorporated Transitioning Data Don ’t Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. t WTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last write data shown at T9. 3. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and MR0[12] = 1 during the WRITE command at T0. The READ command at Ta0 can be either BC4 or BL8, depending on MR0[1:0] and the A12 status at Ta0. 4. DI n = data-in for column n. 5. RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5). www.logicdevices.com 126 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A CK# CK Command 1 Add ress3 DQS, DQS# DQ 4 T0 T1 T2 T3 T4 T5 NOP T6 NOP T7 NOP T8 NOP T9 READ Ta0 t WTR 2 Don ’t Care Vali d NOP DI n+3 t WPST NOP Vali d DI n+2 NOP DI n+1 NOP t WPRE DI n NOP WL = 5 Indicates a Break in Time Scale Transitioning Data WRITE Notes: 1. NOP commands are shown for ease of illustrati on; other commands may be valid at these times. 2. t WTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last write data shown at T7. 3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0 and the READ command at Ta0. 4. DI n = data-in for column n. 5. BC4 (fixed), WL = 5 (AL = 0, CWL = 5), RL = 5 (AL = 0, CL = 5). High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 127 www.logicdevices.com LOGIC Devices Incorporated L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 81 - WRITE TO READ (BC4 MODE REGISTER SETTING) CK CK# C ommand 1 Add ress 3 DQS, DQS# DQ 4 T0 T1 T2 T3 T4 T5 T6 NOP T7 NOP T8 NOP T9 NOP T10 NOP T11 READ Tn t WTR 2 NOP t BL = 4 clo cks NOP t WPST DI n+3 RL = 5 Don ’t Care Vali d NOP DI n+2 NOP DI n+1 NOP t WPRE DI n NOP WL = 5 Indicates a Break in Time Scale Transitioning Data WRITE Vali d Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. t WTR controls the WRITE-to -READ delay to the same device and starts after t BL. 3. The BC4 OTF setting is activated by MR0[1:0] = 01 and A 12 = 0 during the WRITE command at T0 and the READ command at Tn. 4. DI n = data-in for column n. 5. BC4, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5). High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 128 www.logicdevices.com LOGIC Devices Incorporated L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 82 - WRITE (BC4 OTF) TO READ (BC4 OTF) L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 83 - WRITE (BL8) TO PRECHARGE CK# T0 T1 T2 T3 T4 T5 T6 T7 WRITE NOP NOP NOP NOP NOP NOP NOP T8 T9 T10 T11 T12 Ta0 Ta1 NOP NOP NOP NOP NOP NOP PRE CK Command Add ress Vali d Vali d t WR WL = AL + CWL DQS, DQS# DI n DQ BL8 DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 Indicates a Break in Time Scale Notes: Transitioning Data Don ’t Care 1. DI n = data-in from column n. 2. Seven subsequent elements of data-in are applie d in the programmed order following DO n. 3. Shown for WL = 7 (AL = 0, CWL = 7). FIGURE 84 - WRITE (BC4 MODE REGISTER SETTING) TO PRECHARGE CK# T0 T1 T2 T3 T4 T5 T6 T7 WRITE NOP NOP NOP NOP NOP NOP NOP T8 T9 T10 T11 T12 Ta0 Ta1 NOP NOP NOP NOP NOP NOP PRE CK Comman d Add ress Vali d Vali d t WR WL = AL + CWL DQS, DQS# DI n DQ BC4 DI n+ 1 DI n+ 2 DI n+ 3 Indicates a Break in Time Scale Notes: LOGIC Devices Incorporated Transitioning Data Don ’t Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The write recovery time ( t WR) is referenced from the first rising clock edge after the last write data is shown at T7. t WR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank. 3. The fixed BC4 setting is activated by MR0[ 1:0] = 10 during the WRITE command at T0. 4. DI n = data-in for column n. 5. BC4 (fixed), WL = 5, RL = 5. www.logicdevices.com 129 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 85 - WRITE (BC4 OTF) TO PRECHARGE T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP Tn CK# CK Command 1 PRE t WR2 Bank, Col n Add ress 3 Valid t WPST t WPRE DQS, DQS # DI n DQ4 DI n+1 DI n+2 DI n+3 WL = 5 Indicates a Break In Time Scale Notes: Transitioning Data Don ’t Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The write recovery time ( t WR) is referenced from the rising clock edge at T9. t WR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank. 3. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0. 4. DI n = data-in for column n. 5. BC4 (OTF), WL = 5, RL = 5. DQ INPUT TIMING Figure 76 shows the strobe to clock timing during a WRITE. DQSx, DQSx\ must transition within 0.25tCK of the clock transitions as limited by tDQSS. All data and data mask setup and hold timings are measured relative to the DQSx, DQSx\ crossings, not the clock crossing. memory controller after the last data is written to the SDRAM during the WRITE postamble,tWPST. Data setup and hold times are shown in Figure 86. All setup and hold times are measured from the crossing points of DQSx and DQSx\. These setup and hold values pertain to data input and data mask input. The WRITE preamble and postamble are also shown. One clock prior to data input to the SDRAM, DQSx must be HIGH and DQSx\ must be LOW. Then for a half clock, DQSx is driven LOW (DQSx\ is driven HIGH) during the WRITE preamble. tWPRE, likewise, DQSx must be kept LOW by the Additionally, the half period of the data input strobe is specified by tDQSH and tDQSL. FIGURE 86 - DATA INPUT TIMING DQ S, DQS# t WPRE t DQSH t WPST t DQSL DI b DQ DM t DS t DH Transitioning Data LOGIC Devices Incorporated www.logicdevices.com 130 Don ’t Care High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) PRECHARGE Input A10 determines whether one bank or all banks are to be PRECHARGED and in the case where only one bank is to be precharged, inputs BA[2:0] select the array BANK. When all banks are to be PRECHARGED, inputs BA[2:0] are treated as “Don’t Care”. After a bank is PRECHARGED, it is in the IDLE State and must be ACTIVATED prior to any READ or WRITE commands being issued. SELF REFRESH The SELF REFRESH command is initiated like a REFRESH command except CKE is LOW. The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled and reset upon exiting SELF REFRESH. All power supply inputs (including VREFCA and VREFDQ) must be maintained at valid levels upon entry/exit and during SELF REFRESH mode operation. VREFDQ may float or not drive VccQ/2 while in the SELF REFRESH mode under certain conditions: • Vss<VREFDQ<Vcc is maintained • VREFDQ is valid and stable prior to CKE going back HIGH • The first WRITE operation may not occur earlier than 512 clocks after VREFDQ is valid • All other SELF REFRESH mode exit timing requirements are met The SDRAM must be idle with all BANKS in the PRECHARGE state (tRP is satisfied and no bursts are in progress) before a SELF REFRESH entry command can be issued. ODT must also be turned off before SELF REFRESH entry by registering the ODT ball LOW prior to the SELF REFRESH entry command (see “On-Die Termination (ODT) for timing requirements). If RTT_NOM and RTT_WR are disabled in the mode registers, ODT can be a “Don’t Care”. After the SELF REFRESH entry command is registered, CKE must be held LOW to keep the SDRAM in SELF REFRESH mode. After the SDRAM has entered SELF REFRESH mode, all external control signals, except CKE and RESET\, become “Don’t Care”. The SDRAM initiates a minimum of one REFRESH command internally within the tCKE period when it enters SELF REFRESH mode. The requirements for entering and exiting SELF REFRESH mode depend on the state of the clock during SELF REFRESH mode. First and foremost, the clock must be stable (meeting tCK specifications) when SELF REFRESH mode is entered. If the clock remains stable and the frequency in not altered while in SELF REFRESH mode, then the SDRAM is allowed to exit SELF REFRESH after tCKESR is satisfied (CKE is allowed to transition HIGH tCKESR later than when CKE was registered LOW). Since the clock remains stable in SELF REFRESH mode (no frequency change), tCKSRE and tCKSRX are not required. However, if the clock is altered during SELF REFRESH mode, then tCKSRE and tCKSRX must be satisfied. When entering SELF REFRESH, tCKSRE must be satisfied prior to altering the clock’s frequency. Prior to exiting SELF REFRESH, tCKSRX must be satisfied prior to registering CKE HIGH. When CKE is HIGH during SELF REFRESH exit, NOP or DES must be issued for tXS time. tXS is required for the completion of any internal REFRESH that is already in progress and must be satisfied before a valid command not requiring a locked DLL can be issued to the device. tXS is also the earliest time that a SELF REFRESH re-entry may occur (see Figure 87). Before a command requiring a locked DLL can be applied, a ZQCL command must be issued. tZQOPER timing must be met and tXSDLL must be satisfied. ODT must be off during tXSDLL. LOGIC Devices Incorporated www.logicdevices.com 131 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 87 - SELF REFRESH ENTRY/EXIT TIMING T0 T1 T2 Ta0 Tb0 Tc 0 Tc1 Td0 Te0 Tf0 Vali d Vali d CK# CK t CKSRX1 t CKSRE1 t IS t IH t CPDED t IS CKE t CKESR (MIN)1 t IS ODT2 Vali d ODTL RESET# 2 Command SRE(REF)3 NOP NOP 4 SRX (NOP) NOP 5 Add ress Vali d 6 Vali d 7 Vali d Vali d t XS 6 , 9 t RP 8 t XSDLL7, 9 Enter self refresh mode (synchronous) Exit self refresh mode (asynchronous) Indicates a Break in Time Scale Notes: LOGIC Devices Incorporated Don ’t Care 1. The clock must be valid and stable meeting t CK specifications at least t CKSRE after entering self refresh mode, and at least t CKSRX prior to exiting self refresh mode, if the clock is stopped or altered between states Ta0 and Tb0. If the clock remains valid and unchanged from entry and during self refresh mode, then t CKSRE and t CKSRX do not apply; however, t CKESR must be satisfied prior to exiting at SRX. 2. ODT must be disabled and R TT off prior to entering self re fresh at state T1. If both R TT_NOM and RTT_WR are disabled in the mode registers, ODT can be a “Don’t Care.” 3. Self refresh entry (SRE) is synchronous via a REFRESH command with CKE LOW. 4. A NOP or DES command is required at T2 after the SRE command is issued prior to the inputs becoming “Don’t Care.” 5. NOP or DES commands are required prior to exiting self refresh mode until state Te0. 6. t XS is required before any commands not requiring a locked DLL. 7. t XSDLL is required before any commands requiring a locked DLL. 8. The device must be in the all banks idle state prior to entering self refresh mode. For example, all banks must be precharged, t RP must be met, and no data bursts can be in progress. 9. Self refresh exit is asynchronous; however, t XS and t XSDLL timings start at the first rising clock edge where CKE HIGH satisfies t ISXR at Tc1.t CKSRX timing is also measured so that t ISXR is satisfied at Tc1. www.logicdevices.com 132 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) EXTENDED TEMPERATURE USAGE LOGIC Devices, Inc iMOD DDR3 SDRAM module supports the optional extended temperature range up to ≤95˚C while supporting SELF REFRESH/AUTO REFRESH and support Tc temperatures >95˚C ≤125˚C with MANUAL REFRESH only. When using SELF REFRESH/AUTO REFRESH and the case temperature is >85˚C, SRT and ASR options must be used. The extended range temperature range SDRAM must be REFRESHED externally at 2X anytime the case temperature is >85˚C. The external REFRESHING requirement is accomplished by reducing the REFRESH PERIOD from 64ms to 32ms. SELF REFRESH mode requires the use of ASR or SRT to support the extended temperature. TABLE 68: SELF REFRESH TEMPERATURE AND AUTO SELF REFRESH DESCRIPTION Field MR2 Bits Self Refresh Temperature (SRT) 7 SRT Description If ASR is disabled (MR2[6]=0), SRT must be programmed to indicate tOPER during SELF REFRESH; * MR2[7] = 0: Normal operating temperature range (0˚C to ≤ 85˚C) * MR2[7] = 1: Extended operating temperature range (>85˚C to ≤ 105˚C) If ASR is enabled (MR2[7]=1), SRT must be set to 0, even if the extended temperature range is supported. *MR2[7]=0: SRT is disabled. Auto Self Refresh (ASR) 6 ASR When ASR is enabled, the SDRAM automatically provides SELF REFRESH power management functions, (refresh rate for all supported operating temperature values) *MR2[6]=1: ASR is enabled (M7 must = 0) When ASR is not enabled, the SRT bit must be programmed to indicate tOPER during SELF REFRESH operation. *MR2[6]=0: ASR is disabled, must use manual SELF REFRESH (SRT) TABLE 69: SELF REFRESH MODE SUMMARY MR2[6] (ASR) 0 0 MR2[7] (SRT) Permitted Operating Temperature Range for Self Refresh Mode SELF REFRESH Operation 0 SELF REFRESH Mode is supported in the normal temperature range. Normal (0°C to 85°C) 1 SELF REFRESH Mode is supported in normal and extended (≤ 95˚C MAX) Normal and extended (0°C to 95°C) temperature ranges; When SRT is enabled, it increases self refresh power consumption. 1 0 Self refresh mode is supported in normal and extended temperature ranges; Normal and extended (0°C to 95°C) Self refresh power consumption may be temperature-dependent. 1 1 Illegal. POWER-DOWN MODE Power-down is synchronously entered when CKE is registered LOW coincident with a NOP or DES command. CKE is not allowed to go LOW while either an MRS, MPR, ZQCAL, READ or WRITE operation is in progress. CKE is allowed to go LOW while any of the other legal operations are in progress. However, the POWER-DOWN Icc specifications are not applicable until such operations have been completed. Depending on the previous SDRAM state and the command issued prior to CKE going LOW, certain timing constraints must be satisfied (as noted in Table 70). Timing diagrams detailing the different POWER-DOWN mode entry and exits are shown in Figure 88 through Figure 97. LOGIC Devices Incorporated www.logicdevices.com 133 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 70: COMMAND TO POWER-DOWN ENTRY PARAMETERS Last Command prior to CKE Low 1 Parameter (MIN) Parameter Value Figure Idle or Active ACTIVATE tACTPDEN 1tCK Figure 95 Idle or Active PRECHARGE tPRPDEN 1tCK Figure 96 READ or READAP tRDPDEN RL = 4tCK + 1tCK Figure 91 WRITE: BL8OTF, BL8MRS, BC4OTF tWRPDEN WL + 4tCK + tWR/ tCK Figure 92 WL + 2tCK + tWR/ tCK Figure 92 WL + 4tCK + WR + 1tCK Figure 93 WL + 2tCK + WR + 1tCK Figure 93 REFRESH tREFPDEN 1tCK Figure 94 REFRESH tXPDLL Greater of 10tCK or 24ns Figure 98 MODE REGISTER SET tMRSPDEN tMOD Figure 97 SDRAM Status Active Active WRITE: BC4MRS Active WRITEAP: BL8OTF, BL8MRS, BC4OTF Active tWRAPDEN WRITEAP: BC4MRS Active Idle POWER-DOWN Idle Entering POWER-DOWN mode disables the input and output buffers, excluding CK, CK\, ODT, CKE and RESET\. NOP or DES commands are required until tCPDED has been satisfied, at which time all specified input/output buffers will be disabled. The DLL should be in a locked state when POWER-DOWN is entered for the fastest mode timing. If the DLL is not locked during the POWER-DOWN entry, the DLL must be reset after exiting POWER-DOWN for proper READ operation as well as synchronous ODT operation. During POWER-DOWN entry, if any bank remains open after all in-progress commands are complete, the SDRAM will be in ACTIVE POWER-DOWN. If all banks are closed after all in-progress commands are complete, the SDRAM will be in PRECHARGE POWER-DOWN mode or fast EXIT mode. When entering PRECHARGE POWER-DOWN, the DLL is turned off in slow exit mode or kept on in fast EXIT mode. The DLL remains on when entering ACTIVE POWER-DOWN as well. ODT has special timing constraints when slow EXIT mode, PRECHARGE POWERDOWN is enabled and entered. Refer to “Asynchronous ODT Mode” for detailed ODT usage requirements in slow EXIT mode PRECHARGE POWER-DOWN. A summary of the two POWER-DOWN modes is listed in Table 71. While in either POWER-DOWN state, CKE is held LOW, RESET\ is held HIGH, and a stable clock signal must be maintained. ODT must be in a valid state but all other input signals are a “Don’t Care”. If RESET\ goes LOW during POWER-DOWN, the SDRAM will switch out of POWER-DOWN and go into the RESET state. After CKE is registered LOW, CKE must remain LOW until tPD (MIN) has been satisfied. The maximum time allowed for POWER-DOWN duration is tPD (MAX) (9 x tREFI). The POWER-DOWN states are synchronously exited when CKE is registered HIGH (with a required NOP or DES command). CKE must be maintained HIGH until tCKE has been satisfied. A valid, executable command may be applied after POWER-DOWN EXIT LATENCY, tXP, tXPDLL have been satisfied. A summary of the POWER-DOWN modes is listed in Table 71. TABLE 71: POWER-DOWN MODES MR1[12] DLL State POWER-DOWN exit “Don’t Care” ON FAST tXP to any other valid COMMAND 1 ON FAST tXP to any other valid COMMAND SDRAM State ACTIVE (any bank open) PRECHARGE (all banks PRECHARGED) Relevant Parameters tXDLL 0 OFF SLOW tXP LOGIC Devices Incorporated www.logicdevices.com 134 to COMMANDS that require the DLL to be locked (READ, RDAP, ODT ON). to any other valid COMMAND. High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 88 - ACTIVE POWER-DOWN ENTRY AND EXIT T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 NOP NOP NOP Valid CK# CK Command t CK t CH t CL NOP Valid NOP t PD t IS CKE Address t IH t IS t IH t CKE (MIN) Valid Valid t CPDED t XP Enter power-down mode Exit power-down mode Indicates a Break in Time Scale Don’t Care FIGURE 89 - PRECHARGE POWER-DOWN (FAST-EXIT MODE) ENTRY AND EXIT T0 T1 T2 T3 T4 T5 NOP NOP Ta0 Ta1 NOP Valid CK# CK Co m m an d t CK t CH t CL NOP NOP t CPDED t CKE (MIN) t IH t IS tCKEmin CKE tCKEmin t IS t XP t PD Enter power-down mode Exit power-down mode Indicates a Break in Time Scale LOGIC Devices Incorporated www.logicdevices.com 135 Don’t Care High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 90 - PRECHARGE POWER-DOWN (SLOW-EXIT MODE) ENTRY AND EXIT T0 T1 T2 T3 T4 Ta Ta1 NOP NOP Tb CK# CK t CK Command t CH t CL NOP PRE NOP Valid 1 Valid 2 t CKE (MIN) t CPDED t XP t IS t IH CKE t IS t XPDLL t PD Enter power-down mode Exit power-down mode Indicates a Break in Time Scale Notes: Don’t Care 1. Any valid command not requiring a locked DLL. 2. Any valid command requiring a locked DLL. FIGURE 91 - POWER-DOWN ENTRY AFTER READ OR READ WITH AUTO PRECHARGE (RDAP) CK# T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 READ/ RDAP NOP NOP NOP NOP NOP NOP NOP NOP Ta7 Ta8 Ta9 Ta10 Ta11 Ta12 CK Command NOP t IS NOP t CPDED CKE Add ress Vali d t PD RL = AL + CL DQS, DQS# DQ BL8 DQ BC4 DI n DI DI n+1 n+2 DI n+3 DI n DI n+1 DI n+3 DI n+2 DI n+4 DI n+ 5 DI n+6 DI n+7 t RDPDEN Power- down or self refresh entry Indicates a Break In Time Scale LOGIC Devices Incorporated www.logicdevices.com 136 Transitionin g Data Don ’t Care High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 92 - POWER-DOWN ENTRY AFTER WRITE CK# T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Tb1 Tb2 Tb3 Tb4 CK Command NOP t IS NOP t CPDED CKE Add ress Valid t WR WL = AL + CWL t PD DQS, DQS# DQ BL8 DI n DI DI n+1 n+2 DI n+3 DQ BC4 DI n DI n+1 DI n+3 DI n+2 DI n+4 DI n+5 DI n+6 DI n+7 t WRPDEN Power- down or self refresh entry 1 Indicates A Break in Time Scale Transitioning Data Don ’t Care 1. CKE can go LOW 2 tCK earlier if BC4MRS. Notes: FIGURE 93 - POWER-DOWN ENTRY AFTER WRITE WITH AUTO PRECHARGE (WRAP) CK# T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 Tb1 Tb2 Tb3 WRAP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Tb4 CK Command t IS t CPDED CKE Add ress Vali d A10 WR1 WL = AL + CWL t PD DQS, DQS# DQ BL8 DI n DI n+1 DI n+2 DI DI n+3 n+4 DQ BC4 DI n DI n+1 DI n+2 DI n+3 DI n+5 DI n+6 DI n+7 t WRAPDEN Start internal pre char ge Power- down or self refresh entry 2 Indicates a Break in Time Scale Notes: LOGIC Devices Incorporated Transitioning Data Don ’t Care is programmed through MR0[11:9] and represents t WR (MIN)ns/ t CK rounded up to the next integer t CK. 2. CKE can go LOW 2 tCK earlier if BC4MRS. 1. t WR www.logicdevices.com 137 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 94 - REFRESH TO POWER-DOWN ENTRY T0 T1 T2 T3 NOP NOP Ta0 Ta1 Ta2 Tb0 NOP NOP Valid CK# CK t CK Command t CH t CL REFRESH t CPDED t CKE (MIN) t PD t IS CKE t XP (MIN) t REFPDEN t RFC (MIN)1 Indicates a Break In Time Scale Notes: Don’t Care 1. After CKE goes HIGH during t RFC, CKE must remain HIGH until t RFC is satisfied. FIGURE 95 - ACTIVATE TO POWER-DOWN ENTRY T0 T1 T2 T3 T4 T5 T6 T7 CK# CK Command Address t CK t CH t CL ACTIVE NOP NOP Valid t CPDED t IS t PD CKE t ACTPDEN tCKE Don’t Care LOGIC Devices Incorporated www.logicdevices.com 138 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 96 - PRECHARGE TO POWER-DOWN ENTRY T0 T1 T2 T3 NOP NOP T4 T5 T6 T7 CK# CK t CK Command t CH t CL PRE All/single bank Address t CPDED t IS t PD CKE t PREPDEN Don’t Care FIGURE 97 - MRS COMMAND TO POWER-DOWN ENTRY T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 CK# CK t CK Command MRS Address Valid t CH NOP t CL t CPDED NOP NOP NOP NOP t PD t MRSPDEN t IS CKE Indicates a Break in Time Scale LOGIC Devices Incorporated www.logicdevices.com 139 Don’t Care High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 98 - POWER-DOWN EXIT TO REFRESH TO POWER-DOWN ENTRY T0 T1 T2 T3 T4 Ta0 Ta1 Tb0 NOP REFRESH NOP NOP CK# CK Command t CK NOP t CH t CL NOP NOP t CPDED t XP1 t IH t IS CKE t IS t PD t XPDLL2 Enter power-down mode Exit power-down mode Enter power-down mode Indicates a Break in Time Scale Notes: Don’t Care 1. t XP must be satisfied before issuing the command. 2. t XPDLL must be satisfied (referenced to the registration of power-down exit) before the next power-down can be entered. RESET The RESET signal (RESET\) is an asynchronous signal that triggers any time it drops LOW and there are no restrictions about when it can go LOW. After RESET\ is driven LOW, it must remain LOW for 100ns. During this time, the outputs are disabled, ODT (RTT) turns off (HIGH-Z) and the DDR3 SDRAM resets itself. CKE should be brought LOW prior to RESET\ being driven HIGH. After RESET\ goes HIGH, the SDRAM must be re-initialized as though a normal power up were executed (see Figure 99). All refresh counters on the SDRAM are RESET and data stored in the SDRAM is assumed unknown after RESET\ has been driven LOW. LOGIC Devices Incorporated www.logicdevices.com 140 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 99 - RESET SEQUENCE System RESET (warm boot) Sta ble an d vali d clo ck T1 T0 Tc0 Tb0 Ta0 t CK Td0 CK# CK t CL t CL T (MIN) = MAX (10ns, 5 t CK) T = 100ns (MIN) RESET# t IOZ T=10ns (MIN) t IS Vali d CKE ODT Vali d Vali d Vali d Vali d ZQ CL Vali d t IS MRS MRS MRS MRS Add ress Code Code Code Code A10 Code Code Code Code BA0 = L BA1 = H BA2 = L BA0 = H BA1 = H BA2 = L BA0 = H BA1 = L BA2 = L BA0 = L BA1 = L BA2 = L Command NOP DM BA[2:0] DQS DQ RTT A10 = H Vali d Vali d High-Z High-Z High-Z t MRD t MRD t XPR T = 500μs (MIN) MR2 All voltage supplies valid and stable Vali d MR3 DRAM rea dy for external commands t MRD MR1 with DLL ENABLE t MOD MR0 with DLL RESET ZQ CAL t ZQ INIT t DLLK Normal operation Indicates a Break in Time Scale LOGIC Devices Incorporated www.logicdevices.com 141 Don ’t Care High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) ON-DIE TERMINATION (ODT) FUNCTIONAL REPRESENTATION OF ODT ODT is a feature that enables the SDRAM to enable/disable on-die termination resistance for each DQ, LDQSx, LDQSx\ , UDQSx, UDQSx\ LDMx and UDMx for the four words contained in LDI’s DDR3 iMOD. The value of RTT (ODT termination value) is determined by the settings of several mode register bits (see Table 75). The ODT ball is ignored while in SELF REFRESH mode (must be turned off prior to SELF REFRESH entry) or if mode registers MR1 and MR2 are programmed to disable ODT. ODT is comprised of nominal ODT and dynamic ODT modes and either of these can function in synchronous or asynchronous modes (when the DLL is off during PRECHARGE POWER-DOWN or when the DLL is synchronizing). Nominal ODT is the base termination and is used in any allowable ODT state. Dynamic ODT is applied only during WRITEs and provides OTF switching from no RTT or RTT_NOM to RTT_WR. The ODT feature is designed to improve signal integrity of the memory array/ sub-system by enabling the DDR3 memory controller to independently turn on or off the SDRAMS internal termination resistance for any grouping of SDRAM devices. The ODT feature is not supported during DLL disable mode. A simple functional representation of the SDRAM ODT feature is shown in Figure 100. The switch is enabled by the internal ODT control logic, which uses the external ODT ball and other control information. The actual effective termination, RTT_EFF may be different from the RTT targeted due to nonlinearity of the termination. For RTT_EFF values and calculations, see “ODT Characteristics”. FIGURE 100 - ON-DIE TERMINATION NOMINAL ODT ODT (NOM) is the base termination resistance for each applicable ball, enabled or disabled via MR1[9,6,2] (see Figure 46), and it is turned on or off via the ODT ball. ODT To other circuitry such as RCV, ... VCCQ/2 RTT Switch DQ, DQS, DQS#, DM TABLE 72: POWER-DOWN MODES MR1[9,6,2] SDRAM Termination State SDRAM State Notes 000 ODT Pin 0 RTT_NOM disabled, ODT OFF Any valid 1,2 000 1 RTT_NOM disabled, ODT ON Any valid except SELF REFRESH, READ 1,3 000-101 0 RTT_NOM enabled, ODT OFF Any valid 1,2 000-101 1 RTT_NOM enabled, ODT ON Any valid except SELF REFRESH, READ 1,3 110 and 111 X RTT_NOM reserved, ODT ON or OFF Illegal NOTES: 1. Assumes dynamic ODT is disabled. 2. ODT is enabled and active during most WRITES for proper termination, 3. ODT must be disabled during READs. The RTT_NOM value is restricted during WRITES. Dynamic ODT is applicable if enabled. but it is not illegal to have it off during WRITES. LOGIC Devices Incorporated www.logicdevices.com 142 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) NOMINAL ODT Nominal ODT resistance RTT_NOM is defined by MR1[9,6,2], as shown in Figure 46. The RTT_NOM termination value applies to the output pins previously mentioned. DDR3 SDRAM iMODs support multiple RTT_NOM values based on RZQ/n where n can be 2,4,6,8 or 12 and RZQ is 240Ω±1%. RTT_NOM termination is allowed any time after the SDRAM is initialized, calibrated and not performing READ accesses or when it is not in SELF REFRESH mode. WRITE access uses RTT_NOM id dynamic ODT (RTT_WR) is disabled. If RTT_NOM is used during WRITEs, only RZQ/2, RZQ/4 and RZQ/6 are allowed (see Table 71). ODT timings are summarized in Table 73, as well as, listed in Table 50. Examples of nominal ODT timing are shown in conjunction with the synchronous mode of operation in “Synchronous ODT Mode”. TABLE 73: ODT PARAMETER Begins at Defined to Definition for All DDR3 bins Units ODTL ON ODT synchronous turn on delay ODT registered HIGH RTT_ON ± tAON CWL + AL - 2 tCK ODTL OFF ODT synchronous turn off delay ODT registered HIGH RTT_ON ± tAOF CWL + AL - 2 tCK tAONPD ODT asynchronous on delay ODT registered HIGH RTT_ON 1-9 ns tAOFFPD ODT asynchronous on delay ODT registered HIGH RTT_OFF 1-9 ns ODT registered LOW 4TcK tCK tCK Symbol Description ODT registered HIGH or WRITE ODTH4 ODT minimum HIGH time after ODT assertion or WRITE (BC4) registration with ODT HIGH ODTH8 ODT minimum HIGH time after WRITE (BL8) WRITE registration with ODT HIGH ODT registered LOW 6TcK tAON ODT turn-on relative to ODTL on completion Completion of ODTL on RTT_ON See Table 50 ps 0.5TcK ± 0.2TcK tCK tAOF ODT turn-off relative to ODTL off completion Completion of ODTL off RTT_OFF DYNAMIC ODT In certain applications, to further enhance signal integrity on the data bus, it is desirable that the termination strength, be changed without issuing an MRS command, essentially changing the ODT termination resistance on-the-fly. With dynamic ODT (RTT_WR) enabled, the SDRAM switches from nominal ODT (RTT_NOM) to dynamic ODT when beginning a WRITE burst and subsequently switches back to nominal ODT at the completion of the WRITE burst sequence. This requirement and the supporting DYNAMIC ODT feature of the DDR3 SDRAM makes it feasible and is described in further detail below: DYNAMIC ODT FUNCTIONAL DESCRIPTION: The dynamic ODT mode is enabled if either MR2[9] or mR2[10] is set to “1”. Dynamic ODT is not supported during DLL disable mode, so RTT_WR must be disabled. The dynamic ODT function is described, as follows: • Two RTT values are available – RTT_NOM and RTT_WR: • The value of RTT_NOM is preselected via MR1[9,6,2] • The value for RTT_WR is preselected via MR2[10,9] • During SDRAM operations without READ or WRITE commands, the termination is controlled as follows: • Termination ON/OFF timing is controlled via the ODT ball and LATENCIES ODTl on and ODTL off • Nominal termination strength RTT_NOM is used • When a WRITE command (WR, WRAP, WRS4, WRS8, WRAPS4, WRAPS8) is registered and if dynamic ODT is enabled, the ODT termination is controlled as follows: • A latency of ODTLCNW after the WRITE command: termination strength RTT_NOM switches to RTT_WR • A Latency of ODTLCWN8 (for BL8, fixed or OTF) or ODTLCWN4 (for BC4, fixed or OTF) after the WRITE command: termination strength RTT_WR switches back to RTT_NOM • ON/OFF termination timing is controlled via the ODT ball and determined by ODTL on, ODTL off, ODTH4 and ODTH8. • During the tADC transition window, the value of RTT is undefined ODT is constrained during WRITEs and when dynamic ODT is enabled (see Table 74). LOGIC Devices Incorporated www.logicdevices.com 143 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 74: DYNAMIC ODT SPECIFIC PARAMETERS Symbol Description Begins at Defined to Definition for All DDR3 bins Units ODTLCNW Change from RTT_NOM to RTT_WR WRITE registration RTT switched from RTT_NOM to RTT_WR WL - 2 tCK ODTLCWN4 Change from RTT_WR to RTT_NOM (BC4) WRITE registration RTT switched from RTT_WR to RTT_NOM 4tCK + ODTL OFF tCK 6tCK tCK ODTLCWN8 Change from RTT_WR to RTT_NOM (BL8) WRITE registration RTT switched from RTT_WR to RTT_NOM tADC RTT change skew ODTLCNW RTT trans complete + ODTL OFF 0.5tCK ± 0.2tCK tCK TABLE 75: MODE REGISTERS FOR RTT_NOM M9 MR1(RTT_NOM) M6 0 0 0 0 0 0 M2 RTT_NOM (RZQ) RTT_NOM(Ohms) RTT_NOM Mode Restriction 0 Off Off n/a 1 RZQ/4 60 SELF REFRESH 1 0 RZQ/2 120 1 1 RZQ/6 40 1 0 0 RZQ/12 20 1 0 1 RZQ/8 30 1 1 0 Reserved Reserved n/a 1 1 1 Reserved Reserved n/a SELF REFRESH, WRITE TABLE 76: MODE REGISTERS FOR RTT_WR MR1(RTT_NOM) M10 M2 0 0 0 1 1 0 RZQ/2 120 1 1 Reserved Reserved n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a RTT_NOM (RZQ) RTT_NOM(Ohms) Dynamic ODT OFF: WRITE does not affect RTT_NOM 60 RZQ/4 TABLE 77: TIMING DIAGRAMS FOR DYNAMIC ODT Figure Title Dynamic ODT: ODT asserted before and after the WRITE, BC4 Figure 101 Figure 102 Dynamic ODT: Without WRITE command Figure 103 Dynamic ODT: ODT pin asserted together with WRITE command for 6 CK cycles, BL8 Figure 104 Dynamic ODT: ODT pin asserted with WRITE command for 6 CK cycles, BC4 Figure 105 Dynamic ODT: ODT pin asserted with WRITE command for 4 CK cycles, BC4 LOGIC Devices Incorporated www.logicdevices.com 144 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 101 - DYNAMIC ODT: ODT ASSERTED BEFORE AND AFTER THE WRITE, BC4 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 NOP NOP NOP NOP WRS4 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command Add ress Vali d ODTH4 ODTL off ODTH4 ODT ODTLCWN 4 ODTL on t ADC (MIN) t AON (MIN) RTT RTT_NOM t AON (MAX) t ADC (MIN) t AOF (MIN) RTT_WR RTT_NOM t AOF (MAX) t ADC (MAX) t ADC (MAX) ODTLCNW DQS, DQS# DQ DI n WL DI n +1 DI n +2 DI n +3 Transitioning Notes: Don ’t Care 1. Via MRS or OTF. AL = 0, CWL = 5. RTT_NOM and RTT_WR are enabled. 2. ODTH4 applies to first registering ODT HIGH and then to the registration of the WRITE command. In this example, ODTH4 is satisfied if ODT goes LOW at T8 (four clocks after the WRITE command). FIGURE 102 - DYNAMIC ODT: WITHOUT WRITE COMMAND CK# CK Command T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 Vali d Vali d Vali d Vali d Vali d Vali d Vali d Vali d Vali d Vali d Vali d Vali d Add ress ODTH4 ODTL on ODTL off ODT t AON (MAX) t AOF (MIN) RTT_NOM RTT t AOF (MAX) t AON (MIN) DQS, DQS# DQ Transitionin g Notes: LOGIC Devices Incorporated Don ’t Care 1. AL = 0, CWL = 5. RTT_NOM is enabled and R TT_WR is either enabled or disabled. 2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW; in this example, ODTH4 is satisfied. ODT registered LOW at T5 is also legal. www.logicdevices.com 145 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 103 - DYNAMIC ODT: ODT PIN ASSERTED TOGETHER WITH WRITE COMMAND FOR 6 CLOCK CYCLES, BL8 T0 T1 T2 NOP WRS8 NOP T3 T4 T5 T6 T7 T8 T9 T10 T11 NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command ODTLCNW Vali d Add ress ODTH8 ODTLOFF ODTLON ODT t ADC (MAX) t AOF (MIN) RTT_WR RTT t AON (MIN) t AOF (MAX) ODTLCWN 8 DQS, DQS# WL DI b DQ DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+7 DI b+6 Transitioning Notes: Don ’t Care 1. Via MRS or OTF; AL = 0, CWL = 5. If RTT_NOM can be either enabled or disabled, ODT can be HIGH. RTT_WR is enabled. 2. In this example, ODTH8 = 6 is satisfied exactly. FIGURE 104 - DYNAMIC ODT: ODT PIN ASSERTED WITH WRITE COMMAND FOR 6 CLOCK CYCLES, BC4 T0 T1 T2 NOP WRS4 NOP T3 T4 T5 T6 NOP NOP NOP NOP T7 T8 T9 T10 T11 NOP NOP NOP NOP NOP CK# CK Command ODTLCNW Address Vali d ODTH4 ODTL off ODT ODTL on t ADC (MAX) RTT t AOF (MIN) t ADC (MIN) RTT_WR RTT_NOM t AON (MIN) t ADC (MAX) t AOF (MAX) ODTLCWN 4 DQS, DQS# DI n DQ DI n+1 DI n+2 DI n+3 WL Transitioning Notes: LOGIC Devices Incorporated Don ’t Care 1. Via MRS or OTF. AL = 0, CWL = 5. RTT_NOM and RTT_WR are enabled. 2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW, so in this example, ODTH4 is satisfied. ODT registered LOW at T5 is also legal. www.logicdevices.com 146 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 105 - DYNAMIC ODT: ODT PIN ASSERTED WITH WRITE COMMAND FOR 4 CLOCK CYCLES, BC4 T0 T1 T2 NOP WRS4 NOP T3 T4 T5 T6 T7 T8 T9 T10 T11 NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command ODTLCNW Add ress Valid ODTL off ODTH4 ODT t AOF (MIN) t ADC (MAX) ODTL on RTT R_TTWR _WR RTT t AON (MIN) t AOF (MAX) ODTLCWN 4 DQS, DQS# WL DI n DQ DI n+1 DI n+2 DI n+3 Transitioning Notes: 1. Via MRS or OTF. AL = 0, CWL = 5. RTT_NOM can be either enabled or disabled. If disabled, ODT can remain HIGH. RTT_WR is enabled. 2. In this example ODTH4 = 4 is satisfied exactly. SYNCHRONOUS ODT MODE ODT LATENCY AND POSTED ODT Synchronous ODT is selected whenever the DLL is turned on and locked while RTT_NOM or RTT_WR is enabled. Based on the POWER-DOWN definition, these modes are: In synchronous ODT mode, RTT turns on ODTL on clock cycles after ODT is sampled HIGH by a rising clock edge and turns off ODTL off clock cycles after ODT is registered LOW by a rising clock edge. The actual on/off times varies by tAON and tAOF around each clock edge (see Table 78). The ODT LATENCY is tied to the WRITE LATENCY (WL) by ODTL on =WL-2 and ODTL off = WL- 2. • Any bank ACTIVE with CKE HIGH • REFRESH mode with CKE HIGH • DLE mode with CKE HIGH • ACTIVE POWER-DOWN mode (regardless of MR0[12]) • PRECHARGE POWER-DOWN mode if DLL is enabled during PRECHARGE POWER-DOWN by MR0[12] LOGIC Devices Incorporated Don ’t Care www.logicdevices.com Since WRITE LATENCY is made up of CAS WRITE LATENCY (CWL) and ADDITIVE LATENCY (AL), the AL value programmed into the mode register MR1[4,3], also applies to the ODT signal. The SDRAM’s internal ODT signal is delayed a number of clock cycles defined by the AL relative to the external ODT signal. Thus, ODTL on = CWL + AL – 2 and ODTL off = CWL + AL – 2. 147 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) SYNCHRONOUS ODT TIMING PARAMETERS Synchronous ODT mode uses the following timing parameters: ODTL on, ODTL off, ODTH4, ODTH8, tAON and tAOF (see Table 78 and Figure 106). The minimum RTT turn-on time (tAON [MIN]) is the point at which the device leaves HIGH-A and ODT resistance begins to turn on. Maximum RTT turn-on time (tAON [MAX]) is the point at which ODT resistance is fully on. Both are measured relative to ODTL on. The minimum RTT turn-off time (tAOF [min]) is the point at which the device starts to turn-off ODT resistance. Maximum RTT turn-off time (tAOF [MAX]) is the point at which ODT has reached HIGH-Z. Both are measured from ODTL off. When ODT is asserted, it must remain HIGH until ODTH4 is satisfied. If a WRITE command is registered by the SDRAM with ODT HIGH, then ODT must remain HIGH until ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (see Figure 107). ODTH4 and ODTH8 are measured from ODT registered HIGH to ODT registered LOW or from the registration of a WRITE command until ODT is registered LOW. TABLE 78: SYNCHRONOUS ODT PARAMETERS Symbol Description Begins at Defined to Definition for All DDR3 bins Units ODTL ON ODT synchronous TURN-ON delay ODT registered HIGH RTT_ON ± tAON CWL + AL - 2 tCK ODTL OFF ODT synchronous TURN-OFF delay ODT registered HIGH RTT_OFF ± tAOF CWL + AL - 2 tCK ODT registered LOW 4tcK tCK ODT registered HIGH, or WRITE ODTH4 ODT Minimum HIGH time after ODT assertion or WRITE (BC4) registration with ODT HIGH ODTH8 ODT Minimum HIGH time after WRITE registration with ODT HIGH ODT registered LOW 6tcK tCK tAON ODT TURN-ON relative to ODTL on Completion of ODTL on RTT_ON See Table 50 ps tAOF ODT TURN-OFF relative to ODTL off Completion of ODTL off RTT_OFF 0.5tcK ± 0.2tcK tCK WRITE (BL8) completion completion FIGURE 106 - SYNCHRONOUS ODT T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CK# CK CKE AL = 3 CWL - AL = 3 ODT ODTH4 (MIN) ODTL off = CWL + AL - 2 ODTL on = CWL + AL - 2 t AON (MIN) RTT RTT_NOM t AON (MAX) Notes: LOGIC Devices Incorporated 1. AL = 3; CWL = 5; ODTL on = WL = 6.0; ODTL off = WL - 2 = 6. R TT_NOM is enabled. www.logicdevices.com 148 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 107 - SYNCHRONOUS ODT (BC4) T0 T1 T2 NOP NOP NOP T3 T4 T5 T6 T7 NOP NOP NOP WRS4 T8 T9 T10 NOP NOP NOP T11 T12 T13 T14 T15 T16 T17 NOP NOP NOP NOP NOP NOP CK# CK CKE Command NOP NOP ODTH4 (MIN) ODTH4 ODTH4 ODT ODTLoff = WL - 2 ODTL off = WL - 2 ODTL on = WL - 2 ODTL on = WL - 2 t AON (MIN) RTT t AON (MAX) t AOF (MIN) t AOF (MIN) RTT_NOM RTT_NOM t AOF (MAX) t AON (MAX) t AON (MIN) t AOF (MAX) Transitioning Notes: Don ’t Care 1. 2. 3. 4. WL = 7. RTT_NOM is enabled. R TT_WR is disabled. ODT must be held HIGH for at least ODTH4 after assertion (T1). ODT must be kept HIGH ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (T7). ODTH is measured from ODT first registered HIGH to ODT first registered LOW or from the registration of the WRITE command with ODT HIGH to ODT registered LOW. 5. Although ODTH4 is satisfied from ODT registered HIGH at T6, ODT must not go LOW before T11 as ODTH4 must also be satisfied from the registration of the WRITE command at T7. ODT OFF DURING READS As the DDR3 SDRAM cannot terminate and drive at the same time, RTT must be disabled at least one-half clock cycle before the READ preamble by driving the ODT ball LOW. RTT may not be enabled until the end of the postamble as shown in Figure 108. FIGURE 108 - ODT DURING READS T0 T1 T2 T3 T4 T5 T6 Command READ NOP NOP NOP NOP NOP NOP Add ress Vali d T7 T8 T9 T10 T11 T12 T13 T14 T15 NOP NOP NOP NOP NOP NOP NOP NOP T16 T17 NOP NOP CK# CK NOP ODTL on = CWL + AL - 2 ODTL off = CWL + AL - 2 ODT t AOF (MIN) RTT RTT_NOM RTT_NOM t AOF (MAX) RL = AL + CL t AON (MAX) DQS, DQS# DQ DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 Transitioning Notes: LOGIC Devices Incorporated Don ’t Care 1. ODT must be disabled externally during READs by driving ODT LOW. For example, CL = 6; AL = CL - 1 = 5; RL = AL + CL = 11; CWL = 5; ODTL on = CWL + AL - 2 = 8; ODTL off = CWL + AL - 2 = 8. RTT_NOM is enabled. R TT_WR is a “Don’t Care.” www.logicdevices.com 149 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) ASYNCHRONOUS ODT MODE Asynchronous ODT mode is available when the SDRAM runs in DLL ON mode and when either RTT_NOM or RTT_WR is enabled; however, the DLL is temporarily turned off in PRECHARGED POWER-DOWN standby via MR0[12]. Additionally, ODT operates asynchronously when the DLL is synchronizing after being RESET. See “POWER-DOWN MODE” for definition and guidance over POWER-DOWN details. In asynchronous ODT timing mode, the internal ODT command is not delayed by AL relative to the external ODT command. In asynchronous ODT mode, ODT controls RTT by analog time. The timing parameters tAONPD and tAOFPD (see Table 79) replace ODTL on/tAON and ODTL off/tAOF respectively, when ODT operates asynchronously (see Figure 109). The minimum RTT turn-on time (tAONPD [MIN]) is the point at which the device termination circuit leaves HIGH-Z and ODT resistance begins to turn-on. Maximum RTT turn-on time (tAONPD [MAX]) is the point at which ODT resistance is fully on. tAONPD (MIN) and tAONPD (MAX) are measured from ODT being sampled HIGH. The minimum RTT turn-off time (tAOFPD [MIN]) is the point at which the device termination circuit starts to turn off ODT resistance. Maximum RTT turn-off time (tAOFPD [MAX]) is the point at which ODT has reached HIGH-Z. tAOFPD (MIN) and tAOFPD (MAX) are measured from ODT being sampled LOW. FIGURE 109 - ASYNCHRONOUS ODT TIMING WITH FAST ODT TRANSITION T0 T1 T2 T3 T4 T5 T6 T7 T8 T10 T9 T11 T12 T13 T14 T15 T16 T17 CK# CK CKE t IH t IS t IH t IS ODT t AOFPD (MIN) t AONPD (MIN) RTT RTT_NOM t AONPD (MAX) t AOFPD (MAX) Transitioning Notes: Don ’t Care 1. AL is ignored. TABLE 79: ASYNCHRONOUS ODT TIMING PARAMETERS FOR ALL SPEED BINS Symbol MIN MAX Units tAON PD Asynchronous RTT TURN-ON delay (POWER-DOWN with DLL off) 2 8.5 ns tAOF PD Asynchronous RTT TURN-OFF delay (POWER-DOWN with DLL off) 2 8.5 ns LOGIC Devices Incorporated Description www.logicdevices.com 150 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) SYNCHRONOUS TO ASYNCHRONOUS ODT MODE TRANSITION (POWER-DOWN ENTRY) There is a transition period around POWER-DOWN ENTRY (PDE) where the SDRAM’s ODT may exhibit either synchronous or asynchronous behavior. This transition period occurs if the DLL is selected to be off when in PRECHARGE POWER-DOWN mode by the setting of MR0[12] = 0. POWER-DOWN entry begins tANPD prior to CKE first being registered LOW and it ends when CLE is first registered LOW. tANPD is equal to the greater of ODTL off + 1tCK or ODTL on + 1tCK. If a REFRESH command has been issued, and it is in progress when CKE goes LOW, POWER-DOWN entry will end tRFC after the REFRESH command rather than when CKE is first registered LOW. POWER-DOWN ENTRY will then become the greater of tANPD and tRFC – REFRESH command to CKE registered LOW. ODT assertion during POWER-DOWN ENTRY results in an RTT change as early as the lesser of tAONPD (MIN) and ODTL on x tCK + tAON (MIN) or as late as the greater of tAONPD (MAX) and ODTL on x tCK + tAON (MAX). ODT de-assertion during POWER-DOWN ENTRY may result in an RTT change as early as the lesser of tAOFPD (MIN) and ODTL off x tCK + tAOF (MIN) or as late as the greater of tAOFPD (MAX) and ODTL off x tCK + tAOF (MAX). Table 80 summarizes these parameters. If the AL has a large value, the uncertainty of the state of RTT becomes quite large. This is because ODTL on and ODTL off are derived from the WL and WL is equal to CWL + AL. Figure 110 shows three different cases; • ODT_A: Synchronous behavior before tANPD • ODT_B: ODT state changes during the transition period with tAONPD (MIN) less than ODTL on x tCK + tAON (MIN) and tAONPD (MAX) greater than ODTL on x tCK + tAON (MAX) • ODT_C: ODT state changes after the transition period with asynchronous behavior TABLE 80: ODT PARAMETERS FOR POWER-DOWN (DLL OFF) ENTRY AND EXIT TRANSITION PERIOD Description MIN tAN POWER-DOWN entry transition (POWER-DOWN exit) ODT to RTT TURN-ON delay (ODTL on = WL - 2) ODT to RTT TURN-OFF delay (ODTL off = WL - 2) tAN LOGIC Devices Incorporated PD + tXPDLL Lesser of: tANPD (MIN) [1ns] or Lesser of: tANPD (MIN) [1ns] or ODL on x tCK + tAON (MIN) ODL on x tCK + tAON (MIN) Lesser of: tAOFPD (MIN) [1ns] or Lesser of: tAOFPD (MIN) [1ns] or ODL off x tCK + tAOF (MIN) ODL off x tCK + tAOF (MIN) WL - 1 (Greater of ODTL off + 1 or ODTL on + 1) PD www.logicdevices.com MAX Greater of: tANPD or tRFC - REFRESH to CKE LOW POWER-DOWN entry transition period (POWER-DOWN entry) 151 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 110 - SYNCHRONOUS TO ASYNCHRONOUS TRANSITION DURING PRECHARGE POWER-DOWN (DLL OFF) ENTRY T0 T1 T2 T3 T4 NOP REF NOP NOP NOP T5 T6 T7 T8 T9 T10 T11 T12 T13 Ta0 Ta1 Ta2 Ta3 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK CKE Command t RFC (MIN) t ANPD PDE transition period ODT A synchronous DRAM RTT A synchronous t AOF (MIN) RTT_NOM ODTL off ODTL off + t AOFPD (MIN) t AOF (MAX) t AOFPD (MAX) ODT B asynchronous or synchronous DRAM RTT B asynchronous or synchronous t AOFPD (MIN) RTT_NOM ODTL off + t AOFPD (MAX) ODT C asynchronous t AOFPD (MIN) DRAM RTT C asynchronous RTT_NOM t AOFPD (MAX) Indicates a Break In Time Scale Notes: Transitioning Don ’t Care 1. AL = 0; CWL = 5; ODTL off = WL - 2 = 3. ASYNCHRONOUS TO SYNCHRONOUS ODT MODE TRANSITION (POWER-DOWN EXIT) The SDRAM’s ODT may exhibit either asynchronous or synchronous behavior during POWER-DOWN EXIT (PDX). This transition period occurs if the DLL is selected to be off when in PRECHARGE POWER-DOWN mode by setting MR0[12] to “0”. POWER-DOWN exit begins tANPD prior to CKE first being registered HIGH and it ends tXPDLL after CKE is first registered HIGH. tANPD is equal to the greater of ODTL off + 1tCK or ODTL on + 1tCK. The transition period is tANPD plus tXPDLL. ODT assertion during POWER-DOWN exit results in an RTT change as early as the lesser of tAONPD (MIN) and ODTL on x tCK + tAON (MIN) or as late as the greater of tAONPD (MAX) and ODTL on x tCK + tAON (MAX). ODT de-assertion during POWER-DOWN EXIT may result in an RTT change as early as the lesser of tAOFPD (MIN) and OFTL off x tCK + tAOF (MIN) or as late as the greater of tAOFPD (MAX) and ODTL off x tCK + tAOF (MAX). Table 80 summarizes these parameters. If the AL has a large value, the uncertainty of the RTT state becomes quite large. This is because ODTL on and ODTL off are derived from the WL, and the WL is equal to CWL + AL. Figure 111 shows three different cases. • ODT C: Asynchronous behavior before tANPD • ODT B: ODT state changes during the transition period with tAOFPD (MIN) less than ODTL off x tCK + tAOF (MIN) and ODTL off x tCK + tAOF (MAX) greater than tAOFPD (MAX) • ODT A: ODT state changes after the transition period with synchronous response LOGIC Devices Incorporated www.logicdevices.com 152 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A CK# CK CKE COMMAND ODT A asynchronous DRAM RTT A asynchronous ODT B asynchronous or synchronous RTT B asynchronous or synchronous ODT C synchronous DRAM RTT C synchronous T0 RTT_NOM T1 T2 t ANPD t AOFPD (MIN) t AOFPD (MAX) RTT_NOM Ta0 Ta1 Ta2 Ta3 Ta4 NOP Ta5 NOP Ta 6 NOP T b0 NOP Tb1 NOP Tb2 NOP Tc0 NOP Tc1 NOP Tc2 NOP Td0 NOP Td1 t XPDLL NOP Don ’t Care t AOF (MIN) t AOF (MAX) NOP Transitioning ODTL off NOP t AOFPD (MAX) ODTL off + t AOF (MIN) PDX transition period t AOFPD (MIN) ODTL off + t AOF (MAX) RTT_NOM 1. CL = 6; AL = CL - 1; CWL = 5; ODTL off = WL - 2 = 8. Indicates A Break in Time Scale NOP Notes: High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A 153 www.logicdevices.com LOGIC Devices Incorporated L9D340G64BG2 PRELIMINARY INFORMATION 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 111 - ASYNCHRONOUS TO SYNCHRONOUS TRANSITION DURING PRECHARGE POWER-DOWN (DLL OFF) EXIT PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) ASYNCHRONOUS TO SYNCHRONOUS ODT MODE TRANSITION (SHORT CKE PULSE) If the time in the PRECHARGE POWER DOWN or IDLE states is very short (short CKE LOW pules), the POWER-DOWN ENTRY and POWER-DOWN EXIT transition periods will overlap. When overlap occurs, the response of the SDRAM’s RTT to a change in the ODT state may be synchronous or asynchronous from the start of the POWER-DOWN ENTRY transition period to the end of the POWER-DOWN EXIT transition period even if the ENTRY period ends later than the EXIT period. (see Figure 112). If the time in the idle state is very short (short CKE HIGH pulse), the POWER-DOWN EXIT and POWER-DOWN ENTRY transition periods overlap. When this overlap occurs, the response of the SDRAM’s RTT to a change in the ODT state may be synchronous or asynchronous from the start of the POWER-DOWN EXIT transition period to the end of the POWER-DOWN ENTRY transition period (see Figure 113). FIGURE 112 - TRANSITION PERIOD FOR SHORT CKE LOW CYCLES WITH ENTRY AND EXIT PERIOD OVERLAPPING T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Ta0 Ta1 Ta2 Ta3 Ta4 REF NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command CKE PDE transition period t ANPD t RFC(MIN) PDX transition perio d t XPDLL t ANPD Short CKE LOW transition period (RTT chan ge asynchronous or syn chronous) Indicates a Break in Time Scale Notes: Transitionin g Don ’t Care 1. AL = 0, WL = 5, t ANPD = 4. FIGURE 113 - TRANSITION PERIOD FOR SHORT CKE HIGH CYCLES WITH ENTRY AND EXIT PERIOD OVERLAPPING T0 T1 T2 T3 T4 T5 T6 NOP NOP N NOP OP NOP NOP NOP NOP T7 T8 T9 NOP NOP NOP Ta0 Ta1 Ta2 Ta3 Ta4 NOP NOP NOP NOP NOP CK# CK Command CKE t ANPD t XPDLL t ANPD Short CKE HIGH transition period (R TT chan ge asynchronous or synchonous) Indicates A Break in Time Scale Notes: LOGIC Devices Incorporated www.logicdevices.com Transitionin g Don ’t Care 1. AL = 0, WL = 5, t ANPD = 4. 154 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A PRELIMINARY INFORMATION L9D340G64BG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) REVISION HISTORY Revision A Engineer Issue Date Description Of Change DH/JM 05.19.2009 INITIATE LOGIC Devices Incorporated reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. LOGIC Devices does not assume any liability arising out of the application or use of any product or circuit described herein. In no event shall any liability exceed the product purchase price. Products of LOGIC Devices are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with LOGIC Devices. Furthermore, LOGIC Devices does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. LOGIC Devices Incorporated www.logicdevices.com 155 High Performance, Integrated Memory Module Product May 19, 2009 LDS-L9D340G6BG2-A