7540 Group REJ03B0011-0400 Rev.4.00 Jun 21, 2004 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 7540 Group is the 8-bit microcomputer based on the 740 family core technology. The 7540 Group has a serial I/O, 8-bit timers, a 16-bit timer, and an A/D converter, and is useful for control of home electric appliances and office automation equipment. FEATURES • • • • • • • • • • • • • • Basic machine-language instructions ...................................... 71 The minimum instruction execution time ......................... 0.34 µs (at 6 MHz oscillation frequency, double-speed mode for the shortest instruction) Memory size ROM ............................................ 8 K to 32 K bytes RAM ............................................. 384 to 768 bytes Programmable I/O ports ....................... 29 (25 in 32-pin version) Interrupts ................................................. 15 sources, 15 vectors ................................. (14 sources, 14 vectors for 32-pin version) Timers ............................................................................. 8-bit ✕ 4 ...................................................................................... 16-bit ✕ 1 Serial I/O1 ................... 8-bit ✕ 1 (UART or Clock-synchronized) Serial I/O2 (Note 1) ..................... 8-bit ✕ 1 (Clock-synchronized) A/D converter ............................................... 10-bit ✕ 8 channels .................................................... (6 channels for 32-pin version) Clock generating circuit ............................................. Built-in type (low-power dissipation by an on-chip oscillator enabled) (connect to external ceramic resonator or quartz-crystal oscillator permitting RC oscillation) Watchdog timer ............................................................ 16-bit ✕ 1 Power source voltage XIN oscillation frequency at ceramic oscillation, in double-speed mode At 6 MHz .................................................................... 4.5 to 5.5 V XIN oscillation frequency at ceramic oscillation, in high-speed mode At 8 MHz .................................................................... 4.0 to 5.5 V At 4 MHz .................................................................... 2.4 to 5.5 V At 2 MHz .................................................................... 2.2 to 5.5 V XIN oscillation frequency at RC oscillation in high-speed mode or middle-speed mode At 4 MHz .................................................................... 4.0 to 5.5 V At 2 MHz .................................................................... 2.4 to 5.5 V At 1 MHz .................................................................... 2.2 to 5.5 V Power dissipation Mask ROM version ....................................... 22.5 mW (standard) One Time PROM version ................................ 30 mW (standard) Operating temperature range ................................... –20 to 85 °C (–40 to 85 °C for extended operating temperature version) (–40 to 125 °C for extended operating temperature 125 °C version (Note 2)) Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 1 of 82 APPLICATION Office automation equipment, factory automation equipment, home electric appliances, consumer electronics, car, etc. Notes 1: Serial I/O2 can be used in the following cases; (1) Serial I/O1 is not used, (2) Serial I/O1 is used as UART and BRG output divided by 16 is selected as the synchronized clock. 2: In this version, the operating temperature range and total time are limited as follows; 55 °C to 85 °C: within total 6000 hours, 85 °C to 125 °C: within total 1000 hours. 7540 Group P07 P10/RXD1 P11/TXD1 P12/SCLK1/SCLK2 P13/SRDY1/SDATA2 P14/CNTR0 P20/AN0 P21/AN1 25 26 27 28 29 30 31 18 17 20 19 22 21 23 24 P06 P05 P04 P03/TXOUT P02/TZOUT P01/TYOUT P00/CNTR1 P37/INT0 PIN CONFIGURATION (TOP VIEW) M37540Mx-XXXGP M37540MxT-XXXGP M37540MxV-XXXGP M37540ExGP M37540E8T-XXXGP M37540E8V-XXXGP 16 15 14 13 12 11 10 9 7 8 6 5 4 3 2 P22/AN2 P23/AN3 P24/AN4 P25/AN5 VREF RESET CNVSS VCC 1 32 P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0) VSS XOUT XIN Package type: 32P6U-A Fig. 1 Pin configuration (32P6U-A type) 1 36 2 35 3 34 4 5 6 7 8 9 10 11 12 13 M37540Mx-XXXFP M37540MxT-XXXFP M37540MxV-XXXFP M37540E8FP M37540E8T-XXXFP M37540E8V-XXXFP P12/SCLK1/SCLK2 P13/SRDY1/SDATA2 P14/CNTR0 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 VREF RESET CNVSS Vcc XIN XOUT VSS 33 32 31 30 29 28 27 26 25 24 14 23 15 22 16 21 17 20 18 19 Package type: 36P2R-A Fig. 2 Pin configuration (36P2R-A type) Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 2 of 82 P11/TXD1 P10/RXD1 P07 P06 P05 P04 P03/TXOUT P02/TZOUT P01/TYOUT P00/CNTR1 P37/INT0 P36(LED6)/INT1 P35(LED5) P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0) 7540 Group P12/SCLK1/SCLK2 P13/SRDY1/SDATA2 P14/CNTR0 1 32 P11/TXD1 3 30 P10/RXD1 P07 P20/AN0 4 29 P06 P21/AN1 P22/AN2 5 28 P23/AN3 P24/AN4 7 P05 P04 P03/TXOUT P02/TZOUT P25/AN5 VREF 9 6 8 M37540Mx-XXXSP M37540ExSP 2 31 27 26 25 23 P01/TYOUT P00/CNTR1 22 P37/INT0 21 P34(LED4) 13 20 14 14 19 P33(LED3) P32(LED2) XOUT 15 18 P31(LED1) VSS 16 17 P30(LED0) 10 RESET CNVSS VCC XIN 11 12 24 Package type: 32P4B Fig. 3 Pin configuration (32P4B-A type) 1 42 2 41 3 40 4 39 5 38 6 37 7 36 8 9 10 11 12 13 14 15 M37540RSS P14/CNTR0 NC NC P20/AN0 P21/AN1 NC P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 NC NC VREF RESET CNVSS Vcc XIN XOUT VSS Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 3 of 82 33 32 31 30 29 28 16 27 17 26 18 25 19 24 20 23 21 22 Outline 42S1M Fig. 4 Pin configuration (42S1M type) 35 34 P13/SRDY1/SDATA2 P12/SCLK1/SCLK2 P11/TXD1 P10/RXD1 P07 P06 P05 P04 P03/TXOUT P02/TZOUT P01/TYOUT P00/CNTR1 NC P37/INT0 P36(LED6)/INT1 P35(LED5) P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0) Fig. 5 Functional block diagram (32P6U package) Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 4 of 82 VREF 5 A/D converter (10) Watchdog timer Reset Clock generating circuit T 10 0 PC H I/O port P2 4 3 2 1 32 31 17 16 15 14 13 12 I/O port P3 P2(6) INT0 ROM P3(6) RAM A PS PC L S Y X SI/O1(8) CPU 8 11 SI/O2(8) P1(5) INT0 I/O port P1 30 29 28 27 26 6 RESET 9 Reset input VCC X IN X OU VSS Clock input Clock output P0(8) TZOUT I/O port P0 25 24 23 22 21 20 19 18 CNTR1 Timer A (16) Timer Z (8) TYOUT TXOUT Timer Y (8) Prescaler Y (8) Prescaler Z (8) Timer X (8) CNTR0 Timer 1 (8) Prescaler X (8) Prescaler 1 (8) 7 CNVSS Key-on wakeup FUNCTIONAL BLOCK DIAGRAM (Package: 32P6U) 7540 Group FUNCTIONAL BLOCK Fig. 6 Functional block diagram (36P2R package) Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 5 of 82 17 VREF 12 A/D converter (10) Watchdog timer Reset Clock generating circuit 16 Clock input Clock output X IN X OUT 0 PCH I/O port P2 11 10 9 8 7 6 5 4 26 25 24 23 22 21 20 19 I/O port P3 P2(8) INT0 INT1 ROM P3(8) RAM 15 18 PS PCL S Y X A SI/O1(8) CPU VCC VSS SI/O2(8) P1(5) INT0 I/O port P1 3 2 1 36 35 13 Reset input RESET I/O port P0 34 33 32 31 30 29 28 27 P0(8) CNTR1 TYOUT TZOUT Timer Z (8) Timer A (16) Prescaler Z (8) Timer Y (8) TXOUT Prescaler Y (8) Timer X (8) CNTR0 Timer 1 (8) Prescaler X (8) Prescaler 1 (8) 14 CNVSS Key-on wakeup FUNCTIONAL BLOCK DIAGRAM (Package: 36P2R) 7540 Group Fig. 7 Functional block diagram (32P4B package) Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 6 of 82 15 Clock output X OUT VREF 10 A/D converter (10) Watchdog timer Reset Clock generating circuit 14 Clock input X IN 0 PCH I/O port P2 9 8 7 6 5 4 22 21 20 19 18 17 I/O port P3 P2(6) INT0 ROM P3(6) RAM 13 16 PS PCL S Y X A SI/O1(8) CPU VCC VSS SI/O2(8) P1(5) INT0 I/O port P1 3 2 1 32 31 11 Reset input RESET I/O port P0 TYOUT TZOUT Timer Z (8) 30 29 28 27 26 25 24 23 P0(8) CNTR1 Timer A (16) Prescaler Z (8) Timer Y (8) TXOUT Prescaler Y (8) Timer X (8) CNTR0 Timer 1 (8) Prescaler X (8) Prescaler 1 (8) 12 CNVSS Key-on wakeup FUNCTIONAL BLOCK DIAGRAM (Package: 32P4B) 7540 Group 7540 Group PIN DESCRIPTION Table 1 Pin description Pin Name Vcc, Vss Power source (Note 1) VREF Analog reference voltage CNVss CNVss RESET Reset input XIN Clock input XOUT Clock output P00/CNTR1 P01/TYOUT P02/TZOUT P03/TXOUT P04–P07 I/O port P0 P10/RxD1 I/O port P1 P11/TxD1 P12/SCLK1/SCLK2 P13/SRDY1/SDATA2 P14/CNTR0 P20/AN0–P27/AN7 I/O port P2 (Note 2) P30–P35 I/O port P3 (Note 3) P36/INT1 P37/INT0 Function •Apply voltage of 2.2 to 5.5 V to Vcc, and 0 V to Vss. Function expect a port function •Reference voltage input pin for A/D converter •Chip operating mode control pin, which is always connected to Vss. •Reset input pin for active “L” •Input and output pins for main clock generating circuit •Connect a ceramic resonator or quartz crystal oscillator between the XIN and XOUT pins. •For using RC oscillator, short between the XIN and XOUT pins, and connect the capacitor and resistor. •If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. • When the on-chip oscillator is selected as the main clock, connect XIN pin to VSS and leave XOUT open. • Key-input (key-on wake up •8-bit I/O port. interrupt input) pins •I/O direction register allows each pin to be individually pro• Timer Y, timer Z, timer X and grammed as either input or output. timer A function pin •CMOS compatible input level •CMOS 3-state output structure •Whether a built-in pull-up resistor is to be used or not can be determined by program. •5-bit I/O port •I/O direction register allows each pin to be individually programmed as either input or output. •CMOS compatible input level •CMOS 3-state output structure •CMOS/TTL level can be switched for P10, P12 and P13 • Serial I/O1 function pin • Serial I/O1 function pin • Serial I/O2 function pin • Timer X function pin •8-bit I/O port having almost the same function as P0 • Input pins for A/D converter •CMOS compatible input level •CMOS 3-state output structure •8-bit I/O port •I/O direction register allows each pin to be individually programmed as either input or output. •CMOS compatible input level (CMOS/TTL level can be switched for P36 and P37). •CMOS 3-state output structure •P30 to P36 can output a large current for driving LED. •Whether a built-in pull-up resistor is to be used or not can be determined by program. • Interrupt input pins Notes 1: VCC = 2.4 to 5.5 V for the extended operating temperature version and the extended operating temperature 125 °C version. 2: P26/AN6 and P27/AN7 do not exist for the 32-pin version, so that Port P2 is a 6-bit I/O port. 3: P35 and P36/INT1 do not exist for the 32-pin version, so that Port P3 is a 6-bit I/O port. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 7 of 82 7540 Group GROUP EXPANSION Renesas plans to expand the 7540 group as follow: Memory type Support for Mask ROM version, One Time PROM version, and Emulator MCU . Memory size ROM/PROM size ................................................. 8 K to 32 K bytes RAM size .............................................................. 384 to 768 bytes Package 32P4B .................................................. 32-pin plastic molded SDIP 32P6U-A ...................... 0.8 mm-pitch 32-pin plastic molded LQFP 36P2R-A ...................... 0.8 mm-pitch 36-pin plastic molded SSOP 42S1M .................................... 42-pin shrink ceramic PIGGY BACK ROM size (bytes) M37540E8V 32K M37540E8T M37540E8 M37540M4V 16K M37540M4T M37540M4 M37540E2 M37540M2V 8K M37540M2T M37540M2 384 0 Fig. 8 Memory expansion plan Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 8 of 82 512 768 RAM size (bytes) 7540 Group Currently supported products are listed below. Table 2 List of supported products (P) ROM size (bytes) RAM size Part Number (bytes) ROM size for User () 384 8192 M37540M2-XXXSP (8062) M37540M2-XXXFP M37540M2T-XXXFP M37540M2V-XXXFP M37540M2-XXXGP M37540M2T-XXXGP M37540M2V-XXXGP M37540M4-XXXSP M37540M4-XXXFP M37540M4T-XXXFP M37540M4V-XXXFP M37540M4-XXXGP M37540M4T-XXXGP M37540M4V-XXXGP M37540E2SP M37540E2FP M37540E2GP M37540E8SP M37540E8FP M37540E8T-XXXFP 16384 (16254) 512 8192 (8062) 384 32768 (32638) 768 M37540E8V-XXXFP M37540E8GP M37540E8T-XXXGP M37540E8V-XXXGP M37540RSS Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z 768 page 9 of 82 Package Remarks 32P4B Mask ROM version 36P2R-A Mask ROM version Mask ROM version (extended operating temperature version) Mask ROM version (extended operating temperature 125 °C version) 32P6U-A Mask ROM version Mask ROM version (extended operating temperature version) Mask ROM version (extended operating temperature 125 °C version) 32P4B Mask ROM version 36P2R-A Mask ROM version Mask ROM version (extended operating temperature version) Mask ROM version (extended operating temperature 125 °C version) 32P6U-A Mask ROM version Mask ROM version (extended operating temperature version) Mask ROM version (extended operating temperature 125 °C version) 32P4B One Time PROM version (blank) 36P2R-A One Time PROM version (blank) 32P6U-A One Time PROM version (blank) 32P4B One Time PROM version (blank) 36P2R-A One Time PROM version (blank) One Time PROM version (shipped after programming, extended operating temperature version) One Time PROM version (shipped after programming, extended operating temperature 125 °C version) 32P6U-A One Time PROM version (blank) One Time PROM version (shipped after programming, extended operating temperature version) One Time PROM version (shipped after programming, extended operating temperature 125 °C version) 42S1M Emulator MCU 7540 Group FUNCTIONAL DESCRIPTION Stack pointer (S) Central Processing Unit (CPU) The MCU uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine-language instructions or the SERIES 740 <SOFTWARE> USER’S MANUAL for details on each instruction set. Machine-resident 740 family instructions are as follows: 1. The FST and SLW instructions cannot be used. 2. The MUL and DIV instructions can be used. 3. The WIT instruction can be used. 4. The STP instruction can be used. (This instruction cannot be used while an on-chip oscillator is operating.) Accumulator (A) The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. Index register X (X), Index register Y (Y) Both index register X and index register Y are 8-bit registers. In the index addressing modes, the value of the OPERAND is added to the contents of register X or register Y and specifies the real address. When the T flag in the processor status register is set to “1”, the value contained in index register X becomes the address for the second OPERAND. b7 b7 b0 b7 Index Register X b0 Y b7 Index Register Y b0 S b7 Stack Pointer b0 Program Counter PCL b7 The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. Accumulator X PCH Program counter (PC) b0 A b15 The stack pointer is an 8-bit register used during subroutine calls and interrupts. The stack is used to store the current address data and processor status when branching to subroutines or interrupt routines. The lower eight bits of the stack address are determined by the contents of the stack pointer. The upper eight bits of the stack address are determined by the Stack Page Selection Bit. If the Stack Page Selection Bit is “0”, then the RAM in the zero page is used as the stack area. If the Stack Page Selection Bit is “1”, then RAM in page 1 is used as the stack area. The Stack Page Selection Bit is located in the SFR area in the zero page. Note that the initial value of the Stack Page Selection Bit varies with each microcomputer type. Also some microcomputer types have no Stack Page Selection Bit and the upper eight bits of the stack address are fixed. The operations of pushing register contents onto the stack and popping them from the stack are shown in Fig. 10. b0 N V T B D I Z C Processor Status Register (PS) Carry Flag Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Negative Flag Fig. 9 740 Family CPU register structure Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 10 of 82 7540 Group On-going Routine Interrupt request (Note) M (S) Execute JSR M (S) Store Return Address on Stack (S) (PC H) (S) (S – 1) M (S) (PCL) (S) (S – 1) M (S) Subroutine Restore Return Address (S + 1) (PCL) M (S) (S) (S + 1) (PCH) M (S) (S – 1) (PC L) (S) (S – 1) M (S) (PS) (S) (S – 1) Interrupt Service Routine Execute RTS (S) (PC H) Execute RTI Note : The condition to enable the interrupt (S) (S + 1) (PS) M (S) (S) (S + 1) (PC L) M (S) (S) (S + 1) (PC H) M (S) Store Return Address on Stack Store Contents of Processor Status Register on Stack I Flag “0” to “1” Fetch the Jump Vector Restore Contents of Processor Status Register Restore Return Address Interrupt enable bit is “1” Interrupt disable flag is “0” Fig. 10 Register push and pop at interrupt generation and subroutine call Table 3 Push and pop instructions of accumulator or processor status register Push instruction to stack PHA PHP Accumulator Processor status register Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 11 of 82 Pop instruction from stack PLA PLP 7540 Group Processor status register (PS) The processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. After reset, the Interrupt disable (I) flag is set to “1”, but all other flags are undefined. Since the Index X mode (T) and Decimal mode (D) flags directly affect arithmetic operations, they should be initialized in the beginning of a program. (1) Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. (2) Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”. (3) Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”. When an interrupt occurs, this flag is automatically set to “1” to prevent other interrupts from interfering until the current interrupt is serviced. (4) Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. (5) Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”. The saved processor status is the only place where the break flag is ever set. (6) Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed between accumulator and memory, e.g. the results of an operation between two memory locations is stored in the accumulator. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations, i.e. between memory and memory, memory and I/O, and I/O and I/O. In this case, the result of an arithmetic operation performed on data in memory location 1 and memory location 2 is stored in memory location 1. The address of memory location 1 is specified by index register X, and the address of memory location 2 is specified by normal addressing modes. (7) Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. (8) Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 4 Set and clear instructions of each bit of processor status register Set instruction Clear instruction C flag SEC CLC Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z Z flag – – page 12 of 82 I flag SEI CLI D flag SED CLD B flag – – T flag SET CLT V flag – CLV N flag – – 7540 Group [CPU mode register] CPUM The CPU mode register contains the stack page selection bit. This register is allocated at address 003B16. b7 b0 CPU mode register (CPUM: address 003B16, initial value: 8016) Switching method of CPU mode register Switch the CPU mode register (CPUM) at the head of program after releasing Reset in the following method. Processor mode bits (Note 1) b1 b0 0 0 Single-chip mode 0 1 1 0 Not available 1 1 Stack page selection bit 0 : 0 page 1 : 1 page On-chip oscillator oscillation control bit 0 : On-chip oscillator oscillation enabled 1 : On-chip oscillator oscillation stop XIN oscillation control bit 0 : Ceramic or RC oscillation enabled 1 : Ceramic or RC oscillation stop Oscillation mode selection bit (Note 1) 0 : Ceramic oscillation 1 : RC oscillation Clock division ratio selection bits b7 b6 0 0 : f(φ) = f(XIN)/2 (High-speed mode) 0 1 : f(φ) = f(XIN)/8 (Middle-speed mode) 1 0 : applied from on-cihp oscillator 1 1 : f(φ) = f(XIN) (Double-speed mode)(Note 2) Note 1: The bit can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. However, by reset the bit is initialized and can be rewritten, again. (It is not disable to write any data to the bit for emulator MCU “M37540RSS”.) 2: These bits are used only when a ceramic oscillation is selected. Do not use these when an RC oscillation is selected. Fig. 11 Structure of CPU mode register After releasing reset Switch the oscillation mode selection bit (bit 5 of CPUM) Wait by on-chip oscillator operation until establishment of oscillator clock Switch the clock division ratio selection bits (bits 6 and 7 of CPUM) Main routine Fig. 12 Switching method of CPU mode register Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 13 of 82 Start with an on-chip oscillator An initial value is set as a ceramic oscillation mode. When it is switched to an RC oscillation, its oscillation starts. When using a ceramic oscillation, wait until establlishment of oscillation from oscillation starts. When using an RC oscillation, wait time is not required basically (time to execute the instruction to switch from an on-chip oscillator meets the requirement). Select 1/1, 1/2, 1/8 or on-chip oscillator. 7540 Group Memory Special function register (SFR) area The SFR area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for a stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is a user area for storing programs. Interrupt vector area The interrupt vector area contains reset and interrupt vectors. Zero page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special page The 256 bytes from addresses FF0016 to FFFF 16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. 000016 SFR area Zero page 004016 RAM 010016 RAM area RAM capacity (bytes) address XXXX16 384 512 768 01BF16 023F16 033F16 XXXX16 Reserved area 044016 Not used YYYY16 Reserved ROM area (128 bytes) ZZZZ16 ROM FF0016 ROM area ROM capacity (bytes) address YYYY16 address ZZZZ16 8192 16384 32768 E00016 C00016 800016 E08016 C08016 808016 Fig. 13 Memory map diagram Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 14 of 82 Special page FFDC16 Interrupt vector area FFFE16 FFFF16 Reserved ROM area 7540 Group 000016 Port P0 (P0) 002016 Timer Y, Z mode register (TYZM) 000116 Port P0 direction register (P0D) 002116 Prescaler Y (PREY) 000216 Port P1 (P1) 002216 Timer Y secondary (TYS) 000316 Port P1 direction register (P1D) 002316 Timer Y primary (TYP) 000416 Port P2 (P2) 002416 Timer Y, Z waveform output control register (PUM) 000516 Port P2 direction register (P2D) 002516 Prescaler Z (PREZ) 000616 Port P3 (P3) 002616 Timer Z secondary (TZS) 000716 Port P3 direction register (P3D) 002716 Timer Z primary (TZP) 002816 Prescaler 1 (PRE1) 000916 002916 Timer 1 (T1) 000A16 002A16 One-shot start register (ONS) 000B16 002B16 Timer X mode register (TXM) 000C16 002C16 Prescaler X (PREX) 000D16 002D16 Timer X (TX) Timer count source set register (TCSS) 000816 000E16 002E16 000F16 002F16 001016 003016 Serial I/O2 control register (SIO2CON) 001116 003116 Serial I/O2 register (SIO2) 001216 003216 001316 003316 001416 003416 A/D control register (ADCON) 001516 003516 A/D conversion register (low-order) (ADL) A/D conversion register (high-order) (ADH) 001616 Pull-up control register (PULL) 003616 001716 Port P1P3 control register (P1P3C) 003716 001816 Transmit/Receive buffer register (TB/RB) 003816 001916 Serial I/O1 status register (SIO1STS) 003916 Watchdog timer control register (WDTCON) 001A16 Serial I/O1 control register (SIO1CON) 003A16 Interrupt edge selection register (INTEDGE) 001B16 UART control register (UARTCON) 003B16 CPU mode register (CPUM) 001C16 Baud rate generator (BRG) 003C16 Interrupt request register 1 (IREQ1) 001D16 Timer A mode register (TAM) 003D16 Interrupt request register 2 (IREQ2) 001E16 Timer A (low-order) (TAL) 003E16 Interrupt control register 1 (ICON1) 001F16 Timer A (high-order) (TAH) 003F16 Interrupt control register 2 (ICON2) Note : Do not access to the SFR area including nothing. Fig. 14 Memory map of special function register (SFR) Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 15 of 82 MISRG 7540 Group I/O Ports [Direction registers] PiD The I/O ports have direction registers which determine the input/ output direction of each pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input or output. When “1” is set to the bit corresponding to a pin, this pin becomes an output port. When “0” is set to the bit, the pin becomes an input port. When data is read from a pin set to output, not the value of the pin itself but the value of port latch is read. Pins set to input are floating, and permit reading pin values. If a pin set to input is written to, only the port latch is written to and the pin remains floating. b7 [Pull-up control register] PULL By setting the pull-up control register (address 001616), ports P0 and P3 can exert pull-up control by program. However, pins set to output are disconnected from this control and cannot exert pull-up control. Note: P26/AN6, P27/AN7, P35 and P36 do not exist for the 32-pin version. Accordingly, the following settings are required; . Set direction registers of ports P26 and P27 to output. . Set direction registers of ports P35 and P36 to output. [Port P1P3 control register] P1P3C By setting the port P1P3 control register (address 001716 ), a CMOS input level or a TTL input level can be selected for ports P10, P12, P13, P36, and P37 by program. b0 Pull-up control register (PULL: address 001616, initial value: 0016) P00 pull-up control bit P01 pull-up control bit P02, P03 pull-up control bit P04 – P07 pull-up control bit P30 – P33 pull-up control bit P34 pull-up control bit P35, P36 pull-up control bit 0 : Pull-up Off 1 : Pull-up On P37 pull-up control bit Note : Pins set to output ports are disconnected from pull-up control. Fig. 15 Structure of pull-up control register b7 b0 Port P1P3 control register (P1P3C: address 0017 16, initial value: 00 16) P37/INT 0 input level selection bit 0 : CMOS level 1 : TTL level P36/INT 1 input level selection bit 0 : CMOS level 1 : TTL level P10,P1 2,P13 input level selection bit 0 : CMOS level 1 : TTL level Not used Note: Keep setting the P3 6/INT 1 input level selection bit to “0” (initial value) for 32-pin version. Fig. 16 Structure of port P1P3 control register Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 16 of 82 7540 Group Table 5 I/O port function table Pin P00/CNTR1 P01/TYOUT P02/TZOUT P03/TXOUT P04–P07 Name Input/output I/O format I/O port P0 I/O individual •CMOS compatible bits input level •CMOS 3-state output (Note 1) Non-port function Key input interrupt Timer X function output Timer Y function output Timer Z function output Timer A function input P10/RxD1 P11/TxD1 P12/SCLK1/SCLK2 P13/SRDY1/SDATA2 P14/CNTR0 P20/AN0– P27/AN7 P30–P35 P36/INT1 P37/INT0 I/O port P1 Serial I/O1 function input/output Serial I/O2 function input/output Timer X function input/output A/D conversion input I/O port P2 (Note 2) I/O port P3 (Note 3) External interrupt input Notes 1: Ports P10, P12, P13, P36, and P37 are CMOS/TTL level. 2: P26/AN6 and P27/AN7 do not exist for the 32-pin version. 3: P35 and P36/INT1 do not exist for the 32-pin version. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 17 of 82 Diagram No. Related SFRs (1) Pull-up control register (2) Timer Y mode register (3) Timer Z mode register (4) Timer X mode register Timer Y,Z waveform output control register Timer A mode register (5) Serial I/O1 control register (6) (7) Serial I/O1 control register (8) Serial I/O2 control register (9) Timer X mode register (10) A/D control register Interrupt edge selection register (11) (12) 7540 Group (1)Port P00 (2)Ports P01, P02 Pull-up control Pull-up control Direction register Direction register Data bus Port latch Data bus Port latch ** Programmable waveform generation mode Timer output CNTR1 interrupt input To key input interrupt generating circuit P00 key-on wakeup selection bit (3)Port P03 To key input interrupt generating circuit (4)Ports P04–P07 Pull-up control Pull-up control Direction register Data bus Direction register Data bus Port latch Port latch Timer output P03/TXOUT output valid To key input interrupt generating circuit To key input interrupt generating circuit (5)Port P10 (6)Port P11 Serial I/O1 enable bit Receive enable bit P11/TxD1 P-channel output disable bit Serial I/O1 enable bit Transmit enable bit Direction register Data bus Direction register Port latch P10, P12, P13 input level selection bit Data bus Port latch Serial I/O1 input * (7)Port P12 Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Serial I/O1 output SCLK2 pin selection bit Serial I/O1 mode selection bit Serial I/O1 enable bit Direction register Data bus Port latch P10, P12, P13 input level selection bit Serial I/O1, serial I/O2 clock output Serial I/O1, serial I/O2 clock input * P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register. When the TTL level is selected, there is no hysteresis characteristics. * ** P02/TZOUT; Programmable waveform generation mode Programmable one-shot generation mode Programmable wait one-shot generation mode Fig. 17 Block diagram of ports (1) Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 18 of 82 7540 Group (8) Port P13 (9) Port P14 SDATA2 output in operation signal SDATA2 pin selection bit Direction register Serial I/O mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register Data bus Data bus Port latch Port latch Pulse output mode Timer output P10, P12, P13 input level selection bit CNTR0 interrupt input Serial I/O1 ready output Serial I/O2 output Serial I/O2 input * (11) Ports P30–P35 (10) Ports P20–P27 Direction register Pull-up control Direction register Data bus Port latch Data bus Port latch A/D converter input Analog input pin selection bit (12) Ports P36, P37 Pull-up control Direction register Data bus Port latch P3 input level selection bit INT interrupt input * * P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register. When the TTL level is selected, there is no hysteresis characteristics. Fig. 18 Block diagram of ports (2) Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 19 of 82 7540 Group Interrupts Interrupts occur by 15 different sources : 5 external sources, 9 internal sources and 1 software source. Interrupt control All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit, and they are controlled by the interrupt disable flag. When the interrupt enable bit and the interrupt request bit are set to “1” and the interrupt disable flag is set to “0”, an interrupt is accepted. The interrupt request bit can be cleared by program but not be set. The interrupt enable bit can be set and cleared by program. The reset and BRK instruction interrupt can never be disabled with any flag or bit. All interrupts except these are disabled when the interrupt disable flag is set. When several interrupts occur at the same time, the interrupts are received according to priority. Interrupt operation Upon acceptance of an interrupt the following operations are automatically performed: 1. The processing being executed is stopped. 2. The contents of the program counter and processor status register are automatically pushed onto the stack. 3. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 4. Concurrently with the push operation, the interrupt destination address is read from the vector table into the program counter. ■ Notes on use When setting the followings, the interrupt request bit may be set to “1”. •When setting external interrupt active edge Related register: Interrupt edge selection register (address 003A16) Timer X mode register (address 2B16) Timer A mode register (address 1D16) When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ➀ Set the corresponding interrupt enable bit to “0” (disabled). ➁ Set the interrupt edge select bit (active edge switch bit) to “1”. ➂ Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the corresponding interrupt enable bit to “1” (enabled). Table 6 Interrupt vector address and priority Interrupt source Priority Vector addresses (Note 1) High-order Low-order Reset (Note 2) Serial I/O1 receive Serial I/O1 transmit 1 2 3 FFFD16 FFFB16 FFF916 FFFC16 FFFA16 FFF816 INT0 4 FFF716 FFF616 INT1 (Note 3) 5 FFF516 FFF416 Key-on wake-up 6 FFF316 FFF216 CNTR0 7 FFF116 FFF016 CNTR1 8 FFEF16 FFEE16 Timer X Timer Y Timer Z Timer A Serial I/O2 A/D conversion Timer 1 Reserved area BRK instruction 9 10 11 12 13 14 15 16 17 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDF16 FFDD16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE16 FFDC16 Interrupt request generating conditions Remarks At reset input At completion of serial I/O1 data receive At completion of serial I/O1 transmit shift or when transmit buffer is empty At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At falling of conjunction of input logical level for port P0 (at input) At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At timer X underflow At timer Y underflow At timer Z underflow At timer A underflow At completion of transmit/receive shift At completion of A/D conversion At timer 1 underflow Not available At BRK instruction execution Non-maskable Valid only when serial I/O1 is selected Valid only when serial I/O1 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (valid at falling) Note 1: Vector addressed contain internal jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 3: It is an interrupt which can use only for 36 pin version. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 20 of 82 External interrupt (active edge selectable) External interrupt (active edge selectable) STP release timer underflow Non-maskable software interrupt 7540 Group Interrupt request bit Interrupt enable bit Interrupt disable flag I BRK instruction Reset Interrupt request Fig. 19 Interrupt control b7 b0 Interrupt edge selection register (INTEDGE : address 003A16, initial value : 0016) INT0 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active INT1 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active Not used (returns “0” when read) P00 key-on wakeup enable bit 0 : Key-on wakeup enabled 1 : Key-on wakeup disabled b7 b0 Interrupt request register 1 (IREQ1 : address 003C16, initial value : 0016) Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit INT0 interrupt request bit INT1 interrupt request bit Key-on wake up interrupt request bit CNTR0 interrupt request bit CNTR1 interrupt request bit Timer X interrupt request bit b7 b0 Interrupt request register 2 (IREQ2 : address 003D16, initial value : 0016) Timer Y interrupt request bit Timer Z interrupt request bit Timer A interrupt request bit Serial I/O2 interrupt request bit A/D conversion interrupt request bit Timer 1 interrupt request bit Not used (returns “0” when read) b7 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued b0 Interrupt control register 1 (ICON1 : address 003E16, initial value : 0016) Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit INT0 interrupt enable bit INT1 interrupt enable bit (Do not write “1” to this bit for 32-pin version) Key-on wake up interrupt enable bit CNTR0 interrupt enable bit CNTR1 interrupt enable bit Timer X interrupt enable bit 0 : Interrupts disabled 1 : Interrupts enabled b7 b0 Interrupt control register 2 (ICON2 : address 003F16, initial value : 0016) Timer Y interrupt enable bit Timer Z interrupt enable bit Timer A interrupt enable bit Serial I/O2 interrupt enable bit A/D conversion interrupt enable bit Timer 1 interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit) Fig. 20 Structure of Interrupt-related registers Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 21 of 82 0 : Interrupts disabled 1 : Interrupts enabled 7540 Group Key Input Interrupt (Key-On Wake-Up) A key-on wake-up interrupt request is generated by applying “L” level to any pin of port P0 that has been set to input mode. In other words, it is generated when the AND of input level goes from “1” to “0”. An example of using a key input interrupt is shown in Figure 21, where an interrupt request is generated by pressing one of the keys provided as an active-low key matrix which uses ports P00 to P03 as input ports. Port PXx “L” level output PULL register bit 3 = “0” * ** P07 output Port P07 Direction register = “1” Key input interrupt request Port P07 latch Falling edge detection PULL register bit 3 = “0” * ** P06 output Port P06 Direction register = “1” Port P06 latch Falling edge detection PULL register bit 3 = “0” * ** P05 output Port P05 Direction register = “1” Port P05 latch Falling edge detection PULL register bit 3 = “0” * ** P04 output Port P04 Direction register = “1” Port P04 latch PULL register bit 2 = “1” * ** P03 input Port P03 Direction register = “0” Port P03 latch PULL register bit 2 = “1” * ** P02 input Falling edge detection Falling edge detection Port P02 Direction register = “0” Port P02 latch Falling edge detection PULL register bit 1 = “1” * ** P01 input Port P01 Direction register = “0” Port P01 latch Falling edge detection PULL register bit 0 = “1” * ** P00 input Port P00 Direction register = “0” Port P00 latch Falling edge detection Port P00 key-on wakeup selection bit * P-channel transistor for pull-up ** CMOS output buffer Fig. 21 Connection example when using key input interrupt and port P0 block diagram Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 22 of 82 Port P0 Input read circuit 7540 Group Timers ●Timer A The 7540 Group has 5 timers: timer 1, timer A, timer X, timer Y and timer Z. The division ratio of every timer and prescaler is 1/(n+1) provided that the value of the timer latch or prescaler is n. All the timers are down count timers. When a timer reaches “0”, an underflow occurs at the next count pulse, and the corresponding timer latch is reloaded into the timer. When a timer underflows, the interrupt request bit corresponding to each timer is set to “1”. Timer A is a 16-bit timer and counts the signal which is the oscillation frequency divided by 16. When Timer A underflows, the timer A interrupt request bit is set to “1”. Timer A consists of the low-order of Timer A (TAL) and the high-order of Timer A (TAH). Timer A has the timer A latch to retain the reload value. The value of timer A latch is set to Timer A at the timing shown below. • When Timer A undeflows. • When an active edge is input from CNTR1 pin (valid only when period measurement mode and pulse width HL continuously measurement mode). When writing to both the low-order of Timer A (TAL) and the highorder of Timer A (TAH) is executed, the value is written to both the timer A latch and Timer A. When reading from the low-order of Timer A (TAL) and the high-order of Timer A (TAH) is executed, the following values are read out according to the operating mode. • In timer mode, event counter mode: The count value of Timer A is read out. • In period measurement mode, pulse width HL continuously measurement mode: The measured value is read out. ●Timer 1 Timer 1 is an 8-bit timer and counts the prescaler output. When Timer 1 underflows, the timer 1 interrupt request bit is set to “1”. Prescaler 1 is an 8-bit prescaler and counts the signal which is the oscillation frequency divided by 16. Prescaler 1 and Timer 1 have the prescaler 1 latch and the timer 1 latch to retain the reload value, respectively. The value of prescaler 1 latch is set to Prescaler 1 when Prescaler 1 underflows.The value of timer 1 latch is set to Timer 1 when Timer 1 underflows. When writing to Prescaler 1 (PRE1) is executed, the value is written to both the prescaler 1 latch and Prescaler 1. When writing to Timer 1 (T1) is executed, the value is written to both the timer 1 latch and Timer 1. When reading from Prescaler 1 (PRE1) and Timer 1 (T1) is executed, each count value is read out. Timer 1 always operates in the timer mode. Prescaler 1 counts the signal which is the oscillation frequency divided by 16. Each time the count clock is input, the contents of Prescaler 1 is decremented by 1. When the contents of Prescaler 1 reach “0016”, an underflow occurs at the next count clock, and the prescaler 1 latch is reloaded into Prescaler 1 and count continues. The division ratio of Prescaler 1 is 1/(n+1) provided that the value of Prescaler 1 is n. The contents of Timer 1 is decremented by 1 each time the underflow signal of Prescaler 1 is input. When the contents of Timer 1 reach “0016”, an underflow occurs at the next count clock, and the timer 1 latch is reloaded into Timer 1 and count continues. The division ratio of Timer 1 is 1/(m+1) provided that the value of Timer 1 is m. Accordingly, the division ratio of Prescaler 1 and Timer 1 is 1/((n+1)✕(m+1)) provided that the value of Prescaler 1 is n and the value of Timer 1 is m. Timer 1 cannot stop counting by software. Be sure to write to/read out the low-order of Timer A (TAL) and the high-order of Timer A (TAH) in the following order; Read Read the high-order of Timer A (TAH) first, and the low-order of Timer A (TAL) next and be sure to read out both TAH and TAL. Write Write to the low-order of Timer A (TAL) first, and the high-order of Timer A (TAH) next and be sure to write to both TAL and TAH. Timer A can be selected in one of 4 operating modes by setting the timer A mode register. (1) Timer mode Timer A counts the oscillation frequency divided by 16. Each time the count clock is input, the contents of Timer A is decremented by 1. When the contents of Timer A reach “000016”, an underflow occurs at the next count clock, and the timer A latch is reloaded into Timer A. The division ratio of Timer A is 1/(n+1) provided that the value of Timer A is n. (2) Period measurement mode In the period measurement mode, the pulse period input from the P00/CNTR1 pin is measured. CNTR 1 interrupt request is generated at rising/falling edge of CNTR1 pin input singal. Simultaneousuly, the value in the timer A latch is reloaded inTimer A and count continues. The active edge of CNTR1 pin input signal can be selected from rising or falling by the CNTR1 active edge switch bit .The count value when trigger input from CNTR1 pin is accepted is retained until Timer A is read once. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 23 of 82 7540 Group (3) Event counter mode Timer A counts signals input from the P00/CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. The active edge of CNTR 1 pin input signal can be selected from rising or falling by the CNTR1 active edge switch bit . (4) Pulse width HL continuously measurement mode In the pulse width HL continuously measurement mode, the pulse width (“H” and “L” levels) input to the P00/CNTR1 pin is measured. CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. The count value when trigger input from the CNTR 1 pin is accepted is retained until Timer A is read once. Timer A can stop counting by setting “1” to the timer A count stop bit in any mode. Also, when Timer A underflows, the timer A interrupt request bit is set to “1”. Note on Timer A is described below; ■ Note on Timer A CNTR1 interrupt active edge selection CNTR1 interrupt active edge depends on the CNTR 1 active edge switch bit. When this bit is “0”, the CNTR1 interrupt request bit is set to “1” at the falling edge of the CNTR1 pin input signal. When this bit is “1”, the CNTR1 interrupt request bit is set to “1” at the rising edge of the CNTR1 pin input signal. However, in the pulse width HL continuously measurement mode, CNTR 1 interrupt request is generated at both rising and falling edges of CNTR 1 pin input signal regardless of the setting of CNTR1 active edge switch bit. b7 b0 Timer A mode register (TAM : address 001D 16, initial value: 00 16) Not used (return “0” when read) Timer A operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode CNTR1 active edge switch bit 0 : Count at rising edge in event counter mode Measure the falling edge period in period measurement mode Falling edge active for CNTR 1 interrupt 1 : Count at falling edge in event counter mode Measure the rising edge period in period measurement mode Rising edge active for CNTR 1 interrupt Timer A count stop bit 0 : Count start 1 : Count stop Fig. 22 Structure of timer A mode register Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 24 of 82 ●Timer X Timer X is an 8-bit timer and counts the prescaler X output. When Timer X underflows, the timer X interrupt request bit is set to “1”. Prescaler X is an 8-bit prescaler and counts the signal selected by the timer X count source selection bit. Prescaler X and Timer X have the prescaler X latch and the timer X latch to retain the reload value, respectively. The value of prescaler X latch is set to Prescaler X when Prescaler X underflows.The value of timer X latch is set to Timer X when Timer X underflows. When writing to Prescaler X (PREX) is executed, the value is written to both the prescaler X latch and Prescaler X. When writing to Timer X (TX) is executed, the value is written to both the timer X latch and Timer X. When reading from Prescaler X (PREX) and Timer X (TX) is executed, each count value is read out. Timer X can can be selected in one of 4 operating modes by setting the timer X operating mode bits of the timer X mode register. (1) Timer mode Prescaler X counts the count source selected by the timer X count source selection bits. Each time the count clock is input, the contents of Prescaler X is decremented by 1. When the contents of Prescaler X reach “0016”, an underflow occurs at the next count clock, and the prescaler X latch is reloaded into Prescaler X and count continues. The division ratio of Prescaler X is 1/(n+1) provided that the value of Prescaler X is n. The contents of Timer X is decremented by 1 each time the underflow signal of Prescaler X is input. When the contents of Timer X reach “0016”, an underflow occurs at the next count clock, and the timer X latch is reloaded into Timer X and count continues. The division ratio of Timer X is 1/(m+1) provided that the value of Timer X is m. Accordingly, the division ratio of Prescaler X and Timer X is 1/((n+1)✕(m+1)) provided that the value of Prescaler X is n and the value of Timer X is m. (2) Pulse output mode In the pulse output mode, the waveform whose polarity is inverted each time timer X underflows is output from the CNTR0 pin. The output level of CNTR0 pin can be selected by the CNTR0 active edge switch bit. When the CNTR0 active edge switch bit is “0”, the output of CNTR0 pin is started at “H” level. When this bit is “1”, the output is started at “L” level. Also, the inverted waveform of pulse output from CNTR0 pin can be output from TXOUT pin by setting “1” to the P03/TXOUT output valid bit. When using a timer in this mode, set the port P14 and P03 direction registers to output mode. (3) Event counter mode The timer A counts signals input from the P14/CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. The active edge of CNTR0 pin input signal can be selected from rising or falling by the CNTR0 active edge switch bit . 7540 Group (4) Pulse width measurement mode In the pulse width measurement mode, the pulse width of the signal input to P14/CNTR0 pin is measured. The operation of Timer X can be controlled by the level of the signal input from the CNTR0 pin. When the CNTR0 active edge switch bit is “0”, the signal selected by the timer X count source selection bit is counted while the input signal level of CNTR0 pin is “H”. The count is stopped while the pin is “L”. Also, when the CNTR0 active edge switch bit is “1”, the signal selected by the timer X count source selection bit is counted while the input signal level of CNTR0 pin is “L”. The count is stopped while the pin is “H”. b7 b0 Timer X mode register (TXM : address 002B 16, initial value: 00 16) Timer X operating mode bits b1 b0 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR 0 active edge switch bit 0 : Interrupt at falling edge Count at rising edge (in event counter mode) 1 : Interrupt at rising edge Count at falling edge (in event counter mode) Timer X count stop bit 0 : Count start 1 : Count stop Timer X can stop counting by setting “1” to the timer X count stop bit in any mode. Also, when Timer X underflows, the timer X interrupt request bit is set to “1”. Note on Timer X is described below; ■ Note on Timer X CNTR0 interrupt active edge selection CNTR0 interrupt active edge depends on the CNTR0 active edge switch bit. When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at the falling edge of CNTR0 pin input signal. When this bit is “1”, the CNTR 0 interrupt request bit is set to “1” at the rising edge of CNTR0 pin input signal. P03/TXOUT output valid bit 0 : Output invalid (I/O port) 1 : Output valid (Inverted CNTR 0 output) Not used (return “0” when read) Fig. 23 Structure of timer X mode register b7 b0 Timer count source set register (TCSS : address 002E16, initial value: 0016) Timer X count source selection bits b1 b0 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : f(XIN) (Note 1) 1 1 : Not available Timer Y count source selection bits b3 b2 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : On-chip oscillator output (Note 2) 1 1 : Not available Timer Z count source selection bits b5 b4 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : Timer Y underflow 1 1 : Not available Fix this bit to “0”. Not used (return “0” when read) Notes 1: f(XIN) can be used as timer X count source when using a ceramic resonator or on-chip oscillator. Do not use it at RC oscillation. 2: System operates using an on-chip oscillator as a count source by setting the on-cihp oscillator to oscillation enabled by bit 3 of CPUM. Fig. 24 Timer count source set register Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 25 of 82 7540 Group ●Timer Y Timer Y is an 8-bit timer and counts the prescaler Y output. When Timer Y underflows, the timer Y interrupt request bit is set to “1”. Prescaler Y is an 8-bit prescaler and counts the signal selected by the timer Y count source selection bit. Prescaler Y has the prescaler Y latch to retain the reload value. Timer Y has the timer Y primary latch and timer Y secondary latch to retain the reload value. The value of prescaler Y latch is set to Prescaler Y when Prescaler Y underflows.The value of timer Y primary latch or timer Y secondary latch are set to Timer Y when Timer Y underflows. As for the value to transfer to Timer Y, either of timer Y primary or timer Y secondary is selected depending on the timer Y operating mode. When writing to Prescaler Y (PREY), timer Y primary (TYP) or timer Y secondary (TYS) is executed, writing to “latch only” or “latch and prescaler (timer)” can be selected by the setting value of the timer Y write control bit. Be sure to set the timer Y write control bit because there are some notes according to the operating mode. When reading from Prescaler Y (PREY) is executed, the count value of Prescaler Y is read out. When reading from timer Y primary (TYP) is executed, the count value of Timer Y is read out. The count value of Timer Y can be read out by reading from the timer Y primary (TYP) even when the value of timer Y primary latch or timer Y secondary latch is counted. When reading the timer Y secondary (TYS) is executed, the undefined value is read out. (2) Programmable waveform generation mode In the programmable waveform generation mode, timer counts the setting value of timer Y primary and the setting value of timer Y secondary alternately, the waveform inverted each time Timer Y underflows is output from TYOUT pin. When using this mode, be sure to set “1” to the timer Y write control bit to select “write to latch only”. Also, set the port P01 direction registers to output mode. The active edge of output waveform is set by the timer Y output level latch (b5) of the timer Y, Z waveform output control register (PUM). When “0” is set to b5 of PUM, “H” interval by the setting value of TYP or “L” interval by the setting value of TYS is output alternately. When “1” is set to b5 of PUM, “L” interval by the setting value of TYP or “H” interval by the setting value of TYS is output alternately. Also, in this mode, the primary interval and the secondary interval of the output waveform can be extended respectively for 0.5 cycle of timer count source clock by setting the timer Y primary waveform extension control bit (b2) and the timer Y secondary waveform extension control bit (b3) of PUM to “1”. As a result, the waveforms of more accurate resolution can be output. When b2 and b3 of PUM are used, the frequency and duty of the output waveform are as follows; Waveform frequency: FYOUT= 2✕TMYCL 2✕(TYP+1)+2✕(TYS+1)+(EXPYP+EXPYS) Duty: 2✕(TYP+1)+EXPYP (2✕(TYP+1)+EXPYP)+(2✕(TYS+1)+EXPYS) Timer Y can be selected in one of 2 operating modes by setting the timer Y operating mode bits of the timer Y, Z mode register. DYOUT= (1) Timer mode Prescaler Y counts the count source selected by the timer Y count source selection bits. Each time the count clock is input, the contents of Prescaler Y is decremented by 1. When the contents of Prescaler Y reach “0016”, an underflow occurs at the next count clock, and the prescaler Y latch is reloaded into Prescaler Y. The division ratio of Prescaler Y is 1/(n+1) provided that the value of Prescaler Y is n. The contents of Timer Y is decremented by 1 each time the underflow signal of Prescaler Y is input. When the contents of Timer Y reach “0016”, an underflow occurs at the next count clock, and the timer Y primary latch is reloaded into Timer Y and count continues. (In the timer mode, the contents of timer Y primary latch is counted. Timer Y secondary latch is not used in this mode.) The division ratio of Timer Y is 1/(m+1) provided that the value of Timer Y is m. Accordingly, the division ratio of Prescaler Y and Timer Y is 1/((n+1)✕(m+1)) provided that the value of Prescaler Y is n and the value of Timer Y is m. In the timer mode, writing to “latch only” or “latches and Prescaler Y and timer Y primary” can be selected by the setting value of the timer Y write control bit. TMYCL: Timer Y count source (frequency) TYP: Timer Y primary (8bit) TYS: Timer Y secondary (8bit) EXPYP: Timer Y primary waveform extension control bit (1bit) EXPYS: Timer Y secondary waveform extension control bit (1bit) Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 26 of 82 In the programmable waveform generation mode, when values of the TYP, TYS, EXPYP and EXPYS are changed, the output waveform is changed at the beginning (timer Y primary waveform interval) of waveform period. When the count values are changed, set values to the TYS, EXPYP and EXPYS first. After then, set the value to TYP. The values are set all at once at the beginning of the next waveform period when the value is set to TYP. (When writing at timer stop is executed, writing to TYP at last is required.) Notes on programmable waveform generation mode is described below; 7540 Group ■ Notes on programmable generation waveform mode • Count set value In the programmable waveform generation mode, values of TYS, EXPYP, and EXPYS are valid by writing to TYP because the setting to them is executed all at once by writing to TYP. Even when changing TYP is not required, write the same value again. • Write timing to TYP In the programmable waveform generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TYP and the timing of timer underflow during the secondary interval simultanesously. • Usage of waveform extension function The waveform extension function by the timer Y waveform extension control bit can be used only when “0016” is set to Prescaler Y. When the value other than “0016” is set to Prescaler Y, be sure to set “0” to EXPYP and EXPYS. • Timer Y write mode When using this mode, be sure to set “1” to the timer Y write control bit to select “write to latch only”. Timer Y can stop counting by setting “1” to the timer Y count stop bit in any mode. Also, when Timer Y underflows, the timer Y interrupt request bit is set to “1”. Timer Y reloads the value of latch when counting is stopped by the timer Y count stop bit. (When timer is read out while timer is stopped, the value of latch is read. The value of timer can be read out only while timer is operating.) Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 27 of 82 7540 Group ●Timer Z Timer Z is an 8-bit timer and counts the prescaler Z output. When Timer Z underflows, the timer Z interrupt request bit is set to “1”. Prescaler Z is an 8-bit prescaler and counts the signal selected by the timer Z count source selection bit. Prescaler Z has the prescaler Z latch to retain the reload value. Timer Z has the timer Z primary latch and timer Z secondary latch to retain the reload value. The value of prescaler Z latch is set to Prescaler Z when Prescaler Z underflows.The value of timer Z primary latch or timer Z secondary latch are set to Timer Z when Timer Z underflows. As for the value to transfer to Timer Z, either of timer Z primary or timer Z secondary is selected depending on the timer Z operating mode. When writing to Prescaler Z (PREZ), timer Z primary (TZP) or timer Z secondary (TZS) is executed, writing to “latch only” or “latches and Prescaler Z and Timer Z” can be selected by the setting value of the timer Z write control bit. Be sure to set the write control bit because there are some notes according to the operating mode. When reading from Prescaler Z (PREZ) is executed, the count value of Prescaler Z is read out. When reading from timer Z primary (TZP) is executed, the count value of Timer Z is read out. The count value of Timer Z can be read out by reading from the timer Z primary (TZP) even when the value of timer Z primary latch or timer Z secondary latch is counted. When reading the timer Z secondary (TZS) is executed, the undefined value is read out. (2) Programmable waveform generation mode In the programmable waveform generation mode, timer counts the setting value of timer Z primary and the setting value of timer Z secondary alternately, the waveform inverted each time Timer Z underflows is output from TZOUT pin. When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”. Also, set the port P02 direction registers to output mode. The active edge of output waveform is set by the timer Z output level latch (b4) of the timer Y, Z waveform output control register (PUM). When “0” is set to b4 of PUM, “H” interval by the setting value of TZP or “L” interval by the setting value of TZS is output alternately. When “1” is set to b4 of PUM, “L” interval by the setting value of TZP or “H” interval by the setting value of TZS is output alternately. Also, in this mode, the primary interval and the secondary interval of the output waveform can be extended respectively for 0.5 cycle of timer count source clock by setting the timer Z primary waveform extension control bit (b0) and the timer Z secondary waveform extension control bit (b1) of PUM to “1”. As a result, the waveforms of more accurate resolution can be output. When b0 and b1 of PUM are used, the frequency and duty of the output waveform are as follows; Waveform frequency: FZOUT= 2✕TMZCL 2✕(TZP+1)+2✕(TZS+1)+(EXPZP+EXPZS) Duty: 2✕(TZP+1)+EXPZP (2✕(TZP+1)+EXPZP)+(2✕(TZS+1)+EXPZS Timer Z can be selected in one of 4 operating modes by setting the timer Z operating mode bits of the timer Y, Z mode register. DZOUT= (1) Timer mode Prescaler Z counts the count source selected by the timer Z count source selection bits. Each time the count clock is input, the contents of Prescaler Z is decremented by 1. When the contents of Prescaler Z reach “0016”, an underflow occurs at the next count clock, and the prescaler Z latch is reloaded into Prescaler Z. The division ratio of Prescaler Z is 1/(n+1) provided that the value of Prescaler Z is n. The contents of Timer Z is decremented by 1 each time the underflow signal of Prescaler Z is input. When the contents of Timer Z reach “0016”, an underflow occurs at the next count clock, and the timer Z primary latch is reloaded into Timer Z and count continues. (In the timer mode, the contents of timer Z primary latch is counted. Timer Z secondary latch is not used in this mode.) The division ratio of Timer Z is 1/(m+1) provided that the value of Timer Z is m. Accordingly, the division ratio of Prescaler Z and Timer Z is 1/((n+1)✕(m+1)) provided that the value of Prescaler Z is n and the value of Timer Z is m. In the timer mode, writing to “latch only” or “latches and Prescaler Z and timer Z primary” can be selected by the setting value of the timer Z write control bit. TMZCL: Timer Z count source (frequency) TZP: Timer Z primary (8bit) TZS: Timer Z secondary (8bit) EXPZP: Timer Z primary waveform extension control bit (1bit) EXPZS: Timer Z secondary waveform extension control bit (1bit) Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 28 of 82 In the programmable waveform generation mode, when values of the TZP, TZS, EXPZP and EXPZS are changed, the output waveform is changed at the beginning (timer Z primary waveform interval) of waveform period. When the count values are changed, set values to the TZS, EXPZP and EXPZS first. After then, set the value to TZP. The values are set all at once at the beginning of the next waveform period when the value is set to TZP. (When writing at timer stop is executed, writing to TZP at last is required.) 7540 Group Notes on the programmable waveform generation mode are described below; ■ Notes on programmable waveform generation mode • Count set value In the programmable waveform generation mode, values of TZS, EXPZP, and EXPZS are valid by writing to TZP because the setting to them is executed all at once by writing to TZP. Even when changing TZP is not required, write the same value again. • Write timing to TZP In the programmable waveform generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow during the secondary interval simultanesously. • Usage of waveform extension function The waveform extension function by the timer Z waveform extension control bit can be used only when “0016” is set to Prescaler Z. When the value other than “0016” is set to Prescaler Z, be sure to set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the count source, the waveform extension function cannot be used. • Timer Z write mode When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”. (3) Programmable one-shot generation mode In the programmable one-shot generation mode, the one-shot pulse by the setting value of timer Z primary can be output from TZOUT pin by software or external trigger. When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”. Also, set the port P0 2 direction registers to output mode. In this mode, TZS is not used. The active edge of output waveform is set by the timer Z output level latch (b5) of the timer Y, Z waveform output control register (PUM). When “0” is set to b5 of PUM, “H” pulse during the interval of the TZP setting value is output. When “1” is set to b5 of PUM, “L” pulse during the interval of the TZP setting value is output. Also, in this mode, the interval of the one-shot pulse output can be extended for 0.5 cycle of timer count source clock by setting the timer Z primary waveform extension control bit (b2) of PUM to “1”. As a result, the waveforms of more accurate resolution can be output. In the programmable one-shot generation mode, the trigger by software or the external INT0 pin can be accepted by writing “0” to the timer Z count stop bit after the count value is set. (At the time when “0” is written to the timer Z count stop bit, Timer Z stops.) By writing “1” to the timer Z one-shot start bit, or by inputting the valid trigger to the INT 0 pin after the trigger to the INT0 pin becomes valid by writing “1” to the INT0 pin one-shot trigger control bit, Timer Z starts counting, at the same time, the output of TZOUT pin is inverted. When Timer Z underflows, the output of TZOUT pin is inverted again and Timer Z stops. When also the trigger of INT0 pin is accepted, the contents of the one-shot start bit is changed to “1” by hardware. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 29 of 82 The falling or rising can be selected as the edge of the valid trigger of INT0 pin by the INT0 pin one-shot trigger edge selection bit. During the one-shot pulse output interval, the one-shot pulse output can be stopped forcibly by writing “0” to the timer Z one-shot start bit. In the programmable one-shot generation mode, when the count values are changed, set value to the EXPZP first. After then, set the value to TZP. The values are set all at once at the beginning of the next one-shot pulse when the value is set to TZP. (When writing at timer stop is executed, writing to TZP at last is required.) Notes on the programmable one-shot generation mode are described below; ■ Notes on programmable one-shot generation mode • Count set value In the programmable one-shot generation mode, the value of EXPZP becomes valid by writing to TZP. Even when changing TZP is not required, write the same value again. • Write timing to TZP In the programmable one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow simultanesously. • Usage of waveform extension function The waveform extension function by the timer Z waveform extension control bit can be used only when “0016” is set to Prescaler Z. When the value other than “0016” is set to Prescaler Z, be sure to set “0” to EXPZP. Also, when the timer Y underflow is selected as the count source, the waveform extension function cannot be used. • Timer Z write mode When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”. 7540 Group (4) Programmable wait one-shot generation mode In the programmable wait one-shot generation mode, the one-shot pulse by the setting value of timer Z secondary can be output from TZOUT pin by software or external trigger to INT0 pin after the wait by the setting value of the timer Z primary. When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”. Also, set the port P0 2 direction registers to output mode. The active edge of output waveform is set by the timer Z output level latch (b5) of the timer Y, Z waveform output control register (PUM). When “0” is set to b5 of PUM, after the wait during the interval of the TZP setting value, “H” pulse during the interval of the TZS setting value is output. When “1” is set to b5 of PUM, after the wait during the interval of the TZP setting value, “L” pulse during the interval of the TZS setting value is output. Also, in this mode, the intervals of the wait and the one-shot pulse output can be extended for 0.5 cycle of timer count source clock by setting EXPZP and EXPZS of PUM to “1”. As a result, the waveforms of more accurate resolution can be output. In the programmable one-shot generation mode, the trigger by software or the external INT0 pin can be accepted by writing “0” to the timer Z count stop bit after the count value is set. (At the time when “0” is written to the timer Z count stop bit, Timer Z stops.) By writing “1” to the timer Z one-shot start bit, or by inputting the valid trigger to the INT 0 pin after the trigger to the INT0 pin becomes valid by writing “1” to the INT0 pin one-shot trigger control bit, Timer Z starts counting. While Timer Z counts the TZP, the initial value of the TZOUT pin output is retained. When Timer Z underflows, the value of TZS is reloaded, at the same time, the output of TZOUT pin is inverted. When Timer Z underflows, the output of TZOUT pin is inverted again and Timer Z stops. When also the trigger of INT0 pin is accepted, the contents of the one-shot start bit is changed to “1” by hardware. The falling or rising can be selected as the edge of the valid trigger of INT0 pin by the INT0 pin one-shot trigger edge selection bit. During the wait interval and the one-shot pulse output interval, the one-shot pulse output can be stopped forcibly by writing “0” to the timer Z one-shot start bit. In the programmable wait one-shot generation mode, when the count values are changed, set values to the TZS, EXPZP and EXPZS first. After then, set the value to TZP. The values are set all at once at the beginning of the next wait interval when the value is set to TZP. (When writing at timer stop is executed, writing to TZP at last is required.) Notes on the programmable wait one-shot generation mode are described below; Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 30 of 82 ■ Notes on programmable wait one-shot generation mode • Count set value In the programmable wait one-shot generation mode, values of TZS, EXPZP and EXPZS are valid by writing to TZP. Even when changing TZP is not required, write the same value again. • Write timing to TZP In the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow during the secondary interval simultanesously. • Usage of waveform extension function The waveform extension function by the timer Z waveform extension control bit can be used only when “0016” is set to Prescaler Z. When the value other than “0016” is set to Prescaler Z, be sure to set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the count source, the waveform extension function cannot be used. • Timer Z write mode When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”. Timer Z can stop counting by setting “1” to the timer Z count stop bit in any mode. Also, when Timer Z underflows, the timer Z interrupt request bit is set to “1”. Timer Z reloads the value of latch when counting is stopped by the timer Z count stop bit. (When timer is read out while timer is stopped, the value of latch is read. The value of timer can be read out only while timer is operating.) 7540 Group b7 b0 Timer Y, Z mode register (TYZM : address 0020 16, initial value: 00 16) Timer Y operating mode bit 0 : Timer mode 1 : Programmable waveform generation mode Not used (return “0” when read) Timer Y write control bit 0 : Write to latch and timer simultaneously 1 : Write to only latch Timer Y count stop bit 0 : Count start 1 : Count stop Timer Z operating mode bits b5 b4 0 0 : Timer mode 0 1 : Programmable waveform generation mode 1 0 : Programmable one-shot generation mode 1 1 : Programmable wait one-shot generation mode Timer Z write control bit 0 : Write to latch and timer simultaneously 1 : Write to only latch Timer Z count stop bit 0 : Count start 1 : Count stop Fig. 25 Structure of timer Y, Z mode register b7 b0 Timer Y, Z waveform output control register (PUM : address 0024 16, initial value: 00 16) Timer Y primary waveform extension control bit 0 : Waveform not extended 1 : Waveform extended Timer Y secondary waveform extension control bit 0 : Waveform not extended 1 : Waveform extended Timer Z primary waveform extension control bit 0 : Waveform not extended 1 : Waveform extended Timer Z secondary waveform extension control bit 0 : Waveform not extended 1 : Waveform extended Timer Y output level latch 0 : “L” output 1 : “H” output Timer Z output level latch 0 : “L” output 1 : “H” output INT0 pin one-shot trigger control bit 0 : INT 0 pin one-shot trigger invalid 1 : INT 0 pin one-shot trigger valid INT0 pin one-shot trigger active edge selection bit 0 : Falling edge trigger 1 : Rising edge trigger Fig. 26 Structure of timer YZ waveform output control register b7 b0 One-shot start register (ONS : address 002A 16, initial value: 00 16) Timer Z one-shot start bit 0 : One-shot stop 1 : One-shot start Not used (return “0” when read) Fig. 27 Structure of one-shot start register Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 31 of 82 7540 Group Data bus Timer 1 latch (8) Prescaler 1 latch (8) Prescaler 1 (8) f(XIN)/16 Timer 1 (8) Timer 1 interrupt request bit Pulse width HL continuously measurement mode Rising edge detected Period measurement mode Falling edge detected P00/CNTR1 CNTR1 active edge switch bit Data bus Timer A (low-order) latch (8) Timer A (low-order) (8) f(XIN)/16 Timer A operation mode bit Timer A count stop bit Fig. 28 Block diagram of timer 1 and timer A Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 32 of 82 Timer A (high-order) latch (8) Timer A (high-order) (8) Timer A interrupt request bit 7540 Group Data bus f(XIN)/16 f(XIN)/2 f(XIN) Timer X count source selection bits CNTR0 active edge switch bit “0” P14/CNTR0 Prescaler X latch (8) Timer X latch (8) Prescaler X (8) Timer X (8) Pulse width Timer mode measurement Pulse output mode mode Event counter mode Timer X count stop bit CNTR0 interrupt request bit “1” CNTR0 active “1” edge switch bit Q Toggle flip-flop T Q R “0” Port P14 latch Port P14 direction register Timer X interrupt request bit Writing to timer X latch Pulse output mode Pulse output mode P03/ TXOUT Port P03 latch Data bus P03/TXOUT output valid Port P03 direction register Prescaler Y latch (8) Timer Y primary latch (8) Timer Y secondary latch (8) Timer Y count source selection bits f(XIN)/16 Prescaler Y (8) Timer Y (8) f(XIN)/2 Timer Y count stop bit On-chip oscillator clock RING (on-chip oscillator output in Fig. 51, 52) Timer Y interrupt request bit Timer Y primary waveform extension control bit Q Toggle flip-flop T Waveform extension function Q P01/TYOUT Port P01 latch Port P01 direction register Timer Y output level latch Timer Y secondary waveform extension control bit Programmable waveform gengeration mode Data bus Prescaler Z latch (8) Timer Z count source selection bits f(XIN)/16 f(XIN)/2 Timer Z primary latch (8) Prescaler Z (8) Timer Z secondary latch (8) Timer Z (8) Programmable one-shot generation mode Programmable wait one-shot generation mode Timer Z count stop bit Timer Z one-shot start bit INT0 pin trigger active edge selection bit P37/INT0 INT0 interrupt request bit One-shot pulse trigger input Timer Z primary waveform extenstion control bit Q Port P02 latch Port P02 direction register Programmable waveform generation mode Programmable one-shot generation mode Programmable wait one-shot generation mode Fig. 29 Block diagram of timer X, timer Y and timer Z Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z Toggle flip flop T Waveform extension function Q P02/TZOUT page 33 of 82 Timer Z interrupt request bit Timer Z output level latch Timer Z secondary waveform extenstion control bit 7540 Group Serial I/O ●Serial I/O1 (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O1 mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6) to “1”. For clock synchronous serial I/O1, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB. Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. Data bus Serial I/O1 control register Address 0018 16 Receive buffer register Receive buffer full flag (RBF) Receive interrupt request (RI) Receive shift register P10/RXD1 Address 001A 16 Shift clock Clock control circuit P12/SCLK1 Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) BRG count source selection bit XIN Baud rate generator Address 001C16 1/4 P13/SRDY1 F/F 1/4 Clock control circuit Falling-edge detector Shift clock P11/TXD1 Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit shift register Transmit buffer register Address 0018 16 Transmit buffer empty flag (TBE) Serial I/O1 status register Address 0019 16 Data bus Fig. 30 Block diagram of clock synchronous serial I/O1 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD D0 D1 D2 D3 D4 D5 D6 D7 Serial input RxD D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal SRDY1 Write pulse to receive/transmit buffer register (address 0018 16) TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Fig. 31 Operation of clock synchronous serial I/O1 function Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 34 of 82 7540 Group The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. Data bus Address 0018 16 P10/RXD1 Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) Receive buffer register OE Character length selection bit ST detector 7 bits Receive shift register 1/16 8 bits PE FE UART control register Address 001B16 SP detector Clock control circuit Serial I/O1 synchronous clock selection bit P12/SCLK1 XIN BRG count source selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C 16 1/4 ST/SP/PA generator Transmit shift completion flag (TSC) 1/16 P11/TXD1 Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit shift register Character length selection bit Transmit buffer register Address 001816 Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Data bus Fig. 32 Block diagram of UART serial I/O1 Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD TBE=0 TSC=1✽ TBE=1 ST D0 D1 SP ST D0 Receive buffer read signal SP D1 ✽ 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) Generated at 2nd bit in 2-stop-bit mode RBF=0 RBF=1 Serial input RXD ST D0 D1 SP RBF=1 ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1.” 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Fig. 33 Operation of UART serial I/O1 function Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 35 of 82 7540 Group [Transmit buffer register/receive buffer register (TB/RB)] 001816 The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. [Serial I/O1 status register (SIO1STS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at reset, but if the transmit enable bit of the serial I/O1 control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Serial I/O1 control register (SIO1CON)] 001A16 The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART control register (UARTCON)] 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P11/TXD1 pin. [Baud rate generator (BRG)] 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 36 of 82 ■ Notes on serial I/O • Serial I/O interrupt When setting the transmit enable bit to “1”, the serial I/O transmit interrupt request bit is automatically set to “1”. When not requiring the interrupt occurrence synchronized with the transmission enabled, take the following sequence. ➀ Set the serial I/O transmit interrupt enable bit to “0” (disabled). ➁ Set the transmit enable bit to “1”. ➂ Set the serial I/O transmit interrupt request bit to “0” after 1 or more instructions have been executed. ➄ Set the serial I/O transmit interrupt enable bit to “1” (enabled). • I/O pin function when serial I/O1 is enabled. The functions of P12 and P13 are switched with the setting values of a serial I/O1 mode selection bit and a serial I/O1 synchronous clock selection bit as follows. (1) Serial I/O1 mode selection bit → “1” : Clock synchronous type serial I/O is selected. Setup of a serial I/O1 synchronous clock selection bit “0” : P12 pin turns into an output pin of a synchronous clock. “1” : P12 pin turns into an input pin of a synchronous clock. Setup of a SRDY1 output enable bit (SRDY) “0” : P13 pin can be used as a normal I/O pin. “1” : P13 pin turns into a SRDY output pin. (2) Serial I/O1 mode selection bit → “0” : Clock asynchronous (UART) type serial I/O is selected. Setup of a serial I/O1 synchronous clock selection bit “0”: P12 pin can be used as a normal I/O pin. “1”: P12 pin turns into an input pin of an external clock. When clock asynchronous (UART) type serial I/O is selected, it is P13 pin. It can be used as a normal I/O pin. 7540 Group b7 b0 Serial I/O1 status register (SIO1STS : address 0019 16, initial value: 00 16) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns “1” when read) b7 b0 UART control register (UARTCON : address 001B 16, initial value: E0 16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P11/TXD1 P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return “1” when read) Fig. 34 Structure of serial I/O1-related registers Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 37 of 82 b7 b0 Serial I/O1 control register (SIO1CON : address 001A 16, initial value: 00 16) BRG count source selection bit (CSS) 0: f(X IN) 1: f(X IN)/4 Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P1 3 pin operates as ordinary I/O pin 1: P1 3 pin operates as S RDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P1 0 to P1 3 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P1 0 to P1 3operate as serial I/O pins) 7540 Group ●Serial I/O2 The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2 the transmitter and the receiver must use the same clock. When the internal clock is used, transfer is started by a write signal to the serial I/O2 register. Note: Serial I/O2 can be used in the following cases; (1) Serial I/O1 is not used, (2) Serial I/O1 is used as UART and BRG output divided by 16 is selected as the synchronized clock. b7 b0 Serial I/O2 control register (SIO2CON: address 003016, initila value: 0016) Internal synchronous clock selection bits 000 : f(XIN)/8 001 : f(XIN)/16 010 : f(XIN)/32 011 : f(XIN)/64 110 : f(XIN)/128 111 : f(XIN)/256 SDATA2 pin selection bit (Note) 0 : I/O port / SDATA2 input 1 : SDATA2 output Not used (returns “0” when read) [Serial I/O2 control register] SIO2CON The serial I/O2 control register contains 8 bits which control various serial I/O functions. • Set “0” to bit 3 to receive. • At reception, clear bit 7 to “0” by writing a dummy data to the serial I/O2 register after completion of shift. Transfer direction selection bit 0 : LSB first 1 : MSB first SCLK2 pin selection bit 0 : External clock (SCLK2 is an input) 1 : Internal clock (SCLK2 is an output) Transmit / receive shift completion flag 0 : shift in progress 1 : shift completed Note : When using it as a SDATA input, set the port P13 direction register to “0”. Fig. 35 Structure of serial I/O2 control registers Data bus 1/8 1/16 1/32 Divider XIN SCLK2 pin selection bit 1/64 1/128 1/256 “1” SCLK “0” Internal synchronous clock selection bits SCLK2 pin selection bit “0” P12/SCLK2 P12 latch Serial I/O counter 2 (3) “1” SDATA2 pin selection bit “0” P13/SDATA2 P13 latch “1” SDATA2 pin selection bit Serial I/O shift register 2 (8) Fig. 36 Block diagram of serial I/O2 Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 38 of 82 Serial I/O2 interrupt request 7540 Group Serial I/O2 operation By writing to the serial I/O2 register (address 003116) the serial I/ O2 counter is set to “7”. After writing, the SDATA2 pin outputs data every time the transfer clock shifts from “H” to “L”. And, as the transfer clock shifts from “L” to “H”, the SDATA2 pin reads data, and at the same time the contents of the serial I/O2 register are shifted by 1 bit. When the internal clock is selected as the transfer clock source, the following operations execute as the transfer clock counts up to 8. • Serial I/O2 counter is cleared to “0”. • Transfer clock stops at an “H” level. • Interrupt request bit is set. • Shift completion flag is set. Also, the SDATA2 pin is in a high impedance state after the data transfer is completed (refer to Fig.37). When the external clock is selected as the transfer clock source, the interrupt request bit is set as the transfer clock counts up to 8, but external control of the clock is required since it does not stop. Notice that the SDATA2 pin is not in a high impedance state on the completion of data transfer. Also, after the receive operation is completed, the transmit/receive shift completion flag is cleared by reading the serial I/O2 register. At transmit, the transmit/receive shift completion flag is cleared and the transmit operation is started by writing to serial I/O2 register. Synchronous clock Transfer clock Serial I/O2 register write signal (Note) SDATA2 at serial I/O2 output transmit D0 D1 D2 D3 D4 D5 D6 D7 SDATA2 at serial I/O2 input receive Serial I/O2 interrupt request bit set Transmit/receive shift completion flag set Note : When the internal clock is selected as the transfer and the direction register of P1 3/SDATA2 pin is set to the input mode, the SDATA2 pin is in a high impedance state after the data transfer is completed. Fig. 37 Serial I/O2 timing (LSB first) Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 39 of 82 7540 Group A/D Converter (2) When V REF voltage is lower than [3.0 V], the accuracy at the low temperature may become extremely low compared with that at room temperature When the system would be used at low temperature, the use at V REF =3.0 V or more is recommended. The functional blocks of the A/D converter are described below. [A/D conversion register] AD The A/D conversion register is a read-only register that stores the result of A/D conversion. Do not read out this register during an A/ D conversion. b7 b0 A/D control register (ADCON : address 003416, initial value: 1016) [A/D control register] ADCON The A/D control register controls the A/D converter. Bit 2 to 0 are analog input pin selection bits. Bit 4 is the AD conversion completion bit. The value of this bit remains at “0” during A/D conversion, and changes to “1” at completion of A/D conversion. A/D conversion is started by setting this bit to “0”. Analog input pin selection bits 000 : P20/AN0 001 : P21/AN1 010 : P22/AN2 011 : P23/AN3 100 : P24/AN4 101 : P25/AN5 110 : P26/AN6 (Note) 111 : P27/AN7 (Note) Not used (returns “0” when read) AD conversion completion bit 0 : Conversion in progress 1 : Conversion completed Not used (returns “0” when read) [Comparison voltage generator] The comparison voltage generator divides the voltage between AVSS and VREF by 1024, and outputs the divided voltages. Note: These can be used only for 36 pin version. [Channel selector] The channel selector selects one of ports P2 7/AN 7 to P20/AN 0, and inputs the voltage to the comparator. Fig. 38 Structure of A/D control register [Comparator and control circuit] The comparator and control circuit compares an analog input voltage with the comparison voltage and stores its result into the A/D conversion register. When A/D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to “1”. Because the comparator is constructed linked to a capacitor, set f(XIN) to 500 kHz or more during A/D conversion. Read 8-bit (Read only address 003516) b7 (Address 003516) b9 b8 (Address 003516) b7 b6 b0 A/D interrupt request A/D control circuit Channel selector b2 b9 b8 b0 b0 b5 b4 b3 Fig. 39 Structure of A/D conversion register 3 A/D conversion register (high-order) (Address 003616) A/D conversion register (low-order) (Address 003516) 10 Resistor ladder VREF page 40 of 82 b3 b2 b1 b0 Note: High-order 6-bit of address 003616 returns “0” when read. b7 Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z b4 b7 A/D control register (Address 003416) Fig. 40 Block diagram of A/D converter b5 (Address 003616) Data bus Comparator b6 Read 10-bit (read in order address 003616, 003516) b7 ■ Note on A/D converter As for AD translation accuracy, on the following operating conditions, accuracy may become low. (1) Since the analog circuit inside a microcomputer becomes sensitive to noise when V REF voltage is set up lower than Vcc voltage, accuracy may become low rather than the case where VREF voltage and Vcc voltage are set up to the same value. P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 b7 b0 VSS 7540 Group Watchdog Timer The watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. The watchdog timer consists of an 8-bit watchdog timer H and an 8-bit watchdog timer L, being a 16-bit counter. Standard operation of watchdog timer The watchdog timer stops when the watchdog timer control register (address 0039 16) is not set after reset. Writing an optional value to the watchdog timer control register (address 0039 16) causes the watchdog timer to start to count down. When the watchdog timer H underflows, an internal reset occurs. Accordingly, it is programmed that the watchdog timer control register (address 003916) can be set before an underflow occurs. When the watchdog timer control register (address 0039 16) is read, the values of the high-order 6-bit of the watchdog timer H, STP instruction disable bit and watchdog timer H count source selection bit are read. Operation of watchdog timer H count source selection bit A watchdog timer H count source can be selected by bit 7 of the watchdog timer control register (address 003916). When this bit is “0”, the count source becomes a watchdog timer L underflow signal. The detection time is 131.072 ms at f(XIN)=8 MHz. When this bit is “1”, the count source becomes f(XIN)/16. In this case, the detection time is 512 µs at f(XIN)=8 MHz. This bit is cleared to “0” after reset. Operation of STP instruction disable bit When the watchdog timer is in operation, the STP instruction can be disabled by bit 6 of the watchdog timer control register (address 003916). When this bit is “0”, the STP instruction is enabled. When this bit is “1”, the STP instruction is disabled, and an internal reset occurs if the STP instruction is executed. Once this bit is set to “1”, it cannot be changed to “0” by program. This bit is cleared to “0” after reset. Initial value of watchdog timer By a reset or writing to the watchdog timer control register (address 0039 16 ), the watchdog timer H is set to “FF 16” and the watchdog timer L is set to “FF16”. Data bus Write “FF16” to the watchdog timer control register Watchdog timer L (8) 1/16 XIN “0” “1” Watchdog timer H (8) Write "FF16" to the watchdog timer control register Watchdog timer H count source selection bit STP Instruction disable bit STP Instruction Reset circuit RESET Internal reset Fig. 41 Block diagram of watchdog timer b7 b0 Watchdog timer control register (WDTCON: address 0039 16, initial value: 3F 16) Watchdog timer H (read only for high-order 6-bit) STP instruction disable bit 0 : STP instruction enabled 1 : STP instruction disabled Watchdog timer H count source selection bit 0 : Watchdog timer L underflow 1 : f(XIN)/16 Fig. 42 Structure of watchdog timer control register Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 41 of 82 7540 Group Reset Circuit Poweron The microcomputer is put into a reset status by holding the RESET pin at the “L” level for 2 µs or more when the power source voltage is 2.2 to 5.5 V and XIN is in stable oscillation. After that, this reset status is released by returning the RESET pin to the “H” level. The program starts from the address having the contents of address FFFD16 as high-order address and the contents of address FFFC16 as low-order address. In the case of f(φ) ≤ 6 MHz, the reset input voltage must be 0.9 V or less when the power source voltage passes 4.5 V. In the case of f(φ) ≤ 4 MHz, the reset input voltage must be 0.8 V or less when the power source voltage passes 4.0 V. In the case of f(φ) ≤ 2 MHz, the reset input voltage must be 0.48 V or less when the power source voltage passes 2.4 V. In the case of f(φ) ≤ 1 MHz, the reset input voltage must be 0.44 V or less when the power source voltage passes 2.2 V. RESET VCC Power source voltage 0V Reset input voltage 0V (Note) 0.2 VCC Note : Reset release voltage Vcc = 2.2 V RESET VCC Power source voltage detection circuit Fig. 43 Example of reset circuit Clock from on-chip oscillator RING φ RESET RESETOUT SYNC Address ? Data ? ? 8-13 clock cycles Fig. 44 Timing diagram at reset Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 42 of 82 ? ? ? ? FFFC ? ? ? FFFD ADL ADH,ADL ADH Reset address from the vector table Notes 1 : An on-chip oscillator applies about RING•2 MHz, φ•250 kHz frequency clock at average of Vcc = 5 V. 2 : The mark “?” means that the address is changeable depending on the previous state. 3 : These are all internal signals except RESET. 7540 Group Address (1) Port P0 direction register 000116 (2) Port P1 direction register 000316 Register contents 0016 X X X 0 0 (3) Port P2 direction register 000516 0016 (4) Port P3 direction register 000716 0016 (5) Pull-up control register 001616 0016 (6) Port P1P3 control register 001716 0016 (7) Serial I/O1 status register 001916 1 0 0 0 0 001A16 (9) UART control register 001B16 (10) Timer A mode register 001D16 0016 (11) Timer A (low-order) 001E16 FF16 (12) Timer A (high-order) 001F16 FF16 (13) Timer Y, Z mode register 002016 0016 (14) Prescaler Y 002116 FF16 (15) Timer Y secondary 002216 FF16 (16) Timer Y primary 002316 FF16 (17) Timer Y, Z waveform output control register 002416 0016 (18) Prescaler Z 002516 FF16 (19) Timer Z secondary 002616 FF16 (20) Timer Z primary 002716 FF16 (21) Prescaler 1 002816 FF16 (22) Timer 1 002916 0116 (23) One-shot start register 002A16 0016 (24) Timer X mode register 002B16 0016 (25) Prescaler X 002C16 FF16 (26) Timer X 002D16 FF16 (27) Timer count source set register 002E16 0016 (28) Serial I/O2 control register 003016 0016 (29) Serial I/O2 register 003116 0016 (30) A/D control register 003416 1016 (31) MISRG 003816 0016 (32) Watchdog timer control register 003916 (33) Interrupt edge selection register 003A16 (34) CPU mode register 003B16 1 0 1 0 1 1 0 1 0 1 1 0 0 0 0 (35) Interrupt request register 1 003C16 (36) Interrupt request register 2 003D16 0016 (37) Interrupt control register 1 003E16 0016 (38) Interrupt control register 2 003F16 0016 (40) Program counter 0 0 0 0 0 0 0 1 1 1 0 0 0 1 X X 0016 0016 (PS) 0 0016 (8) Serial I/O1 control register (39) Processor status register 0 X X X X X (PCH) Contents of address FFFD16 (PCL) Contents of address FFFC16 Note X : Undefined Fig. 45 Internal status of microcomputer at reset Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 43 of 82 7540 Group Clock Generating Circuit An oscillation circuit can be formed by connecting a resonator between XIN and XOUT, and an RC oscillation circuit can be formed by connecting a resistor and a capacitor. Use the circuit constants in accordance with the resonator manufacturer's recommended values. Note: Externally connect a M37540 XI N XOUT Rd (1) On-chip oscillator operation When the MCU operates by the on-chip oscillator for the main clock, connect XIN pin to VSS and leave XOUT pin open. The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. (2) Ceramic resonator When the ceramic resonator is used for the main clock, connect the ceramic resonator and the external circuit to pins X IN and XOUT at the shortest distance. A feedback resistor is built in between pins XIN and XOUT. (3) RC oscillation When the RC oscillation is used for the main clock, connect the XIN pin and XOUT pin to the external circuit of resistor R and the capacitor C at the shortest distance. The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits. COUT CIN damping resistor Rd depending on the oscillation frequency. (A feedback resistor is built-in.) Use the resonator manufacturer’s recommended value because constants such as capacitance depend on the resonator. Fig. 46 External circuit of ceramic resonator Note: Connect the external M37540 XI N XOUT circuit of resistor R and the capacitor C at the shortest distance. The frequency is affected by a capacitor, a resistor and a microR computer. So, set the constants C within the range of the frequency limits. Fig. 47 External circuit of RC oscillation (4) External clock When the external signal clock is used for the main clock, connect the XIN pin to the clock source and leave XOUT pin open. M37540 XIN XOUT External oscillation circuit Open VCC VSS Fig. 48 External clock input circuit M37540 XI N Note: The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable freXOUT quencies and obtain the Open sufficient margin. Fig. 49 Processing of XIN and XOUT pins at on-chip oscillator operation Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 44 of 82 7540 Group (1) Oscillation control • Stop mode When the STP instruction is executed, the internal clock φ stops at an “H” level and the XIN oscillator stops. At this time, timer 1 is set to “0116” and prescaler 1 is set to “FF16” when the oscillation stabilization time set bit after release of the STP instruction is “0”. On the other hand, timer 1 and prescaler 1 are not set when the above bit is “1”. Accordingly, set the wait time fit for the oscillation stabilization time of the oscillator to be used. f(XIN)/16 is forcibly connected to the input of prescaler 1. When an external interrupt is accepted, oscillation is restarted but the internal clock φ remains at “H” until timer 1 underflows. As soon as timer 1 underflows, the internal clock φ is supplied. This is because when a ceramic oscillator is used, some time is required until a start of oscillation. In case oscillation is restarted by reset, no wait time is generated. So apply an “L” level to the RESET pin while oscillation becomes stable. Also, the STP instruction cannot be used while CPU is operating by an on-chip oscillator. ● Oscillation stop detection circuit (Note) • Wait mode If the WIT instruction is executed, the internal clock φ stops at an “H” level, but the oscillator does not stop. The internal clock restarts if a reset occurs or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that interrupts will be received to release the STP or WIT state, interrupt enable bits must be set to “1” before the STP or WIT instruction is executed. Ceramic or RC oscillation stop detection function active bit 0: Detection function inactive 1: Detection function active ■ Notes on clock generating circuit For use with the oscillation stabilization set bit after release of the STP instruction set to “1”, set values in timer 1 and prescaler 1 after fully appreciating the oscillation stabilization time of the oscillator to be used. • Switch of ceramic and RC oscillations After releasing reset the operation starts by starting an on-chip oscillator. Then, a ceramic oscillation or an RC oscillation is selected by setting bit 5 of the CPU mode register. • Double-speed mode When a ceramic oscillation is selected, a double-speed mode can be used. Do not use it when an RC oscillation is selected. • CPU mode register Bits 5, 1 and 0 of CPU mode register are used to select oscillation mode and to control operation modes of the microcomputer. In order to prevent the dead-lock by error-writing (ex. program run-away), these bits can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. (The emulator MCU “M37540RSS” is excluded.) Also, when the read-modify-write instructions (SEB, CLB) are executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked. • Clock division ratio, XIN oscillation control, on-chip oscillator control The state transition shown in Fig. 52 can be performed by setting the clock division ratio selection bits (bits 7 and 6), XIN oscillation control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of CPU mode register. Be careful of notes on use in Fig. 52. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 45 of 82 The oscillation stop detection circuit is used for reset occurrence when a ceramic resonator or an oscillation circuit stops by disconnection. When internal reset occurs, reset because of oscillation stop can be detected by setting “1” to the oscillation stop detection status bit. Also, when using the oscillation stop detection circuit, an on-chip oscillator is required. Figure 53 shows the state transition. Note: The oscillation stop detection circuit is not included in the emulator MCU “M37540RSS”. b7 b0 MISRG(address 0038 16, initial value: 00 16) Oscillation stabilization time set bit after release of the STP instruction 0: Set “0116” in timer1, and “FF 16” in prescaler 1 automatically 1: Not set automatically Reserved bits (return “0” when read) (Do not write “1” to these bits) Not used (return “0” when read) Oscillation stop detection status bit 0: Oscillation stop not detected 1: Oscillation stop detected Fig. 50 Structure of MISRG 7540 Group XIN XOUT Rf Clock division ratio selection bit Middle-, high-, low-speed mode 1/2 Timer 1 Prescaler 1 1/2 1/4 On-chip oscillator mode Clock division ratio selection bit Middle-speed mode Timing φ (Internal clock) High-speed mode Double-speed mode RING 1/8 On-chip oscillator On-chip oscillator mode Q S Q S WIT instruction STP instruction R S Q R RESET R STP instruction Reset Interrupt disable flag l Interrupt request Fig. 51 Block diagram of internal clock generating circuit (for ceramic resonator) XOUT XIN Clock division ratio selection bit Middle-, high-, low-speed mode 1/2 1/2 1/4 Prescaler 1 Timer 1 On-chip oscillator mode Delay Clock division ratio selection bit Middle-speed mode Timing φ (Internal clock) High-speed mode Double-speed mode RING On-chip oscillator 1/8 On-chip oscillator mode S Q S STP instruction R WIT instruction Q R Reset Interrupt disable flag l Interrupt request Fig. 52 Block diagram of internal clock generating circuit (for RC oscillation) Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 46 of 82 Q S RESET R STP instruction 7540 Group Stop mode Wait mode Interrupt WIT instruction Interrupt STP instruction State 1 Operation clock source: f(XIN) (Note 1) f(XIN) oscillation enabled On-chip oscillator stop CPUM3←02 CPUM3←12 Interrupt WIT instruction State 2 CPUM76←102 Operation clock source: f(XIN) (Note 1) f(XIN) oscillation enabled On-chip oscillator enabled CPUM76←002 State 3 Operation clock source: On-chip oscillator (Note 3) f(XIN) oscillation enabled On-chip oscillator enalbed 012 112 (Note 2) MISRG1←12 MISRG1←02 MISRG1←12 State 2’ CPUM76←102 Operation clock source: f(XIN) (Note 1) On-chip oscillator enabled CPUM76←002 012 112 (Note 2) Oscillation stop detection circuit valid MISRG1←02 State 3’ Operation clock source: On-chip oscillator (Note 3) f(XIN) oscillation enabled On-chip oscillator enalbed Reset released Reset state Fig. 53 State transition Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 47 of 82 CPUM4←12 CPUM4←02 State 4 Operation clock source: On-chip oscillator (Note 3) f(XIN) oscillation stop On-chip oscillator enalbed Notes on switch of clock (1) In operation clock source = f(XIN), the following can be selected for the CPU clock division ratio. ● f(XIN)/2 (high-speed mode) ● f(XIN)/8 (middle-speed mode) ● f(XIN) (double-speed mode, only at a ceramic oscillation) (2) Execute the state transition state 3 to state 2 or state 3’ to state 2’ after stabilizing XIN oscillation. (3) In operation clock source = on-chip oscillator, the middlespeed mode is selected for the CPU clock division ratio. (4) When the state transition state 2 → state 3 → state 4 is performed, execute the NOP instruction as shown below according to the division ratio of CPU clock. • CPUM76 → 102 (State 2 → state 3) • NOP instruction • CPUM4 → 12 (State 3 → state 4) Double-speed mode at on-chip oscillator: NOP ✕ 3 High-speed mode at on-chip oscillator: NOP ✕ 1 Middle-speed mode at on-chip oscillator: NOP ✕ 0 7540 Group NOTES ON PROGRAMMING State transition Processor Status Register Do not stop the clock selected as the operation clock because of setting of CM3, 4. The contents of the processor status register (PS) after reset are undefined except for the interrupt disable flag I which is “1”. After reset, initialize flags which affect program execution. In particular, it is essential to initialize the T flag and the D flag because of their effect on calculations. Interrupts The contents of the interrupt request bit do not change even if the BBC or BBS instruction is executed immediately after they are changed by program because this instruction is executed for the previous contents. For executing the instruction for the changed contents, execute one instruction before executing the BBC or BBS instruction. Decimal Calculations • For calculations in decimal notation, set the decimal mode flag D to “1”, then execute the ADC instruction or SBC instruction. In this case, execute SEC instruction, CLC instruction or CLD instruction after executing one instruction before the ADC instruction or SBC instruction. • In the decimal mode, the values of the N (negative), V (overflow) and Z (zero) flags are invalid. Ports • The values of the port direction registers cannot be read. That is, it is impossible to use the LDA instruction, memory operation instruction when the T flag is “1”, addressing mode using direction register values as qualifiers, and bit test instructions such as BBC and BBS. It is also impossible to use bit operation instructions such as CLB and SEB and read/modify/write instructions of direction registers for calculations such as ROR. For setting direction registers, use the LDM instruction, STA instruction, etc. A/D Conversion Do not execute the STP instruction during A/D conversion. Instruction Execution Timing The instruction execution time can be obtained by multiplying the frequency of the internal clock φ by the number of cycles mentioned in the machine-language instruction table. The frequency of the internal clock φ is the same as that of the XIN in double-speed mode, twice the X IN cycle in high-speed mode and 8 times the XIN cycle in middle-speed mode. CPU Mode Register The oscillation mode selection bit and processor mode bits can be rewritten only once after releasing reset. However, after rewriting it is disable to write any value to the bit. (Emulator MCU is excluded.) When a ceramic oscillation is selected, a double-speed mode of the clock division ratio selection bits can be used. Do not use it when an RC oscillation is selected. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 48 of 82 NOTES ON HARDWARE Handling of Power Source Pin In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 µF to 0.1 µF is recommended. One Time PROM Version The CNVss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (VPP pin) as well. To improve the noise reduction, connect a track between CNVss pin and Vss pin with 1 to 10 kΩ resistance. The mask ROM version track of CNVss pin has no operational interference even if it is connected via a resistor. 7540 Group NOTES ON PERIPHERAL FUNCTIONS ■ Interrupt • Timer Y write mode When using this mode, be sure to set “1” to the timer Y write control bit to select “write to latch only”. When setting the followings, the interrupt request bit may be set to “1”. •When setting external interrupt active edge Related register: Interrupt edge selection register (address 003A16) Timer X mode register (address 2B16) Timer A mode register (address 1D16) Timer Y can stop counting by setting “1” to the timer Y count stop bit in any mode. Also, when Timer Y underflows, the timer Y interrupt request bit is set to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ➀ Set the corresponding interrupt enable bit to “0” (disabled). ➁ Set the interrupt edge select bit (active edge switch bit) to “1”. ➂ Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the corresponding interrupt enable bit to “1” (enabled). ■ Timers • When n (0 to 255) is written to a timer latch, the frequency division ratio is 1/(n+1). • When a count source of timer X, timer Y or timer Z is switched, stop a count of timer X. ■ Timer A CNTR1 interrupt active edge selection CNTR1 interrupt active edge depends on the CNTR1 active edge switch bit. When this bit is “0”, the CNTR1 interrupt request bit is set to “1” at the falling edge of the CNTR1 pin input signal. When this bit is “1”, the CNTR1 interrupt request bit is set to “1” at the rising edge of the CNTR1 pin input signal. However, in the pulse width HL continuously measurement mode, CNTR 1 interrupt request is generated at both rising and falling edges of CNTR 1 pin input signal regardless of the setting of CNTR1 active edge switch bit. ■ Timer X CNTR0 interrupt active edge selection CNTR0 interrupt active edge depends on the CNTR0 active edge switch bit. When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at the falling edge of CNTR0 pin input signal. When this bit is “1”, the CNTR0 interrupt request bit is set to “1” at the rising edge of CNTR0 pin input signal. ■ Timer Y: Programmable Generation Waveform Mode • Count set value In the programmable waveform generation mode, values of TYS, EXPYP, and EXPYS are valid by writing to TYP because the setting to them is executed all at once by writing to TYP. Even when changing TYP is not required, write the same value again. • Write timing to TYP In the programmable waveform generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TYP and the timing of timer underflow during the secondary interval simultanesously. • Usage of waveform extension function The waveform extension function by the timer Y waveform extension control bit can be used only when “0016” is set to Prescaler Y. When the value other than “0016” is set to Prescaler Y, be sure to set “0” to EXPYP and EXPYS. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 49 of 82 Timer Y reloads the value of latch when counting is stopped by the timer Y count stop bit. (When timer is read out while timer is stopped, the value of latch is read. The value of timer can be read out only while timer is operating.) ■ Ti m e r Z : P r o g r a m m a b l e Wa v e f o r m Generation Mode • Count set value In the programmable waveform generation mode, values of TZS, EXPZP, and EXPZS are valid by writing to TZP because the setting to them is executed all at once by writing to TZP. Even when changing TZP is not required, write the same value again. • Write timing to TZP In the programmable waveform generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow during the secondary interval simultanesously. • Usage of waveform extension function The waveform extension function by the timer Z waveform extension control bit can be used only when “0016” is set to Prescaler Z. When the value other than “0016” is set to Prescaler Z, be sure to set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the count source, the waveform extension function cannot be used. • Timer Z write mode When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”. ■ Ti m e r Z : P r o g r a m m a b l e O n e - s h o t Generation Mode • Count set value In the programmable one-shot generation mode, the value of EXPZP becomes valid by writing to TZP. Even when changing TZP is not required, write the same value again. • Write timing to TZP In the programmable one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow simultanesously. • Usage of waveform extension function The waveform extension function by the timer Z waveform extension control bit can be used only when “0016” is set to Prescaler Z. When the value other than “0016” is set to Prescaler Z, be sure to set “0” to EXPZP. Also, when the timer Y underflow is selected as the count source, the waveform extension function cannot be used. • Timer Z write mode When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”. 7540 Group ■ Timer Z: Programmable Wait One-shot Generation Mode • Count set value In the programmable wait one-shot generation mode, values of TZS, EXPZP and EXPZS are valid by writing to TZP. Even when changing TZP is not required, write the same value again. • Write timing to TZP In the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow during the secondary interval simultanesously. • Usage of waveform extension function The waveform extension function by the timer Z waveform extension control bit can be used only when “0016” is set to Prescaler Z. When the value other than “0016” is set to Prescaler Z, be sure to set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the count source, the waveform extension function cannot be used. • Timer Z write mode When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”. Timer Z can stop counting by setting “1” to the timer Z count stop bit in any mode. Also, when Timer Z underflows, the timer Z interrupt request bit is set to “1”. Timer Z reloads the value of latch when counting is stopped by the timer Z count stop bit. (When timer is read out while timer is stopped, the value of latch is read. The value of timer can be read out only while timer is operating.) (2) Serial I/O1 mode selection bit → “0” : Clock asynchronous (UART) type serial I/O is selected. Setup of a serial I/O1 synchronous clock selection bit “0”: P12 pin can be used as a normal I/O pin. “1”: P12 pin turns into an input pin of an external clock. When clock asynchronous (UART) type serial I/O is selected, it is P13 pin. It can be used as a normal I/O pin. ■ A/D Converter • The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(XIN) is 500kHz or more during A/D conversion. • As for AD translation accuracy, on the following operating conditions, accuracy may become low. (1) Since the analog circuit inside a microcomputer becomes sensitive to noise when V REF voltage is set up lower than Vcc voltage, accuracy may become low rather than the case where VREF voltage and Vcc voltage are set up to the same value. (2) When VREF voltage is lower than [3.0 V], the accuracy at the low temperature may become extremely low compared with that at room temperature When the system would be used at low temperature, the use at VREF=3.0 V or more is recommended. ■ Notes on clock generating circuit For use with the oscillation stabilization set bit after release of the STP instruction set to “1”, set values in timer 1 and prescaler 1 after fully appreciating the oscillation stabilization time of the oscillator to be used. • Switch of ceramic and RC oscillations After releasing reset the operation starts by starting an on-chip oscillator. Then, a ceramic oscillation or an RC oscillation is selected by setting bit 5 of the CPU mode register. ■ Serial I/O • Serial I/O interrupt When setting the transmit enable bit to “1”, the serial I/O transmit interrupt request bit is automatically set to “1”. When not requiring the interrupt occurrence synchronized with the transmission enabled, take the following sequence. ➀ Set the serial I/O transmit interrupt enable bit to “0” (disabled). ➁ Set the transmit enable bit to “1”. ➂ Set the serial I/O transmit interrupt request bit to “0” after 1 or more instructions have been executed. ➄ Set the serial I/O transmit interrupt enable bit to “1” (enabled). • I/O pin function when serial I/O1 is enabled. The functions of P12 and P13 are switched with the setting values of a serial I/O1 mode selection bit and a serial I/O1 synchronous clock selection bit as follows. (1) Serial I/O1 mode selection bit → “1” : Clock synchronous type serial I/O is selected. Setup of a serial I/O1 synchronous clock selection bit “0” : P12 pin turns into an output pin of a synchronous clock. “1” : P12 pin turns into an input pin of a synchronous clock. Setup of a SRDY1 output enable bit (SRDY) “0” : P13 pin can be used as a normal I/O pin. “1” : P13 pin turns into a SRDY output pin. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 50 of 82 • Double-speed mode When a ceramic oscillation is selected, a double-speed mode can be used. Do not use it when an RC oscillation is selected. • CPU mode register Bits 5, 1 and 0 of CPU mode register are used to select oscillation mode and to control operation modes of the microcomputer. In order to prevent the dead-lock by error-writing (ex. program run-away), these bits can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. (The emulator MCU “M37540RSS” is excluded.) Also, when the read-modify-write instructions (SEB, CLB) are executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked. • Clock division ratio, XIN oscillation control, on-chip oscillator control The state transition shown in Fig. 53 can be performed by setting the clock division ratio selection bits (bits 7 and 6), XIN oscillation control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of CPU mode register. Be careful of notes on use in Fig. 53. • On-chip oscillator operation The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. 7540 Group ■ Note on Power Source Voltage ROM PROGRAMMING METHOD When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. The built-in PROM of the blank One Time PROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. ■ Electric Characteristic Differences Among Mask ROM and One TIme PROM Version MCUs There are differences in electric characteristics, operation margin, noise immunity, and noise radiation among mask ROM and One Time PROM version MCUs due to the differences in the manufacturing processes. When manufacturing an application system with One Time PROM version and then switching to use of the mask ROM version, perform sufficient evaluations for the commercial samples of the mask ROM version. DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: 1.Mask ROM Order Confirmation Form * 2.Mark Specification Form * 3.Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk. DATA REQUIRED FOR ROM PROGRAMMING ORDERS The following are necessary when ordering a One Time PROM production: 1.ROM Programming Order Confirmation Form * 2.Mark Specification Form * 3.Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk. * For the mask ROM confirmation and the mark specifications, refer to the "Renesas Technology Corp." Homepage (http://www.renesas.com/en/rom). Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 51 of 82 Table 7 Special programming adapter Package 32P4B 32P6U-A 36P2R-A Name of Programming Adapter PCA7435SPG02 PCA7435GPG03 PCA7435FPG02 The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 54 is recommended to verify programming. Programming with PROM programmer Screening (Caution) (150 °C for 40 hours) Verification with PROM programmer Functional check in target device Caution: The screening temperature is far higher than the storage temperature. Never expose to 150 °C exceeding 100 hours. Fig. 54 Programming and testing of One Time PROM version 7540 Group ELECTRICAL CHARACTERISTICS 1.7540Group (General purpose) Applied to: M37540M2-XXXFP/SP/GP, M37540M4-XXXFP/SP/GP, M37540E2FP/SP/GP, M37540E8FP/SP/GP Absolute Maximum Ratings (General purpose) Table 8 Absolute maximum ratings Symbol VCC VI VI VI VO Pd Topr Tstg Parameter Power source voltage Input voltage P00–P07, P10–P14, P20–P27, P30–P37, VREF Input voltage RESET, XIN Input voltage CNVSS (Note 2) Output voltage P00–P07, P10–P14, P20–P27, P30–P37, XOUT Power dissipation Operating temperature Storage temperature Conditions All voltages are based on VSS. Output transistors are cut off. Ta = 25°C Notes 1: This is the rating value for the Mask ROM version. The rating value for the One Time PROM version is –0.3 to 7.0 V. 2: It is a rating only for the One Time PROM version. Connect to VSS for the mask ROM version. 3: 200 mW for the 32P6U package product. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 52 of 82 Ratings –0.3 to 6.5 (Note 1) –0.3 to VCC + 0.3 Unit V V –0.3 to VCC + 0.3 –0.3 to 13 –0.3 to VCC + 0.3 V V V 300 (Note 3) –20 to 85 –40 to 125 mW °C °C 7540 Group Recommended Operating Conditions (General purpose) Table 9 Recommended operating conditions (1) (VCC = 2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol VCC Parameter Power source voltage (ceramic) Power source voltage (RC) VSS VREF VIH VIH VIH VIL VIL VIL VIL ∑IOH(peak) ∑IOL(peak) ∑IOL(peak) ∑IOH(avg) ∑IOL(avg) ∑IOL(avg) f(XIN) = 8 MHz (High-, Middle-speed mode) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 2 MHz (High-, Middle-speed mode) f(XIN) = 6 MHz (Double-speed mode) f(XIN) = 4 MHz (Double-speed mode) f(XIN) = 2 MHz (Double-speed mode) f(XIN) = 1 MHz (Double-speed mode) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 2 MHz (High-, Middle-speed mode) f(XIN) = 1 MHz (High-, Middle-speed mode) Power source voltage Analog reference voltage “H” input voltage P00–P07, P10–P14, P20–P27, P30–P37 “H” input voltage (TTL input level selected) P10, P12, P13, P36, P37 (Note 1) “H” input voltage RESET, XIN “L” input voltage P00–P07, P10–P14, P20–P27, P30–P37 “L” input voltage (TTL input level selected) P10, P12, P13, P36, P37 (Note 1) “L” input voltage RESET, CNVSS “L” input voltage XIN “H” total peak output current (Note 2) P00–P07, P10–P14, P20–P27, P30–P37 “L” total peak output current (Note 2) P00–P07, P10–P14, P20–P27, P37 “L” total peak output current (Note 2) P30–P36 “H” total average output current (Note 2) P00–P07, P10–P14, P20–P27, P30–P37 “L” total average output current (Note 2) P00–P07, P10–P14, P20–P27, P37 “L” total average output current (Note 2) P30–P36 Limits Min. 4.0 2.4 2.2 4.5 4.0 2.4 2.2 4.0 2.4 2.2 Typ. 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 Unit 2.0 0.8VCC VCC V V V V V V V V V V V V V 2.0 VCC V 0.8VCC VCC V 0 0.3VCC V 0 0.8 V 0 0.2VCC V 0 0.16VCC V –80 mA 80 mA 60 mA –40 mA 40 mA 30 mA VCC Note 1: Vcc = 4.0 to 5.5V 2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 53 of 82 7540 Group Recommended Operating Conditions (General purpose)(continued) Table 10 Recommended operating conditions (2) (VCC = 2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) Limits Parameter Min. “H” peak output current (Note 1) P00–P07, P10–P14, P20–P27, P30–P37 “L” peak output current (Note 1) P00–P07, P10–P14, P20–P27, P37 “L” peak output current (Note 1) P30–P36 “H” average output current (Note 2) P00–P07, P10–P14, P20–P27, P30–P37 “L” average output current (Note 2) P00–P07, P10–P14, P20–P27, P37 “L” average output current (Note 2) P30–P36 Internal clock oscillation frequency (Note 3) VCC = 4.5 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) VCC = 2.2 to 5.5 V at ceramic oscillation or external clock input Internal clock oscillation frequency (Note 3) at ceramic oscillation or external clock input Internal clock oscillation frequency (Note 3) at ceramic oscillation or external clock input Internal clock oscillation frequency (Note 3) at ceramic oscillation or external clock input Internal clock oscillation frequency (Note 3) at RC oscillation Internal clock oscillation frequency (Note 3) at RC oscillation Internal clock oscillation frequency (Note 3) at RC oscillation Double-speed mode VCC = 4.0 to 5.5 V High-, Middle-speed mode VCC = 2.4 to 5.5 V High-, Middle-speed mode VCC = 2.2 to 5.5 V High-, Middle-speed mode VCC = 4.0 to 5.5 V High-, Middle-speed mode VCC = 2.4 to 5.5 V High-, Middle-speed mode VCC = 2.2 to 5.5 V High-, Middle-speed mode Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50 %. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 54 of 82 Typ. Unit Max. –10 10 30 –5 5 15 6 mA mA mA mA mA mA MHz 4 MHz 2 MHz 1 MHz 8 MHz 4 MHz 2 MHz 4 MHz 2 MHz 1 MHz 7540 Group Electrical Characteristics (General purpose) Table 11 Electrical characteristics (1) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol VOH VOL VOL VT+–VT– VT+–VT– VT+–VT– IIH IIH IIH IIL IIL IIL IIL VRAM ROSC DOSC Parameter “H” output voltage P00–P07, P10–P14, P20–P27, P30–P37 (Note 1) “L” output voltage P00–P07, P10–P14, P20–P27, P37 “L” output voltage P30–P36 Hysteresis CNTR0, CNTR1, INT0, INT1(Note 2) P00–P07 (Note 3) Hysteresis RXD, SCLK1, SCLK2, SDATA2 (Note 2) Hysteresis RESET “H” input current P00–P07, P10–P14, P20–P27, P30–P37 “H” input current RESET “H” input current XIN “L” input current P00–P07, P10–P14, P20–P27, P30–P37 “L” input current RESET, CNVSS “L” input current XIN “L” input current P00–P07, P30–P37 RAM hold voltage On-chip oscillator oscillation frequency Oscillation stop detection circuit detection frequency Test conditions IOH = –5 mA VCC = 4.0 to 5.5 V IOH = –1.0 mA VCC = 2.2 to 5.5 V IOL = 5 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 2.2 to 5.5 V IOL = 15 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 10 mA VCC = 2.2 to 5.5 V Min. Typ. Max. Unit VCC–1.5 V VCC–1.0 V V 0.3 V 1.0 V 2.0 V 0.3 V 1.0 V 0.4 V 0.5 V 0.5 V VI = VCC (Pin floating. Pull up transistors “off”) VI = VCC VI = VCC 1.5 5.0 µA 5.0 µA µA 4.0 VI = VSS (Pin floating. Pull up transistors “off”) VI = VSS –5.0 µA –5.0 µA µA VI = VSS –4.0 VI = VSS (Pull up transistors “on”) When clock stopped VCC = 5.0 V, Ta = 25 °C VCC = 5.0 V, Ta = 25 °C –0.2 –0.5 mA 2000 125 5.5 3000 187.5 V kHz kHz 2.0 1000 62.5 Notes 1: P11 is measured when the P11/TXD1 P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: RXD1, SCLK1, SCLK2, SDATA2, INT0, and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to “0” (CMOS level). 3: It is available only when operating key-on wake up. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 55 of 82 7540 Group Electrical Characteristics (General purpose)(continued) Table 12 Electrical characteristics (2) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol ICC Parameter Power source current Test conditions One Time PROM version Mask ROM version Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 56 of 82 High-speed mode, f(XIN) = 8 MHz Output transistors “off” High-speed mode, f(XIN) = 2 MHz, VCC = 2.2 V Output transistors “off” Double-speed mode, f(XIN) = 6 MHz Output transistors “off” Middle-speed mode, f(XIN) = 8 MHz Output transistors “off” On-chip oscillator operation mode, VCC = 5 V Output transistors “off” f(XIN) = 8 MHz (in WIT state), functions except timer 1 disabled, Output transistors “off” f(XIN) = 2 MHz, VCC = 2.2 V (in WIT state), functions except timer 1 disabled, Output transistors “off” On-chip oscillator operation mode, VCC = 5V Output transistors “off” Increment when A/D conversion is executed f(XIN) = 8 MHz, VCC = 5 V All oscillation stopped Ta = 25 °C (in STP state) Ta = 85 °C Output transistors “off” High-speed mode, f(XIN) = 8 MHz Output transistors “off” High-speed mode, f(XIN) = 2 MHz, VCC = 2.2 V Output transistors “off” Double-speed mode, f(XIN) = 6 MHz Output transistors “off” Middle-speed mode, f(XIN) = 8 MHz Output transistors “off” On-chip oscillator operation mode, VCC = 5 V Output transistors “off” f(XIN) = 8 MHz (in WIT state), functions except timer 1 disabled, Output transistors “off” f(XIN) = 2 MHz, VCC = 2.2 V (in WIT state), functions except timer 1 disabled, Output transistors “off” On-chip oscillator operation mode, VCC = 5V Output transistors “off” Increment when A/D conversion is executed f(XIN) = 8 MHz, VCC = 5 V Ta = 25 °C All oscillation stopped (in STP state) Ta = 85 °C Output transistors “off” Min. Unit Typ. Max. 5.0 8.0 mA 0.5 1.5 mA 6.0 10.0 mA 2.0 5.0 mA 350 1000 µA 1.6 3.2 mA 0.2 150 mA 450 0.5 µA mA 0.1 1.0 10 µA µA 3.5 6.5 mA 0.4 1.2 mA 4.5 8.0 mA 2.0 5.0 mA 300 900 µA 1.6 3.2 mA 0.2 150 mA 450 0.5 0.1 µA mA 1.0 10 µA µA 7540 Group A/D Converter Characteristics (General purpose) Table 13 A/D Converter characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol One Time PROM version Parameter — — Resolution Linearity error — Differential nonlinear error VOT Zero transition voltage VFST Full scale transition voltage tCONV Conversion time RLADDER Ladder resistor IVREF Reference power source input current Mask ROM version II(AD) — — A/D port input current Resolution Linearity error — Differential nonlinear error VOT Zero transition voltage VFST Full scale transition voltage tCONV Conversion time RLADDER Ladder resistor IVREF Reference power source input current II(AD) A/D port input current Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 57 of 82 Test conditions VCC = 2.7 to 5.5 V Ta = 25 °C VCC = 2.7 to 5.5 V Ta = 25 °C VCC = VREF = 5.12 V VCC = VREF = 3.072 V VCC = VREF = 5.12 V VCC = VREF = 3.072 V VREF = 5.0 V VREF = 3.0 V VCC = 2.7 to 5.5 V Ta = 25 °C VCC = 2.7 to 5.5 V Ta = 25 °C VCC = VREF = 5.12 V VCC = VREF = 3.072 V VCC = VREF = 5.12 V VCC = VREF = 3.072 V VREF = 5.0 V VREF = 3.0 V Limits Min. Typ. 0 0 5105 3060 5 3 5115 3069 50 50 55 150 70 0 0 5105 3060 15 9 5125 3075 50 50 55 150 70 Max. Unit 10 ±3 Bits LSB ±0.9 LSB 20 15 5125 3075 122 mV mV mV mV tc(XIN) kΩ µA 200 120 5.0 10 ±3 µA Bits LSB ±1.5 LSB 35 21 5150 3090 122 mV mV mV mV tc(XIN) kΩ µA 200 120 5.0 µA 7540 Group Timing Requirements (General purpose) Table 14 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(CNTR1) tWH(CNTR1) tWL(CNTR1) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1–SCLK1) th(SCLK1–RxD1) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SDATA2–SCLK2) th(SCLK2–SDATA2) Limits Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0 input cycle time CNTR0, INT0, INT1, input “H” pulse width CNTR0, INT0, INT1, input “L” pulse width CNTR1 input cycle time CNTR1 input “H” pulse width CNTR1 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time Min. 2 125 50 50 200 80 80 2000 800 800 800 370 370 220 100 1000 400 400 200 200 Typ. Unit Max. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected). When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4. Table 15 Timing requirements (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(CNTR1) tWH(CNTR1) tWL(CNTR1) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1–SCLK1) th(SCLK1–RxD1) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SDATA2–SCLK2) th(SCLK2–SDATA2) Limits Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0 input cycle time CNTR0, INT0, INT1, input “H” pulse width CNTR0, INT0, INT1, input “L” pulse width CNTR1 input cycle time CNTR1 input “H” pulse width CNTR1 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time Min. 2 250 100 100 500 230 230 4000 1600 1600 2000 950 950 400 200 2000 950 950 400 400 Typ. Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected). When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 58 of 82 Unit Max. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7540 Group Table 16 Timing requirements (3) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(CNTR1) tWH(CNTR1) tWL(CNTR1) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1–SCLK1) th(SCLK1–RxD1) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SDATA2–SCLK2) th(SCLK2–SDATA2) Limits Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0 input cycle time CNTR0, INT0, INT1, input “H” pulse width CNTR0, INT0, INT1, input “L” pulse width CNTR1 input cycle time CNTR1 input “H” pulse width CNTR1 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time Min. 2 500 200 200 1000 460 460 8000 3200 3200 4000 1900 1900 800 400 4000 1900 1900 800 800 Typ. Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected). When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 59 of 82 Unit Max. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7540 Group Switching Characteristics (General purpose) Table 17 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1–TxD1) tv(SCLK1–TxD1) tr(SCLK1) tf(SCLK1) tWH(SCLK2) tWL(SCLK2) td(SCLK2–SDATA2) tv(SCLK2–SDATA2) tr(SCLK2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time Limits Min. Typ. Max. tC(SCLK1)/2–30 tC(SCLK1)/2–30 140 –30 30 30 tC(SCLK2)/2–30 tC(SCLK2)/2–30 140 0 CMOS output rising time (Note 1) CMOS output falling time (Note 1) 10 10 30 30 30 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1: Pin XOUT is excluded. Table 18 Switching characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1–TxD1) tv(SCLK1–TxD1) tr(SCLK1) tf(SCLK1) tWH(SCLK2) tWL(SCLK2) td(SCLK2–SDATA2) tv(SCLK2–SDATA2) tr(SCLK2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Note 1: Pin XOUT is excluded. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 60 of 82 Limits Min. Typ. Max. tC(SCLK1)/2–50 tC(SCLK1)/2–50 350 –30 50 50 tC(SCLK2)/2–50 tC(SCLK2)/2–50 350 0 20 20 50 50 50 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7540 Group Table 19 Switching characteristics (3) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1–TxD1) tv(SCLK1–TxD1) tr(SCLK1) tf(SCLK1) tWH(SCLK2) tWL(SCLK2) td(SCLK2–SDATA2) tv(SCLK2–SDATA2) tr(SCLK2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Note 1: Pin XOUT is excluded. Measured output pin 100 pF /// CMOS output Switching characteristics measurement circuit diagram (General purpose) Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 61 of 82 Limits Min. Typ. Max. tC(SCLK1)/2–70 tC(SCLK1)/2–70 450 –30 70 70 tC(SCLK2)/2–70 tC(SCLK2)/2–70 450 0 25 25 70 70 70 70 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7540 Group tC(CNTR0) tWL(CNTR0) tWH(CNTR0) CNTR0 0.8VCC 0.2VCC tC(CNTR1) tWL(CNTR1) tWH(CNTR1) 0.8VCC CNTR1 0.2VCC tWL(CNTR0) tWH(CNTR0) INT0, INT1 0.8VCC 0.2VCC tW(RESET) RESET 0.8VCC 0.2VCC tC(XIN) tWL(XIN) tWH(XIN) 0.8VCC XIN tC(SCLK1) tr tf SCLK1 0.2VCC tWL(SCLK1) tWH(SCLK1 ) 0.8VCC 0.2VCC tsu(RxD1-SCLK1) th(SCLK1 -RxD1) 0.8VCC 0.2VCC RXD1 (at receive) td(SCLK1 -TxD1) tv(SCLK1-TxD1) TXD1 (at transmit) tC(SCLK2) tr tf SCLK2 tWL(SCLK2) 0.2VCC tsu(SDATA2 -SCLK2) td(SCLK2 -SDATA2 ) Fig. 55 Timing chart (General purpose) Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 62 of 82 th(SCLK2 -SDATA2 ) 0.8VCC 0.2VCC SDATA2 (at receive) SDATA2 (at transmit) tWH(SCLK2 ) 0.8VCC tv(SCLK2-SDATA2 ) 7540 Group ELECTRICAL CHARACTERISTICS 2.7540Group (Extended operating temperature version) Applied to: M37540M2T-XXXFP/GP, M37540M4T-XXXFP/GP, M37540E8T-XXXFP/GP Absolute Maximum Ratings (Extended operating temperature version) Table 20 Absolute maximum ratings Symbol VCC VI VI VO Pd Topr Tstg Parameter Power source voltage Input voltage P00–P07, P10–P14, P20–P27, P30–P37, VREF Input voltage RESET, XIN, CNVSS Output voltage P00–P07, P10–P14, P20–P27, P30–P37, XOUT Power dissipation Operating temperature Storage temperature Notes 1: This is the rating value for the Mask ROM version. The rating value for the One Time PROM version is –0.3 to 7.0 V. 2: 200 mW for the 32P6U package product. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 63 of 82 Conditions All voltages are based on VSS. Output transistors are cut off. Ta = 25°C Ratings –0.3 to 6.5 (Note 1) –0.3 to VCC + 0.3 Unit V V –0.3 to VCC + 0.3 –0.3 to VCC + 0.3 V V 300 (Note 2) –40 to 85 –65 to 150 mW °C °C 7540 Group Recommended Operating Conditions (Extended operating temperature version) Table 21 Recommended operating conditions (1) (VCC = 2.4 to 5.5 V, Ta = –40 to 85 °C, unless otherwise noted) Symbol VCC Parameter Power source voltage (ceramic) Power source voltage (RC) VSS VREF VIH VIH VIH VIL VIL VIL VIL ∑IOH(peak) ∑IOL(peak) ∑IOL(peak) ∑IOH(avg) ∑IOL(avg) ∑IOL(avg) f(XIN) = 8 MHz (High-, Middle-speed mode) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 6 MHz (Double-speed mode) f(XIN) = 4 MHz (Double-speed mode) f(XIN) = 2 MHz (Double-speed mode) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 2 MHz (High-, Middle-speed mode) Power source voltage Analog reference voltage “H” input voltage P00–P07, P10–P14, P20–P27, P30–P37 “H” input voltage (TTL input level selected) P10, P12, P13, P36, P37 (Note 1) “H” input voltage RESET, XIN “L” input voltage P00–P07, P10–P14, P20–P27, P30–P37 “L” input voltage (TTL input level selected) P10, P12, P13, P36, P37 (Note 1) “L” input voltage RESET, CNVSS “L” input voltage XIN “H” total peak output current (Note 2) P00–P07, P10–P14, P20–P27, P30–P37 “L” total peak output current (Note 2) P00–P07, P10–P14, P20–P27, P37 “L” total peak output current (Note 2) P30–P36 “H” total average output current (Note 2) P00–P07, P10–P14, P20–P27, P30–P37 “L” total average output current (Note 2) P00–P07, P10–P14, P20–P27, P37 “L” total average output current (Note 2) P30–P36 Limits Min. 4.0 2.4 4.5 4.0 2.4 4.0 2.4 Typ. 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 Unit 2.0 0.8VCC VCC V V V V V V V V V V 2.0 VCC V 0.8VCC VCC V 0 0.3VCC V 0 0.8 V 0 0.2VCC V 0 0.16VCC V –80 mA 80 mA 60 mA –40 mA 40 mA 30 mA VCC Note 1: Vcc = 4.0 to 5.5V 2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 64 of 82 7540 Group Recommended Operating Conditions (Extended operating temperature version)(continued) Table 22 Recommended operating conditions (2) (VCC = 2.4 to 5.5 V, Ta = –40 to 85 °C, unless otherwise noted) Limits Symbol Parameter Min. “H” peak output current (Note 1) P00–P07, P10–P14, P20–P27, P30–P37 “L” peak output current (Note 1) P00–P07, P10–P14, P20–P27, P37 “L” peak output current (Note 1) P30–P36 “H” average output current (Note 2) P00–P07, P10–P14, P20–P27, P30–P37 “L” average output current (Note 2) P00–P07, P10–P14, P20–P27, P37 “L” average output current (Note 2) P30–P36 Internal clock oscillation frequency (Note 3) VCC = 4.5 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V at ceramic oscillation or external clock input High-, Middle-speed mode Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V at ceramic oscillation or external clock input High-, Middle-speed mode Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V at RC oscillation High-, Middle-speed mode Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V at RC oscillation High-, Middle-speed mode Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50 %. IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 65 of 82 Typ. Unit Max. –10 10 30 –5 5 15 6 mA mA mA mA mA mA MHz 4 MHz 2 MHz 8 MHz 4 MHz 4 MHz 2 MHz 7540 Group Electrical Characteristics (Extended operating temperature version) Table 23 Electrical characteristics (1) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Limits Symbol VOH VOL VOL VT+–VT– VT+–VT– VT+–VT– IIH IIH IIH IIL IIL IIL IIL VRAM ROSC DOSC Parameter “H” output voltage P00–P07, P10–P14, P20–P27, P30–P37 (Note 1) “L” output voltage P00–P07, P10–P14, P20–P27, P37 “L” output voltage P30–P36 Hysteresis CNTR0, CNTR1, INT0, INT1(Note 2) P00–P07 (Note 3) Hysteresis RXD, SCLK1, SCLK2, SDATA2 (Note 2) Hysteresis RESET “H” input current P00–P07, P10–P14, P20–P27, P30–P37 “H” input current RESET “H” input current XIN “L” input current P00–P07, P10–P14, P20–P27, P30–P37 “L” input current RESET, CNVSS “L” input current XIN “L” input current P00–P07, P30–P37 RAM hold voltage On-chip oscillator oscillation frequency Oscillation stop detection circuit detection frequency Test conditions IOH = –5 mA VCC = 4.0 to 5.5 V IOH = –1.0 mA VCC = 2.4 to 5.5 V IOL = 5 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 2.4 to 5.5 V IOL = 15 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 10 mA VCC = 2.4 to 5.5 V Min. Typ. Max. Unit VCC–1.5 V VCC–1.0 V V 0.3 V 1.0 V 2.0 V 0.3 V 1.0 V 0.4 V 0.5 V 0.5 V VI = VCC (Pin floating. Pull up transistors “off”) VI = VCC VI = VCC 1.5 5.0 µA 5.0 µA µA 4.0 VI = VSS (Pin floating. Pull up transistors “off”) VI = VSS –5.0 µA –5.0 µA µA VI = VSS –4.0 VI = VSS (Pull up transistors “on”) When clock stopped VCC = 5.0 V, Ta = 25 °C VCC = 5.0 V, Ta = 25 °C –0.2 –0.5 mA 2000 125 5.5 3000 187.5 V kHz kHz 2.0 1000 62.5 Notes 1: P11 is measured when the P11/TXD1 P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: RXD1, SCLK1, SCLK2, SDATA2, INT0, and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to “0” (CMOS level). 3: It is available only when operating key-on wake up. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 66 of 82 7540 Group Electrical Characteristics (Extended operating temperature version)(continued) Table 24 Electrical characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Limits Symbol ICC Test conditions One Time PROM version High-speed mode, f(XIN) = 8 MHz Output transistors “off” High-speed mode, f(XIN) = 2 MHz, VCC = 2.4 V Output transistors “off” Double-speed mode, f(XIN) = 6 MHz, Output transistors “off” Middle-speed mode, f(XIN) = 8 MHz, Output transistors “off” On-chip oscillator operation mode, VCC = 5 V Output transistors “off” f(XIN) = 8 MHz (in WIT state), functions except timer 1 disabled, Output transistors “off” f(XIN) = 2 MHz, VCC = 2.4 V (in WIT state), functions except timer 1 disabled, Output transistors “off” On-chip oscillator operation mode, VCC = 5V (in WIT state), functions except timer 1 disabled, Output transistors “off” Increment when A/D conversion is executed f(XIN) = 8 MHz, VCC = 5 V All oscillation stopped Ta = 25 °C (in STP state) Ta = 85 °C Output transistors “off” High-speed mode, f(XIN) = 8 MHz Mask ROM version Output transistors “off” High-speed mode, f(XIN) = 2 MHz, VCC = 2.4 V Output transistors “off” Double-speed mode, f(XIN) = 6 MHz Output transistors “off” Middle-speed mode, f(XIN) = 8 MHz Output transistors “off” On-chip oscillator operation mode, VCC = 5 V Output transistors “off” f(XIN) = 8 MHz (in WIT state), functions except timer 1 disabled, Output transistors “off” f(XIN) = 2 MHz, VCC = 2.4 V (in WIT state), functions except timer 1 disabled, Output transistors “off” On-chip oscillator operation mode, VCC = 5V (in WIT state), functions except timer 1 disabled, Output transistors “off” Increment when A/D conversion is executed f(XIN) = 8 MHz, VCC = 5 V All oscillation stopped Ta = 25 °C (in STP state) Ta = 85 °C Output transistors “off” Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 67 of 82 Min. Unit Typ. Max. 5.0 8.0 mA 0.5 1.5 mA 6.0 10.0 mA 2.0 5.0 mA 350 1000 µA 1.6 3.2 mA mA 0.2 150 450 µA mA 0.5 0.1 1.0 10 µA µA 3.5 6.5 mA 0.4 1.2 mA 4.5 8.0 mA 2.0 5.0 mA 300 900 µA 1.6 3.2 mA mA 0.2 150 450 mA 0.5 0.1 µA 1.0 10 µA µA 7540 Group A/D Converter Characteristics (Extended operating temperature version) Table 25 A/D Converter characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Symbol One Time PROM version Parameter — — Resolution Linearity error — Differential nonlinear error VOT Zero transition voltage VFST Full scale transition voltage tCONV Conversion time RLADDER Ladder resistor IVREF Reference power source input current Mask ROM version II(AD) — — A/D port input current Resolution Linearity error — Differential nonlinear error VOT Zero transition voltage VFST Full scale transition voltage tCONV Conversion time RLADDER Ladder resistor IVREF Reference power source input current II(AD) A/D port input current Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 68 of 82 Test conditions VCC = 2.7 to 5.5 V Ta = 25 °C VCC = 2.7 to 5.5 V Ta = 25 °C VCC = VREF = 5.12 V VCC = VREF = 3.072 V VCC = VREF = 5.12 V VCC = VREF = 3.072 V VREF = 5.0 V VREF = 3.0 V VCC = 2.7 to 5.5 V Ta = 25 °C VCC = 2.7 to 5.5 V Ta = 25 °C VCC = VREF = 5.12 V VCC = VREF = 3.072 V VCC = VREF = 5.12 V VCC = VREF = 3.072 V VREF = 5.0 V VREF = 3.0 V Limits Min. Typ. 0 0 5105 3060 5 3 5115 3069 50 50 55 150 70 0 0 5105 3060 15 9 5125 3075 50 30 55 150 70 Max. Unit 10 ±3 Bits LSB ±0.9 LSB 20 15 5125 3075 122 mV mV mV mV tc(XIN) kΩ µA 200 120 5.0 10 ±3 µA Bits LSB ±1.5 LSB 35 21 5150 3090 122 mV mV mV mV tc(XIN) kΩ µA 200 120 5.0 µA 7540 Group Timing Requirements (Extended operating temperature version) Table 26 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(CNTR1) tWH(CNTR1) tWL(CNTR1) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1–SCLK1) th(SCLK1–RxD1) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SDATA2–SCLK2) th(SCLK2–SDATA2) Limits Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0 input cycle time CNTR0, INT0, INT1, input “H” pulse width CNTR0, INT0, INT1, input “L” pulse width CNTR1 input cycle time CNTR1 input “H” pulse width CNTR1 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time Min. 2 125 50 50 200 80 80 2000 800 800 800 370 370 220 100 1000 400 400 200 200 Typ. Unit Max. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected). When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4. Table 27 Timing requirements (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(CNTR1) tWH(CNTR1) tWL(CNTR1) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1–SCLK1) th(SCLK1–RxD1) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SDATA2–SCLK2) th(SCLK2–SDATA2) Limits Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0 input cycle time CNTR0, INT0, INT1, input “H” pulse width CNTR0, INT0, INT1, input “L” pulse width CNTR1 input cycle time CNTR1 input “H” pulse width CNTR1 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time Min. 2 250 100 100 500 230 230 4000 1600 1600 2000 950 950 400 200 2000 950 950 400 400 Typ. Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected). When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 69 of 82 Unit Max. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7540 Group Switching Characteristics (Extended operating temperature version) Table 28 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1–TxD1) tv(SCLK1–TxD1) tr(SCLK1) tf(SCLK1) tWH(SCLK2) tWL(SCLK2) td(SCLK2–SDATA2) tv(SCLK2–SDATA2) tr(SCLK2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Limits Min. Typ. Max. tC(SCLK1)/2–30 tC(SCLK1)/2–30 140 –30 30 30 tC(SCLK2)/2–30 tC(SCLK2)/2–30 140 0 30 30 10 10 30 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1: Pin XOUT is excluded. Table 29 Switching characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1–TxD1) tv(SCLK1–TxD1) tr(SCLK1) tf(SCLK1) tWH(SCLK2) tWL(SCLK2) td(SCLK2–SDATA2) tv(SCLK2–SDATA2) tr(SCLK2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Note 1: Pin XOUT is excluded. Measured output pin 100 pF /// CMOS output Switching characteristics measurement circuit diagram (General purpose) Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 70 of 82 Limits Min. Typ. Max. tC(SCLK1)/2–50 tC(SCLK1)/2–50 350 –30 50 50 tC(SCLK2)/2–50 tC(SCLK2)/2–50 350 0 20 20 50 50 50 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7540 Group tC(CNTR0) tWL(CNTR0) tWH(CNTR0) CNTR0 0.8VCC 0.2VCC tC(CNTR1) tWL(CNTR1) tWH(CNTR1) 0.8VCC CNTR1 0.2VCC tWL(CNTR0) tWH(CNTR0) INT0, INT1 0.8VCC 0.2VCC tW(RESET) RESET 0.8VCC 0.2VCC tC(XIN) tWL(XIN) tWH(XIN) 0.8VCC XIN tC(SCLK1) tr tf SCLK1 0.2VCC tWL(SCLK1) tWH(SCLK1 ) 0.8VCC 0.2VCC tsu(RxD1-SCLK1) th(SCLK1 -RxD1) 0.8VCC 0.2VCC RXD1 (at receive) td(SCLK1 -TxD1) tv(SCLK1-TxD1) TXD1 (at transmit) tC(SCLK2) tr tf SCLK2 tWL(SCLK2) 0.2VCC tsu(SDATA2 -SCLK2) td(SCLK2 -SDATA2 ) SDATA2 (at transmit) Fig. 56 Timing chart (Extended operating temperature version) page 71 of 82 th(SCLK2 -SDATA2 ) 0.8VCC 0.2VCC SDATA2 (at receive) Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z tWH(SCLK2 ) 0.8VCC tv(SCLK2-SDATA2 ) 7540 Group ELECTRICAL CHARACTERISTICS 3.7540Group (Extended operating temperature 125 °C version) Applied to: M37540M2V-XXXFP/GP, M37540M4V-XXXFP/GP, M37540E8V-XXXFP/GP Absolute Maximum Ratings (Extended operating temperature 125 °C version) Table 30 Absolute maximum ratings Symbol VCC VI VI VO Pd Topr Tstg Parameter Power source voltage Input voltage P00–P07, P10–P14, P20–P27, P30–P37, VREF Input voltage RESET, XIN, CNVSS Output voltage P00–P07, P10–P14, P20–P27, P30–P37, XOUT Power dissipation Operating temperature Storage temperature Conditions All voltages are based on VSS. Output transistors are cut off. Ta = 25°C Notes 1: This is the rating value for the Mask ROM version. The rating value for the One Time PROM version is –0.3 to 7.0 V. 2: 200 mW for the 32P6U package product. 3: In this version, the operating temperature range and total time are limited as follows; 55 °C to 85 °C: within total 6000 hours, 85 °C to 125 °C: within total 1000 hours. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 72 of 82 Ratings –0.3 to 6.5 (Note 1) –0.3 to VCC + 0.3 Unit V V –0.3 to VCC + 0.3 –0.3 to VCC + 0.3 V V 300 (Note 2) –40 to 125 (Note 3) –65 to 150 mW °C °C 7540 Group Recommended Operating Conditions (Extended operating temperature 125 °C version) Table 31 Recommended operating conditions (1) (VCC = 2.4 to 5.5 V, Ta = –40 to 125 °C, unless otherwise noted) Symbol VCC Parameter Power source voltage (ceramic) Power source voltage (RC) VSS VREF VIH VIH VIH VIL VIL VIL VIL ∑IOH(peak) ∑IOL(peak) ∑IOL(peak) ∑IOH(avg) ∑IOL(avg) ∑IOL(avg) f(XIN) = 8 MHz (High-, Middle-speed mode) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 4 MHz (Double-speed mode) f(XIN) = 2 MHz (Double-speed mode) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 2 MHz (High-, Middle-speed mode) Power source voltage Analog reference voltage “H” input voltage P00–P07, P10–P14, P20–P27, P30–P37 “H” input voltage (TTL input level selected) P10, P12, P13, P36, P37 (Note 1) “H” input voltage RESET, XIN “L” input voltage P00–P07, P10–P14, P20–P27, P30–P37 “L” input voltage (TTL input level selected) P10, P12, P13, P36, P37 (Note 1) “L” input voltage RESET, CNVSS “L” input voltage XIN “H” total peak output current (Note 2) P00–P07, P10–P14, P20–P27, P30–P37 “L” total peak output current (Note 2) P00–P07, P10–P14, P20–P27, P37 “L” total peak output current (Note 2) P30–P36 “H” total average output current (Note 2) P00–P07, P10–P14, P20–P27, P30–P37 “L” total average output current (Note 2) P00–P07, P10–P14, P20–P27, P37 “L” total average output current (Note 2) P30–P36 Limits Min. 4.0 2.4 4.0 2.4 4.0 2.4 Typ. 5.0 5.0 5.0 5.0 5.0 5.0 0 Max. 5.5 5.5 5.5 5.5 5.5 5.5 Unit 2.0 0.8VCC VCC V V V V V V V V V 2.0 VCC V 0.8VCC VCC V 0 0.3VCC V 0 0.8 V 0 0.2VCC V 0 0.16VCC V –80 mA 80 mA 60 mA –40 mA 40 mA 30 mA VCC Note 1: Vcc = 4.0 to 5.5V 2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 73 of 82 7540 Group Recommended Operating Conditions (Extended operating temperature 125 °C version) (continued) Table 32 Recommended operating conditions (2) (VCC = 2.4 to 5.5 V, Ta = –40 to 125 °C, unless otherwise noted) Limits Symbol Parameter Min. “H” peak output current (Note 1) P00–P07, P10–P14, P20–P27, P30–P37 “L” peak output current (Note 1) P00–P07, P10–P14, P20–P27, P37 “L” peak output current (Note 1) P30–P36 “H” average output current (Note 2) P00–P07, P10–P14, P20–P27, P30–P37 “L” average output current (Note 2) P00–P07, P10–P14, P20–P27, P37 “L” average output current (Note 2) P30–P36 Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V at ceramic oscillation or external clock input High-, Middle-speed mode Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V at ceramic oscillation or external clock input High-, Middle-speed mode Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V at RC oscillation High-, Middle-speed mode Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V at RC oscillation High-, Middle-speed mode Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50 %. IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 74 of 82 Typ. Unit Max. –10 10 30 –5 5 15 4 mA mA mA mA mA mA MHz 2 MHz 8 MHz 4 MHz 4 MHz 2 MHz 7540 Group Electrical Characteristics (Extended operating temperature 125 °C version) Table 33 Electrical characteristics (1) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 125 °C, unless otherwise noted) Limits Symbol VOH VOL VOL VT+–VT– VT+–VT– VT+–VT– IIH IIH IIH IIL IIL IIL IIL VRAM ROSC DOSC Parameter “H” output voltage P00–P07, P10–P14, P20–P27, P30–P37 (Note 1) “L” output voltage P00–P07, P10–P14, P20–P27, P37 “L” output voltage P30–P36 Hysteresis CNTR0, CNTR1, INT0, INT1(Note 2) P00–P07 (Note 3) Hysteresis RXD, SCLK1, SCLK2, SDATA2 (Note 2) Hysteresis RESET “H” input current P00–P07, P10–P14, P20–P27, P30–P37 “H” input current RESET “H” input current XIN “L” input current P00–P07, P10–P14, P20–P27, P30–P37 “L” input current RESET, CNVSS “L” input current XIN “L” input current P00–P07, P30–P37 RAM hold voltage On-chip oscillator oscillation frequency Oscillation stop detection circuit detection frequency Test conditions IOH = –5 mA VCC = 4.0 to 5.5 V IOH = –1.0 mA VCC = 2.4 to 5.5 V IOL = 5 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 2.4 to 5.5 V IOL = 15 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 10 mA VCC = 2.4 to 5.5 V Min. Typ. Max. Unit VCC–1.5 V VCC–1.0 V V 0.3 V 1.0 V 2.0 V 0.3 V 1.0 V 0.4 V 0.5 V 0.5 V VI = VCC (Pin floating. Pull up transistors “off”) VI = VCC VI = VCC 1.5 5.0 µA 5.0 µA µA 4.0 VI = VSS (Pin floating. Pull up transistors “off”) VI = VSS –5.0 µA –5.0 µA µA VI = VSS –4.0 VI = VSS (Pull up transistors “on”) When clock stopped VCC = 5.0 V, Ta = 25 °C VCC = 5.0 V, Ta = 25 °C –0.2 –0.5 mA 2000 125 5.5 3000 187.5 V kHz kHz 2.0 1000 62.5 Notes 1: P11 is measured when the P11/TXD1 P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: RXD1, SCLK1, SCLK2, SDATA2, INT0, and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to “0” (CMOS level). 3: It is available only when operating key-on wake up. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 75 of 82 7540 Group Electrical Characteristics (Extended operating temperature 125°C version)(continued) Table 34 Electrical characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 125 °C, unless otherwise noted) Limits Symbol ICC Test conditions One Time PROM version High-speed mode, f(XIN) = 8 MHz Output transistors “off” High-speed mode, f(XIN) = 2 MHz, VCC = 2.4 V Output transistors “off” Middle-speed mode, f(XIN) = 8 MHz, Output transistors “off” On-chip oscillator operation mode, VCC = 5 V Output transistors “off” f(XIN) = 8 MHz (in WIT state), functions except timer 1 disabled, Output transistors “off” f(XIN) = 2 MHz, VCC = 2.4 V (in WIT state), functions except timer 1 disabled, Output transistors “off” On-chip oscillator operation mode, VCC = 5V (in WIT state), functions except timer 1 disabled, Output transistors “off” Increment when A/D conversion is executed f(XIN) = 8 MHz, VCC = 5 V Ta = 25 °C All oscillation stopped (in STP state) Ta = 125 °C Output transistors “off” Mask ROM version High-speed mode, f(XIN) = 8 MHz Output transistors “off” High-speed mode, f(XIN) = 2 MHz, VCC = 2.4 V Output transistors “off” Middle-speed mode, f(XIN) = 8 MHz, Output transistors “off” On-chip oscillator operation mode, VCC = 5 V Output transistors “off” f(XIN) = 8 MHz (in WIT state), functions except timer 1 disabled, Output transistors “off” f(XIN) = 2 MHz, VCC = 2.4 V (in WIT state), functions except timer 1 disabled, Output transistors “off” On-chip oscillator operation mode, VCC = 5V (in WIT state), functions except timer 1 disabled, Output transistors “off” Increment when A/D conversion is executed f(XIN) = 8 MHz, VCC = 5 V All oscillation stopped Ta = 25 °C (in STP state) Ta = 125 °C Output transistors “off” Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 76 of 82 Min. Unit Typ. Max. 5.0 8.0 mA 0.5 1.5 mA 2.0 5.0 mA 350 1000 µA 1.6 3.2 mA mA 0.2 150 450 µA mA 0.5 0.1 1.0 50 µA µA 3.5 6.5 mA 0.4 1.2 mA 2.0 5.0 mA 300 900 µA 1.6 3.2 mA mA 0.2 150 450 mA 0.5 0.1 µA 1.0 50 µA µA 7540 Group A/D Converter Characteristics (Extended operating temperature 125 °C version) Table 35 A/D Converter characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –40 to 125 °C, unless otherwise noted) Symbol One Time PROM version Parameter — — Resolution Linearity error — Differential nonlinear error VOT Zero transition voltage VFST Full scale transition voltage tCONV Conversion time RLADDER Ladder resistor IVREF Reference power source input current Mask ROM version II(AD) — — A/D port input current Resolution Linearity error — Differential nonlinear error VOT Zero transition voltage VFST Full scale transition voltage tCONV Conversion time RLADDER Ladder resistor IVREF Reference power source input current II(AD) A/D port input current Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 77 of 82 Test conditions VCC = 2.7 to 5.5 V Ta = 25 °C VCC = 2.7 to 5.5 V Ta = 25 °C VCC = VREF = 5.12 V VCC = VREF = 3.072 V VCC = VREF = 5.12 V VCC = VREF = 3.072 V VREF = 5.0 V VREF = 3.0 V VCC = 2.7 to 5.5 V Ta = 25 °C VCC = 2.7 to 5.5 V Ta = 25 °C VCC = VREF = 5.12 V VCC = VREF = 3.072 V VCC = VREF = 5.12 V VCC = VREF = 3.072 V VREF = 5.0 V VREF = 3.0 V Limits Min. Typ. 0 0 5105 3060 5 3 5115 3069 50 30 55 150 70 0 0 5105 3060 15 9 5125 3075 50 30 55 150 70 Max. Unit 10 ±3 Bits LSB ±0.9 LSB 20 15 5125 3075 122 mV mV mV mV tc(XIN) kΩ µA 200 120 7.0 10 ±3 µA Bits LSB ±1.5 LSB 35 21 5150 3090 122 mV mV mV mV tc(XIN) kΩ µA 200 120 7.0 µA 7540 Group Timing Requirements (Extended operating temperature 125 °C version) Table 36 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 125 °C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(CNTR1) tWH(CNTR1) tWL(CNTR1) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1–SCLK1) th(SCLK1–RxD1) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SDATA2–SCLK2) th(SCLK2–SDATA2) Limits Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0 input cycle time CNTR0, INT0, INT1, input “H” pulse width CNTR0, INT0, INT1, input “L” pulse width CNTR1 input cycle time CNTR1 input “H” pulse width CNTR1 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time Min. 2 125 50 50 200 80 80 2000 800 800 800 370 370 220 100 1000 400 400 200 200 Typ. Unit Max. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected). When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4. Table 37 Timing requirements (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 125 °C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(CNTR1) tWH(CNTR1) tWL(CNTR1) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1–SCLK1) th(SCLK1–RxD1) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SDATA2–SCLK2) th(SCLK2–SDATA2) Limits Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0 input cycle time CNTR0, INT0, INT1, input “H” pulse width CNTR0, INT0, INT1, input “L” pulse width CNTR1 input cycle time CNTR1 input “H” pulse width CNTR1 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time Min. 2 250 100 100 500 230 230 4000 1600 1600 2000 950 950 400 200 2000 950 950 400 400 Typ. Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected). When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4. Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 78 of 82 Unit Max. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7540 Group Switching Characteristics (Extended operating temperature 125 °C version) Table 38 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 125 °C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1–TxD1) tv(SCLK1–TxD1) tr(SCLK1) tf(SCLK1) tWH(SCLK2) tWL(SCLK2) td(SCLK2–SDATA2) tv(SCLK2–SDATA2) tr(SCLK2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Limits Min. Typ. Max. tC(SCLK1)/2–30 tC(SCLK1)/2–30 140 –30 30 30 tC(SCLK2)/2–30 tC(SCLK2)/2–30 140 0 30 30 10 10 30 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1: Pin XOUT is excluded. Table 39 Switching characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 125 °C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1–TxD1) tv(SCLK1–TxD1) tr(SCLK1) tf(SCLK1) tWH(SCLK2) tWL(SCLK2) td(SCLK2–SDATA2) tv(SCLK2–SDATA2) tr(SCLK2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Note 1: Pin XOUT is excluded. Measured output pin 100 pF /// CMOS output Switching characteristics measurement circuit diagram (General purpose) Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 79 of 82 Limits Min. Typ. Max. tC(SCLK1)/2–50 tC(SCLK1)/2–50 350 –30 50 50 tC(SCLK2)/2–50 tC(SCLK2)/2–50 350 0 20 20 50 50 50 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7540 Group tC(CNTR0) tWL(CNTR0) tWH(CNTR0) CNTR0 0.8VCC 0.2VCC tC(CNTR1) tWL(CNTR1) tWH(CNTR1) 0.8VCC CNTR1 0.2VCC tWL(CNTR0) tWH(CNTR0) INT0, INT1 0.8VCC 0.2VCC tW(RESET) RESET 0.8VCC 0.2VCC tC(XIN) tWL(XIN) tWH(XIN) 0.8VCC XIN tC(SCLK1) tr tf SCLK1 0.2VCC tWL(SCLK1) tWH(SCLK1 ) 0.8VCC 0.2VCC tsu(RxD1-SCLK1) th(SCLK1 -RxD1) 0.8VCC 0.2VCC RXD1 (at receive) td(SCLK1 -TxD1) tv(SCLK1-TxD1) TXD1 (at transmit) tC(SCLK2) tr tf SCLK2 tWL(SCLK2) 0.8VCC 0.2VCC tsu(SDATA2 -SCLK2) td(SCLK2 -SDATA2 ) SDATA2 (at transmit) Fig. 57 Timing chart (Extended operating temperature 125 °C version) page 80 of 82 th(SCLK2 -SDATA2 ) 0.8VCC 0.2VCC SDATA2 (at receive) Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z tWH(SCLK2 ) tv(SCLK2-SDATA2 ) 7540 Group PACKAGE OUTLINE 32P6U-A Recommended EIAJ Package Code LQFP32-P-0707-0.80 Plastic 32pin 7✕7mm body LQFP Weight(g) Lead Material Cu Alloy MD b2 HD D ME e JEDEC Code – 32 25 I2 24 Recommended Mount Pad Symbol E HE 1 8 17 9 16 A b x L Lp M y A3 x y c A2 A1 F A3 L1 e A A1 A2 b c D E e HD HE L L1 Lp b2 I2 MD ME Detail F Recommended 36P2R-A EIAJ Package Code SSOP36-P-450-0.80 JEDEC Code – Dimension in Millimeters Min Nom Max – – 1.7 0.1 0.2 0 – – 1.4 0.32 0.37 0.45 0.105 0.125 0.175 6.9 7.0 7.1 6.9 7.0 7.1 – 0.8 – 8.8 9.0 9.2 8.8 9.0 9.2 0.3 0.5 0.7 1.0 – – 0.45 0.6 0.75 – 0.25 – – – 0.2 – – 0.1 – 0° 10° 0.5 – – 1.0 – – 7.4 – – – – 7.4 Plastic 36pin 450mil SSOP Weight(g) 0.53 e b2 19 E HE e1 I2 36 Lead Material Alloy 42 Recommended Mount Pad F Symbol 1 18 A D G A2 e b L L1 y A1 A A1 A2 b c D E e HE L L1 z Z1 y c z Z1 Detail G Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 81 of 82 Detail F b2 e1 I2 Dimension in Millimeters Min Nom Max 2.4 – – – – 0.05 – 2.0 – 0.5 0.4 0.35 0.2 0.15 0.13 15.2 15.0 14.8 8.6 8.4 8.2 – 0.8 – 12.23 11.93 11.63 0.7 0.5 0.3 – 1.765 – – 0.7 – – – 0.85 0.15 – – 0° – 10° – 0.5 – – 11.43 – – 1.27 – 7540 Group Recommended 32P4B JEDEC Code – Plastic 32pin 400mil SDIP Weight(g) 2.2 Lead Material Alloy 42/Cu Alloy 17 1 16 E 32 e1 c EIAJ Package Code SDIP32-P-400-1.78 D L A1 A A2 Symbol e SEATING PLANE Rev.4.00 Jun 21, 2004 REJ03B0011-0400Z page 82 of 82 b1 b b2 A A1 A2 b b1 b2 c D E e e1 L Dimension in Millimeters Min Nom Max – – 5.08 0.51 – – – 3.8 – 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 27.8 28.0 28.2 8.75 8.9 9.05 – 1.778 – – 10.16 – 3.0 – – 0° – 15° Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. http://www.renesas.com RENESAS SALES OFFICES Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 ©1999, 2004. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .1.0 REVISION DESCRIPTION LIST Rev. No. 7540 Group DATA SHEET Revision Description Rev. date 1.0 First Edition 991122 2.0 Page 1: 010108 FEATURES • The minimum instruction execution time revised; 0.34 µs (at 6 MHz oscillation frequency, double-speed mode for the shortest instruction) • Power source voltage added; XIN oscillation frequency at ceramic oscillation , in high-speed mode At 6 MHz.......................................4.5 to 5.5 V • Power dissipation revised; Mask ROM version........................22.5 mW (standard) One Time PROM version..............30 mW (standard) PIN CONFIGURATION Fig. 1 revised; Package type → 32P6U-A, Product name “M37540M4T-XXXGP” added Page 2: Fig. 2 revised; Product name “M37540M4T-XXXFP” added Page 3: Fig. 4 M37540RSS pin configuration (42S1M) added Page 4: Fig. 5 Functional block diagram revised; Package type → 32P6U Page 7: PIN DESCRIPTION revised; Notes 1 to 3 added Page 8: Package type revised; → 32P6U-A.....0.8 mm-pitch plastic molded LQFP → 36P2R-A.....0.8 mm-pitch plastic molded SSOP Table 2 revised; Package type → 32P6U-A Pages 9 to 11: Structure of CPU added Page 12: Fig. 11 Initial value added, Fig. 12 Description revised Page 16: Table 5 Non-port function of port P0 revised, Notes 2 and 3 added Page 17: Fig. 17 Port P0 revised Page 18: Fig. 18 Note added Page 20: Fig. 20 Initial values added, Interrupt enable bit of ICON1; Note added Page 21: Fig. 21 Port P00 key-on wakeup selection bit added (1/5) REVISION DESCRIPTION LIST Rev. No. 2.0 7540 Group DATA SHEET Revision Description (continued) Rev. date 010108 Pages 22 to 30: Description of timers revised all Page 31: Fig. 25 to Fig. 27 Initial values added Page 33: Fig. 29 Reference of Figure revised → Fig. 50, 51 Page 36: Description of SIO1STS revised; “All bits” → “Bits 0 to 6” Description of UARTCON revised; “P12/SCLK1” pin eliminated Page 37: Fig. 34 Initial value added Page 38: Fig. 35 Initial value added Page 39: Fig. 37 Note revised Page 40: Fig. 38 Initial value added Page 41: Fig. 42 Initial value added Page 42: Description in the case of 6 MHz added Page 43: Fig. 45 Contents of (7), (8) revised Page 45: Fig. 49 Functions of b1 and b7 revised, Initial value added Page 46: Fig. 50 A resistor of XOUT pin eliminated Page 47: Description of oscillation stop detection circuit added, Fig. 52 revised Page 48: Notes on Ports revised Pages 50 to 68: Electrical characteristics revised all Page 69: Package type revised; 32P6U-A 3.0 All pages: The following is eliminated; 020610 “PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change.” Page 1: • Memory size ROM/RAM size revised, • Operating temperature range 125 °C version added, and Note revised Page 2: Fig. 1 and Fig. 2 Product name revised Page 3: Fig. 3 Product name revised Page 7: Table 1 XIN, XOUT Functional description added, Note 1 125 °C version added Page 8: Memory size ROM/RAM size, Package description, and Fig. 8 revised Page 9: Table 2 revised Page 14: Fig. 13 ROM/RAM area added (2/5) REVISION DESCRIPTION LIST Rev. No. 3.0 7540 Group DATA SHEET Revision Description (continued) Rev. date 020610 Page 19: Fig. 18 (9) Port P14 revised Page 20: Note revised Page 23: ● Timer 1 “Prescaler 1 counts the signal which is the oscillation frequency divided by 16.” (1) Timer mode “Timer A counts the oscillation frequency divided by 16.” Page 24: ● Timer X “Timer X can can be selected in one of 4 operating modes by setting the timer X operating mode bits of the timer X mode register.” (1) Timer mode “Prescaler X counts the count source selected by the timer X count source selection bits.” Page 26: ● Timer Y “Timer Y can can be selected in one of 4 operating modes by setting the timer Y operating mode bits of the timer Y mode register.” (1) Timer mode “Prescaler Y counts the count source selected by the timer Y count source selection bits.” Page 27: Note on reading timer added. Page 28: ● Timer Z “Timer Z can can be selected in one of 4 operating modes by setting the timer Z operating mode bits of the timer Z mode register.” (1) Timer mode “Prescaler Z counts the count source selected by the timer Z count source selection bits.” Page 30: Note on reading timer added. Page 36: Note on Serial I/O added. Page 44: Clock generating circuit The following description added. (1) On-chip oscillator operation, (2) Ceramic resonator, (3) RC oscillation, and (4) External clock Fig. 46 Resistor and Note added, Fig. 47 Note added, and Fig. 49 added. Page 45: ● Oscillation stop detection circuit Note added. Page 46: Fig. 51 and Fig. 52 revised. Page 47: Fig. 53 Note 4 added. Pages 48 to 50: Notes revised Page 51: DATA REQUIRED FOR MASK ORDERS revised DATA REQUIRED FOR ROM PROGRAMMING ORDERS added (3/5) REVISION DESCRIPTION LIST Rev. No. 3.0 7540 Group DATA SHEET Revision Description (continued) Rev. date 020610 Page 52: Product name added, Table 8 Note revised. Page 57: Table 13 Ladder resistor value revised, Layout revised. Page 63: Product name added, Table 20 Note revised. Page 67: Table 24 Characteristics for One Time PROM version added. Mask ROM version; “VCC = 5 V” eliminated from the following Test condition. f(XIN) = 6 MHz f(XIN) = 8MHz, middle-speed mode Page 68: Table 25 Ladder resistor value revised, Layout revised. Page 72 to 80: Extended operating temperature 125 °C version added. 3.1 Page 57: Table 13, Page 68: Table 25 and Page 77: Table 35 Error of the ladder resistor in A/D converter characteristics corrected. As usual, (Rev.2.0 or before), the value is not changed from Typical 55 kΩ. (4/5) 020701 7540 Group Data Sheet REVISION HISTORY Rev. Date Description Summary Page 3.20 May. 28, 2003 16 [Pull-up control register] PULL; Note added. Fig.15; Note 2 eliminated. 18 Fig.17; (2) Ports P01,P02 revised. 33 Fig.29; Port P03 direction register block, Port P0 1 direction register block and Port P02 direction register block revised. 44 (3) RC oscillation revised. 4.00 Jun. 21, 2004 All pages Words standardized: On-chip oscillator, A/D converter 8 Fig. 8: “Under development” eliminated. 9 Table 2: “Under development” eliminated. 10 CPU: Description revised. 16 [Pull-up control register] PULL: Note added, Fig. 15: Note eliminated. 18 Fig.17 (2) Ports P01, P02 revised. Fig. 29 P03/TXOUT, P01/TYOUT, P02/TZOUT revised. 33 Note on A/D converter added. 40 Fig. 49 revised. 44 Note on A/D converter added. 50 Notes on clock generating circuit added. Note on Power Source Voltage, and Electrical Characteristic Difference Among 51 Mask ROM and One Time PROM Version MCUs added. 32P6U-A revised. 81 (5/5)