MX30LF1G08AA
MX30LF1G08AA
1G-bit NAND Flash Memory
REV. 1.5, SEP. 17, 2014
P/N: PM1113
1
MX30LF1G08AA
Contents
1.FEATURES........................................................................................................................................4
2. GENERAL DESCRIPTIONS..............................................................................................................4
Figure 1. Logic Diagram.......................................................................................................................... 4
2-1.
ORDERING INFORMATION....................................................................................................5
3. PIN CONFIGURATIONS....................................................................................................................6
3-1.
PIN DESCRIPTIONS...............................................................................................................7
4. PIN FUNCTIONS................................................................................................................................8
5. BLOCK DIAGRAM.............................................................................................................................9
Figure 2. AC Waveform for Command / Address / Data Latch Timing.................................................. 10
Figure 3. AC Waveforms for Address Input Cycle................................................................................. 10
6. DEVICE OPERATIONS....................................................................................................................10
Figure 4. AC Waveforms for Command Input Cycle............................................................................. 11
Figure 5. AC Waveforms for Data Input Cycle...................................................................................... 11
Figure 6. AC Waveforms for Read Cycle.............................................................................................. 12
Figure 7. AC Waveforms for Read Operation (Intercepted by CE#)..................................................... 13
Figure 8. Read Operation with CE# Don't Care.................................................................................... 14
Figure 9. AC Waveforms for Sequential Data Out Cycle (After Read).................................................. 14
Figure 10. AC Waveforms for Random Data Output............................................................................. 15
Figure 11. AC Waveforms for Cache Read........................................................................................... 17
Figure 12. AC Waveforms for Program Operation after Command 80H............................................... 18
Figure 13. AC Waveforms for Random Data In (For Page Program).................................................... 19
Figure 14. Program Operation with CE# Don't Care............................................................................. 20
Figure 15-1. AC Waveforms for Cache Program ................................................................................. 22
Figure 15-2. Sequence of Cache Program .......................................................................................... 23
Figure 16. AC Waveforms for Erase Operation..................................................................................... 24
Figure 17. AC Waveforms for ID Read Operation................................................................................. 25
Figure 18. AC Waveforms for Status Read Operation.......................................................................... 26
Figure 19. Reset Operation................................................................................................................... 27
7.PARAMETERS.................................................................................................................................28
7-1.
ABSOLUTE MAXIMUM RATINGS........................................................................................28
Figure 20. Device Under Test................................................................................................................ 30
Table 1. Operating Range..................................................................................................................... 29
Table 2. DC Characteristics................................................................................................................... 29
Table 3. Capacitance............................................................................................................................. 29
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MX30LF1G08AA
Table 4. AC Testing Conditions............................................................................................................. 30
Table 5. Program, Read and Erase Characteristics.............................................................................. 30
Table 6. AC Characteristics over Operating Range............................................................................... 31
8. SCHEMATIC CELL LAYOUT AND ADDRESS ASSIGNMENT.......................................................32
Table 7. Address Allocation................................................................................................................... 32
9. OPERATION MODES: LOGIC AND COMMAND TABLES.............................................................33
Figure 21. Bit Assignment (HEX Data).................................................................................................. 34
Table 8. Logic Table.............................................................................................................................. 33
Table 9. HEX Command Table.............................................................................................................. 34
Table 10. Status Output......................................................................................................................... 35
Table 11. ID Codes Read Out by ID Read Command 90H................................................................... 35
Table 12. The Definition of 3rd Code of ID Table................................................................................. 36
Table 13. The Definition of 4th Code of ID Table.................................................................................. 36
9-1.
9-2.
R/B#: TERMINATION FOR THE READY/BUSY# PIN (R/B#)..............................................37
Figure 22. R/B# Pin Timing Information................................................................................................ 37
POWER ON/OFF SEQUENCE..............................................................................................38
Figure 23. Power On/Off Sequence...................................................................................................... 38
Figure 24. Enable Programming........................................................................................................... 39
Figure 25. Disable Programming.......................................................................................................... 39
Figure 26. Enable Erasing..................................................................................................................... 39
Figure 27. Disable Erasing.................................................................................................................... 39
10.SOFTWARE ALGORITHM...............................................................................................................40
10-1. INVALID BLOCKS (BAD BLOCKS)......................................................................................40
Figure 28. Bad Blocks........................................................................................................................... 40
Table 14. Valid Blocks........................................................................................................................... 40
10-2. BAD BLOCK TEST FLOW....................................................................................................41
10-3. FAILURE PHENOMENA FOR READ/PROGRAM/ERASE OPERATIONS..........................41
Table 15. Failure Modes........................................................................................................................ 41
10-4.PROGRAM.............................................................................................................................42
Figure 30. Failure Modes...................................................................................................................... 42
Figure 31. Program Flow Chart............................................................................................................. 42
10-5.ERASE...................................................................................................................................42
Figure 32. Erase Flow Chart................................................................................................................. 43
Figure 33. Read Flow Chart.................................................................................................................. 43
11.PACKAGE INFORMATION..............................................................................................................45
12.REVISION HISTORY .......................................................................................................................47
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MX30LF1G08AA
1G-bit (128 M x 8 bit) NAND Flash Memory
1. FEATURES
•
1 Gbit SLC NAND Flash
• Block Erase Architecture
- 128 M x 8 bit
- Block size: (128K+4K) bytes per block
- 64 K pages of (2,048+64) bytes each
- 1K blocks, 64 pages each
- 1K blocks of 64 pages each
- Block Erase Time: 2ms (Typ.)
• Multiplexed Command/Address/Data
• Hardware Data Protection: WP# pin
• 4 MByte User Redundancy
• Multiple Device Status Indicators
- 64 bytes attached to each page
- Ready/Busy (R/B#) pin
• Fast Read Access
- Status Register
- First-byte latency: 25us
• Chip Enable Don't Care
- Sequential read: 30ns/byte
- Simplify System Interface
• Cache Read Support
• Status Register
• Page Program Operation
• Electronic Signature (Four Cycles)
• Cache Program
• High Reliability
- Internal cache of (2,048+64) bytes
- Endurance: 100K cycles (with 1-bit ECC per 528-byte)
- Data Retention: 10 years
• Program Time: Page program 250us (typ.)
• Single Voltage Operation: 3.3V
• Wide Temperature Operating Range:
• Low Power Dissipation - Max. 30mA active
current (RD/PGM/ERS)
-40°C to +85°C
• Package:
- 48-TSOP(I) (12mm x 20mm),
- 63-ball 9mmx11mm VFBGA
- All packaged devices are RoHS Compliant &
Halogen-free.
• Automatic Sleep Mode
- 50uA (Max) standby current
2. GENERAL DESCRIPTIONS
The MX30LF1G08AA is a 1Gb SLC NAND Flash
memory device. Its standard NAND Flash features
and reliable quality make it most suitable for
embedded system code and data storage usage.
Fast programming is supported, enabling page
programming at a rate of 8MB/sec (approx.)
The MX30LF1G08AA power consumption is
30 mA during all modes of operations (Read/
Program/Erase), and 50uA in standby mode.
The MX30LF1G08AA is typically accessed
in pages of 2,112 bytes, both for read and for
program operations.
Figure 1. Logic Diagram
The MX30LF1G08AA array is organized as
1024 blocks, which is composed by 64 pages of
(2,048+64) byte in two NAND strings structure
with 32 serial connected cells in each string. Each
page has an additional 64 bytes for ECC and
other purposes. The device has an on-chip buffer
of 2,112 bytes for data load and access.
ALE
IO7 - IO0
CLE
CE#
RE#
The Cache Read Operation of the MX30LF1G08AA
enable first-byte read-access latency of 25us and
sequential read of 30ns per byte.
1Gb
R/B#
WE#
WP#
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MX30LF1G08AA
2-1. ORDERING INFORMATION
Part Name Description
MX 30 L F 1G 08 A A - T
I
x
RESERVE
OPERATING TEMPERATURE:
I: Industrial (-40°C to 85°C)
PACKAGE TYPE:
T: 48TSOP
XK: 0.8mm Ball Pitch, 0.45mm Ball Size and 1.0mm height of VFBGA
Package: RoHS Compliant and Halogen-free
GENERATION (Tech. Code)
A
MODE:
A = Die#: 1, CE#: 1, R/B#: 1, Reserve: 0
OPTION CODE:
08 = x8
DENSITY:
1G = 1Gbit
CLASSIFICATION:
F = SLC + Large Block
VOLTAGE:
L = 2.7V to 3.6V
TYPE:
30 = NAND Flash
BRAND:
MX
PART NUMBER
ORGANIZATION
VCC RANGE
PACKAGE
TEMPERATUR GRADE
MX30LF1G08AA-TI
x8
2.7V - 3.6 Volt
48-TSOP
Industrial (-40° to 85°C)
MX30LF1G08AA-XKI
x8
2.7V - 3.6 Volt
63-VFBGA
Industrial (-40° to 85°C)
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MX30LF1G08AA
3. PIN CONFIGURATIONS
48-TSOP
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
NC
NC
IO7
IO6
IO5
IO4
NC
NC
NC
VCC
VSS
DNU
NC
NC
IO3
IO2
IO1
IO0
NC
NC
NC
NC
63-ball 9mmx11mm VFBGA
1
2
A
NC
NC
B
NC
3
4
5
6
7
8
C
WP#
ALE
VSS
CE#
WE#
R/B#
D
NC
RE#
CLE
NC
NC
NC
E
NC
NC
NC
NC
NC
NC
F
NC
NC
NC
NC
NC
NC
G
DNU
NC
NC
NC
NC
NC
H
NC
IO0
NC
NC
NC
VCC
J
NC
IO1
NC
VCC
IO5
IO7
K
VSS
IO2
IO3
IO4
IO6
VSS
9
10
NC
NC
NC
NC
L
NC
NC
NC
NC
M
NC
NC
NC
NC
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MX30LF1G08AA
3-1. PIN DESCRIPTIONS
SYMBOL
IO7 - IO0
PIN NAME
Data I/O port
CE#
Chip Enable (Active Low)
RE#
Read Enable (Active Low)
WE#
Write Enable (Active Low)
CLE
Command Latch Enable
ALE
Address Latch Enable
WP#
Write Protect (Active Low)
R/B#
Ready/Busy (Open Drain)
VSS
Ground
VCC
Power Supply for Device Operation
NC
DNU
Not Connected Internally
Do Not Use (Do Not Connect)
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MX30LF1G08AA
4. PIN FUNCTIONS
COMMAND LATCH ENABLE: CLE
The MX30LF1G08AA device is a sequential
access memory that utilizes multiplexing input of
Command/Address/Data.
The CLE controls the command input. When the
CLE goes high, the command data is latched at
the rising edge of the WE#.
I/O PORT: IO7 - IO0
ADDRESS LATCH ENABLE: ALE
The IO7 to IO0 pins are for address/command
input and data output to and from the device.
The ALE controls the address input. when the
ALE goes high, the address is latched at the rising
edge of WE#.
CHIP ENABLE: CE#
The device goes into low-power Standby Mode
when CE# goes High during a Read operation and
not at busy stage.
WRITE PROTECT: WP#
The WP# signal keeps low and then the memory
will not accept the program/erase operation. The
WP# pin is not latched by WE# for ensuring of
the data can be protected during power-on. It is
recommended to keep WP# pin low during power
on/off sequence. Please refer to the waveform of
"Power On/Off Sequence".
The CE# goes low to enable the device to be
ready for standard operation. When the CE# goes
high, the device is deselected. However, when the
device is at busy stage, the device will not go to
standby mode when CE# pin goes high.
READ ENABLE: RE#
READY/Busy: R/B#
The RE# (Read Enable) allows the data to be
output by a tREA time after the falling edge of
RE#. The internal address counter is automatically
increased by one at the falling edge of RE#.
The R/B# is an open-drain output pin. The R/B#
outputs the ready/busy status of read/program/
erase operation of the device. When the R/B# is
at low, the device is busy for read or program or
erase operation. When the R/B# is at high, the
read/program/erase operation is finished.
WRITE ENABLE: WE#
Please refer to Section 9.1 for details.
When the WE# goes low, the address/data/command are latched at the rising edge of WE#.
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MX30LF1G08AA
CE#
High Voltage
Circuit
CLE
WE#
WP#
RE#
R/B#
IO[7:0]
IO Port
ALE
Control
Logic
X-DEC
5. BLOCK DIAGRAM
Memory
Array
Page Buffer
Address
Counter
Y-DEC
Data
Buffer
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MX30LF1G08AA
6. DEVICE OPERATIONS
ADDRESS INPUT / COMMAND INPUT / DATA INPUT
Address input bus operation is for address input to select the memory address. The command input bus
operation is for giving command to the memory. The data input bus is for data input to the memory device.
Figure 2. AC Waveform for Command / Address / Data Latch Timing
CLE
ALE
CE#
tCS
/
/ tCLS / tALS
tCH tCLH
tWP
WE#
tDS
tDH
IO[7:0]
Figure 3. AC Waveforms for Address Input Cycle
tCLS
CLE
tWC
tWC
tWC
CE#
tWP
tWH
tWP
tWH
tWP
tWH
tWP
WE#
tALS
tALH
ALE
tDS
IO[7:0]
tDH
A7-A0
tDS
tDH
A11-A8
tDS
tDH
A19 - A12
tDS
tDH
A27-A20
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MX30LF1G08AA
Figure 4. AC Waveforms for Command Input Cycle
CLE
tCLS
tCLH
tCS
tCH
CE#
tWP
WE#
tALS
tALH
ALE
tDS
tDH
IO[7:0]
Figure 5. AC Waveforms for Data Input Cycle
tCLH
CLE
tCH
CE#
tWC
tWP
tWH
tWP
tWH
tWP
tWP
WE#
ALE
tALS
tDS
IO[7:0]
tDH
Din0
tDS
tDH
Din1
tDS
tDH
Din2
tDS
tDH
DinN
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MX30LF1G08AA
PAGE READ
When power is on, the default stage of the NAND flash memory is at read mode, so the 00h command cycle
is not needed for the read operation. The MX30LF1G08AA array is accessed in Page of 2,112 bytes. External
reads begins after the R/B# pin goes to READY.
The Read operation may also be initiated by writing the 00h command and giving the address (column and
row address) and being confirmed by the 30h command, the MX30LF1G08AA begins the internal read
operation and the chip enters busy state. The data can be read out in sequence after the chip is ready. Refer
to the waveform for Read Operation as below.
To access the data in the same page randomly, a command of 05h may be written and only column address
following and then confirmed by E0h command. The random read mode is not supported during cache read
operation.
Figure 6. AC Waveforms for Read Cycle
CLE
tCLS
tCLS
tCLH
tCLH
tCS
CE#
tWC
WE#
tALS
tCHZ
tAR
tALH
tALH
tOH
ALE
tRR
tWB
RE#
tR
tDS
IO[x:0]
tRC
00h
tDH
tDS tDH
1st Address
Cycle
tDS
2nd Address
Cycle
tDH
tDS tDH
3rd Address
Cycle
tDS
tDH
4th Address
Cycle
tREA
tDS tDH
Dout
30h
Dout
R/B#
Busy
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MX30LF1G08AA
Figure 7. AC Waveforms for Read Operation (Intercepted by CE#)
CLE
CE#
tCHZ
WE#
tAR
ALE
tOH
tRC
RE#
tRR
tWB
tR
IO[7:0]
00h
A7-A0
A11-A8
A19-A12
A27-A20
30h
Dout N
Dout N+1
Dout N+2
R/B#
Busy
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MX30LF1G08AA
Figure 8. Read Operation with CE# Don't Care
CLE
CE# Don’t Care
CE#
WE#
ALE
RE#
IO[7:0]
Start Addr (4 Cycles)
00h
Data Output (Sequential)
30h
R/B#
Busy
Note: The CE# "Don't Care" feature may simplify the system interface, which allows controller to
directly download the code from flash device, and the CE# transitions will not stop the read
operation during the latency time.
Figure 9. AC Waveforms for Sequential Data Out Cycle (After Read)
tCEA
CE#
tRC
tCHZ
tRP
tREH
tRP
tREH
tRP
tRP
RE#
tRHZ
tREA
IO[7:0]
tOH
Dout0
tRHZ
tRHZ
tOH
tOH
Dout2
DoutN
tRHZ
tREA
tOH
Dout1
tREA
tRR
R/B#
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MX30LF1G08AA
Figure 10. AC Waveforms for Random Data Output
A
tCLR
CLE
CE#
WE#
tAR
ALE
tRC
RE#
tRHW
tRR
tWB
tR
IO[7:0]
00h
A7-A0
A11-A8
A19-A12
A27-A20
Dout M
30h
Dout M+1
05h
R/B#
CLE
Busy
A
CE#
WE#
tWHR
ALE
RE#
tREA
IO[7:0]
05h
A7-A0
A11-A8
E0h
Dout N
Dout N+1
R/B#
Repeat if needed
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MX30LF1G08AA
CACHE READ
The cache read operation is for throughput enhancement by using the internal cache buffer. It allows
automatic downloading of the consecutive pages and reading the entire flash memory, no additional dead
time between pages or blocks. While the data is read out on one page, the data of next page can be read into
the cache buffer.
After writing the 00h command, the column and row address should be given for the start page selection. The
address A[11:0] for the start page should be 000h. Cache read begin command 31h should be issued to start
the cache read operation.
The random data out is not available for cache read operation. After the latency time tR, the data can be read
out continuously.
The user can check the chip status by the following method:
- R/B# pin ("0" means the data is not ready, "1" means the user can read the data)
- Status Register (SR[6] behaves the same as R/B# pin, SR[5] indicates the internal chip operation, "0"
means the chip is in internal operation and "1" means the chip is idle.) Status Register can be checked
after the Read Status command (70h) is issued. Command 00h should be given to return to the cache read
operation. To exit the cache read operation, the user needs to issue cache read end command (34h) or Reset
command. After the command is issued, the device will become idle within 5 us.
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MX30LF1G08AA
Figure 11. AC Waveforms for Cache Read
A
tCLR
CLE
CE#
WE#
tAR
ALE
tRC
RE#
tRR
tWB
tR
IO[7:0]
A7-A0
00h
A11-A8
A19-A12
A27-A20
Page 1
Dout 0
31h
Page 1
Page 1
Dout 1
Dout 2111
Page 2
Dout 0
R/B#
Busy
A
CLE
CE#
WE#
ALE
RE#
IO[7:0]
Page 1
Dout 2111
Page 2
Dout 0
Page 2
Dout 2111
Page
Page N
Dout 0
Repeat
Page N
Dout 2111
34h
tRCBSY
R/B#
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MX30LF1G08AA
PAGE PROGRAM
The memory is programmed by page, which is 2,112 bytes. After Program load command (80h) is issued
and the row and column address is given, the data will be loaded into the chip sequentially. Random Data
Input command (85h) allows multi-data load in non-sequential address. After data load is complete, program
confirm command (10h) is issued to start the page program operation. Partial program in a page is allowed
up to 4 times. However, the random data input mode for programming a page is allowed and number of times
is not limited.
The status of the program completion can be detected by R/B# pin or Status register bit (IO6).
The program result is shown in the chip status bit (SR[0]). SR[0] = 1 indicates the Page Program is not
successful and SR[0] = 0 means the program operation is successful.
During the Page Program progressing, only the read status register command and reset command are
accepted, others are ignored.
Figure 12. AC Waveforms for Program Operation after Command 80H
CLE
tCLS
tCLH
CE#
tCS
tWC
WE#
tALS
tALH
tWB
tALH
ALE
RE#
tDS
IO[7:0]
80h
tDH
A7A0
-
A11A8
A19- A12
A27A20
Din
1
Din
N
10h
70h
Status
Output
tPROG
R/B#
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MX30LF1G08AA
Figure 13. AC Waveforms for Random Data In (For Page Program)
A
CLE
CE#
tWC
tADL
WE#
ALE
RE#
IO[7:0]
80h
A7-A0
A11-A8
A19-A12
Din A
A27-A20
Din A+N
85h
A7-A0
R/B#
A
CLE
CE#
tWC
tADL
WE#
tWB
ALE
RE#
IO[7:0]
Din A+N
85h
A7-A0
A11-A8
Din B+M
Din B
Status
70h
10h
tPROG
R/B#
Repeat if needed
IO0 = 0; Pass
IO0 = 1; Fail
Note: Random Data In is also supported in cache program.
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MX30LF1G08AA
Figure 14. Program Operation with CE# Don't Care
A
CLE
CE#
WE#
ALE
IO[7:0]
80h
Start Add. (4 Cycles)
Data Input
A
CLE
CE#
WE#
ALE
IO[7:0]
Data Input
Data Input
10h
Note: The CE# "Don't Care" feature may simplify the system interface, which allows the controller to
directly write data into flash device, and the CE# transitions will not stop the program operation
during the latency time.
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MX30LF1G08AA
CACHE PROGRAM
The cache program feature enhances the program performance by using the cache buffer of 2,112-byte. The
serial data can be input to the cache buffer while the previous data stored in the buffer are programming into the
memory cell. Cache Program command sequence is almost the same as page program command sequence.
Only the Program Confirm command (10h) is replaced by cache Program command (15h).
After the Cache Program command (15h) is issued. The user can check the status by the following methods.
- R/B# pin
- Cache Status Bit (SR[6] = 0 indicates the cache is busy; SR[6] = 1 means the cache is ready).
The user can issue another Cache Program Command Sequence after the Cache is ready. The user can always
monitor the chip state by Ready/Busy Status Bit (SR[5]). The user can issues either program confirm command
(10h) or cache program command (15h) for the last page if the user monitor the chip status by issuing Read Status
Command (70h).
However, if the user only monitors the R/B# pin, the user needs to issue the program confirm command (10h) for
the last page.
The user can check the Pass/Fail Status through P/F Status Bit (SR[0]) and Cache P/F Status Bit (SR[1]). SR[1]
represents Pass/Fail Status of the previous page. SR[1] is updated when SR[6] change from 0 to 1 or Chip is
ready. SR[0] shows the Pass/Fail status of the current page. It is updated when SR[5] change from "0" to "1" or the
end of the internal programming. For more details, please refer to the related waveforms.
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MX30LF1G08AA
Figure 15-1. AC Waveforms for Cache Program
A
CLE
CE#
tADL
tWC
WE#
tWB
ALE
RE#
IO[x:0]
80h
1st Address
Cycle
2nd Address
Cycle
3rd Address
Cycle
4th Address
Cycle
Din
Din
15h
tCBSY
R/B#
Busy
A
CLE
CE#
tADL
WE#
tWB
ALE
RE#
IO[x:0]
80h
1st Address
Cycle
2nd
Address
A11-A8
Cycle
3rd Address
Cycle
4th Address
Cycle
Din
Din
70h
10h
Status
Output
tPROG
R/B#
Note
Busy
Note: It indicates the last page Input & Program.
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Figure 15-2. Sequence of Cache Program
A
IO[7:0]
A7-A0
80h
A11-A8 A19-A12 A27-A20
Din
Din
15h
80h
A7-A0
A11-A8 A19-A12 A27-A20
Din
Din
15h
80h
R/B#
Busy / tCBSY
Busy / tCBSY
A
IO[7:0]
80h
A7-A0
A11-A8 A19-A12 A27-A20
Din
Din
15h
80h
A7-A0
A11-A8 A19-A12 A27-A20
Din
Din
10h
70h
R/B#
Busy / tCBSY
Busy /tPROG
Note 2
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MX30LF1G08AA
BLOCK ERASE
The MX30LF1G08AA supports a block erase command. This command will erase a block of 64 pages associated with the 10 most significant address bits (A27-A18).
The completion of the erase operation can be detected by R/B# pin or Status register bit (IO6). Recommend
to check the status register bit IO0 after the erase operation completes.
During the erasing process, only the read status register command and reset command can be accepted,
others are ignored.
Figure 16. AC Waveforms for Erase Operation
CLE
tCLS
tCLH
CE#
tCS
tWC
WE#
tALH
tALS
ALE
tWB
RE#
tDS
IO[7:0]
tDH
tDS
tDH
tDS
tDH
60h
70h
D0h
Row Address 1
Row Address ２
Stauts
Output
tERASE
R/B#
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MX30LF1G08AA
ID READ
The device contains ID codes that identify the device type and the manufacturer. The ID READ command
sequence includes one command Byte (90h), one address byte (00h). The Read ID command 90h may
provide the manufacturer ID (C2h) of one-byte and device ID (F1h) of one-byte, also 3rd and 4th ID code are
followed.
Figure 17. AC Waveforms for ID Read Operation
CLE
tCLS
tCS
CE#
tCHZ
WE#
tALH
tALS
tAR
ALE
tOH
RE#
tDS
IO[7:0]
90H
tDH
00H
tREA
C2H
F1H
(note)
(note)
Note: Also see Table 12. ID Codes Read Out by ID Read Command 90H.
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MX30LF1G08AA
STATUS READ
The MX30LF1G08AA provides a status register that outputs the device status by writing a command code
70h, and then the IO pins output the status at the falling edge of CE# or RE# which occurs last. Even though
when multiple flash devices are connecting in system and the R/B#pins are common-wired, the two lines of
CE# and RE# may be checked for individual devices status separately. It is not required to toggle the CE# or
RE# for getting the status.
The status read command 70h will keep the device at the status read mode unless next valid command is
issued. The resulting information is outlined in Table 11.
Figure 18. AC Waveforms for Status Read Operation
tCLR
CLE
tCLS
tCLH
CE#
tCS
tWP
WE#
tCHZ
tWHR
RE#
tOH
tIR
tDS tDH
IO[7:0]
tREA
Status
Output
70H
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MX30LF1G08AA
RESET
The reset command FFh resets the read/program/erase operation and clear the status register to be E0h (when
WP# is high). The reset command during the program/erase operation will result in the content of the selected
locations(perform programming/erasing) might be partially programmed/erased.
If the Flash memory has already been set to reset stage with reset command, the additional new reset
command is invalid.
Figure 19. Reset Operation
CLE
WE#
ALE
RE#
IO[7:0]
FFh
tRST
R/B#
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7. PARAMETERS
7-1. ABSOLUTE MAXIMUM RATINGS
Temperature under Bias
-50°C to +125°C
Storage temperature
-65°C to +150°C
All input voltages with respect to ground (Note 2)
-0.6V to 4.6V
VCC supply voltage with respect to ground (Note 2)
-0.6V to 4.6V
ESD protection
>2000V
All output voltages with respect to ground (Note 2)
-0.6V to 4.6V
Notes:
1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
2. Minimum voltage may undershoot to -2V for the period of time less than 20ns.
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Table 1. Operating Range
VCC
Tolerance
+3.3 V
2.7 ~ 3.6 V
Temperature
-40°C to +85°C
Table 2. DC Characteristics
Symbol
Parameter
VIL
Input low level
VIH
Input high level
VOL
Output low voltage
VOH
Output high voltage
ISB1
VCC standby current (CMOS)
ISB2
VCC standby current (TTL)
ICC1
VCC active current
(Sequential Read)
ICC2
Test Conditions
IOL =2.1 mA,
VCC=VCC MIN
IOH= -400uA,
VCC=VCC MIN
CE# = VCC - 0.2 V,
WP#= 0/VCC
CE# = VIH MIN,
WP#= 0/VCC
tRC Minimum
CE#= VIL,
IOUT=0mA
Min.
Typical
Max.
Unit
-0.3
0.2VCC
V
0.8VCC
VCC+0.3
V
0.4
V
2.4
V
10
50
uA
1
mA
15
30
mA
VCC active current (Program)
15
30
mA
ICC3
VCC active current (Erase)
15
30
mA
ILI
Input leakage current
±10
uA
ILO
Output leakage current ±10
uA
ILO (R/B#)
Output current of R/B# pin
VIN = 0 to VCC MAX
VOUT = 0 to VCC
MAX
VOUT = VOL,
VCC = VCC MAX
8
10
mA
Table 3. Capacitance
TA = +25°C, F = 1 MHz
Symbol
Parameter
Max.
Units
Conditions
CIN
Input capacitance
Typ.
10
pF
VIN = 0 V
COUT
Output capacitance
10
pF
VOUT = 0 V
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Table 4. AC Testing Conditions
Testing Conditions
Input pulse level
Output load capacitance
Input rise and fall time
Input timing measurement reference levels
Output timing measurement reference levels
Value
Unit
0 to VCC
1 TTL + CL (50)
5
VCC/2
VCC/2
V
pF
ns
V
V
Figure 20. Device Under Test
VCC
VCC/2
0V
TEST
POINTS
VCC/2
INPUT
OUTPUT
3V
3.3k/ohm
DEVICE
UNDER
TEST
OUT
CL
6.2k/ohm
C L = 50 pF
Table 5. Program, Read and Erase Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Unit
250
700
us
4
700
us
tPROG
Page programming time
tCBSY (Program)
Dummy busy time for cache
tRCBSY (Read)
Dummy busy time for cache read
5
us
NOP
Number of partial program cycles in
same page
4
cycles
tERASE (Block)
Block erase time
3
ms
P/E
Number of program/erase cycles
per block
2
100,000
cycles
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Table 6. AC Characteristics over Operating Range
Symbol
Parameter
Min.
Max.
Unit
tCLS
tCLH
tCS
tCH
tWP
tALS
CLE setup time
CLE hold time
CE# setup time
CE# hold time
Write pulse width
ALE setup time
15
5
20
5
15
15
-
ns
ns
ns
ns
ns
ns
tALH
ALE hold time
5
-
ns
tDS
Data setup time
5
-
ns
tDH
Data hold time
5
-
ns
tWC
Write cycle time
30
-
ns
tWH
WE# high hold time
10
-
ns
tADL
100
-
ns
tWW
tRR
Last address latched to data loading time during
program operations
WP# transition to WE# high
Read -to- RE# falling edge
100
20
-
ns
ns
tRP
Read pulse width
15
-
ns
tRC
Read cycle time
30
-
ns
tREA
RE# access time (serial data access)
-
20
ns
tCEA
CE# access time
-
25
ns
tOH
Data output hold time
10
-
ns
tRHZ
RE# -high-to-output-high impedance
-
50
ns
tCHZ
CE#-high-to-output-high impedance
-
50
ns
tREH
RE# -high hold time
10
-
ns
tIR
Output-high-impedance-to- RE# falling edge
0
-
ns
tRHW
RE# high to WE# low
0
-
ns
tWHR
WE# high to RE# low
60
-
ns
tR
First byte latency
-
25
us
tWB
WE# high to busy
-
100
ns
tCLR
CLE low to RE# low
15
-
ns
tAR
ALE low to RE# low
10
-
ns
tRST
Device reset time (Idle/Read/Program/Erase)
-
5/5/10/500
us
Notes
Note: A maximum 5us time is required for the device goes "busy" mode if the FFh (reset command) is
setting at ready stage.
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8. SCHEMATIC CELL LAYOUT AND ADDRESS ASSIGNMENT
The MX30LF1G08AA array is organized as 1024 blocks, which is composed by 64 pages of (2,048+64)-byte
in two NAND strings structure with 32 serial connected cells in each string. Each page has an additional 64
bytes for ECC and other purposes. The device has an on-chip buffer of 2,112 bytes for data load and access.
Each 2K-Byte page has the two area, one is the main area which is 2048-bytes and the other is spare area
which is 64-byte.
There are four address cycles for the address allocation, please refer to Table 7.
Table 7. Address Allocation
Addresses
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
Column address - 1st cycle
A7
A6
A5
A4
A3
A2
A1
A0
Column address - 2nd cycle
*L
*L
*L
*L
A11
A10
A9
A8
Row address - 3rd cycle
A19
A18
A17
A16
A15
A14
A13
A12
Row address - 4th cycle
A27
A26
A25
A24
A23
A22
A21
A20
Note: IO7 to IO4 must be set to Low in the second cycle.
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MX30LF1G08AA
9. OPERATION MODES: LOGIC AND COMMAND TABLES
Address input, command input and data input/output are managed by the CLE, ALE, CE#, WE#, RE# and
WP# signals, as shown in Table 8.
Program, Erase, Read and Reset are four major operations modes controlled by command sets, please refer
to Table 9.
Table 8. Logic Table
Mode
CE#
RE#
Address Input (Read Mode)
L
Address Input (Write Mode)
WE#
CLE
ALE
WP#
H
L
H
X
L
H
L
H
H
Command Input (Read Mode)
L
H
H
L
X
Command Input (Write Mode)
L
H
H
L
H
Data Input
L
H
L
L
H
Data Output
L
H
L
L
X
During Read (Busy)
X
H
H
L
L
X
During Programming (Busy)
X
X
X
X
X
H
During Erasing (Busy)
X
X
X
X
X
H
Program/Erase Inhibit
X
X
X
X
X
L
Stand-by
H
X
X
X
X
0V/VCC
Notes:
1. H = VIH; L = VIL;
X = VIH or VIL
2. WP# should be biased to CMOS high or CMOS low for stand-by.
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MX30LF1G08AA
Table 9. HEX Command Table
First Cycle
Second Cycle
00H
85H
05H
00H
34H
90H
FFH
80H
80H
60H
70H
30H
E0H
31H
Read Mode
Random Data Input
Random Data Output
Cache Read Begin
Cache Read End
Read ID
Reset
Page Program
Cache Program
Block Erase
Read Status
Acceptable While Busy
V
10H
15H
D0H
-
V
V
Caution: Any undefined command inputs are prohibited except for above command set.
The following is an example of a HEX data bit assignment:
Figure 21. Bit Assignment (HEX Data)
Status Read: 70H
0
1
1
1
0
0
0
0
SR7
6
5
4
3
2
1 SR0
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MX30LF1G08AA
Table 10. Status Output
Pin
Status
SR[0]
Chip Status
SR[1]
Cache Program
Result
SR[2] - SR[4]
Not Used
Related Mode
Page Program, Cache
Program (Page N), Block
Erase
Cache Program (Page
N-1)
Cache Program/Cache
Ready / Busy (For Read operation, other
Page Program/Block
P/E/R Controller) Erase/Read are same as
IO6
Page Program, Block
Ready / Busy
Erase, Cache Program,
Read, Cache Read
Page Program, Block
Write Protect
Erase, Cache Program,
Read
SR[5]
SR[6]
SR[7]
Value
0: Passed
1: Failed 0: Passed
1: Failed
0: Busy
1: Ready
0: Busy
1: Ready
0: Protected
1: Unprotected
Table 11. ID Codes Read Out by ID Read Command 90H
Data
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
Hex
Maker Code
1
1
0
0
0
0
1
0
C2H
Device Code
1
1
1
1
0
0
0
1
F1H
3rd Code
1
0
0
0
0
0
0
0
80H
4th Code
0
0
0
1
1
1
0
1
1DH
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MX30LF1G08AA
Table 12. The Definition of 3rd Code of ID Table
Definition
Information
1 Die
IO1, IO0= 0,0
2 Die
IO1, IO0= 0,1
4 Die
IO1, IO0= 1,0
Reserved
IO1, IO0= 1,1
Single level cell
IO3, IO2= 0,0
2x Mult-level cell
IO3, IO2= 0,1
Reserved
IO3, IO2= 1,0
Reserved
IO3, IO2= 1,1
1
IO5, IO4= 0,0
2
IO5, IO4= 0,1
3
IO5, IO4= 1,0
4
IO5, IO4= 1,1
Not supported
IO6=0
Supported
IO6=1
Not supported
IO7=0
Supported
IO7=1
Die number
Cell Structure
Number of concurrently programmed
pages
Interleaved programming between
diverse devices
Cache Program
Value
Table 13. The Definition of 4th Code of ID Table
Definition
Information
1K-byte
IO1, IO0= 0,0
2K-byte
IO1, IO0= 0,1
4K-byte
IO1, IO0= 1,0
Reserved
IO1, IO0= 1,1
8
IO2=0
16
IO2=1
50ns
IO7, IO3= 0,0
30ns
IO7, IO3= 0,1
Page Size (exclude spare area)
Size of spare area (byte per 512-byte)
Sequential Read Cycle Time
Block Size (exclude spare area)
Value
25ns
IO7, IO3= 1,0
Reserved
IO7, IO3= 1,1
64K-byte
IO5, IO4= 0,0
128K-byte
IO5, IO4= 0,1
256K-byte
IO5, IO4= 1,0
512K-byte
IO5, IO4= 1,1
8-bit
16-bit
IO6=0
IO6=1
Organization
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MX30LF1G08AA
9-1. R/B#: TERMINATION FOR THE READY/BUSY# PIN (R/B#)
The R/B# is an open-drain output pin and a pull-up resistor is necessary to add on the R/B# pin. The R/B#
outputs the ready/busy status of read/program/ erase operation of the device. When the R/B# is at low, the
device is busy for read or program or erase operation. When the R/B# is at high, the read/program/erase
operation is finished.
Figure 22. R/B# Pin Timing Information
@ Vcc = 3.3 V, Ta = 25°C, CL=50pF
tr, tf [s]
2.4
200
ibusy
200n
1.2
100
100n
2m ibusy [A]
150
1m
0.8
tr
50
0.6
tf
1.8
1k
1.8
1.8
1.8
2k
3k
4k
Rp (ohm)
VCC
VCC
Device
Ready Vcc
Rp
CL
VOH
R/B#
VOL
Busy
VOL
VSS
tf
tr
Rp Value Guidence
Rp (min.) =
Vcc (Max.) - VOL (Max.)
IOL+ΣIL
=
3.2V
8mA + ΣIL
Where IL is the sum of the input currnts of all devices tied to the R/B pin.
Rp (max) is determined by maximum permissible limit of tr.
Considering of the variation of device-by-device, the above data is for reference to decide the resistor value.
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MX30LF1G08AA
9-2. POWER ON/OFF SEQUENCE
After the Chip reaches the power on level (Vth = 2.5 V), the internal power on reset sequence will be
triggered. During the internal power on reset period, no any external command is accepted. There are two
ways to identify the termination of the internal power on reset sequence. Please refer to the “power on/off
sequence” waveform.
•
R/B# pin
•
Wait 1 ms
During the power on and power off sequence, it is recommended to keep the WP# = Low for internal data
protection.
Figure 23. Power On/Off Sequence
2.5 V (Vth)
Vcc
WP#
WE#
1 ms
1 us (min.)
R/B#
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MX30LF1G08AA
9-2-1. WP# Signal
Below figures show the relationship between WP# signal and the four operations of the enabled/disable
program and enabled/disabled erase.
Figure 24. Enable Programming
WE#
IO[7:0]
WP#
80h
10h
tWW
WE#
Figure 25. Disable Programming
IO[7:0]
80h
10h
tWW
WP#
Figure 26. Enable Erasing
WE#
IO[7:0]
WP#
Figure 27. Disable Erasing
60h
D0h
tWW
WE#
IO[7:0]
60h
D0h
tWW
WP#
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10. SOFTWARE ALGORITHM
10-1.INVALID BLOCKS (BAD BLOCKS)
The bad blocks are included in the device while it is shipped. During the time of using the device, the
additional bad blocks might be increasing; therefore, it is recommended to check the bad block marks and
avoid to use the bad blocks. Furthermore, please read out the bad block information before any erase
operation since it may be cleared by any erase operation.
Figure 28. Bad Blocks
Bad Block
Bad Block
While the device is shipped, the value of all data bytes of the good blocks are FFh. The 1st byte of the 1st
or 2nd page in the spare area for bad block will not be FFh. The erase operation at the bad blocks is not
recommended.
After the device is installed in the system, the bad block checking is recommended. The figure shows the brief
test flow by the system software managing the bad blocks while the bad blocks were found. When a block
gets damaged, it should not be used any more.
Due to the blocks are isolated from bit-line by the selected gate, the performance of good blocks will not be
impacted by bad ones.
Table 14. Valid Blocks
Min
Valid (Good) Block Number
1004
Typ.
Max
Unit
1024
Block
Remark
Block 0 is guaranteed to be good
up to 1K cycles with 1 bit ECC per
528-byte
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MX30LF1G08AA
10-2.BAD BLOCK TEST FLOW
Although the initial bad blocks are marked by the flash vendor, they could be inadvertently erased and
destroyed by a user that does not pay attention to them. To prevent this from occurring, it is necessary to
always know where any bad blocks are located. Continually checking for bad block markers during normal
use would be very time consuming, so it is highly recommended to initially locate all bad blocks and build a
bad block table and reference it during normal NAND flash use. This will prevent having the initial bad block
markers erased by an unexpected program or erase operation. Failure to keep track of bad blocks can be
fatal for the application. For example, if boot code is programmed into a bad block, a boot up failure may
occur. The following section shows the recommended flow for creating a bad block table.
Figure 29. Bad Block Test Flow
Start
Block No. = 0
Fail
Create (or Update)
Bad Block Table
Read FFh (Note)
Check
Pass
Block No. = Block No. + 1
Block No. = 1023
No
Yes
End
Note: Read FFh check is at the 1st byte of the 1st and 2nd pages of the block spare area.
10-3.FAILURE PHENOMENA FOR READ/PROGRAM/ERASE OPERATIONS
The device may fail during a Read, Program or Erase operation. The following possible failure modes should
be considered when implementing a highly reliable system:
Table 15. Failure Modes
Failure Mode
Detection and Countermeasure
Sequence
Erase Failure
Status Read after Erase
Block Replacement
Programming Failure
Status Read after Program
Block Replacement
Read Failure
Read Failure
ECC
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MX30LF1G08AA
10-4.PROGRAM
When an error occurs in page A, please re-load the data from the data buffer to re-program data to other good
page (e.g. page B) of other good blocks. It is recommended to create the bad block table or other method by
system software to avoid using the bad blocks.
Figure 30. Failure Modes
Program error occurs in Page A
Buffer
Memory
Block
Another good block
Page B
Figure 31. Program Flow Chart
Start
Command 80h
Program
Command
Flow
Set Address
Write Data
Write 10h
Read Status Register
No
SR[6] = 1 ?
(or R/B# = 1 ?)
Yes
* Program Error
No
SR[0] = 0 ?
Yes
Program Completed
10-5.ERASE
When an error occurs during erase operation, it is recommended to create the bad block table or other
method by system software to avoid using the bad blocks.
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MX30LF1G08AA
Figure 32. Erase Flow Chart
Start
Command 60h
Set Block Address
Command D0h
Read Status Register
SR[6] = 1 ?
(or R/B# = 1 ?)
No
Yes
No
SR[0] = 0 ?
* Erase Error
Yes
Erase Completed
*
The failed blocks will be identified and given errors
in status register bits for attempts on erasing them.
Figure 33. Read Flow Chart
Start
Command 00h
Set Address
Command 30h
Read Status Register
SR[6] = 1 ?
(or R/B# = 1 ?)
No
Yes
Read Data Out
ECC Generation
Host controller
ECC handling
Verify ECC
No
Reclaim the Error
Yes
Page Read Completed
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MX30LF1G08AA
Application Notes
1) Ready time depends on the pull-up resistor tied to the R/B# pin.
2) No programming is allowed on an un-erased page. If this is done no PGM is performed and a status
register is given to the user. User then needs only to choose a different address and not to insert the data
again. It is recommended to forbid cosecutive programming on its own controller.
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11. PACKAGE INFORMATION
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Title: Package Outline for 63-VFBGA (9x11x1.0mm, Ball-pitch: 0.8mm, Ball-diameter: 0.45mm)
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MX30LF1G08AA
12. REVISION HISTORY
Rev. No.
Descriptions
Page
Date
0.01
1. Figures 3, 5, 6, 7, 8, 10, 12, 15, 16, 17, 18, 22, 24, modified P10, 12 to 14, 16, 17,
OCT/19/2011
P22 to 25, 31 to 33, 37, 39 to 43
2. Chapter 8 & 9: description updated
P32, 33
3. Table 8. Logic & Command Table modified
P33
0.02
1. "Optional code" added in part number
2. NOP modified from 8 (main area plus spare area) to 4 3. Typical program time modified from 200us to 250us 4. Ready/busy pin timing information axis adjustment 5. Power on timing spec modified from 2ms to 1ms
All
P16, 28
P4, 28
P37
P38
APR/18/2011
0.03
1. Changed datasheet title to Preliminary
P4
MAY/05/2011
0.04 1. Ordering information revised due to part name changed
All
from MX30LF1G08AM to MX30LF1G08AA
2. Wording-rephrase & capitalization
All
3. Waveforms adjustmentAll
4. Table 2. VLKO specifications removed
P30
AUG/19/2011
0.05
1. Rephrased and adjusted waveform sequences
2. Added "DNU" ball for VFBGA
3. Modified Figure "AC Waveform for Cache Read" 4. Added the check mark of "Acceptable while busy" for Cache Read End item in Command Table
5. Added "Read Failure" in table of Failure Modes 6. Marked the VFBGA as "Advanced Information"
7. Removed "Secure OTP (Optional)"
8. Removed C grade descripton
9. Added R/B# timing in Power On/Off Waveform
All
P6
P17
P34
DEC/28/2011
0.06
1. Modified the VFBGA ball-out: H8 from "NC" to "VCC" P6
FEB/08/2012
1.0
1.1
1.2
1. Removed "Preliminary" from Datasheet title
1. Removed "Advanced Information" for VFBGA package
1. Content wording rephrased
2. Flow chart modifications
P4
P4, 5
P9, 32, 37, 39, 40, 42
P42,43
JUN/04/2012
AUG/13/2012
MAR/28/2013
1.3
1.4 1.5
1. Added "Bad Block Table Build up" descriptions
P41
1. Changed tCLR from 15ns to 10ns P31 1. Corrected tALS timing waveform as ALE high till WE# high P18
for Figure 12. P41
P4, 5
P4
P4, 5, 29
P38
DEC/18/2013
FEB/27/2014
SEP/17/2014
REV. 1.5, SEP. 17, 2014
P/N: PM1113
47
MX30LF1G08AA
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thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit,
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MACRONIX INTERNATIONAL CO., LTD.
http://www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
REV. 1.5, SEP. 17, 2014
P/N: PM1113
48