MX29LV065B MX29LV065B DATASHEET The MX29LV065B product will be phase-out, and is not recommended for new design. P/N:PM1082 REV. 1.7, APR. 18, 2008 1 MX29LV065B 64M-BIT [8M x 8] EQUAL SECTOR FLASH MEMORY The MX29LV065B product will be phase-out, and is not recommended for new design. FEATURES GENERAL FEATURES • 8,388,608 x 8 structure • One hundred twenty-eight Equal Sectors with 64KB each - Any combination of sectors can be erased with erase suspend/resume function • Thirty-two Sector Groups - Provides sector group protect function to prevent program or erase operation in the protected sector group - Provides chip unprotected function to allow code changing - Provides temporary sector group unprotected function for code changing in previously protected sector groups • Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations • Latch-up protected to 250mA from -1V to Vcc + 1V • Low Vcc write inhibit is equal to or less than 2.5V • Compatible with JEDEC standard - Pinout and software compatible to single power supply Flash • Extra 128-byte sector for security - Feature factory locked and identifiable, and customer locked PERFORMANCE • High Performance - Fast access time: 90/120ns - Fast program time: 7us/byte, 42s/chip (typical) - Fast erase time: 0.9s/sector, 45s/chip (typical) • Low Power Consumption - Low active read current: 9mA (typical) at 5MHz - Low standby current: 200nA (typical) • Minimum 100,000 erase/program cycle • 20-years data retention SOFTWARE FEATURES • Erase Suspend/ Erase Resume - Suspends sector erase operation to read data from or program data to another sector which is not being erased • Status Reply - Data# polling & Toggle bits provide detection of program and erase operation completion • Support Command Flash Interface (CFI) HARDWARE FEATURES • Ready/Busy# (RY/BY#) Output - Provides a hardware method of detecting program and erase operation completion • Hardware Reset (RESET#) Input - Provides a hardware method to reset the internal state machine to read mode • ACC input pin - Provides accelerated program capability P/N:PM1082 REV. 1.7, APR. 18, 2008 2 MX29LV065B PACKAGE • 48-pin TSOP • All Pb-free devices are RoHS Compliant • All non RoHS Compliant devices are not recommeded for new design in PIN CONFIGURATION 48 TSOP NC A22 A16 A15 A14 A13 A12 A11 A9 A8 WE# RESET# ACC RY/BY# A18 A7 A6 A5 A4 A3 A2 A1 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 MX29LV065B PIN DESCRIPTION SYMBOL A0~A22 Q0~Q7 CE# WE# OE# RESET# RY/BY# VCC ACC VI/O GND NC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC A17 GND A20 A19 A10 Q7 Q6 Q5 Q4 VCC VI/O A21 Q3 Q2 Q1 Q0 OE# GND CE# A0 NC NC LOGIC SYMBOL PIN NAME Address Input 8 Data Inputs/Outputs Chip Enable Input Write Enable Input Output Enable Input Hardware Reset Pin, Active Low Read/Busy Output +3.3V single power supply Hardware Acceleration Pin Input/Output buffer (2.7V~3.6V) this input should be tied directly to VCC Ground Pin Not Connected Internally 23 A0-A22 8 Q0-Q7 V I/O CE# OE# WE# RY/BY# RESET# ACC P/N:PM1082 REV. 1.7, APR. 18, 2008 3 MX29LV065B BLOCK DIAGRAM CE# OE# WE# RESET# ACC WRITE CONTROL STATE INPUT LOGIC HIGH VOLTAGE MACHINE (WSM) LATCH BUFFER STATE MX29LV065B FLASH REGISTER ARRAY ARRAY Y-DECODER AND X-DECODER ADDRESS A0-A22 PROGRAM/ERASE Y-PASS GATE SOURCE HV COMMAND DATA DECODER SENSE AMPLIFIER PGM DATA HV COMMAND DATA LATCH PROGRAM DATA LATCH Q0-Q7 I/O BUFFER P/N:PM1082 REV. 1.7, APR. 18, 2008 4 MX29LV065B Table 1. SECTOR (GROUP) STRUCTURE Sector A22 A21 A20 A19 A18 A17 A16 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 P/N:PM1082 8-bit Address Range (in hexadecimal) 000000-00FFFF 010000-01FFFF 020000-02FFFF 030000-03FFFF 040000-04FFFF 050000-05FFFF 060000-06FFFF 070000-07FFFF 080000-08FFFF 090000-09FFFF 0A0000-0AFFFF 0B0000-0BFFFF 0C0000-0CFFFF 0D0000-0DFFFF 0E0000-0EFFFF 0F0000-0FFFFF 100000-10FFFF 110000-11FFFF 120000-12FFFF 130000-13FFFF 140000-14FFFF 150000-15FFFF 160000-16FFFF 170000-17FFFF 180000-18FFFF 190000-19FFFF 1A0000-1AFFFF 1B0000-1BFFFF 1C0000-1CFFFF 1D0000-1DFFFF 1E0000-1EFFFF 1F0000-1FFFFF 200000-20FFFF 210000-21FFFF 220000-22FFFF 230000-23FFFF 240000-24FFFF 250000-25FFFF REV. 1.7, APR. 18, 2008 5 MX29LV065B Sector A22 A21 A20 A19 A18 A17 A16 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 8-bit Address Range (in hexadecimal) 260000-26FFFF 270000-27FFFF 280000-28FFFF 290000-29FFFF 2A0000-2AFFFF 2B0000-2BFFFF 2C0000-2CFFFF 2D0000-2DFFFF 2E0000-2EFFFF SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2F0000-2FFFFF 300000-30FFFF 310000-31FFFF 320000-32FFFF 330000-33FFFF 340000-34FFFF 350000-35FFFF 360000-36FFFF 370000-37FFFF 380000-38FFFF 390000-39FFFF 3A0000-3AFFFF 3B0000-3BFFFF 3C0000-3CFFFF 3D0000-3DFFFF 3E0000-3EFFFF 3F0000-3FFFFF 400000-40FFFF 410000-41FFFF 420000-42FFFF 430000-43FFFF 440000-44FFFF 450000-45FFFF 460000-46FFFF 470000-47FFFF 480000-48FFFF 490000-49FFFF 4A0000-4AFFFF 4B0000-4BFFFF 4C0000-4CFFFF 4D0000-4DFFFF P/N:PM1082 REV. 1.7, APR. 18, 2008 6 MX29LV065B Sector A22 A21 A20 A19 A18 A17 A16 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 P/N:PM1082 8-bit Address Range (in hexadecimal) 4E0000-4EFFFF 4F0000-4FFFFF 500000-50FFFF 510000-51FFFF 520000-52FFFF 530000-53FFFF 540000-54FFFF 550000-55FFFF 560000-56FFFF 570000-57FFFF 580000-58FFFF 590000-59FFFF 5A0000-5AFFFF 5B0000-5BFFFF 5C0000-5CFFFF 5D0000-5DFFFF 5E0000-5EFFFF 5F0000-5FFFFF 600000-60FFFF 610000-60FFFF 620000-62FFFF 630000-63FFFF 640000-64FFFF 650000-65FFFF 660000-66FFFF 670000-67FFFF 680000-68FFFF 690000-69FFFF 6A0000-6AFFFF 6B0000-6BFFFF 6C0000-6CFFFF 6D8000-6DFFFF 6E0000-6EFFFF 6F8000-6FFFFF 700000-70FFFF 710000-71FFFF 720000-72FFFF 730000-73FFFF 740000-74FFFF 750000-75FFFF REV. 1.7, APR. 18, 2008 7 MX29LV065B Sectpr A21 A20 A19 A18 A17 A16 A15 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 8-bit Address Range (in hexadecimal) 760000-76FFFF 770000-77FFFF 780000-78FFFF 790000-79FFFF 7A0000-7AFFFF 7B0000-7BFFFF 7C0000-7CFFFF 7D0000-7DFFFF 7E0000-7EFFFF SA127 1 1 1 1 1 1 1 7F0000-7FFFFF Note: All sector groups are 64K bytes in size. P/N:PM1082 REV. 1.7, APR. 18, 2008 8 MX29LV065B Sector Group Protection/Unprotected Address Table Sector Group A21-A17 SA0-SA3 00000 SA4-SA7 00001 SA8-SA11 00010 SA12-SA15 00011 SA16-SA19 00100 SA20-SA23 00101 SA24-SA27 00110 SA28-SA31 00111 SA32-SA35 01000 SA36-SA39 01001 SA40-SA43 01010 SA44-SA47 01011 SA48-SA51 01100 SA52-SA55 01101 SA56-SA59 01110 SA60-SA63 01111 SA64-SA67 10000 SA68-SA71 10001 SA72-SA75 10010 SA76-SA79 10011 SA80-SA83 10100 SA84-SA87 10101 SA88-SA91 10110 SA92-SA95 10111 SA96-SA99 11000 SA100-SA103 11001 SA104-SA107 11010 SA108-SA111 11011 SA112-SA115 11100 SA116-SA119 11101 SA120-SA123 11110 SA124-SA127 11111 Note: All sector groups are 256K bytes in size. P/N:PM1082 REV. 1.7, APR. 18, 2008 9 MX29LV065B Table 2. BUS OPERATION--1 Mode Select RESET# CE# WE# OE# ACC Address Data (I/O) Q0~Q7 Device Reset L X X X X X HighZ Standby Mode Vcc±0.3V Vcc±0.3V X X H X HighZ Output Disable H L H H X X HighZ Read Mode H L H L X AIN DOUT Write (Note1) H L L H X AIN DIN Vhv X X X X AIN DIN Vhv L L H X Sector Address, DIN, DOUT Temporary Sector-Group Unprotect Sector-Group Protect (Note2) A6=L, A1=H, A0=L Chip Unprotect Vhv L L H X (Note2) Sector Address, DIN, DOUT A6=H, A1=H, A0=L Accelerated H L L H Vhv AIN DIN, DOUT Program Notes: 1. All sectors will be unprotected if ACC=Vhv. 2. Q0~Q7 are input (DIN) or output (DOUT) pins according to the requests of command sequence, sector protection, or data polling algorithm. 3. AM: MSB of address. P/N:PM1082 REV. 1.7, APR. 18, 2008 10 MX29LV065B BUS OPERATION--2 Item Control Input CE# WE# OE# AM A11 to to A8 A9 A12 A10 Sector Lock Status L H L SA x to A5 A6 A7 Vhv x to A1 A0 Q0~Q7 H L 01h or A2 L x Verification 00h (Note1) Read Silicon ID L H L x x Vhv x L x L L C2H Read Silicon ID L H L x x Vhv x L x L H 93H Read Indicator Bit L H L x x Vhv x L x H H 90h or Manufacturer Code (Q7) For Security 10h Sector (Note2) Notes: 1. Sector unprotected code:00h. Sector protected code:01h. 2. Factory locked code: 90h. Factory unlocked code: 10h. 3. AM: MSB of address. P/N:PM1082 REV. 1.7, APR. 18, 2008 11 MX29LV065B WRITE COMMANDS/COMMAND SEQUENCES To write a command to the device, system must drive WE# and CE# to Vil, and OE# to Vih. In a command cycle, all address are latched at the later falling edge of CE# and WE#, and all data are latched at the earlier rising edge of CE# and WE#. Figure 1 illustrates the AC timing waveform of a write command, and Table 3 defines all the valid command sets of the device. System is not allowed to write invalid commands not defined in this datasheet. Writing an invalid command will bring the device to an undefined state. REQUIREMENTS FOR READING ARRAY DATA Read array action is to read the data stored in the array. While the memory device is in powered up or has been reset, it will automatically enter the status of read array. If the microprocessor wants to read the data stored in the array, it has to drive CE# (device enable control pin) and OE# (Output control pin) as Vil, and input the address of the data to be read into address pin at the same time. After a period of read cycle (Tce or Taa), the data being read out will be displayed on output pin for microprocessor to access. If CE# or OE# is Vih, the output will be in tri-state, and there will be no data displayed on output pin at all. After the memory device completes embedded operation (automatic Erase or Program), it will automatically return to the status of read array, and the device can read the data in any address in the array. In the process of erasing, if the device receives the Erase suspend command, erase operation will be stopped temporarily after a period of time no more than Tready1 and the device will return to the status of read array. At this time, the device can read the data stored in any address except the sector being erased in the array. In the status of erase suspend, if user wants to read the data in the sectors being erased, the device will output status data onto the output. Similarly, if program command is issued after erase suspend, after program operation is completed, system can still read array data in any address except the sectors to be erased. The device needs to issue reset command to enable read array operation again in order to arbitrarily read the data in the array in the following two situations: 1. In program or erase operation, the programming or erasing failure causes Q5 to go high. 2. The device is in auto select mode or CFI mode. In the two situations above, if reset command is not issued, the device is not in read array mode and system must issue reset command before reading array data. ACCELERATED PROGRAM OPERATION The accelerated program can improve programming performance compared with byte program. By applying Vhv on ACC pin, the device will enter accelerated program and draw current no more than Icw from ACC pin. Removing the Vhv from ACC pin will put the device back to normal operation (not accelerated). P/N:PM1082 REV. 1.7, APR. 18, 2008 12 MX29LV065B RESET# OPERATION Driving RESET# pin low for a period more than Trp will reset the device back to read mode. If the device is in program or erase operation, the reset operation will take at most a period of Tready1 for the device to return to read array mode. Before the device returns to read array mode, the RY/BY# pin remains low (busy status). When RESET# pin is held at GND±0.3V, the device consumes standby current(Isb).However, device draws larger current if RESET# pin is held at Vil but not within GND±0.3V. It is recommended that the system to tie its reset signal to RESET# pin of flash memory, so that the flash memory will be reset during system reset and allows system to read boot code from flash memory. SECTOR GROUP PROTECT OPERATION When a sector group is protected, program or erase operation will be disabled on these sectors. MX29LV065B provides two methods for sector group protection. Once the sector group is protected, the sector group remains protected until next chip unprotect, or is temporarily unprotected by asserting RESET# pin at Vhv. Refer to temporary sector group unprotect operation for further details. The first method is by applying Vhv on RESET# pin. Refer to Figure 13 for timing diagram and Figure 14 for the algorithm for this method. The other method is asserting Vhv on A9 and OE# pins, with A6 and CE# at Vil. The protection operation begins at the falling edge of WE# and terminates at the rising edge. Contact Macronix for details. CHIP UNPROTECT OPERATION MX29LV065B provides two methods for chip unprotect. The chip unprotect operation unprotects all sectors within the device. It is recommended to protect all sectors before activating chip unprotect mode. All sector groups are unprotected when shipped from the factory. The first method is by applying Vhv on RESET# pin. Refer to Figure 13 for timing diagram and Figure 14 for algorithm of the operation. The other method is asserting Vhv on A9 and OE# pins, with A6 at Vih and CE# at Vil (see Table 2). The unprotect operation begins at the falling edge of WE# and terminates at the rising edge. Contact Macronix for details. TEMPORARY SECTOR GROUP UNPROTECT OPERATION System can apply RESET# pin at Vhv to place the device in temporary unprotect mode. In this mode, previously protected sectors can be programmed or erased just as it is unprotected. The devices returns to normal operation once Vhv is removed from RESET# pin and previously protected sectors are again protected. P/N:PM1082 REV. 1.7, APR. 18, 2008 13 MX29LV065B AUTOMATIC SELECT OPERATION When the device is in Read array mode, erase-suspended read array mode or CFI mode, user can issue read silicon ID command to enter read silicon ID mode. After entering read silicon ID mode, user can query several silicon IDs continuously and does not need to issue read silicon ID mode again. When A0 is Low, device will output Macronix Manufacture ID C2. When A0 is high, device will output Device ID. In read silicon ID mode, issuing reset command will reset device back to read array mode or erase-suspended read array mode. Another way to enter read silicon ID is to apply high voltage on A9 pin with CE#, OE#, A6 and A1 at Vil. While the high voltage of A9 pin is discharged, device will automatically leave read silicon ID mode and go back to read array mode or erase-suspended read array mode. When A0 is Low, device will output Macronix Manufacture ID C2. When A0 is high, device will output Device ID. VERIFY SECTOR GROUP PROTECT STATUS OPERATION MX29LV065B provides hardware sector protection against Program and Erase operation for protected sectors. The sector protect status can be read through Sector Protect Verify command. This method requires Vhv on A9 pin, Vih on WE# and A1 pins, Vil on CE#, OE#, A6 and A0 pins, and sector address on A12 to Am pins. If the read out data is 01H, the designated sector is protected. Oppositely, if the read out data is 00H, the designated sector is not protected. SECURITY SECTOR FLASH MEMORY REGION The security sectors can be locked upon shipping from factory, or it can be locked by customer after shipping. Customer can issue Security Sector Factory Protect Verify and/or Security Sector Protect Verify to query the lock status of the device. In factory-locked device, security sector region is protected when shipped from factory and the security silicon sector indicator bit is set to "1". In customer lockable device, security sector region is unprotected when shipped from factory and the security silicon indicator bit is set to "0". Factory Locked: Security Sector Programmed and Protected at the Factory In a factory locked device, the security silicon region is permanently locked after shipping from factory. The device will have a 16-byte ESN in the security region. In device : 000000h - 00000Fh. Customer Lockable: Security Sector NOT Programmed or Protected at the Factory When the security feature is not required, the security region can act as an extra memory space. The security silicon sector can be read, programmed at address 000010h-00008Fh. Security silicon sector can also be protected by two methods. Note that once the security silicon sector is protected, there is no way to unprotect the security silicon sector and the content of it can no longer be altered. The first method is to write a three-cycle command of Enter Security Region, and then follow the sector group protect algorithm as illustrated in Figure 14, except that RESET# pin may at either Vih or Vhv. The other method is to write a three-cycle command of Enter Security Region, and then follow the alternate method of P/N:PM1082 REV. 1.7, APR. 18, 2008 14 MX29LV065B sector protect with A9, OE# at Vhv. After the security silicon is locked and verified, system must write Exit Security Sector Region, go through a power cycle, or issue a hardware reset to return the device to read normal array mode. DATA PROTECTION To avoid accidental erasure or programming of the device, the device is automatically reset to read array mode during power up. Besides, only after successful completion of the specified command sets will the device begin its erase or program operation. Other features to protect the data from accidental alternation are described as followed. LOW VCC WRITE INHIBIT The device refuses to accept any write command when Vcc is less than 2.5V. This prevents data from spuriously altered. The device automatically resets itself when Vcc is lower than 2.5V and write cycles are ignored until Vcc is greater than 2.5V. System must provide proper signals on control pins after Vcc is larger than 2.5V to avoid unintentional program or erase operation WRITE PULSE "GLITCH" PROTECTION CE#, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle. LOGICAL INHIBIT A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is ignored when either CE# at Vih, WE# a Vih, or OE# at Vil. POWER-UP SEQUENCE Upon power up, MX29LV065B is placed in read array mode. Furthermore, program or erase operation will begin only after successful completion of specified command sequences. POWER-UP WRITE INHIBIT When WE#, CE# is held at Vil and OE# is held at Vih during power up, the device ignores the first command on the rising edge of WE#. POWER SUPPLY DECOUPLING A 0.1uF capacitor should be connected between the Vcc and GND to reduce the noise effect. P/N:PM1082 REV. 1.7, APR. 18, 2008 15 MX29LV065B TABLE 3. MX29LV065B COMMAND DEFINITIONS Read Mode Reset Mode Silicon ID Addr Addr XXX Data Data F0 2nd Bus Cyc 4th Bus Cyc 5th Bus Cyc Protect Sector Exit Security Factory Verify Region Sector Program XXX XXX XXX XXX XXX XXX XXX AA XXX AA XXX AA XXX AA XXX AA XXX AA XXX AA XXX Addr 55 XXX 55 XXX 55 XXX 55 XXX 55 XXX 55 XXX 55 XXX Data 90 90 90 90 88 Addr Data 3rd Bus Cyc Security ID Command 1st Bus Cyc Automatic Selecty Sector Device Addr X00 Data C2H X01 93H X03 90/10 90 A0 (Sector) X02 XXX Addr 00/01 0 Data Addr Data 6th Bus Cyc Addr Data Command Chip Erase Sector Erase CFI Read Erase Erase Suspend Resume 1st Bus Cyc Addr XXX XXX xx XXX XXX Data AA XXX B0 30 Addr AA XXX 98 2nd Bus Cyc 3rd Bus Cyc Addr 55 XXX 55 XXX 80 XXX 80 Data Data 4th Bus Cyc Addr Data 5th Bus Cyc Addr Data 6th Bus Cyc AA XXX 555 AA 2AA Addr 55 XXX 55 Sector Data 10 30 P/N:PM1082 REV. 1.7, APR. 18, 2008 16 MX29LV065B RESET In the following situations, executing reset command will reset device back to read array mode: • Among erase command sequence (before the full command set is completed) • Sector erase time-out period • Erase fail (while Q5 is high) • Among program command sequence (before the full command set is completed, erase-suspended program included) • Program fail (while Q5 is high, and erase-suspended program fail is included) • Read silicon ID mode • Sector protect verify • CFI mode While device is at the status of program fail or erase fail (Q5 is high), user must issue reset command to reset device back to read array mode. While the device is in read silicon ID mode, sector protect verify or CFI mode, user must issue reset command to reset device back to read array mode. When the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ignore reset command. AUTOMATIC SELECT COMMAND SEQUENCE Automatic Select mode is used to access the manufacturer ID, device ID and to verify whether or not secured silicon is locked and whether or not a sector is protected. The automatic select mode has four command cycles. The first two are unlock cycles, and followed by a specific command. The fourth cycle is a normal read cycle, and user can read at any address any number of times without entering another command sequence. The reset command is necessary to exit the Automatic Select mode and back to read array. The following table shows the identification code with corresponding address. Address Data (Hex) Manufacturer ID X00 C2 Device ID X02 93h Secured Silicon X06 90/10 Factory locked/unlocked (Sector address) X 04 00/01 Unprotected/protected Sector Protect Verify Representation There is an alternative method to that shown in Table 2, which is intended for EPROM programmers and requires Vhv on address bit A9. P/N:PM1082 REV. 1.7, APR. 18, 2008 17 MX29LV065B AUTOMATIC PROGRAMMING The MX29LV065B can provide the user program function by the form of Byte-Mode. As long as the users enter the right cycle defined in the Table.3 (including 2 unlock cycles and A0H), any data user inputs will automatically be programmed into the array. Once the program function is executed, the internal write state controller will automatically execute the algorithms and timings necessary for program and verification, which includes generating suitable program pulse, verifying whether the threshold voltage of the programmed cell is high enough and repeating the program pulse if any of the cells does not pass verification. Meanwhile, the internal control will prohibit the programming to cells that pass verification while the other cells fail in verification in order to avoid over-programming. With the internal write state controller, the device requires the user to write the program command and data only. Programming will only change the bit status from "1" to "0". That is to say, it is impossible to convert the bit status from "0" to "1" by programming. Meanwhile, the internal write verification only detects the errors of the "1" that is not successfully programmed to "0". Any command written to the device during programming will be ignored except hardware reset, which will terminate the program operation after a period of time no more than Tready1. When the embedded program algorithm is complete or the program operation is terminated by hardware reset, the device will return to the reading array data mode. The typical chip program time at room temperature of the MX29LV065B is less than 42 seconds. When the embedded program operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status Q7 Q6 Q5 RY/BY#*2 In progress*1 Q7# Toggling 0 0 Finished Q7 Stop toggling 0 1 Exceed time limit Q7# Toggling 1 0 *1: The status "in progress" means both program mode and erase-suspended program mode. *2: RY/BY# is an open drain output pin and should be weakly connected to VDD through a pull-up resistor. *3: When an attempt is made to program a protected sector, Q7 will output its complement data or Q6 continues to toggle for about 1us or less and the device returns to read array state without programing the data in the protected sector. P/N:PM1082 REV. 1.7, APR. 18, 2008 18 MX29LV065B CHIP ERASE Chip Erase is to erase all the data with "1" and "0" as all "1". It needs 6 cycles to write the action in, and the first two cycles are "unlock" cycles, the third one is a configuration cycle, the fourth and fifth are also "unlock" cycles, and the sixth cycle is the chip erase operation. During chip erasing, all the commands will not be accepted except hardware reset or the working voltage is too low that chip erase will be interrupted. After Chip Erase, the chip will return to the state of Read Array. When the embedded chip erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status Q7 Q6 Q5 Q2 RY/BY# In progress 0 Toggling 0 Toggling 0 Finished 1 Stop toggling 0 1 1 Exceed time limit 0 Toggling 1 Toggling 0 SECTOR ERASE Sector Erase is to erase all the data in a sector with "1" and "0" as all "1". It requires six command cycles to issue. The first two cycles are "unlock cycles", the third one is a configuration cycle, the fourth and fifth are also "unlock cycles" and the sixth cycle is the sector erase command. After the sector erase command sequence is issued, there is a timeout period of 50us counted internally. During the time-out period, additional sector address and sector erase command can be written multiply. Once user enters another sector erase command, the time-out period of 50us is recounted. If user enters any command other than sector erase or erase suspend during time-out period, the erase command would be aborted and the device is reset to read array condition. The number of sectors could be from one sector to all sectors. After time-out period passing by, additional erase command is not accepted and erase embedded operation begins. During sector erasing, all commands will not be accepted except hardware reset and erase suspend and user can check the status as chip erase. When the embedded erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status Q7 Q6 Q5 Q3 Q2 RY/BY#*2 Time-out period 0 Toggling 0 0 Toggling 0 In progress 0 Toggling 0 1 Toggling 0 Finished 1 Stop toggling 0 1 1 1 Exceed time limit 0 Toggling 1 1 Toggling 0 *1: The status Q3 is the time-out period indicator. When Q3=0, the device is in time-out period and is acceptible to another sector address to be erased. When Q3=1, the device is in erase operation and only erase suspend is valid. *2: RY/BY# is open drain output pin and should be weakly connected to VDD through a pull-up resistor. *3: When an attempt is made to erase a protected sector, Q7 will output its complement data or Q6 continues to toggle for 100us or less and the device returned to read array status without erasing the data in the protected sector. P/N:PM1082 REV. 1.7, APR. 18, 2008 19 MX29LV065B SECTOR ERASE SUSPEND During sector erasure, sector erase suspend is the only valid command. If user issue erase suspend command in the time-out period of sector erasure, device time-out period will be over immediately and the device will go back to erasesuspended read array mode. If user issue erase suspend command during the sector erase is being operated, device will suspend the ongoing erase operation, and after the Tready1 (<=20us) suspend finishes and the device will enter erase-suspended read array mode. User can judge if the device has finished erase suspend through Q6, Q7, and RY/ BY#. After device has entered erase-suspended read array mode, user can read other sectors not at erase suspend by the speed of Taa; while reading the sector in erase-suspend mode, device will output its status. User can use Q6 and Q2 to judge the sector is erasing or the erase is suspended. Status Q7 Q6 Q5 Q3 Q2 RY/BY# 1 No toggle 0 N/A Toggle 1 Erase suspend read in non-erase suspended sector Data Data Data Data Data 1 Erase suspend program in non-erase suspended sector Q7# Toggle 0 N/A N/A 0 Erase suspend read in erase suspended sector When the device has suspended erasing, user can execute the command sets except sector erase and chip erase, such as read silicon ID, sector protect verify, program, CFI query and erase resume. SECTOR ERASE RESUME Sector erase resume command is valid only when the device is in erase suspend state. After erase resume, user can issue another erase suspend command, but there should be a 4mS interval between erase resume and the next erase suspend. If user issue infinite suspend-resume loop, or suspend-resume exceeds 1024 times, the time for erasing will increase. P/N:PM1082 REV. 1.7, APR. 18, 2008 20 MX29LV065B QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE MX29LV065B features CFI mode. Host system can retrieve the operating characteristics, structure and vendorspecified information such as identifying information, memory size, byte/word configuration, operating voltages and timing information of this device by CFI mode. The device enters the CFI Query mode when the system writes the CFI Query command, 98H, to address XXH any time the device is ready to read array data. The system can read CFI information at the addresses given in Table 4. A reset command is required to exit CFI mode and go back to ready array mode or erase suspend mode. The system can write the CFI Query command only when the device is in read mode, erase suspend, standby mode or automatic select mode. Table 4-1. CFI mode: Identification Data Values (All values in these tables are in hexadecimal) Description Query-unique ASCII string "QRY" Primary vendor command set and control interface ID code Address for primary algorithm extended query table Alternate vendor command set and control interface ID code (none) Address for alternate algorithm extended query table (none) Address (h) (Byte Mode) Data (h) 10 11 12 13 14 15 16 17 18 19 1A 51 52 59 02 00 40 00 00 00 00 00 Address (h) (Byte Mode) 1B 1C 1D 1E 1F 20 21 22 Data (h) 23 24 25 26 05 00 04 00 Table 4-2. CFI Mode: System Interface Data Values Description Vcc supply minimum program/erase voltage Vcc supply maximum program/erase voltage VPP supply minimum program/erase voltage (none) VPP supply maximum program/erase voltage (none) Typical timeout per single word/byte write, 2n us Typical timeout for maximum-size buffer write, 2n us Typical timeout per individual block erase, 2n ms Typical timeout for full chip erase, 2n ms Maximum timeout for word/byte write, 2n times typical Maximum timeout for buffer write, 2n times typical Maximum timeout per individual block erase, 2n times typical Maximum timeout for chip erase, 2n times typical (not supported) P/N:PM1082 27 36 00 00 04 00 0A 00 REV. 1.7, APR. 18, 2008 21 MX29LV065B Table 4-3. CFI Mode: Device Geometry Data Values Description Address (h) Data (h) (Byte Mode) n Device size = 2 in number of bytes 27 17 Flash device interface description (02=asynchronous x8/x16) 28 00 29 00 2A 00 2B 00 Number of erase regions within device 2C 01 Index for Erase Bank Area 1 2D 7F [2E,2D] = # of same-size sectors in region 1-1 2E 00 [30, 2F] = sector size in multiples of 256-bytes 2F 00 30 01 31 00 32 00 33 00 34 00 35 00 36 00 37 00 38 00 39 00 3A 00 3B 00 3C 00 n Maximum number of bytes in buffer write = 2 (not support) Index for Erase Bank Area 2 Index for Erase Bank Area 3 Index for Erase Bank Area 4 P/N:PM1082 REV. 1.7, APR. 18, 2008 22 MX29LV065B Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values Description Address (h) Data (h) (Byte Mode) Query - Primary extended table, unique ASCII string, PRI 40 50 41 52 42 49 Major version number, ASCII 43 31 Minor version number, ASCII 44 31 Unlock recognizes address (0= recognize, 1= don't recognize) 45 01 Erase suspend (2= to both read and program) 46 02 Sector protect (N= # of sectors/group) 47 04 Temporary sector unprotect (1=supported) 48 01 Sector protect/Chip unprotect scheme 49 04 Simultaneous R/W operation (0=not supported) 4A 00 Burst mode (0=not supported) 4B 00 Page mode (0=not supported) 4C 00 Maximum acceleration supply (0= not supported), [D7:D4] for volt, 4D B5 4E C5 4F 00 [D3:D0] for 100mV Minimum acceleration supply (0= not supported), [D7:D4] for volt, [D3:D0] for 100mV Top/Bottom boot block indicator 02h=bottom 03h=top P/N:PM1082 REV. 1.7, APR. 18, 2008 23 MX29LV065B ABSOLUTE MAXIMUM STRESS RATINGS Surrounding Temperature with Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to +125oC Storage Temperature . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to +150oC Voltage Range Vcc . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V RESET#, A9 and OE# . .. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +12.5 V The other pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to Vcc +0.5 V Output Short Circuit Current (less than one second) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 mA OPERATING TEMPERATURE AND VOLTAGE Commercial (C) Grade Surrounding Temperature (TA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Industrial (I) Grade Surrounding Temperature (TA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C VCC Supply Voltages VCC range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 V to 3.6 V P/N:PM1082 REV. 1.7, APR. 18, 2008 24 MX29LV065B DC CHARACTERISTICS Symbol Description Iilk Input Leak Iilk9 A9 Leak Iolk Output Leak Icr1 Read Current(5MHz) Min Typ Max Remark ± 1.0uA 35uA A9=12.5V ± 1.0uA 9mA 16mA CE#=Vil, OE#=Vih Icr2 Read Current(1MHz) 2mA 4mA CE#=Vil, OE#=Vih Icw Write Current 26mA 30mA CE#=Vil, OE#=Vih, WE#=Vil Isb Standby Current 0.2uA 15uA Vcc=Vcc max, other pin disable Isbr Reset Current 0.2uA 15uA Vcc=Vccmax, Reset# enable, other pin disable Isbs Sleep Mode Current 0.2uA 15uA Icp1 Accelerated Pgm Current, 5mA 10mA WP#/Acc pin (Word/Byte) Icp2 CE#=Vil, OE#=Vih, Accelerated Pgm Current, 15mA 30mA Vcc pin, (Word/Byte) CE#=Vil, OE#=Vih, Vil Input Low Voltage -0.5V 0.8V Vih Input High Voltage 0.7xVcc Vcc+0.3V Vhv Very High Voltage for hardware 11.5V 12.5V Protect/Unprotect/Accelerated Program/Auto Select/Temporary Unprotect Vol Output Low Voltage 0.45V Voh1 Ouput High Voltage 0.85xVcc Ioh1=-2mA Voh2 Ouput High Voltage Vcc-0.4V Ioh2=-100uA P/N:PM1082 Iol=4.0mA REV. 1.7, APR. 18, 2008 25 MX29LV065B SWITCHING TEST CIRCUITS Vcc R2 TESTED DEVICE 0.1uF +3.3V CL R1 DIODES=IN3064 OR EQUIVALENT R1=6.2K ohm R2=2.7K ohm Test Condition Output Load : 1 TTL gate Output Load Capacitance,CL : 30pF(90ns)/100pF(120ns) Rise/Fall Times : 5ns In/Out reference levels :1.5V SWITCHING TEST WAVEFORMS 3.0V 1.5V 1.5V Test Points 0.0V INPUT OUTPUT P/N:PM1082 REV. 1.7, APR. 18, 2008 26 MX29LV065B AC CHARACTERISTICS Symbol Description Taa Min Typ Max Unit Valid data output after address 90/120 ns Tce Valid data output after CE# low 90/120 ns Toe Valid data output after OE# low 35/50 ns Tdf Data output floating after OE# high 30 ns Toh Output hold time from the earliest rising edge of address, 0 ns CE#, OE# Trc Read period time 90/120 ns Twc Write period time 90/120 ns Tcwc Command write period time 90/120 ns Tas Address setup time 0 ns Tah Address hold time 45/50 ns Tds Data setup time 45/50 ns Tdh Data hold time 0 ns Tvcs Vcc setup time 50 us Tcs Chip enable Setup time 0 ns Tch Chip enable hold time 0 ns Toes Output enable setup time 0 ns Read 0 ns Toggle & 10 ns Toeh Toeh Output enable hold time Data# Polling Tws WE# setup time 0 ns Twh WE# hold time 0 ns Tcep CE# pulse width 45/50 ns Tceph CE# pulse width high 30 ns Twp WE# pulse width 35/50 ns Twph WE# pulse width high 30 ns Tbusy Program/Erase active time by RY/BY# Tghwl Read recover time before write 0 ns Tghel Read recover time before write 0 ns Twhwh1 Program operation Twhwh2 Sector erase operation Tbal Sector add hold time 90 ns 7 us 1.6 sec 50 P/N:PM1082 us REV. 1.7, APR. 18, 2008 27 MX29LV065B Figure 1. COMMAND WRITE OPERATION Tcwc CE# Vih Vil Tch Tcs WE# Vih Vil Toes OE# Twph Twp Vih Vil Addresses Vih VA Vil Tah Tas Tdh Tds Vih Data Vil DIN VA: Valid Address P/N:PM1082 REV. 1.7, APR. 18, 2008 28 MX29LV065B READ/RESET OPERATION Figure 2. READ TIMING WAVEFORMS Tce Vih CE# Vil Vih WE# Vil Toeh Tdf Toe Vih OE# Vil Toh Taa Trc Vih ADD Valid Addresses Vil Outputs Voh HIGH Z DATA Valid HIGH Z Vol P/N:PM1082 REV. 1.7, APR. 18, 2008 29 MX29LV065B AC CHARACTERISTICS Item Description Setup Speed Unit Trp1 RESET# Pulse Width (During Automatic Algorithms) MIN 10 us Trp2 RESET# Pulse Width (NOT During Automatic Algorithms) MIN 500 ns Trh RESET# High Time Before Read MIN 50 ns Trb1 RY/BY# Recovery Time (to CE#, OE# go low) MIN 0 ns Tready1 RESET# PIN Low (During Automatic Algorithms) MAX 20 us MAX 500 ns to Read or Write Tready2 RESET# PIN Low (NOT During Automatic Algorithms) to Read or Write Figure 3. RESET# TIMING WAVEFORM Trb1 CE#, OE# Tready1 RY/BY# RESET# Trp1 Reset Timing during Automatic Algorithms CE#, OE# Trh RY/BY# RESET# Trp2 Tready2 Reset Timing NOT during Automatic Algorithms P/N:PM1082 REV. 1.7, APR. 18, 2008 30 MX29LV065B ERASE/PROGRAM OPERATION Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM CE# Tch Twhwh2 Twp WE# Twph Tcs Tghwl OE# Last 2 Erase Command Cycle Twc Address Read Status Tah Tas xxxh VA xxxh Tds Tdh 55h VA In Progress Complete 10h Data Tbusy Trb RY/BY# P/N:PM1082 REV. 1.7, APR. 18, 2008 31 MX29LV065B Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART START Write Data AAH Write Data 55H Write Data 80H Write Data AAH Write Data 55H Write Data 10H Data# Polling Algorithm or Toggle Bit Algorithm NO Data=FFh ? YES Auto Chip Erase Completed P/N:PM1082 REV. 1.7, APR. 18, 2008 32 MX29LV065B Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM Read Status CE# Tch Twhwh2 Twp WE# Twph Tcs Tghwl OE# Tbal Last 2 Erase Command Cycle Twc Address Tas Sector Address 0 xxxh Tds Tdh 55h Sector Address 1 Sector Address n Tah VA VA In Progress Complete 30h 30h 30h Data Tbusy Trb RY/BY# P/N:PM1082 REV. 1.7, APR. 18, 2008 33 MX29LV065B Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART START Write Data AAH Write Data 55H Write Data 80H Write Data AAH Write Data 55H Write Data 30H Sector Address Last Sector to Erase NO YES Data# Polling Algorithm or Toggle Bit Algorithm Data=FFh NO YES Auto Sector Erase Completed P/N:PM1082 REV. 1.7, APR. 18, 2008 34 MX29LV065B Figure 8. ERASE SUSPEND/RESUME FLOWCHART START Write Data B0H NO ERASE SUSPEND Toggle Bit checking Q6 not toggled YES Read Array or Program Reading or Programming End NO YES Write Data 30H ERASE RESUME Continue Erase Another Erase Suspend ? NO YES P/N:PM1082 REV. 1.7, APR. 18, 2008 35 MX29LV065B Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORMS CE# Tch Twhwh1 Twp WE# Tcs Twph Tghwl OE# Last 2 Program Command Cycle XXXh Address Last 2 Read Status Cycle Tah Tas VA PA Tds VA Tdh A0h Status PD DOUT Data Tbusy Trb RY/BY# Figure 10. Accelerated Program Timing Diagram (11.5V ~ 12.5V) Vhv WP#/ACC Vil or Vih Vil or Vih 250nS 250nS P/N:PM1082 REV. 1.7, APR. 18, 2008 36 MX29LV065B Figure 11. CE# CONTROLLED WRITE TIMING WAVEFORM WE# Twhwh1 or Twhwh2 Tcep CE# Tceph Tghwl OE# PA for program SA for sector erase xxx for chip erase xxxh for program xxxh for erase Tas Tah VA Address Tds VA Tdh Status DOUT Data A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase Tbusy RY/BY# P/N:PM1082 REV. 1.7, APR. 18, 2008 37 MX29LV065B Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART START Write Data AAH Write Data 55H Write Data A0H Write Program Data/Address Data# Polling Algorithm or Toggle Bit Algorithm next address Read Again Data: Program Data? No YES No Last Word to be Programed YES Auto Program Completed P/N:PM1082 REV. 1.7, APR. 18, 2008 38 MX29LV065B SECTOR GROUP PROTECT/CHIP UNPROTECT Figure 13. Sector Group Protect/Chip Unprotect Waveform (RESET# Control) 150uS: Sector Protect 15mS: Chip Unprotect 1us CE# WE# OE# Verification Data 60h SA, A6 A1, A0 60h 40h VA VA Status VA Vhv Vih RESET# VA: valid address P/N:PM1082 REV. 1.7, APR. 18, 2008 39 MX29LV065B Figure 14-1. IN-SYSTEM SECTOR GROUP PROTECT WITH RESET#=Vhv START Retry count=0 RESET#=Vhv Wait 1us Temporary Unprotect Mode No First CMD=60h? Yes Write Sector Address with [A6,A1,A0]:[0,1,0] data: 60h Wait 150us Reset PLSCNT=1 Write Sector Address with [A6,A1,A0]:[0,1,0] data: 40h Retry Count +1 Read at Sector Address with [A6,A1,A0]:[0,1,0] No No Retry Count=25? Data=01h? Yes Yes Device fail Protect another sector? Yes No Temporary Unprotect Mode RESET#=Vih Write RESET CMD Sector Protect Done P/N:PM1082 REV. 1.7, APR. 18, 2008 40 MX29LV065B Figure 14-2. CHIP UNPROTECT ALGORITHMS WITH RESET#=Vhv START Retry count=0 RESET#=Vhv Wait 1us Temporary Unprotect No First CMD=60h? Yes All sectors protected? No Protect All Sectors Yes Write [A6,A1,A0]:[1,1,0] data: 60h Wait 15ms Write [A6,A1,A0]:[1,1,0] data: 40h Retry Count +1 Read [A6,A1,A0]:[1,1,0] No No Retry Count=1000? Data=00h? Yes Device fail Yes Temporary Unprotect Write reset CMD Chip Unprotect Done P/N:PM1082 REV. 1.7, APR. 18, 2008 41 MX29LV065B Table 5. TEMPORARY SECTOR GROUP UNPROTECT Parameter Alt Description Condition Speed Unit Trpvhh Tvidr RESET# Rise Time to Vhv and Vhv Fall Time to RESET# MIN 500 ns Tvhhwl Trsp RESET# Vhv to WE# Low MIN 4 us Figure 15. TEMPORARY SECTOR GROUP UNPROTECT WAVEFORMS Program or Erase Command Sequence CE# WE# Tvhhwl RY/BY# Vhv 12V RESET# 0 or Vih Vil or Vih Trpvhh Trpvhh P/N:PM1082 REV. 1.7, APR. 18, 2008 42 MX29LV065B Figure 16. TEMPORARY SECTOR GROUP UNPROTECT FLOWCHART Start Apply Reset# pin Vhv Volt Enter Program or Erase Mode Mode Operation Completed (1) Remove Vhv Volt from Reset# (2) RESET# = Vih Completed Temporary Sector Unprotected Mode Notes: 1. Temporary unprotect all protected sectors Vhv=11.5~12.5V. 2. After leaving temporary unprotect mode, the previously protected sectors are again protected. P/N:PM1082 REV. 1.7, APR. 18, 2008 43 MX29LV065B Figure 17. SILICON ID READ TIMING WAVEFORM Vih CE# Vil Tce Vih WE# Vil Toe Vih OE# Tdf Vil Toh Toh Vhv Vih A9 Vil Vih A0 Vil Taa A1 Taa Vih Vil Vih ADD Vil DATA Q0-Q7 Vih DATA OUT DATA OUT C2H 93H Vil P/N:PM1082 REV. 1.7, APR. 18, 2008 44 MX29LV065B WRITE OPERATION STATUS Figure 18. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) Tce CE# Tch WE# Toe OE# Toeh Tdf Trc Address VA VA Taa Toh Q7 Status Data Complement True Valid Data Q0-Q6 Status Data Status Data True Valid Data High Z High Z Tbusy RY/BY# P/N:PM1082 REV. 1.7, APR. 18, 2008 45 MX29LV065B Figure 19. Data# Polling Algorithm Start Read Q7~Q0 at valid address (Note 1) No Q7 = Data# ? Yes No Q5 = 1 ? Yes Read Q7~Q0 at valid address Q7 = Data# ? (Note 2) No Yes FAIL Pass Notes: 1. For programming, valid address means program address. For erasing, valid address means erase sectors address. 2. Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM1082 REV. 1.7, APR. 18, 2008 46 MX29LV065B Figure 20. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) Tce CE# Tch WE# Toe OE# Toeh Tdf Trc Address VA VA VA VA Taa Toh Q6/Q2 Valid Status (first read) Valid Status Valid Data (second read) (stops toggling) Valid Data Tbusy RY/BY# VA : Valid Address P/N:PM1082 REV. 1.7, APR. 18, 2008 47 MX29LV065B Figure 21. Toggle Bit Algorithm Start Read Q7-Q0 Twice (Note 1) NO Q6 Toggle ? YES NO Q5 = 1? YES Read Q7~Q0 Twice NO Q6 Toggle ? YES PGM/ERS fail Write Reset CMD PGM/ERS Complete Notes: 1. Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 changes to "1". P/N:PM1082 REV. 1.7, APR. 18, 2008 48 MX29LV065B RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. Vcc(min) Vcc GND Tvr Tvcs Tf Tce Tr Vih CE# Vil Vih WE# Vil Tf Toe Tr Vih OE# Vil Tr or Tf Vih ADDRESS Tr or Tf Valid Address Vil Voh DATA Taa High Z Valid Ouput Vol Vih WP#/ACC Vil Figure A. AC Timing at Device Power-Up Symbol Parameter Min. Max. Unit Tvr Vcc Rise Time 20 500000 us/V Tr Input Signal Rise Time 20 us/V Tf Input Signal Fall Time 20 us/V P/N:PM1082 REV. 1.7, APR. 18, 2008 49 MX29LV065B ERASE AND PROGRAMMING PERFORMANCE LIMITS PARAMETER MIN. TYP. MAX. UNITS Chip Erase Time 45 65 sec Sector Erase Time 0.9 15 sec Erase/Program Cycles 100,000 Cycles Chip Programming Time 42 126 sec Byte Programming Time 7 150 us Accelerated Byte Program Time 4 120 us LATCH-UP CHARACTERISTICS MIN. MAX. Input Voltage voltage difference with GND on all pins except I/O pins -1.0V 13.5V Input Voltage voltage difference with GND on all I/O pins -1.0V Vcc + 1.0V -100mA +100mA Vcc Current All pins included except Vcc. Test conditions: Vcc = 3.0V, one pin per testing TSOP PIN CAPACITANCE Parameter Symbol Parameter Description Test Set TYP MAX UNIT CIN2 Control Pin Capacitance VIN=0 7.5 9 pF COUT Output Capacitance VOUT=0 8.5 12 pF CIN Input Capacitance VIN=0 6 7.5 pF P/N:PM1082 REV. 1.7, APR. 18, 2008 50 MX29LV065B ORDERING INFORMATION PART NO. MX29LV065BTC-90 MX29LV065BTC-12 MX29LV065BTI-90 MX29LV065BTI-12 MX29LV065BTC-90G MX29LV065BTC-12G MX29LV065BTI-90G MX29LV065BTI-12G ACCESS TIME PACKAGE (ns) 90 48 Pin TSOP Commercial grade, (Normal Type) Note 1 48 Pin TSOP Commercial grade, (Normal Type) Note 1 48 Pin TSOP Industrial grade, (Normal Type) Note 1 48 Pin TSOP Industrial grade, (Normal Type) Note 1 48 Pin TSOP Commercial grade, (Normal Type) Pb-free 48 Pin TSOP Commercial grade, (Normal Type) Pb-free 48 Pin TSOP Industrial grade, (Normal Type) Pb-free 48 Pin TSOP Industrial grade, (Normal Type) Pb-free 120 90 120 90 120 90 120 Remark Note 1: The part no. is not recommended for new design in. P/N:PM1082 REV. 1.7, APR. 18, 2008 51 MX29LV065B PART NAME DESCRIPTION MX 29 LV 065 B T C 70 G OPTION: G: Pb-free blank: normal SPEED: 90: 90ns 120: 120ns TEMPERATURE RANGE: C: Commercial (0˚CC to 70˚C I: Industrial (-40˚CC to 85˚CC PACKAGE: T: TSOP REVISION: B DENSITY & MODE: 065: 64Mb, x8 Equal Sector TYPE: LV: 3.3V DEVICE: 29:Flash P/N:PM1082 REV. 1.7, APR. 18, 2008 52 MX29LV065B PACKAGE INFORMATION P/N:PM1082 REV. 1.7, APR. 18, 2008 53 MX29LV065B REVISION HISTORY Revision No. 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Description 1. Removed "Preliminary" 1. Removed 63-CSP package information 1. Datasheet format changed 1. Data modification 1. Added statement 1. Added recommedation for non RoHS compliant devices 2. Modified sector erase resume: 400uS --> 4mS 1. Modified Figure 11. CE# Controlled Write Timing Waveform 1. Announced "phase-out" wording P/N:PM1082 Page P1 All All All P54 P1,50 P19 P36 P1,2 Date MAR/08/2005 JAN/09/2006 AUG/15/2006 AUG/24/2006 NOV/06/2006 JAN/24/2007 FEB/26/2008 APR/18/2008 REV. 1.7, APR. 18, 2008 54 MX29LV065B Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. Macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of Macronix's products in the prohibited applications. MACRONIX INTERNATIONAL CO., LTD. Headquarters Macronix, Int'l Co., Ltd. Taipei Office Macronix, Int'l Co., Ltd. 16, Li-Hsin Road, Science Park, Hsinchu, Taiwan, R.O.C. Tel: +886-3-5786688 Fax: +886-3-5632888 19F, 4, Min-Chuan E. Road, Sec. 3, Taipei, Taiwan, R.O.C. Tel: +886-2-2509-3300 Fax: +886-2-2509-2200 Macronix America, Inc. Macronix Europe N.V. 680 North McCarthy Blvd. Milpitas, CA 95035, U.S.A. Tel: +1-408-262-8887 Fax: +1-408-262-8810 Email: [email protected] Koningin Astridlaan 59, Bus 1 1780 Wemmel Belgium Tel: +32-2-456-8020 Fax: +32-2-456-8021 Macronix Japan Cayman Islands Ltd. Singapore Office Macronix Pte. Ltd. NKF Bldg. 5F, 1-2 Higashida-cho, Kawasaki-ku Kawasaki-shi, Kanagawa Pref. 210-0005, Japan Tel: +81-44-246-9100 Fax: +81-44-246-9105 1 Marine Parade Central #11-03 Parkway Centre Singapore 449408 Tel: +65-6346-5505 Fax: +65-6348-8096 Macronix (Hong Kong) Co., Limited. 702-703, 7/F, Building 9, Hong Kong Science Park, 5 Science Park West Avenue, Sha Tin, N.T. Tel: +86-852-2607-4289 Fax: +86-852-2607-4229 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 55