MX29LV320C T/B MX29LV320C T/B DATASHEET The MX29LV320C T/B product family has been discontinued. The MX29LV320C T/B product family is not recommended for new designs. The MX29LV320D T/B family is the recommended replacement. Please refer to MX29LV320D T/B datasheet for full specifications and ordering information, or contact your local sales representative for additional support. P/N:PM1188 REV. 2.2, MAY 04, 2009 1 MX29LV320C T/B Contents FEATURES ............................................................................................................................................................ 5 GENERAL DESCRIPTION .................................................................................................................................... 6 PIN CONFIGURATION ........................................................................................................................................... 7 PIN DESCRIPTION ............................................................................................................................................... 8 BLOCK DIAGRAM ................................................................................................................................................. 9 BLOCK DIAGRAM DESCRIPTION ...................................................................................................................... 10 BLOCK STRUCTURE .......................................................................................................................................... 11 Table 1.a: MX29LV320CT SECTOR GROUP ARCHITECTURE .................................................................. 11 Table 1.b: MX29LV320CB SECTOR GROUP ARCHITECTURE .................................................................. 13 BUS OPERATION ............................................................................................................................................... 15 Table 2-1. BUS OPERATION ...................................................................................................................... 15 Table 2-2. BUS OPERATION ...................................................................................................................... 16 FUNCTIONAL OPERATION DESCRIPTION ........................................................................................................ READ OPERATION ................................................................................................................................... WRITE OPERATION .................................................................................................................................. DEVICE RESET ........................................................................................................................................ STANDBY MODE ...................................................................................................................................... OUTPUT DISABLE .................................................................................................................................... BYTE/WORD SELECTION ........................................................................................................................ HARDWARE WRITE PROTECT ................................................................................................................. ACCELERATED PROGRAMMING OPERATION ........................................................................................ TEMPORARY SECTOR GROUP UNPROTECT OPERATION .................................................................... SECTOR GROUP PROTECT OPERATION ................................................................................................ CHIP UNPROTECT OPERATION .............................................................................................................. AUTOMATIC SELECT BUS OPERATIONS ................................................................................................ SECTOR LOCK STATUS VERIFICATION ................................................................................................... READ SILICON ID MANUFACTURER CODE ............................................................................................ READ SILICON ID MX29LV320CT CODE ................................................................................................. READ SILICON ID MX29LV320CB CODE ................................................................................................. READ INDICATOR BIT (Q7) FOR SECURITY SECTOR ............................................................................ INHERENT DATA PROTECTION ................................................................................................................ COMMAND COMPLETION ........................................................................................................................ LOW VCC WRITE INHIBIT ........................................................................................................................ WRITE PULSE "GLITCH" PROTECTION .................................................................................................. LOGICAL INHIBIT ..................................................................................................................................... P/N:PM1188 17 17 17 17 17 17 17 18 18 18 18 18 19 19 19 19 19 19 20 20 20 20 20 REV. 2.2, MAY 04, 2009 2 MX29LV320C T/B POWER-UP SEQUENCE .......................................................................................................................... 20 POWER-UP WRITE INHIBIT ..................................................................................................................... 20 POWER SUPPLY DECOUPLING ............................................................................................................... 20 COMMAND OPERATIONS .................................................................................................................................. 21 TABLE 3. MX29LV320C T/B COMMAND DEFINITIONS ............................................................................ 21 READING THE MEMORY ARRAY ............................................................................................................. 22 AUTOMATIC PROGRAMMING OF THE MEMORY ARRAY ....................................................................... 22 ERASING THE MEMORY ARRAY ............................................................................................................. 23 SECTOR ERASE ....................................................................................................................................... 23 CHIP ERASE ............................................................................................................................................ 24 ERASE SUSPEND/RESUME .................................................................................................................... 25 SECTOR ERASE RESUME ....................................................................................................................... 25 AUTOMATIC SELECT OPERATIONS ........................................................................................................ 25 AUTOMATIC SELECT COMMAND SEQUENCE ........................................................................................ 26 READ MANUFACTURER ID OR DEVICE ID ............................................................................................. 26 SECURITY SECTOR LOCK STATUS ......................................................................................................... 26 VERIFY SECTOR GROUP PROTECTION ................................................................................................. 26 FACTORY LOCKED: SECURITY SECTOR PROGRAMMED AND PROTECTED AT THE FACTORY ......... 27 CUSTOMER LOCKABLE: SECURITY SECTOR NOT PROGRAMMED OR PROTECTED AT THE FACTORY .................................................................................................................................................................. 27 ENTER AND EXIT SECURITY SECTOR ................................................................................................... 27 SECURITY SECTOR FLASH MEMORY REGION ..................................................................................... 27 RESET OPERATION ................................................................................................................................. 28 COMMON FLASH MEMORY INTERFACE (CFI) MODE ...................................................................................... QUERY COMMAND AND COMMAND FLASH MEMORY INTERFACE (CFI) MODE ................................. Table 4-1. CFI mode: Identification Data Values .......................................................................................... Table 4-2. CFI mode: System Interface Data Values ................................................................................... Table 4-3. CFI mode: Device Geometry Data Values ................................................................................... Table 4-4. CFI mode: Primary Vendor-Specific Extended Query Data Values ............................................... 29 29 29 29 30 31 ELECTRICAL CHARACTERISTICS .................................................................................................................... ABSOLUTE MAXIMUM STRESS RATINGS .............................................................................................. OPERATING TEMPERATURE AND VOLTAGE .......................................................................................... DC CHARACTERISTICS ........................................................................................................................... SWITCHING TEST CIRCUITS ................................................................................................................... SWITCHING TEST WAVEFORMS ............................................................................................................ AC CHARACTERISTICS ........................................................................................................................... 32 32 32 33 34 34 35 WRITE COMMAND OPERATION ........................................................................................................................ 36 Figure 1. COMMAND WRITE OPERATION ................................................................................................ 36 P/N:PM1188 REV. 2.2, MAY 04, 2009 3 MX29LV320C T/B READ/RESET OPERATION ................................................................................................................................ 37 Figure 2. READ TIMING WAVEFORMS ..................................................................................................... 37 Figure 3. RESET# TIMING WAVEFORM ................................................................................................... 38 ERASE/PROGRAM OPERATION ........................................................................................................................ Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART ............................................................. Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM .................................................................. Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART ...................................................... Figure 8. ERASE SUSPEND/RESUME FLOWCHART ............................................................................... Figure 10. ACCELERATED PROGRAM TIMING DIAGRAM ...................................................................... Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORMS ......................................................................... Figure 11. CE# CONTROLLED WRITE TIMING WAVEFORM ..................................................................... Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART ...................................................... 39 40 41 42 43 44 44 45 46 SECTOR GROUP PROTECT/CHIP UNPROTECT ............................................................................................... Figure 13. Sector Group Protect/Chip Unprotect Waveform (RESET# Control) ............................................. Figure 14-1. IN-SYSTEM SECTOR GROUP PROTECT WITH RESET#=Vhv ............................................ Figure 14-2. CHIP UNPROTECT ALGORITHMS WITH RESET#=Vhv ....................................................... Figure 15. TEMPORARY SECTOR GROUP UNPROTECT WAVEFORMS .................................................. Table 5. TEMPORARY SECTOR GROUP UNPROTECT ............................................................................ Figure 16. TEMPORARY SECTOR GROUP UNPROTECT FLOWCHART .................................................. 47 47 48 49 50 50 51 SILICON ID READ OPERATION ......................................................................................................................... 52 Figure 17. SILICON ID READ TIMING WAVEFORM .................................................................................. 52 WRITE OPERATION STATUS ............................................................................................................................. 53 Figure 18. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) ...................... 53 Figure 19. DATA# POLLING ALGORITHM .................................................................................................. 54 Figure 20. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) .......................... 55 Figure 21. TOGGLE BIT ALGORITHM ....................................................................................................... 56 Figure 22. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte mode to ... word mode) ................................................................................................................................................. 57 RECOMMENDED OPERATING CONDITIONS .................................................................................................... TSOP PIN CAPACITANCE .................................................................................................................................. ERASE AND PROGRAMMING PERFORMANCE ................................................................................................ LATCH-UP CHARACTERISTICS ......................................................................................................................... ORDERING INFORMATION ................................................................................................................................ PART NAME DESCRIPTION ............................................................................................................................... PACKAGE INFORMATION ................................................................................................................................... REVISION HISTORY ........................................................................................................................................... P/N:PM1188 58 59 59 59 60 62 63 66 REV. 2.2, MAY 04, 2009 4 MX29LV320C T/B 32M-BIT [4M x 8 / 2M x 16] SINGLE VOLTAGE 3V ONLY FLASH MEMORY The MX29LV320C T/B product family has been discontinued. The MX29LV320C T/B product family is not recommended for new designs. The MX29LV320D T/B family is the recommended replacement. Please refer to MX29LV320D T/B datasheet for full specifications and ordering information, or contact your local sales representative for additional support. FEATURES GENERAL FEATURES • 4,194,304 x 8 / 2,097,152 x 16 switchable • Sector Structure - 8K-Byte x 8 and 64K-Byte x 63 • Extra 64K-Byte sector for security - Features factory locked and identifiable, and customer lockable • Twenty-Four Sector Groups - Provides sector group protect function to prevent program or erase operation in the protected sector group - Provides chip unprotect function to allow code changing - Provides temporary sector group unprotect function for code changing in previously protected sector groups • Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations • Latch-up protected to 100mA from -1V to Vcc + 1V • Low Vcc write inhibit : Vcc <= 1.4V • Compatible with JEDEC standard - Pinout and software compatible to single power supply Flash • Fully compatible with MX29LV320A T/B device PERFORMANCE • High Performance - Fast access time: 70/90ns - Fast program time: 7us/word typical utilizing accelerate function - Fast erase time: 0.9s/sector, 35s/chip (typical) • Low Power Consumption - Low active read current: 10mA (typical) at 5MHz - Low standby current: 200nA (typical) • Minimum 100,000 erase/program cycle • 20 years data retention SOFTWARE FEATURES • Erase Suspend/ Erase Resume - Suspends sector erase operation to read data from or program data to another sector which is not being erased • Status Reply - Data# Polling & Toggle bits provide detection of program and erase operation completion • Support Common Flash Interface (CFI) HARDWARE FEATURES • Ready/Busy# (RY/BY#) Output P/N:PM1188 REV. 2.2, MAY 04, 2009 5 MX29LV320C T/B - Provides a hardware method of detecting program and erase operation completion • Hardware Reset (RESET#) Input - Provides a hardware method to reset the internal state machine to read mode • WP#/ACC input pin - Provides accelerated program capability PACKAGE • 48-Pin TSOP • 48-Ball CSP • All Pb-free devices are RoHS Compliant GENERAL DESCRIPTION MX29LV320CT/B is a 32Mbit flash memory that can be organized as 4Mbytes of 8 bits each or as 2Mbytes of 16 bits each. These devices operate over a voltage range of 2.7V to 3.6V typically using a 3V power supply input. The memory array is divided into 64 equal 64 Kilo byte blocks. However, depending on the device being used as a Top-Boot or Bottom-Boot device, the top or the bottom first block is further subdivided into 8 equal 8Kbyte blocks. The outermost two sectors at the top or at the bottom are respectively the boot blocks for this device. This flash memory also provides an additional factory lockable or customer lockable 64Kbyte sector to provide security feature. The MX29LV320CT/B is offered in a 48-pin TSOP and a 48-ball CSP JEDEC standard package. These packages are offered in leaded, as well as lead-free versions that are compliant to the RoHS specifications. The software algorithm used for this device also adheres to the JEDEC standard for single power supply devices. These flash parts can be programmed in system or on commercially available EPROM/Flash programmers. Separate OE# and CE# (Output Enable and Chip Enable) signals are provided to simplify system design. When used with high speed processors, the 70ns read access time of this flash memory permits operation with minimal time lost due to system timing delays. The automatic program and erase algorithms provided on Macronix flash memories control the entire erase or program operations. The user only needs to write the erase or program commands to the command register. All internal timing, program/erase pulse generation, margin detection, and data verification are performed by the on-chip state machine running these algorithms. Since erasing sectors take much more time than read operations, erase operations can be interrupted in time critical applications to perform read operations in non-erased sectors of the device. For this, Erase Suspend and Erase Resume commands are provided. Data# polling or Toggle bits are used to indicate the end of the erase/program operations. These devices are manufactured at the Macronix fabrication facility using the time tested and proven PACAND (Paired Array Contactless based AND) TECHNOLOGY. This propreitary non-epi process provides a very high degree of latchup protection for stresses up to 100 milliamperes on address and data pins from -1V to Vcc+1V. With low power consumption and enhanced hardware and software features, this flash memory retains data reliably for at least ten years. Erase and programming functions have been tested to meet a minimum specification of 100,000 cycles of operation. P/N:PM1188 REV. 2.2, MAY 04, 2009 6 MX29LV320C T/B PIN CONFIGURATION 48 TSOP A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# NC WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 MX29LV320C T/B A16 BYTE# GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE# GND CE# A0 48-Ball CSP 6mm x 8mm (Ball Pitch = 0.8 mm), Top View, Balls Facing Down BYTE# Q15/ A-1 GND Q14 Q13 Q6 Q12 VCC Q4 Q2 Q10 Q11 Q3 A5 Q0 Q8 Q9 Q1 A2 A1 A0 CE# OE# GND C D E F G H 6 A13 A12 A14 A15 A16 5 A9 A8 A10 A11 Q7 4 WE# RESET# NC A19 Q5 3 RY/ BY# WP# ACC A18 A20 2 A7 A17 A6 1 A3 A4 A B P/N:PM1188 REV. 2.2, MAY 04, 2009 7 MX29LV320C T/B LOGIC SYMBOL PIN DESCRIPTION SYMBOL A0~A20 Q0~Q14 Q15/A-1 CE# WE# OE# BYTE# RESET# RY/BY# Vcc WP#/ACC GND NC PIN NAME Address Input 15 Data Inputs/Outputs Q15(Data Input/Output, word mode); A-1(LSB Address Input, byte mode) Chip Enable Input Write Enable Input Output Enable Input Word/Byte Selection Input Hardware Reset Pin, Active Low Ready/Busy Output 3.0 volt-only single power supply Hardware Write Protect/Acceleration Pin Device Ground Pin Not Connected Internally 21 A0-A20 16 or 8 Q0-Q15 (A-1) CE# OE# WE# RESET# RY/BY# WP#/ACC BYTE# P/N:PM1188 REV. 2.2, MAY 04, 2009 8 MX29LV320C T/B BLOCK DIAGRAM CE# OE# WE# RESET# BYTE# WP#/ACC WRITE CONTROL LOGIC STATE HIGH VOLTAGE MACHINE (WSM) LATCH BUFFER STATE FLASH REGISTER ARRAY ARRAY Y-DECODER AND X-DECODER ADDRESS A0-AM PROGRAM/ERASE INPUT Y-PASS GATE SOURCE HV COMMAND DATA DECODER SENSE AMPLIFIER PGM DATA HV COMMAND DATA LATCH PROGRAM DATA LATCH Q0-Q15/A-1 I/O BUFFER AM: MSB address P/N:PM1188 REV. 2.2, MAY 04, 2009 9 MX29LV320C T/B BLOCK DIAGRAM DESCRIPTION The block diagram on Page 5 illustrates a simplified architecture of MX29LV320C T/B. Each block in the block diagram represents one or more circuit modules in the real chip used to access, erase, program, and read the memory array.. The "CONTROL INPUT LOGIC" block receives input pins CE#, OE#, WE#, RESET#, BYTE#, and WP#/ACC. It creates internal timing control signals according to the input pins and outputs to the “ADDRESS LATCH AND BUFFER” to latch the external address pins A0-AM(A20). The internal addresses are output from this block to the main array and decoders composed of "X-DECODER", "Y-DECODER", "Y-PASS GATE", AND "FLASH ARRAY". The X-decoder decodes the word-lines of the flash array, while the Y-decoder decodes the bit-lines of the flash array. The bit lines are electrically connected to the "SENSE AMPLIFIER" and "PGM DATA HV" selectively through the y-pass gates. Sense amplifiers are used to read out the contents of the flash memory, while the "PGM DATA HV" block is used to selectively deliver high power to bit-lines during programming. The "I/O BUFFER" controls the input and output on the Q0-Q15/A1 pads. During read operation, the I/O buffer receives data from sense amplifiers and drives the output pads accordingly. In the last cycle of program command, the I/O buffer transmits the data on Q0-Q15/A-1 to "PROGRAM DATA LATCH", which controls the high power drivers in "PGM DATA HV" to selectively program the bits in a word or byte according to the user input pattern. The "PROGRAM/ERASE HIGH VOLTAGE" block comprises the circuits to generate and deliver the necessary high voltage to the X-decoder, flash array, and "PGM DATA HV" block. The logic control module comprises of the "WRITE STATE MACHINE, WSM", "STATE REGISTER", "COMMAND DATA DECODER", and "COMMAND DATA LATCH". When the user issues a command by toggling WE#, the command on Q0-A15/A-1 is latched in the command data latch and is decoded by the command data decoder. The state register receives the command and records the current state of the device. The WSM implements the internal algorithms for program or erase according to the current command state by controlling each block in the block diagram. P/N:PM1188 REV. 2.2, MAY 04, 2009 10 MX29LV320C T/B BLOCK STRUCTURE The main flash memory array can be organized as 4M Bytes x 8 or as 2M Words x 16. The details of the address ranges and the corresponding sector addresses are shown in Table 1. Table 1.a shows the sector group architecture for the Top Boot part, whereas Table 1.b shows the sector group architecture for the Bottom Boot part. The specific security sector addresses are shown at the bottom off each of these tables. Table 1.a: MX29LV320CT SECTOR GROUP ARCHITECTURE Sector Sector Size Sector Sector Address Group Byte Mode Word Mode A20-A12 (Kbytes) (Kwords) 1 64 32 SA0 000000xxx 1 64 32 SA1 000001xxx 1 64 32 SA2 000010xxx 1 64 32 SA3 000011xxx 2 64 32 SA4 000100xxx 2 64 32 SA5 000101xxx 2 64 32 SA6 000110xxx 2 64 32 SA7 000111xxx 3 64 32 SA8 001000xxx 3 64 32 SA9 001001xxx 3 64 32 SA10 001010xxx 3 64 32 SA11 001011xxx 4 64 32 SA12 001100xxx 4 64 32 SA13 001101xxx 4 64 32 SA14 001110xxx 4 64 32 SA15 001111xxx 5 64 32 SA16 010000xxx 5 64 32 SA17 010001xxx 5 64 32 SA18 010010xxx 5 64 32 SA19 010011xxx 6 64 32 SA20 010100xxx 6 64 32 SA21 010101xxx 6 64 32 SA22 010110xxx 6 64 32 SA23 010111xxx 7 64 32 SA24 011000xxx 7 64 32 SA25 011001xxx 7 64 32 SA26 011010xxx 7 64 32 SA27 011011xxx 8 64 32 SA28 011100xxx 8 64 32 SA29 011101xxx 8 64 32 SA30 011110xxx 8 64 32 SA31 011111xxx 9 64 32 SA32 100000xxx 9 64 32 SA33 100001xxx 9 64 32 SA34 100010xxx 9 64 32 SA35 100011xxx P/N:PM1188 Address Range Byte Mode (x8) Word Mode (x16) 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 000000h-07FFFh 008000h-0FFFFh 010000h-17FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh REV. 2.2, MAY 04, 2009 11 MX29LV320C T/B Sector Sector Size Group Byte Mode Word Mode (Kbytes) (Kwords) 10 64 32 10 64 32 10 64 32 10 64 32 11 64 32 11 64 32 11 64 32 11 64 32 12 64 32 12 64 32 12 64 32 12 64 32 13 64 32 13 64 32 13 64 32 13 64 32 14 64 32 14 64 32 14 64 32 14 64 32 15 64 32 15 64 32 15 64 32 15 64 32 16 64 32 16 64 32 16 64 32 17 8 4 18 8 4 19 8 4 20 8 4 21 8 4 22 8 4 23 8 4 24 8 4 Sector Sector Address A20-A12 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 100100xxx 100101xxx 100110xxx 100111xxx 101000xxx 101001xxx 101010xxx 101011xxx 101100xxx 101101xxx 101110xxx 101111xxx 110000xxx 110001xxx 110010xxx 110011xxx 110100xxx 110101xxx 110110xxx 110111xxx 111000xxx 111001xxx 111010xxx 111011xxx 111100xxx 111101xxx 111110xxx 111111000 111111001 111111010 111111011 111111100 111111101 111111110 111111111 Address Range Byte Mode (x8) Word Mode (x16) 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3F1FFFh 3F2000h-3F3FFFh 3F4000h-3F5FFFh 3F6000h-3F7FFFh 3F8000h-3F9FFFh 3FA000h-3FBFFFh 3FC000h-3FDFFFh 3FE000h-3FFFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-147FFFh 168000h-14FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1F8FFFh 1F9000h-1F9FFFh 1FA000h-1FAFFFh 1FB000h-1FBFFFh 1FC000h-1FCFFFh 1FD000h-1FDFFFh 1FE000h-1FEFFFh 1FF000h-1FFFFFh Top Boot Security Sector Addresses Sector Size Byte Mode Word Mode (Kbytes) (Kwords) 64 32 Sector Address A20~A12 Address Range Byte Mode (x8) Word Mode (x16) 111111xxx 3F0000h-3FFFFFh P/N:PM1188 1F8000h-1FFFFFh REV. 2.2, MAY 04, 2009 12 MX29LV320C T/B Table 1.b: MX29LV320CB SECTOR GROUP ARCHITECTURE Sector Sector Size Group Byte Mode Word Mode (Kbytes) (Kwords) 1 8 4 2 8 4 3 8 4 4 8 4 5 8 4 6 8 4 7 8 4 8 8 4 9 64 32 9 64 32 9 64 32 10 64 32 10 64 32 10 64 32 10 64 32 11 64 32 11 64 32 11 64 32 11 64 32 12 64 32 12 64 32 12 64 32 12 64 32 13 64 32 13 64 32 13 64 32 13 64 32 14 64 32 14 64 32 14 64 32 14 64 32 15 64 32 15 64 32 15 64 32 15 64 32 16 64 32 16 64 32 16 64 32 16 64 32 Sector Sector Address A20-A12 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 000000000 000000001 000000010 000000011 000000100 000000101 000000110 000000111 000001xxx 000010xxx 000011xxx 000100xxx 000101xxx 000110xxx 000111xxx 001000xxx 001001xxx 001010xxx 001011xxx 001100xxx 001101xxx 001110xxx 001111xxx 010000xxx 010001xxx 010010xxx 010011xxx 010100xxx 010101xxx 010110xxx 010111xxx 011000xxx 011001xxx 011010xxx 011011xxx 011100xxx 011101xxx 011110xxx 011111xxx P/N:PM1188 Address Range Byte Mode (x8) Word Mode (x16) 000000h-001FFFh 002000h-003FFFh 004000h-005FFFh 006000h-007FFFh 008000h-009FFFh 00A000h-00BFFFh 00C000h-00DFFFh 00E000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh REV. 2.2, MAY 04, 2009 13 MX29LV320C T/B Sector Sector Size Group Byte Mode Word Mode (Kbytes) (Kwords) 17 64 32 17 64 32 17 64 32 17 64 32 18 64 32 18 64 32 18 64 32 18 64 32 19 64 32 19 64 32 19 64 32 19 64 32 20 64 32 20 64 32 20 64 32 20 64 32 21 64 32 21 64 32 21 64 32 21 64 32 22 64 32 22 64 32 22 64 32 22 64 32 23 64 32 23 64 32 23 64 32 23 64 32 24 64 32 24 64 32 24 64 32 24 64 32 Sector Sector Address A20-A12 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 100000xxx 100001xxx 100010xxx 100011xxx 100100xxx 100101xxx 100110xxx 100111xxx 101000xxx 101001xxx 101010xxx 101011xxx 101100xxx 101101xxx 101110xxx 101111xxx 110000xxx 110001xxx 110010xxx 110011xxx 110100xxx 110101xxx 110110xxx 110111xxx 111000xxx 111001xxx 111010xxx 111011xxx 111100xxx 111101xxx 111110xxx 111111xxx Address Range Byte Mode (x8) Word Mode (x16) 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh Bottom Boot Security Sector Addresses Sector Size Byte Mode Word Mode (Kbytes) (Kwords) 64 32 Sector Address A20~A12 Address Range Byte Mode (x8) Word Mode (x16) 111111xxx 000000h-00FFFFh P/N:PM1188 00000h-07FFFh REV. 2.2, MAY 04, 2009 14 MX29LV320C T/B BUS OPERATION Table 2-1. BUS OPERATION Mode Select RECE# WE# OE# Address SET# Data (I/O) Q0~Q7 Byte# Vil WP#/ Vih ACC Data (I/O) Q8~Q15 Device Reset L X X X X HighZ HighZ HighZ L/H Standby Mode Vcc± Vcc± X X X HighZ HighZ HighZ H 0.3V 0.3V H L H H X HighZ HighZ HighZ L/H Read Mode H L H L AIN DOUT Q8-Q14= DOUT L/H Write(Note1) H L L H AIN DIN HighZ DIN Note3 Accelerate H L L H AIN DIN Q15= DIN Vhv HighZ DIN Note3 X X L/H X X Note3 Output Disable Program Temporary A-1 Vhv X X X Vhv L L H AIN DIN Sector-Group Unprotect Sector-Group Protect (Note2) Sector Address, DIN, DOUT A6=L, A1=H, A0=L Chip Unprotect (Note2) Vhv L L H Sector Address, DIN, DOUT A6=H, A1=H, A0=L Notes: 1. All sectors will be unprotected if WP#/ACC=Vhv. 2. The two outmost boot sectors are protected if WP#/ACC=Vil. 3. When WP#/ACC = Vih, the protection conditions of the two outmost boot sectors depend on previous protection conditions."Sector/Sector Block Protection and Unprotection" describes the protect and unprotect method. 4. Q0~Q15 are input (DIN) or output (DOUT) pins according to the requests of command sequence, sector protection, or data polling algorithm. 5. In Word Mode (Byte#=Vih), the addresses are AM to A0. In Byte Mode (Byte#=Vil), the addresses are AM to A-1 (Q15). 6. AM: MSB of address. P/N:PM1188 REV. 2.2, MAY 04, 2009 15 MX29LV320C T/B Table 2-2. BUS OPERATION Item Control Input CE# WE# OE# AM A11 to to A8 A9 A12 A10 Sector Lock Status L H L SA x to A5 A6 A7 Vhv x to A1 A0 H L Q0~Q7 Q8~Q15 A2 L x Verification 01h or x 00h (Note1) Read Silicon ID L H L x x Vhv x L x L L C2H x L H L x x Vhv x L x L H A7H 22h(Word) Manufacturer Code Read Silicon ID MX29LV320CT Read Silicon ID x (Byte) L H L x x Vhv x L x L H A8H MX29LV320CB Read Indicator Bit 22h(Word) x (Byte) L H L x x Vhv (Q7) For Security x L x H H 99h or x 19h Sector (Note2) Notes: 1. Sector unprotected code:00h. Sector protected code:01h. 2. Factory locked code: 99h. Factory unlocked code: 19h. 3. AM: MSB of address. P/N:PM1188 REV. 2.2, MAY 04, 2009 16 MX29LV320C T/B FUNCTIONAL OPERATION DESCRIPTION READ OPERATION To perform a read operation, the system addresses the desired memory array or status register location by providing its address on the address pins and simultaneously enabling the chip by driving CE# & OE# LOW, and WE# HIGH. After the Tce and Toa timing requirements have been met, the system can read the contents of the addressed location by reading the Data (I/O) pins. If either the CE# or OE# is held HIGH, the outputs will remain tri-stated and no data will appear on the output pins. WRITE OPERATION To perform a write operation, the system provides the desired address on the address pins, enables the chip by asserting CE# LOW, and disables the Data (I/O) pins by holding OE# HIGH. The system then places data to be written on the Data (I/O) pins and pulses WE# LOW. The device captures the address information on the falling edge of WE# and the data on the rising edge of WE#. To see an example, please refer to the timing diagram in Figure 1 on Page 32. The system is not allowed to write invalid commands (commands not defined in this datasheet) to the device. Writing an invalid command may put the device in an undefined state. DEVICE RESET Driving the RESET# pin LOW for a period of Trp or more will return the device to Read mode. If the device is in the middle of a program or erase operation, the reset operation will take at most a period of Tready1 before the device returns to Read mode. Until the device does returns to Read mode, the RY/BY# pin will remain Low (Busy Status). When the RESET# pin is held at GND±0.3V, the device only consumes standby (Isbr) current. However, the device draws larger current if the RESET# pin is held at a voltage greater than GND+0.3V and less than or equal to Vil. It is recommended to tie the system reset signal to the RESET# pin of the flash memory. This allows the device to be reset with the system and puts it in a state where the system can immediately begin reading boot code from it. STANDBY MODE The device enters Standby mode whenever the RESET# and CE# pins are both held High. While in this mode, WE# and OE# will be ignored, all Data Output pins will be in a high impedance state, and the device will draw minimal (Isb) current. OUTPUT DISABLE While in active mode (RESET# HIGH and CE# LOW), the OE# pin controls the state of the output pins. If OE# is held HIGH, all Data (I/O) pins will remain tri-stated. If held LOW, the Byte or Word Data (I/O) pins will drive data. BYTE/WORD SELECTION The BYTE# input pin is used to select the organization of the array data and how the data is input/output on the Data (I/O) pins. If the BYTE# pin is held HIGH, Word mode will be selected and all 16 data lines (Q0 to Q15) will be active. If BYTE# is forced LOW, Byte mode will be active and only data lines Q0 to Q7 will be active. Data lines Q8 to Q14 will remain in a high impedance state and Q15 becomes the A-1 address input pin. P/N:PM1188 REV. 2.2, MAY 04, 2009 17 MX29LV320C T/B FUNCTIONAL OPERATION DESCRIPTION (cont'd) HARDWARE WRITE PROTECT By driving the WP#/ACC pin LOW, the outermost two boot sectors are protected from all erase/program operations. If WP#/ACC is held HIGH (Vih to VCC), these two outermost sectors revert to their previously protected/unprotected status. ACCELERATED PROGRAMMING OPERATION By applying high voltage (Vhv) to the WP#/ACC pin, the device will enter the Accelerated Programming mode. This mode permits the system to skip the normal command unlock sequences and program byte/word locations directly. Typically, this mode provides a 30% reduction in overall programming times. During accelerated programming, the current drawn from the WP#/ACC pin is no more than ICP1. TEMPORARY SECTOR GROUP UNPROTECT OPERATION The system can apply Vhv to the RESET# pin to place the device in Temporary Unprotect mode. In this mode, previously protected sectors can be programmed/erased just as though they were unprotected. The device returns to normal operation once Vhv is removed from the RESET# pin and previously protected sectors will once again be protected. SECTOR GROUP PROTECT OPERATION The MX29LV320C T/B provides user programmable protection against program/erase operations for selected sectors. Most sectors cannot protected individually. Instead, they are bound in groups of four or less called Sector-Groups. Protection is available for individual Sector-Groups, which includes all member sectors. Boot sectors are the exception to this rule as they are assigned unique Sector-Group addresses and can be protected individually without protecting any adjacent sectors or Sector-Groups. The three sectors adjacent to the boot sectors form a non-standard Sector-Group. Please refer to Table 1a and Table 1b which show all Sector-Group assignments. During the protection operation, the sector address of any sector within a Sector-Group may be used to specify the Sector-Group being protected. There are two methods available to protect Sector-Groups. The first and preferred method is activated by applying Vhv on the RESET# pin and following the timing in Figure 13 and the algorithm shown in Figure 14-1. This is a command operation that can be performed either on an external programmer or in-circuit by the system controller. The second method is strictly a bus operation and is entered by asserting Vhv on A9 and OE# pins, with A6 and CE# at Vil. The protection operation begins at the falling edge of WE# and terminates at the rising edge. Contact Macronix for more details on this method. CHIP UNPROTECT OPERATION The Chip Unprotect operation unprotects all sectors within the device. It is standard procedure and highly recommended to protect all Sector-Groups prior using the Chip Unprotect operation. This will prevent possible damage to the Sector-Group protection logic. All Sector Groups are unprotected when shipped from the factory, so this operation is only necessary if the user has previously protected any Sector-Groups and wishes to unprotect them now. P/N:PM1188 REV. 2.2, MAY 04, 2009 18 MX29LV320C T/B FUNCTIONAL OPERATION DESCRIPTION (cont'd) CHIP UNPROTECT OPERATION (cont'd) MX29LV320C T/B provides two methods for unprotecting the entire chip. The first and preferred method is entered by applying Vhv on RESET# pin and following the timing diagram in Figure 13 and using the algorithm shown in Figure 142. The second method is entered by asserting Vhv on A9 and OE# pins, with A6 at Vih and CE# at Vil. The protection operation begins at the falling edge of WE# and terminates at the rising edge. Contact Macronix for more details on this method. AUTOMATIC SELECT BUS OPERATIONS The following five bus operations require A9 to be raised to Vhv. Please see AUTOMATIC SELECT COMMAND SEQUENCE in the COMMAND OPERATIONS section for details of equivalent command operations that do not require the use of Vhv. SECTOR LOCK STATUS VERIFICATION To determine the protected state of any sector using bus operations, the system performs a READ OPERATION with A9 raised to Vhv, the sector address applied to address pins A20 to A12, address pins A6 & A0 held LOW, and address pin A1 held HIGH. If data bit Q0 is LOW, the sector is not protected, and if Q0 is HIGH, the sector is protected. READ SILICON ID MANUFACTURER CODE To determine the Silicon ID Manufacturer Code, the system performs a READ OPERATION with A9 raised to Vhv and address pins A6, A1, & A0 held LOW. The Macronix ID code of C2h should be present on data bits Q0 to Q7. READ SILICON ID MX29LV320CT CODE To verify the Silicon ID MX29LV320CT Code, the system performs a READ OPERATION with A9 raised to Vhv, address pins A6 & A1 held LOW, and address pin A0 held HIGH. The MX29LV320CT code of A7h should be present on data bits Q0 to Q7. Q15 to Q8 will be tri-stated unless Word mode is selected. In this case, Q15 to Q8 will output the value 22h. READ SILICON ID MX29LV320CB CODE To verify the Silicon ID MX29LV320CB Code, the system performs a READ OPERATION with A9 raised to Vhv, address pins A6 & A1 held LOW, and address pin A0 held HIGH. The MX29LV320CT code of A8h should be present on data bits Q0 to Q7. Q15 to Q8 will be tri-stated unless Word mode is selected. In this case, Q15 to Q8 will output the code 22h. READ INDICATOR BIT (Q7) FOR SECURITY SECTOR To determine if the Security Sector has been locked at the factory, the system performs a READ OPERATION with A9raised to Vhv, address pin A6 held LOW, and address pins A1 & A0 held HIGH. If the Security Sector has been locked at the factory, the code 99h will be present on data bits Q0 to Q7. Otherwise, the factory unlocked code of 19h will be present. P/N:PM1188 REV. 2.2, MAY 04, 2009 19 MX29LV320C T/B FUNCTIONAL OPERATION DESCRIPTION (cont'd) INHERENT DATA PROTECTION To avoid accidental erasure or programming of the device, the device is automatically reset to Read mode during power up. Additionally, the following design features protect the device from unintended data corruption. COMMAND COMPLETION Only after the successful completion of the specified command sets will the device begin its erase or program operation. If any command sequence is interrupted or given an invalid command, the device immediately returns to Read mode. LOW VCC WRITE INHIBIT The device refuses to accept any write command when Vcc is less than 1.4V. This prevents data from spuriously being altered during power-up, power-down, or temporary power interruptions. The device automatically resets itself when Vcc is lower than 1.4V and write cycles are ignored until Vcc is greater than 1.4V. The system must provide proper signals on control pins after Vcc rises above 1.4V to avoid unintentional program or erase operations. WRITE PULSE "GLITCH" PROTECTION CE#, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle. LOGICAL INHIBIT A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is ignored when either CE# at Vih, WE# a Vih, or OE# at Vil. POWER-UP SEQUENCE Upon power up, the MX29LV320C T/B is placed in Read mode. Furthermore, program or erase operation will begin only after successful completion of specified command sequences. POWER-UP WRITE INHIBIT When WE#, CE# is held at Vil and OE# is held at Vih during power up, the device ignores the first command on the rising edge of WE#. POWER SUPPLY DECOUPLING A 0.1uF capacitor should be connected between the Vcc and GND to reduce the noise effect. P/N:PM1188 REV. 2.2, MAY 04, 2009 20 MX29LV320C T/B COMMAND OPERATIONS TABLE 3. MX29LV320C T/B COMMAND DEFINITIONS Automatic Select Sector Reset Mode Word Byte Word Byte Word Byte Addr Addr XXX 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA Data Data F0 AA AA AA AA AA AA AA AA AA AA Addr 2AA 555 2AA 555 2AA 555 2AA 555 2AA 555 Data 55 55 55 55 55 55 55 55 55 55 Addr 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA Data 90 90 90 90 90 90 90 90 88 88 4th Bus Cyc Addr X00 X00 X01 X02 X03 X06 Data C2H C2H ID ID 5th Bus Cyc Addr 6th Bus Cyc Addr Command Hex 1st Bus Cyc 2nd Bus Cyc 3rd Bus Cyc Silicon ID Sector Protect Verify Enter Security Sector Region Read Mode Device ID Factory Word Byte Word Byte Enable (Sector) (Sector)X X02 04 99/19 99/19 00/01 00/01 Data Data Exit Security Sector Command Hex 1st Bus Cyc Program Chip Erase Word Byte Word Byte Word Byte Sector Erase CFI Read Word Byte Word Byte Byte/Word XXX 55 AA Addr 555 AAA 555 AAA 555 AAA 555 AAA Data AA AA AA AA AA AA AA AA Addr 2AA 555 2AA 555 2AA 555 2AA 555 Data 55 55 55 55 55 55 55 55 3rd Bus Cyc Addr 555 AAA AAA 555 AAA Data 90 4th Bus Cyc Addr XXX 00 5th Bus Cyc 2nd Bus Cyc 80 80 80 XXX Addr Addr 555 00 Data Data AA AAA 555 AAA AA AA AA Addr 2AA 555 2AA 555 Data 55 55 55 55 Addr 555 Data 10 Data 6th Bus Cyc 90 555 AAA 555 A0 A0 80 Erase Suspend AAA Sector 10 30 98 98 B0 Erase Resume Byte/Word XXX 30 Sector 30 Notes: ID 22A7h(Top), 22A8h(Bottom). P/N:PM1188 REV. 2.2, MAY 04, 2009 21 MX29LV320C T/B COMMAND OPERATIONS (cont'd) READING THE MEMORY ARRAY Read mode is the default state after power up or after a reset operation. To perform a read operation, please refer to READ OPERATION in the BUS OPERATIONS section above. If the device receives an Erase Suspend command while in the Sector Erase state, the erase operation will pause (after a time delay not exceeding Tready1) and the device will enter Erase-Suspended Read mode. While in the EraseSuspended Read mode, data can be programmed or read from any sector not being erased. Reading from addresses within sector(s) being erased will only return the contents of the status register, which is in fact how the current status of the device can be determined. If a program command is issued to any inactive (not currently being erased) sector during Erase-Suspended Read mode, the device will perform the program operation and automatically return to Erase-Suspended Read mode after the program operation completes successfully. While in Erase-Suspended Read mode, an Erase Resume command must be issued by the system to reactivate the erase operation. The erase operation will resume from where is was suspended and will continue until it completes successfully or another Erase Suspend command is received. After the memory device completes an embedded operation (automatic Chip Erase, Sector Erase, or Program) successfully, it will automatically return to Read mode and data can be read from any address in the array. If the embedded operation fails to complete, as indicated by status register bit Q5 (exceeds time limit flag) going HIGH during the operations, the system must perform a reset operation to return the device to Read mode. There are several states that require a reset operation to return to Read mode: 1. A program or erase failure--indicated by status register bit Q5 going HIGH during the operation. Failures during either of these states will prevent the device from automatically returning to Read mode. 2. The device is in Auto Select mode or CFI mode. These two states remain active until they are terminated by a reset operation. In the two situations above, if a reset operation (either hardware reset or software reset command) is not performed, the device will not return to Read mode and the system will not be able to read array data. AUTOMATIC PROGRAMMING OF THE MEMORY ARRAY The MX29LV320C T/B provides the user the ability to program the memory array in Byte mode or Word mode. As long as the users enters the correct cycle defined in the Table 3 (including 2 unlock cycles and the A0H program command), any byte or word data provided on the data lines by the system will automatically be programmed into the array at the specified location. After the program command sequence has been executed, the internal write state machine (WSM) automatically executes the algorithms and timings necessary for programming and verification, which includes generating suitable program pulses, checking cell threshold voltage margins, and repeating the program pulse if any cells do not pass verification or have low margins. The internal controller protects cells that do pass verification and margin tests from being over-programmed by inhibiting further program pulses to these passing cells as weaker cells continue to be programmed. With the internal WSM automatically controlling the programming process, the user only needs to enter the program command and data once. P/N:PM1188 REV. 2.2, MAY 04, 2009 22 MX29LV320C T/B COMMAND OPERATIONS (cont'd) AUTOMATIC PROGRAMMING OF THE MEMORY ARRAY (cont'd) Programming will only change the bit status from "1" to "0". It is not possible to change the bit status from "0" to "1" by programming. This can only be done by an erase operation. Furthermore, the internal write verification only checks and detects errors in cases where a "1" is not successfully programmed to "0". Any commands written to the device during programming will be ignored except hardware reset, which will terminate the program operation after a period of time no more than Tready1. When the embedded program algorithm is complete or the program operation is terminated by a hardware reset, the device will return to Read mode. The typical chip program time at room temperature of the MX29LV320C T/B is less than 36 seconds. After the embedded program operation has begun, the user can check for completion by reading the following bits in the status register: Status Q7*1 Q6*1 Q5 RY/BY#*2 In progress Q7# Toggling 0 0 Finished Q7 Stop toggling 0 1 Exceed time limit Q7# Toggling 1 0 *1: When an attempt is made to program a protected sector, the program operation will abort thus preventing any data changes in the protected sector. Q7 will output complement data and Q6 will toggle briefly (1us or less) before aborting and returning the device to Read mode. *2: RY/BY# is an open drain output pin and should be connected to VCC through a high value pull-up resistor. ERASING THE MEMORY ARRAY There are two types of erase operations performed on the memory array -- Sector Erase and Chip Erase. In the Sector Erase operation, one or more selected sectors may be erased simultaneously. In the Chip Erase operation, the complete memory array is erased except for any protected sectors. More details of the protected sectors are explained in section 5. SECTOR ERASE The sector erase operation is used to clear data within a sector by returning all of its memory locations to the "1" state. It requires six command cycles to initiate the erase operation. The first two cycles are "unlock cycles", the third is a configuration cycle, the fourth and fifth are also "unlock cycles", and the sixth cycle is the Sector Erase command. After the sector erase command sequence has been issued, an internal 50us time-out counter is started. Until this counter reaches zero, additional sector addresses and Sector Erase commands may be issued thus allowing multiple sectors to be selected and erased simultaneously. After the 50us time-out counter has expired, no new commands will be accepted and the embedded sector erase operation will begin. Note that the 50us timer-out counter is restarted after every erase command sequence. If the user enters any command other than Sector Erase or Erase Suspend during the time-out period, the erase operation will abort and the device will return to Read mode. After the embedded sector erase operation begins, all commands except Erase Suspend will be ignored. The only way to interrupt the operation is with an Erase Suspend command or with a hardware reset. The hardware reset will completely abort the operation and return the device to Read mode. P/N:PM1188 REV. 2.2, MAY 04, 2009 23 MX29LV320C T/B COMMAND OPERATIONS (cont'd) SECTOR ERASE (cont'd) The system can determine the status of the embedded sector erase operation by the following methods: Status Q7 Q6 Q5 Q3 (note 1) Q2 RY/BY#(note 2) Time-out period 0 Toggling 0 0 Toggling 0 In progress 0 Toggling 0 1 Toggling 0 Finished 1 Stop toggling 0 1 1 1 Exceeded time limit 0 Toggling 1 1 Toggling 0 Note : 1. The Q3 status bit is the time-out indicator. When Q3=0, the time-out counter has not yet reached zero and a new Sector Erase command may be issued to specify the address of another sector to be erased. When Q3=1, the time-out counter has expired and the Sector Erase operation has already begun. Erase Suspend is the only valid command that may be issued once the embedded erase operation is underway. 2. RY/BY# is open drain output pin and should be connected to VCC through a high value pull-up resistor. 3. When an attempt is made to erase only protected sector(s), the program operation will abort thus preventing any data changes in the protected sector(s). Q7 will output its complement data and Q6 will toggle briefly (100us or less) before aborting and returning the device to Read mode. If unprotected sectors are also specified, however, they will be erased normally and the protected sector(s) will remain unchanged. 4. Q2 is a localized indicator showing a specified sector is undergoing erase operation or not. Q2 toggles when user reads at addresses where the sectors are actively being erased (in erase mode) or to be erased (in erase suspend mode). When a sector has been completely erased, Q2 stops toggling at the sector even when the device is still in erase operation for remaining selected sectors. At that circumstance, Q2 will still toggle when device is read at any other sector that remains to be erased. CHIP ERASE The Chip Erase operation is used erase all the data within the memory array. All memory cells containing a "0" will be returned to the erased state of "1". This operation requires 6 write cycles to initiate the action. The first two cycles are "unlock" cycles, the third is a configuration cycle, the fourth and fifth are also "unlock" cycles, and the sixth cycle initiates the chip erase operation. During the chip erase operation, no other software commands will be accepted, but if a hardware reset is received or the working voltage is too low, that chip erase will be terminated. After Chip Erase, the chip will automatically return to Read mode. The system can determine the status of the embedded chip erase operation by the following methods: Q7 Q6 Q5 Q2 RY/BY#*1 In progress 0 Toggling 0 Toggling 0 Finished 1 Stop toggling 0 1 1 Exceed time limit 0 Toggling 1 Toggling 0 Status *1: RY/BY# is open drain output pin and should be connected to VCC through a high value pull-up resistor. P/N:PM1188 REV. 2.2, MAY 04, 2009 24 MX29LV320C T/B COMMAND OPERATIONS (cont'd) ERASE SUSPEND/RESUME After beginning a sector erase operation, Erase Suspend is the only valid command that may be issued. If system issues an Erase Suspend command during the 50us time-out period following a Sector Erase command, the time-out period will terminate immediately and the device will enter Erase-Suspended Read mode. If the system issues an Erase Suspend command after the sector erase operation has already begun, the device will not enter Erase-Suspended Read mode until Tready1 time has elapsed. The system can determine if the device has entered the EraseSuspended Read mode through Q6, Q7, and RY/BY#. After the device has entered Erase-Suspended Read mode, the system can read or program any sector(s) except those being erased by the suspended erase operation. Reading any sector being erased or programmed will return the contents of the status register. Whenever a suspend command is issued, user must issue a resume command and check Q6 toggle bit status, before issue another erase command. The system can use the status register bits shown in the following table to determine the current state of the device: Status Q7 Q6 Q5 Q3 Q2 RY/BY# 1 No toggle 0 N/A Toggle 1 Erase suspend read in non-erase suspended sector Data Data Data Data Data 1 Erase suspend program in non-erase suspended sector Q7# Toggle 0 N/A N/A 0 Erase suspend read in erase suspended sector When the device has suspended erasing, user can execute the command sets except sector erase and chip erase, such as read silicon ID, sector protect verify, program, CFI query and erase resume. SECTOR ERASE RESUME The sector Erase Resume command is valid only when the device is in Erase-Suspended Read mode. After erase resumes, the user can issue another Ease Suspend command, but there should be a 400us interval between Ease Resume and the next Erase Suspend command. If the user enters an infinite suspend-resume loop, or suspendresume exceeds 1024 times, erase times will increase dramatically. AUTOMATIC SELECT OPERATIONS When the device is in Read mode, Erase-Suspended Read mode, or CFI mode, the user can issue the Automatic Select command shown in Table 3 (two unlock cycles followed by the Automatic Select command 90h) to enter Automatic Select mode. After entering Automatic Select mode, the user can query the Manufacturer ID, Device ID, Security Sector locked status, or Sector-Group protected status multiple times without issuing a new Automatic Select command. While In Automatic Select mode, issuing a Reset command (F0h) will return the device to Read mode (or EaseSuspended Read mode if Erase-Suspend was active). Another way to enter Automatic Select mode is to use one of the bus operations shown in Table 2-2. BUS OPERATION. After the high voltage (Vhv) is removed from the A9 pin, the device will automatically return to Read mode or EraseSuspended Read mode. P/N:PM1188 REV. 2.2, MAY 04, 2009 25 MX29LV320C T/B COMMAND OPERATIONS (cont'd) AUTOMATIC SELECT COMMAND SEQUENCE Automatic Select mode is used to access the manufacturer ID, device ID and to verify whether or not secured silicon is locked and whether or not a sector is protected. The automatic select mode has four command cycles. The first two are unlock cycles, and followed by a specific command. The fourth cycle is a normal read cycle, and user can read at any address any number of times without entering another command sequence. The Reset command is necessary to exit the Automatic Select mode and back to read array. The following table shows the identification code with corresponding address. Manufacturer ID Device ID Secured Silicon Sector Protect Verify Word Byte Word Byte Word Byte Word Byte Address X00 X00 X01 X02 X03 X06 (Sector address) X 02 (Sector address) X 04 Data (Hex) C2 C2 22A7/22A8 A7/A8 99/19 99/19 00/01 00/01 Representation Top/Bottom Boot Sector Top/Bottom Boot Sector Factory locked/unlocked Factory locked/unlocked Unprotected/protected Unprotected/protected After entering automatic select mode, no other commands are allowed except the reset command. READ MANUFACTURER ID OR DEVICE ID The Manufacturer ID (identification) is a unique hexadecimal number assigned to each manufacturer by the JEDEC committee. Each company has its own manufacturer ID, which is different from the ID of all other companies. The number assigned to Macronix is C2h. The Device ID is a unique hexadecimal number assigned by the manufacturer for each one of the flash devices made by that manufacturer. The above two ID types are stored in a 16-bit register on the flash device -- eight bits for each ID. This register is normally read by the user or by the programming machine to identify the manufacturer and the specific device. After entering Automatic Select mode, performing a read operation with A1 & A0 held LOW will cause the device to output the Manufacturer ID on the Data I/O (Q7 to Q0) pins. Performing a read operation with A1 LOW and A0 HIGH will cause the device to output the Device ID. SECURITY SECTOR LOCK STATUS After entering Automatic Select mode, the customer can check the lock status of the Security Sector by performing a read operations with A0 and A1 held HIGH. If the code 99h is read from data pins Q7 to Q0, the sector has been locked at the factory. If the code 19h is read, the sector has not been locked at the factory. VERIFY SECTOR GROUP PROTECTION After entering Automatic Select mode, performing a read operation with A1 held HIGH and A0 held LOW and the address of the sector to be checked applied to A20 to A12, data bit Q0 will indicate the protected status of the addressed sector. If Q0 is HIGH, the sector is protected. Conversely, if Q0 is LOW, the sector is unprotected. P/N:PM1188 REV. 2.2, MAY 04, 2009 26 MX29LV320C T/B COMMAND OPERATIONS (cont'd) SECURITY SECTOR FLASH MEMORY REGION The Security Sector region is an extra memory space of 64KBytes (32KWords) in length. The Security Sector can be locked by the factory prior to shipping, or it can be locked by the customer later. FACTORY LOCKED: SECURITY SECTOR PROGRAMMED AND PROTECTED AT THE FACTORY In a factory locked device, the Security Sector is permanently locked before shipping from the factory. The device will have a 16-byte (8-word) ESN in the security region. In bottom boot devices, the ESN occupies addresses 00000h to 0000Fh in byte mode or 00000h to 00007h in word mode. In top boot devices, the EXN occupies addresses 3F0000h to 3F000Fh in byte mode or 1F800h to 1F8007h in word mode. CUSTOMER LOCKABLE: SECURITY SECTOR NOT PROGRAMMED OR PROTECTED AT THE FACTORY When the security feature is not required, the Security Sector can provide an extra sector of memory, which can be read, programmed, and erased with the same endurance limitations specified for normal sectors. Two methods are available for protecting the Security Sector. Note that once the Security Sector is protected, there is NO way to unprotect it and its contents can no longer be altered. The first protection method requires writing the three-cycle Enter Security Region command followed by the use of the Sector-Group protect algorithm as illustrated in Figure 14-1 with the following exception: the RESET# pin may be at either Vih or Vhv. Unlike normal Sector-Groups, which do require Vhv on the RESET# pin, the Security Sector may be permanently locked in-circuit without the use of high voltage. The second protection method also uses the three-cycle Enter Security Region command, but uses bus operations that applies Vhv to the A9 and OE# pins with A6, CE#, and WE# held LOW and the SA address applied to A20 to A12. The protection operation begins at the falling edge of WE# and terminates at the rising edge. Contact Macronix for more details on using this method. After the Security Sector is locked and verified, the system must write an Exit Security Sector Region command, go through a power cycle, or issue a hardware reset to return the device to read normal array mode. ENTER AND EXIT SECURITY SECTOR The device allows the user to access the extra 64K-Byte sector identified as the Security Sector, which may contain a random, 128-bits electronic serial number (ESN), or it may contain user data. To access the Security Sector, the user must issue a three-cycle "Enter Security Sector" command sequence. To exit the Security Sector and return to normal operation, the user issues the four-cycle "Exit Security Sector" command. Before issuing the "Exit Security Sector" command, please ensure the entering of security sector region. P/N:PM1188 REV. 2.2, MAY 04, 2009 27 MX29LV320C T/B COMMAND OPERATIONS (cont'd) RESET OPERATION In the following situations, executing reset command will reset device back to Read mode: • • • • • • • • Among erase command sequence (before the full command set is completed) Sector erase time-out period Erase fail (while Q5 is high) Among program command sequence (before the full command set is completed, erase-suspended program included) Program fail (while Q5 is high, and erase-suspended program fail is included) Read silicon ID mode Sector protect verify CFI mode While device is at the status of program fail or erase fail (Q5 is high), user must issue reset command to reset device back to read array mode. While the device is in read silicon ID mode, sector protect verify or CFI mode, user must issue reset command to reset device back to read array mode. When the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ignore reset command. P/N:PM1188 REV. 2.2, MAY 04, 2009 28 MX29LV320C T/B COMMON FLASH MEMORY INTERFACE (CFI) MODE QUERY COMMAND AND COMMAND FLASH MEMORY INTERFACE (CFI) MODE MX29LV320C T/B features CFI mode. Host system can retrieve the operating characteristics, structure and vendorspecified information such as identifying information, memory size, byte/word configuration, operating voltages and timing information of this device by CFI mode. The device enters the CFI Query mode when the system writes the CFI Query command, 98H, to address 55h/AAh (depending on Word/Byte mode) any time the device is ready to read array data. The system can read CFI information at the addresses given in Table 4. Once user enters CFI query mode, user can not issue any other commands except reset command. The reset command is required to exit CFI mode and go back to the mode before entering CFI. The system can write the CFI Query command only when the device is in read mode, erase suspend, standby mode or automatic select mode. Table 4-1. CFI mode: Identification Data Values (All values in these tables are in hexadecimal) Description Query-unique ASCII string "QRY" Primary vendor command set and control interface ID code Address for primary algorithm extended query table Alternate vendor command set and control interface ID code Address for alternate algorithm extended query table Address (h) (Word Mode) 10 11 12 13 14 15 16 17 18 19 1A Address (h) (Byte Mode) 20 22 24 26 28 2A 2C 2E 30 32 34 Data (h) Address (h) (Word Mode) 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 Address (h) (Byte Mode) 36 38 3A 3C 3E 40 42 44 46 48 4A 4C Data (h) 0051 0052 0059 0002 0000 0040 0000 0000 0000 0000 0000 Table 4-2. CFI mode: System Interface Data Values Description Vcc supply minimum program/erase voltage Vcc supply maximum program/erase voltage VPP supply minimum program/erase voltage VPP supply maximum program/erase voltage Typical timeout per single word/byte write, 2n us Typical timeout for maximum-size buffer write, 2n us Typical timeout per individual block erase, 2n ms Typical timeout for full chip erase, 2n ms Maximum timeout for word/byte write, 2n times typical Maximum timeout for buffer write, 2n times typical Maximum timeout per individual block erase, 2n times typical Maximum timeout for chip erase, 2n times typical P/N:PM1188 0027 0036 0000 0000 0004 0000 000A 0000 0005 0000 0004 0000 REV. 2.2, MAY 04, 2009 29 MX29LV320C T/B COMMON FLASH INTERFACE (cont'd) Table 4-3. CFI mode: Device Geometry Data Values Description Address (h) Address (h) (Word Mode) (Byte Mode) Device size = 2n in number of bytes 27 4E 0016 Flash device interface description (02=asynchronous x8/x16) 28 50 0002 29 52 0000 2A 54 0000 2B 56 0000 Number of erase regions within device 2C 58 0002 Index for Erase Bank Area 1 2D 5A 0007 [2E,2D] = # of same-size sectors in region 1-1 2E 5C 0000 [30, 2F] = sector size in multiples of 256-bytes 2F 5E 0020 30 60 0000 31 62 003E 32 64 0000 33 66 0000 34 68 0001 35 6A 0000 36 6C 0000 37 6E 0000 38 70 0000 39 72 0000 3A 74 0000 3B 76 0000 3C 78 0000 Maximum number of bytes in buffer write = 2n (not support) Index for Erase Bank Area 2 Index for Erase Bank Area 3 Index for Erase Bank Area 4 P/N:PM1188 Data (h) REV. 2.2, MAY 04, 2009 30 MX29LV320C T/B COMMON FLASH INTERFACE (cont'd) Table 4-4. CFI mode: Primary Vendor-Specific Extended Query Data Values Description Address (h) Address (h) (Word Mode) (Byte Mode) 40 80 0050 41 82 0052 42 84 0049 Major version number, ASCII 43 86 0031 Minor version number, ASCII 44 88 0031 Unlock recognizes address (0= recognize, 1= don't recognize) 45 8A 0000 Erase suspend (2= to both read and program) 46 8C 0002 Sector protect (N= # of sectors/group) 47 8E 0004 Temporary sector unprotect (1=supported) 48 90 0001 Sector protect/Chip unprotect scheme 49 92 0004 Simultaneous R/W operation (0=not supported) 4A 94 0000 Burst mode (0=not supported) 4B 96 0000 Page mode (0=not supported) 4C 98 0000 Minimum ACC (acceleration) supply (0= not supported), [D7:D4] for volt, 4D 9A 00B5 9C 00C5 9E 000X Query - Primary extended table, unique ASCII string, PRI Data (h) [D3:D0] for 100mV Maximum ACC (acceleration) supply (0= not supported), [D7:D4] for volt, 4E [D3:D0] for 100mV Top/Bottom boot block indicator 4F 02h=bottom boot device 03h=top boot device P/N:PM1188 REV. 2.2, MAY 04, 2009 31 MX29LV320C T/B ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM STRESS RATINGS Surrounding Temperature with Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to +125oC Storage Temperature . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to +150oC Voltage Range Vcc . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to +4.0 V RESET#, A9 and OE# . .. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +12.5 V The other pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..-0.5 V to Vcc +0.5 V Output Short Circuit Current (less than one second) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 mA OPERATING TEMPERATURE AND VOLTAGE Commercial (C) Grade Surrounding Temperature (TA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° C to +70° C Industrial (I) Grade Surrounding Temperature (TA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40° C to +85° C VCC Supply Voltages VCC range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 V to 3.6 V P/N:PM1188 REV. 2.2, MAY 04, 2009 32 MX29LV320C T/B DC CHARACTERISTICS Symbol Description Iilk Input Leak Iilk9 A9 Leak Min Typ Max Remark ± 1.0uA 35uA(0~70° C)/ A9=12.5V 45uA(-40~85° C) Iolk Output Leak Icr1 Read Current(5MHz) ± 1.0uA 10mA 16mA CE#=Vil, OE#=Vih Icr2 Read Current(1MHz) 2mA 4mA CE#=Vil, OE#=Vih Icw Write Current 15mA 30mA CE#=Vil, OE#=Vih, WE#=Vil Isb Standby Current 0.2uA 15uA Vcc=Vcc max, other pin disable Isbr Reset Current 0.2uA 15uA Vcc=Vccmax, Reset# enable, other pin disable Isbs Sleep Mode Current 0.2uA 15uA Icp1 Accelerated Pgm Current, 5mA 10mA WP#/Acc pin(Word/Byte) Icp2 CE#=Vil, OE#=Vih, Accelerated Pgm Current, 15mA 30mA Vcc pin,(Word/Byte) CE#=Vil, OE#=Vih, Vil Input Low Voltage -0.5V 0.8V Vih Input High Voltage 0.7xVcc Vcc+0.3V Vhv Very High Voltage for hardware 11.5V 12.5V Protect/Unprotect/Accelerated Program/Auto Select/Temporary Unprotect Vol Output Low Voltage 0.45V Iol=4.0mA Voh1 Ouput High Voltage 0.85xVcc Ioh1=-2mA Voh2 Ouput High Voltage Vcc-0.4V Ioh2=-100uA Note: Sleep mode enables the lower power when address remain stable for taa+30ns. P/N:PM1188 REV. 2.2, MAY 04, 2009 33 MX29LV320C T/B SWITCHING TEST CIRCUITS Vcc R2 TESTED DEVICE 0.1uF +3.3V CL R1 DIODES=IN3064 OR EQUIVALENT R1=6.2K ohm R2=1.6K ohm Test Condition Output Load : 1 TTL gate Output Load Capacitance,CL : 30pF(70ns)/100pF(90ns) Rise/Fall Times : 5ns In/Out reference levels :1.5V SWITCHING TEST WAVEFORMS 3.0V 1.5V 1.5V Test Points 0.0V INPUT OUTPUT P/N:PM1188 REV. 2.2, MAY 04, 2009 34 MX29LV320C T/B AC CHARACTERISTICS Symbol Description Taa Min Typ Max Unit Valid data output after address 70/90 ns Tce Valid data output after CE# low 70/90 ns Toe Valid data output after OE# low 40 ns Tdf Data output floating after OE# high 30 ns Toh Output hold time from the earliest rising edge of address, 0 ns CE#, OE# Trc Read period time 70/90 ns Twc Write period time 70/90 ns Tcwc Command write period time 70/90 ns Tas Address setup time 0 ns Tah Address hold time 45 ns Tds Data setup time 45 ns Tdh Data hold time 0 ns Tvcs Vcc setup time 50 us Tcs Chip enable Setup time 0 ns Tch Chip enable hold time 0 ns Toes Output enable setup time 0 ns Read 0 ns Toggle & 10 ns Toeh Toeh Output enable hold time Data# Polling Tws WE# setup time 0 ns Twh WE# hold time 0 ns Tcep CE# pulse width 45 ns Tceph CE# pulse width high 30 ns Twp WE# pulse width 35 ns Twph WE# pulse width high 30 ns Tbusy Program/Erase active time by RY/BY# Tghwl Read recover time before write 0 ns Tghel Read recover time before write 0 ns Twhwh1 Program operation Byte 9 us Twhwh1 Program operation Word 11 us Twhwh1 Acc program operation (Word/Byte) 7 us Twhwh2 Sector erase operation 0.9 sec Tbal Sector add hold time 90 50 P/N:PM1188 ns us REV. 2.2, MAY 04, 2009 35 MX29LV320C T/B WRITE COMMAND OPERATION Figure 1. COMMAND WRITE OPERATION Tcwc CE# Vih Vil Tch Tcs WE# Vih Vil Toes OE# Twph Twp Vih Vil Addresses Vih VA Vil Tah Tas Tdh Tds Vih Data Vil DIN VA: Valid Address P/N:PM1188 REV. 2.2, MAY 04, 2009 36 MX29LV320C T/B READ/RESET OPERATION Figure 2. READ TIMING WAVEFORMS Tce Vih CE# Vil Vih WE# Vil Toeh Tdf Toe Vih OE# Vil Toh Taa Trc Vih ADD Valid Addresses Vil Outputs Voh HIGH Z DATA Valid HIGH Z Vol P/N:PM1188 REV. 2.2, MAY 04, 2009 37 MX29LV320C T/B AC CHARACTERISTICS Item Description Setup Speed Unit Trp1 RESET# Pulse Width (During Automatic Algorithms) MIN 10 us Trp2 RESET# Pulse Width (NOT During Automatic Algorithms) MIN 500 ns Trh RESET# High Time Before Read MIN 70 ns Trb1 RY/BY# Recovery Time (to CE#, OE# go low) MIN 0 ns Trb2 RY/BY# Recovery Time (to WE# go low) MIN 50 ns Tready1 RESET# PIN Low (During Automatic Algorithms) MAX 20 us MAX 500 ns to Read or Write Tready2 RESET# PIN Low (NOT During Automatic Algorithms) to Read or Write Figure 3. RESET# TIMING WAVEFORM Trb1 CE#, OE# Trb2 WE# Tready1 RY/BY# RESET# Trp1 Reset Timing during Automatic Algorithms CE#, OE# Trh RY/BY# RESET# Trp2 Tready2 Reset Timing NOT during Automatic Algorithms P/N:PM1188 REV. 2.2, MAY 04, 2009 38 MX29LV320C T/B ERASE/PROGRAM OPERATION Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM CE# Tch Twp WE# Twph Tcs Tghwl OE# Last 2 Erase Command Cycle Twc Address Read Status Tah Tas 2AAh VA SA Tds Tdh 55h VA In Progress Complete 10h Data Tbusy Trb RY/BY# SA: 555h for chip erase P/N:PM1188 REV. 2.2, MAY 04, 2009 39 MX29LV320C T/B Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H Data# Polling Algorithm or Toggle Bit Algorithm NO Data=FFh ? YES Auto Chip Erase Completed P/N:PM1188 REV. 2.2, MAY 04, 2009 40 MX29LV320C T/B Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM Read Status CE# Tch Twhwh2 Twp WE# Twph Tcs Tghwl OE# Tbal Last 2 Erase Command Cycle Twc Address Tas Sector Address 0 2AAh Tds Tdh 55h Sector Address 1 Sector Address n Tah VA VA In Progress Complete 30h 30h 30h Data Tbusy Trb RY/BY# P/N:PM1188 REV. 2.2, MAY 04, 2009 41 MX29LV320C T/B Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address Last Sector to Erase NO YES Data# Polling Algorithm or Toggle Bit Algorithm Data=FFh NO YES Auto Sector Erase Completed P/N:PM1188 REV. 2.2, MAY 04, 2009 42 MX29LV320C T/B Figure 8. ERASE SUSPEND/RESUME FLOWCHART START Write Data B0H NO ERASE SUSPEND Toggle Bit checking Q6 not toggled YES Read Array or Program Reading or Programming End NO YES Write Data 30H ERASE RESUME Continue Erase Another Erase Suspend ? NO YES P/N:PM1188 REV. 2.2, MAY 04, 2009 43 MX29LV320C T/B Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORMS WP#/ACC CE# Tch Twhwh1 Twp WE# Tcs Twph Tghwl OE# Last 2 Program Command Cycle 555h Address Last 2 Read Status Cycle Tah Tas VA PA Tds VA Tdh A0h Status PD DOUT Data Tbusy Trb RY/BY# Figure 10. ACCELERATED PROGRAM TIMING DIAGRAM (11.5V ~ 12.5V) Vhv WP#/ACC Vil or Vih Vil or Vih 250nS 250nS P/N:PM1188 REV. 2.2, MAY 04, 2009 44 MX29LV320C T/B Figure 11. CE# CONTROLLED WRITE TIMING WAVEFORM WE# Twhwh1 or Twhwh2 Tcep CE# Tceph Tghwl OE# Tah Tas Address 555h VA PA Tds VA Tdh A0h Status PD DOUT Data Tbusy RY/BY# P/N:PM1188 REV. 2.2, MAY 04, 2009 45 MX29LV320C T/B Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data# Polling Algorithm or Toggle Bit Algorithm next address Read Again Data: Program Data? No YES No Last Word to be Programed YES Auto Program Completed P/N:PM1188 REV. 2.2, MAY 04, 2009 46 MX29LV320C T/B SECTOR GROUP PROTECT/CHIP UNPROTECT Figure 13. Sector Group Protect/Chip Unprotect Waveform (RESET# Control) 150uS: Sector Protect 15mS: Chip Unprotect 1us CE# WE# OE# Verification Data 60h SA, A6 A1, A0 60h 40h VA VA Status VA Vhv Vih RESET# VA: valid address P/N:PM1188 REV. 2.2, MAY 04, 2009 47 MX29LV320C T/B Figure 14-1. IN-SYSTEM SECTOR GROUP PROTECT WITH RESET#=Vhv START Retry count=0 RESET#=Vhv Wait 1us Temporary Unprotect Mode No First CMD=60h? Yes Write Sector Address with [A6,A1,A0]:[0,1,0] data: 60h Wait 150us Reset PLSCNT=1 Write Sector Address with [A6,A1,A0]:[0,1,0] data: 40h Retry Count +1 Read at Sector Address with [A6,A1,A0]:[0,1,0] No No Retry Count=25? Data=01h? Yes Yes Device fail Protect another sector? Yes No Temporary Unprotect Mode RESET#=Vih Write RESET CMD Sector Protect Done P/N:PM1188 REV. 2.2, MAY 04, 2009 48 MX29LV320C T/B Figure 14-2. CHIP UNPROTECT ALGORITHMS WITH RESET#=Vhv START Retry count=0 RESET#=Vhv Wait 1us Temporary Unprotect No First CMD=60h? Yes All sectors protected? No Protect All Sectors Yes Write [A6,A1,A0]:[1,1,0] data: 60h Wait 15ms Write [A6,A1,A0]:[1,1,0] data: 40h Retry Count +1 Read [A6,A1,A0]:[1,1,0] No No Retry Count=1000? Data=00h? Yes Device fail Yes Temporary Unprotect Write reset CMD Chip Unprotect Done P/N:PM1188 REV. 2.2, MAY 04, 2009 49 MX29LV320C T/B Table 5. TEMPORARY SECTOR GROUP UNPROTECT Parameter Alt Description Condition Speed Unit Trpvhh Tvidr RESET# Rise Time to Vhv and Vhv Fall Time to RESET# MIN 500 ns Tvhhwl Trsp RESET# Vhv to WE# Low MIN 4 us Figure 15. TEMPORARY SECTOR GROUP UNPROTECT WAVEFORMS Program or Erase Command Sequence CE# WE# Tvhhwl RY/BY# Vhv 12V RESET# 0 or Vih Vil or Vih Trpvhh Trpvhh P/N:PM1188 REV. 2.2, MAY 04, 2009 50 MX29LV320C T/B Figure 16. TEMPORARY SECTOR GROUP UNPROTECT FLOWCHART Start Apply Reset# pin Vhv Volt Enter Program or Erase Mode Mode Operation Completed (1) Remove Vhv Volt from Reset# (2) RESET# = Vih Completed Temporary Sector Unprotected Mode Notes: 1. Temporary unprotect all protected sectors Vhv=11.5~12.5V. 2. After leaving temporary unprotect mode, the previously protected sectors are again protected. P/N:PM1188 REV. 2.2, MAY 04, 2009 51 MX29LV320C T/B SILICON ID READ OPERATION Figure 17. SILICON ID READ TIMING WAVEFORM Vih CE# Vil Tce Vih WE# Vil Toe Vih OE# Tdf Vil Toh Toh Vhv Vih A9 Vil Vih A0 Vil Taa A1 Taa Vih Vil Vih ADD Vil DATA Q0-Q7 Vih DATA OUT DATA OUT C2H A7H (TOP boot) A8H (Bottom boot) Vil P/N:PM1188 REV. 2.2, MAY 04, 2009 52 MX29LV320C T/B WRITE OPERATION STATUS Figure 18. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) Tce CE# Tch WE# Toe OE# Toeh Tdf Trc Address VA VA Taa Toh Q7 Status Data Complement True Valid Data Q0-Q6 Status Data Status Data True Valid Data High Z High Z Tbusy RY/BY# P/N:PM1188 REV. 2.2, MAY 04, 2009 53 MX29LV320C T/B Figure 19. DATA# POLLING ALGORITHM Start Read Q7~Q0 at valid address (Note 1) No Q7 = Data# ? Yes No Q5 = 1 ? Yes Read Q7~Q0 at valid address Q7 = Data# ? (Note 2) No Yes FAIL Pass Notes: 1. For programming, valid address means program address. For erasing, valid address means erase sectors address. 2. Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM1188 REV. 2.2, MAY 04, 2009 54 MX29LV320C T/B Figure 20. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) Tce CE# Tch WE# Toe OE# Toeh Tdf Trc Address VA VA VA VA Taa Toh Q6/Q2 Valid Status (first read) Valid Status Valid Data (second read) (stops toggling) Valid Data Tbusy RY/BY# VA : Valid Address P/N:PM1188 REV. 2.2, MAY 04, 2009 55 MX29LV320C T/B Figure 21. TOGGLE BIT ALGORITHM Start Read Q7-Q0 Twice (Note 1) NO Q6 Toggle ? YES NO Q5 = 1? YES Read Q7~Q0 Twice NO Q6 Toggle ? YES PGM/ERS fail Write Reset CMD PGM/ERS Complete Notes: 1. Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 changes to "1". P/N:PM1188 REV. 2.2, MAY 04, 2009 56 MX29LV320C T/B AC CHARACTERISTICS WORD/BYTE CONFIGURATION (BYTE#) Parameter Description Speed Options -70 -90 Unit Telfl/Telfh CE# to BYTE# from L/H MAX 5 5 ns Tflqz BYTE# from L to Output Hiz MAX 25 30 ns Tfhqv BYTE# from H to Output Active MIN 70 90 ns Figure 22. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte mode to word mode) CE# OE# Telfh BYTE# Q0~Q14 DOUT (Q0-Q7) Q15/A-1 VA DOUT (Q0-Q14) DOUT (Q15) Tfhqv P/N:PM1188 REV. 2.2, MAY 04, 2009 57 MX29LV320C T/B RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. Vcc(min) Vcc GND Tvr Tvcs Tf Tce Tr Vih CE# Vil Vih WE# Vil Tf Toe Tr Vih OE# Vil Tr or Tf Vih ADDRESS Tr or Tf Valid Address Vil Voh DATA Taa High Z Valid Ouput Vol Vih WP#/ACC Vil Figure A. AC Timing at Device Power-Up Symbol Parameter Min. Max. Unit Tvr Vcc Rise Time 20 500000 us/V Tr Input Signal Rise Time 20 us/V Tf Input Signal Fall Time 20 us/V P/N:PM1188 REV. 2.2, MAY 04, 2009 58 MX29LV320C T/B ERASE AND PROGRAMMING PERFORMANCE LIMITS PARAMETER MIN. TYP. MAX. UNITS Chip Erase Time 35 50 sec Sector Erase Time 0.9 15 sec Erase/Program Cycles Chip Programming Time 100,000 Cycles Byte Mode 36 108 sec Word Mode 24 72 sec Accelerated Byte/Word Program Time 7 210 us Word Program Time 11 360 us Byte Programming Time 9 300 us DATA RETENTION PARAMETER Data Retention Condition 55°C MIN. 20 MAX. UNITS years LATCH-UP CHARACTERISTICS MIN. MAX. Input Voltage voltage difference with GND on all pins except I/O pins -1.0V 12.5V Input Voltage voltage difference with GND on all I/O pins -1.0V Vcc + 1.0V -100mA +100mA Vcc Current All pins included except Vcc. Test conditions: Vcc = 3.0V, one pin per testing TSOP PIN CAPACITANCE Parameter Symbol Parameter Description Test Set TYP MAX UNIT CIN2 Control Pin Capacitance VIN=0 7.5 9 pF COUT Output Capacitance VOUT=0 8.5 12 pF CIN Input Capacitance VIN=0 6 7.5 pF P/N:PM1188 REV. 2.2, MAY 04, 2009 59 MX29LV320C T/B ORDERING INFORMATION PART NO. ACCESS TIME Ball Pitch/ (ns) Ball Size MX29LV320CTTC-70 70 - 48 Pin TSOP MX29LV320CBTC-70 70 - 48 Pin TSOP MX29LV320CTTI-70 70 - 48 Pin TSOP MX29LV320CBTI-70 70 - 48 Pin TSOP MX29LV320CTTC-90 90 - 48 Pin TSOP MX29LV320CBTC-90 90 - 48 Pin TSOP MX29LV320CTTI-90 90 - 48 Pin TSOP MX29LV320CBTI-90 90 - 48 Pin TSOP MX29LV320CTXBC-70 70 0.8mm/0.3mm 48-Ball CSP MX29LV320CBXBC-70 70 0.8mm/0.3mm 48-Ball CSP MX29LV320CTXEC-70 70 0.8mm/0.4mm 48-Ball CSP MX29LV320CBXEC-70 70 0.8mm/0.4mm 48-Ball CSP MX29LV320CTXBI-70 70 0.8mm/0.3mm 48-Ball CSP MX29LV320CBXBI-70 70 0.8mm/0.3mm 48-Ball CSP MX29LV320CTXEI-70 70 0.8mm/0.4mm 48-Ball CSP MX29LV320CBXEI-70 70 0.8mm/0.4mm 48-Ball CSP MX29LV320CTXBC-90 90 0.8mm/0.3mm 48-Ball CSP MX29LV320CBXBC-90 90 0.8mm/0.3mm 48-Ball CSP MX29LV320CTXEC-90 90 0.8mm/0.4mm 48-Ball CSP MX29LV320CBXEC-90 90 0.8mm/0.4mm 48-Ball CSP MX29LV320CTXBI-90 90 0.8mm/0.3mm 48-Ball CSP MX29LV320CBXBI-90 90 0.8mm/0.3mm 48-Ball CSP MX29LV320CTXEI-90 90 0.8mm/0.4mm 48-Ball CSP MX29LV320CBXEI-90 90 0.8mm/0.4mm 48-Ball CSP P/N:PM1188 PACKAGE Remark REV. 2.2, MAY 04, 2009 60 MX29LV320C T/B PART NO. ACCESS TIME Ball Pitch/ PACKAGE Remark (ns) Ball Size MX29LV320CTTC-70G 70 - 48 Pin TSOP Pb-free MX29LV320CBTC-70G 70 - 48 Pin TSOP Pb-free MX29LV320CTTI-70G 70 - 48 Pin TSOP Pb-free MX29LV320CBTI-70G 70 - 48 Pin TSOP Pb-free MX29LV320CTTC-90G 90 - 48 Pin TSOP Pb-free MX29LV320CBTC-90G 90 - 48 Pin TSOP Pb-free MX29LV320CTTI-90G 90 - 48 Pin TSOP Pb-free MX29LV320CBTI-90G 90 - 48 Pin TSOP Pb-free MX29LV320CTXBC-70G 70 0.8mm/0.3mm 48-Ball CSP Pb-free MX29LV320CBXBC-70G 70 0.8mm/0.3mm 48-Ball CSP Pb-free MX29LV320CTXEC-70G 70 0.8mm/0.4mm 48-Ball CSP Pb-free MX29LV320CBXEC-70G 70 0.8mm/0.4mm 48-Ball CSP Pb-free MX29LV320CTXBI-70G 70 0.8mm/0.3mm 48-Ball CSP Pb-free MX29LV320CBXBI-70G 70 0.8mm/0.3mm 48-Ball CSP Pb-free MX29LV320CTXEI-70G 70 0.8mm/0.4mm 48-Ball CSP Pb-free MX29LV320CBXEI-70G 70 0.8mm/0.4mm 48-Ball CSP Pb-free MX29LV320CTXBC-90G 90 0.8mm/0.3mm 48-Ball CSP Pb-free MX29LV320CBXBC-90G 90 0.8mm/0.3mm 48-Ball CSP Pb-free MX29LV320CTXEC-90G 90 0.8mm/0.4mm 48-Ball CSP Pb-free MX29LV320CBXEC-90G 90 0.8mm/0.4mm 48-Ball CSP Pb-free MX29LV320CTXBI-90G 90 0.8mm/0.3mm 48-Ball CSP Pb-free MX29LV320CBXBI-90G 90 0.8mm/0.3mm 48-Ball CSP Pb-free MX29LV320CTXEI-90G 90 0.8mm/0.4mm 48-Ball CSP Pb-free MX29LV320CBXEI-90G 90 0.8mm/0.4mm 48-Ball CSP Pb-free P/N:PM1188 REV. 2.2, MAY 04, 2009 61 MX29LV320C T/B PART NAME DESCRIPTION MX 29 LV 320 C T T C 70 G OPTION: G: Lead-free package R: Restricted Vcc (3.0V~3.6V) Q: Restricted Vcc (3.0V~3.6V) with Lead-free package blank: normal SPEED: 70: 70nS 90: 90nS TEMPERATURE RANGE: C: Commercial (0˚C to 70˚C) I: Industrial (-40˚C to 85˚C) PACKAGE: T: TSOP X: FBGA (CSP) XB - 0.3mm Ball XE - 0.4mm Ball BOOT BLOCK TYPE: T: Top Boot B: Bottom Boot REVISION: C DENSITY & MODE: 320: 32Mb, x8/x16 Boot Block TYPE: LV: 3V DEVICE: 29:Flash P/N:PM1188 REV. 2.2, MAY 04, 2009 62 MX29LV320C T/B PACKAGE INFORMATION P/N:PM1188 REV. 2.2, MAY 04, 2009 63 MX29LV320C T/B P/N:PM1188 REV. 2.2, MAY 04, 2009 64 MX29LV320C T/B P/N:PM1188 REV. 2.2, MAY 04, 2009 65 MX29LV320C T/B REVISION HISTORY Revision No. Description 1.0 1. Removed "Preliminary" 2. Added "Pb-free devices are RoHS Compliant" 1.1 1. Modified tWES-->tWS; tWEH-->tWH 2. Added note 2 1.2 1. Modified tVCS 1.3 1. Datasheet format changed 1.4 1. Data modification 1.5 1. Added statement 1.6 1. Modified Figure 9. Automatic Program Timing Waveforms 1.7 1. Function description format change (Added "Bus operation" & "Command operation" sections) 2. Added note 4 for Q2 3. "Erase Suspend/Resume" section added "Q6" description 1.8 1. Revised CFI Query description 1.9 1. Modified Figure 11. CE# Controlled Write Timing Waveform 2.0 1. Announced "phase-out" wording 2.1 1. Added note into DC Characteristics 2.2 1. Modified data retention from 10 years to 20 years P/N:PM1188 Page P1 P1 P30 P30 P30 All All P60 P37 P13~27 P23 P24 P28,30 P44 P1,5 P33 P5,59 Date AUG/02/2005 MAR/29/2006 MAY/26/2006 AUG/15/2006 AUG/17/2005 NOV/06/2006 DEC/08/2006 APR/30/2007 JAN/14/2008 FEB/25/2008 APR/08/2008 DEC/24/2008 MAY/04/2009 REV. 2.2, MAY 04, 2009 66 MX29LV320C T/B Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. Macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of Macronix's products in the prohibited applications. Copyright© Macronix International Co., Ltd. 2005~2009. All Rights Reserved. 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